Semiconductor laminate and light receiving element

Abstract

To provide a semiconductor laminate containing a multiplication layer of which an ionization ratio is small, and provide a light receiving element.SOLUTION: A semiconductor laminate comprises: a first conductive type layer; a multiplication layer; a light absorption layer; and a second conductive type layer. The first conductive type layer, the multiplication layer, the light absorption layer, and the second conductive type layer are laminated in this order. The multiplication layer is a superlattice layer containing a first element layer and a second element layer. The first element layer is an InP layer, and the second element layer is a GaAs1-xSbx layer, x is 0.3 or more 1 or less, or the first element layer is AluGa1-uAs1-xSbx layer, the second element layer is an InyGa1-yAs layer, u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, y is 0.3 or more and 1 or less, or the first element layer is AluGa1-uAs1-xSbx layer, the second element layer is a GaAs1-zSbz layer, u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, and z is 0.3 or more and 1 or less.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor laminate and a light receiving element.

Background Art

[0002] In a semiconductor light receiving element (photodiode), an avalanche photodiode that achieves high sensitivity by employing a multiplication layer is known. A strong electric field is applied to the multiplication layer of the avalanche photodiode, and carriers (electrons or holes) generated in the light absorption layer are accelerated by this electric field and collide with atoms in the multiplication layer. As a result, the atoms in the multiplication layer are ionized, and further carriers are generated. In this way, by increasing the number of carriers in the multiplication layer, high sensitivity can be obtained.

[0003] Here, when the number of both electrons and holes increases in the multiplication layer, noise increases and sensitivity decreases. It is required for improving sensitivity that the value obtained by dividing the smaller of the ionization rates α of electrons and β of holes in the multiplication layer by the larger one (the smaller value of α / β and β / α; ionization rate ratio) is small.

[0004] From such a viewpoint, it has been proposed to employ a superlattice layer in which two layers made of different semiconductor materials are alternately laminated instead of a layer made of a single semiconductor material as the multiplication layer. Specifically, it has been proposed to employ a superlattice layer in which an InP layer (indium phosphide layer) and an InGaAs layer (indium gallium arsenide layer) are laminated, or a superlattice layer in which an AlInAs layer (aluminum indium arsenide layer) and an InGaAs layer are laminated as the multiplication layer (see, for example, Non-Patent Document 1 and Non-Patent Document 2).

Prior Art Documents

Non-Patent Documents

[0005]

Non-Patent Document 1

[0006] As described above, in an avalanche photodiode which is a light receiving element including a multiplication layer, a multiplication layer with a small ionization rate ratio is required. Therefore, one of the objects of the present disclosure is to provide a semiconductor laminate and a light receiving element including a multiplication layer with a small ionization rate ratio. [Means for Solving the Problems]

[0007] The semiconductor laminate according to the present disclosure includes a first conductivity type layer composed of a Group III-V compound semiconductor and having a first conductivity type, a multiplication layer composed of a Group III-V compound semiconductor, a light absorption layer composed of a Group III-V compound semiconductor, and a second conductivity type layer composed of a Group III-V compound semiconductor and having a second conductivity type different from the first conductivity type. The first conductivity type layer, the multiplication layer, the light absorption layer, and the second conductivity type layer are laminated in this order. The multiplication layer is a superlattice layer including a first element layer and a second element layer arranged in contact with the first element layer. The first element layer is an InP layer, and the second element layer is a GaAs 1-x Sb x layer (gallium arsenide antimonide layer), where x is 0.3 or more and 1 or less, or the first element layer is Al u Ga 1-u As1-x Sb x layer (aluminum gallium arsenide antimonide layer), and the second element layer is In y Ga 1-y As layer, where u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, y is 0.3 or more and 1 or less, or the first element layer is Al u Ga 1-u As 1-x Sb x layer, and the second element layer is GaAs 1-z Sb z layer, where u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, and z is 0.3 or more and 1 or less.

Advantages of the Invention

[0008] According to the semiconductor laminate, a semiconductor laminate including a multiplication layer with a small ionization rate ratio can be provided.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Modes for Carrying Out the Invention

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. The semiconductor laminate according to the present disclosure is (1) A semiconductor laminate comprising: a first conductivity type layer composed of a group III-V compound semiconductor and having a first conductivity type; a multiplication layer composed of a group III-V compound semiconductor; a light absorption layer composed of a group III-V compound semiconductor; and a second conductivity type layer composed of a group III-V compound semiconductor and having a second conductivity type different from the first conductivity type. The first conductivity type layer, the multiplication layer, the light absorption layer, and the second conductivity type layer are laminated in this order. The multiplication layer is a superlattice layer including a first element layer and a second element layer disposed in contact with the first element layer. The first element layer is an InP layer, and the second element layer is GaAs 1-x Sb x layer, where x is 0.3 or more and 1 or less, or the first element layer is Al u Ga 1-u As 1-x Sb x layer, the second element layer is In y Ga 1-y As layer, where u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, and y is 0.3 or more and 1 or less, or the first element layer is Al u Ga 1-u As 1-x Sb x layer, the second element layer is GaAs 1-z Sb z layer, where u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, and z is 0.3 or more and 1 or less.

[0011] In the semiconductor laminate of the present disclosure, a superlattice layer including an InP layer and a GaAs 1-x Sb x layer, a superlattice layer including an Al u Ga 1-u As 1-x Sb x layer and an In y Ga 1-y As layer, or an Al u Ga 1-u As 1-x Sb x layer and a GaAs 1-z Sb zA superlattice layer including a layer is adopted as a multiplication layer. Since the difference between the energy level difference ΔEc between the conduction bands of the two layers constituting the superlattice layer and the energy level difference ΔEv between the valence bands is large, the ionization rate ratio is small. As a result, according to the semiconductor laminate of the present disclosure, a semiconductor laminate including a multiplication layer with a small ionization rate ratio can be provided. By manufacturing an avalanche photodiode using the semiconductor laminate of the present disclosure, a light receiving element having high sensitivity can be obtained.

[0012] (2) In the above (1), the main surface on the first conductive layer side and the main surface on the light absorption layer side of the multiplication layer may both be constituted by the first element layer. With this configuration, it becomes easy to ensure good crystallinity in the semiconductor laminate.

[0013] (3) In the above (2), the first element layer is an InP layer, and the second element layer is GaAs 1-x Sb x layer, and x may be 0.3 or more and 1 or less. The combination of the InP layer and the GaAs 1-x Sb x layer is particularly suitable as the first element layer and the second element layer constituting the multiplication layer which is a superlattice layer.

[0014] (4) In any of the above (1) to (3), the semiconductor laminate is composed of a III-V compound semiconductor, is disposed between the multiplication layer and the light absorption layer, and may further include a first electric field control layer having a second conductivity type. By adopting such a first electric field control layer, it becomes easy to stably apply a strong electric field to the multiplication layer.

[0015] (5) In the above (4), the semiconductor laminate is composed of a III-V compound semiconductor, is disposed between the multiplication layer and the first conductivity type layer, and may further include a second electric field control layer having a first conductivity type. By adopting such a second electric field control layer in addition to the first electric field control layer, it becomes even easier to stably apply a strong electric field to the multiplication layer.

[0016] (6) In the above (4) or (5), the semiconductor laminate is composed of a III-V compound semiconductor, is disposed between the first field control layer and the light absorption layer, and may further include a composition gradient layer having an energy level of a band edge between those of the first field control layer and the light absorption layer. By adopting such a composition gradient layer, the movement of carriers between the first field control layer and the light absorption layer becomes easy, and the operation speed of the light receiving element is improved.

[0017] (7) In the above (6), the composition gradient layer may include a first main surface that is a main surface on the first field control layer side and a second main surface that is a main surface on the light absorption layer side. The composition of the composition gradient layer may change stepwise such that the energy level of the band edge of the composition gradient layer approaches the energy level of the band edge of the light absorption layer as it approaches the second main surface from the first main surface. By adopting such a configuration, the movement of carriers between the first field control layer and the light absorption layer becomes even easier, and the operation speed of the light receiving element is improved.

[0018] (8) In the above (6), the composition gradient layer may include a first main surface that is a main surface on the first field control layer side and a second main surface that is a main surface on the light absorption layer side. The composition of the composition gradient layer may change continuously such that the energy level of the band edge of the composition gradient layer approaches the energy level of the band edge of the light absorption layer as it approaches the second main surface from the first main surface. Also by adopting such a configuration, the movement of carriers between the first field control layer and the light absorption layer becomes even easier, and the operation speed of the light receiving element is improved.

[0019] The light receiving element according to the present disclosure is (9) includes the semiconductor laminate according to any one of the above (1) to (8) and an electrode disposed on the semiconductor laminate. According to the light receiving element of the present disclosure, by including the semiconductor laminate of the present disclosure including a multiplication layer having a small ionization rate ratio, a light receiving element having high sensitivity can be provided.

[0020] [Details of Embodiments of the Present Disclosure] (Embodiment 1) Next, embodiments of the semiconductor laminate of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals and their description will not be repeated.

[0021] FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor laminate. FIG. 2 is a schematic cross-sectional view showing the structure of a multiplication layer. Referring to FIG. 1, the semiconductor laminate 1 in the present embodiment includes a substrate 11, a buffer layer 12, a multiplication layer 20, a first field control layer 31, an optical absorption layer 40, a cap layer 51, and a contact layer 52.

[0022] The substrate 11 has a first main surface 11A and a second main surface 11B located on the opposite side of the first main surface 11A in the thickness direction. The substrate 11 is composed of a III-V compound. The III-V compound constituting the substrate 11 is, for example, InP. The InP constituting the substrate 11 may contain, for example, Fe (iron) as an impurity. In the present embodiment, the substrate 11 is an insulator. The thickness of the substrate 11 can be, for example, about 150 μm.

[0023] The buffer layer 12 is a semiconductor layer disposed in contact with the second main surface 11B of the substrate 11. The buffer layer 12 has a first main surface 12A and a second main surface 12B located on the opposite side of the first main surface 12A in the thickness direction. The buffer layer 12 is in contact with the second main surface 11B of the substrate 11 at the first main surface 12A. The buffer layer 12 is composed of a III-V compound semiconductor. As the III-V compound semiconductor constituting the buffer layer 12, for example, InP can be adopted. Specifically, for example, InP (p-InP) having a p-type conductivity type is adopted as the compound semiconductor constituting the buffer layer 12. The buffer layer 12 is a first conductivity type layer having a first conductivity type. The concentration of the p-type impurity (an impurity that generates holes as the majority carriers) contained in the compound semiconductor constituting the buffer layer 12 is, for example, 2×10 18 cm -3 or so. The thickness of the buffer layer 12 can be, for example, about 1000 nm.

[0024] The multiplication layer 20 is a semiconductor layer disposed so as to be in contact with the second main surface 12B of the buffer layer 12. The multiplication layer 20 has a first main surface 20A and a second main surface 20B that are located on opposite sides in the thickness direction with respect to the first main surface 20A. The multiplication layer 20 is in contact with the second main surface 12B of the buffer layer 12 at the first main surface 20A. Referring to FIG. 2, the multiplication layer 20 is composed of a III-V compound semiconductor and is a superlattice layer in which a first element layer (barrier layer) 21 and a second element layer (well layer) 22 having different energy levels at the band edges are alternately laminated. The multiplication layer 20 includes a unit structure including the first element layer 21 and the second element layer 22 disposed in contact with the first element layer 21.

[0025] In the present embodiment, the first element layer 21 is composed of InP. The second element layer 22 is composed of GaAs 1-x Sb x where x is 0.3 or more and 1 or less. Also, in the present embodiment, both the first main surface 20A and the second main surface 20B of the multiplication layer 20 are composed of the first element layer 21. That is, both the first main surface 20A and the second main surface 20B of the multiplication layer 20 are composed of InP layers. The lowermost layer and the uppermost layer of the multiplication layer 20 are both composed of InP layers. The thickness of the first element layer 21 can be, for example, about 20 nm. The thickness of the second element layer 22 can be, for example, about 30 nm. The number of unit structures included in the multiplication layer 20 can be, for example, about 10. The thickness of the multiplication layer 20 can be appropriately adjusted according to the desired characteristics of the light receiving element to be manufactured. Specifically, a high multiplication factor can be obtained by increasing the thickness of the multiplication layer 20. The operating speed can be improved by reducing the thickness of the multiplication layer 20.

[0026] Referring to FIG. 1, the first electric field control layer 31 is a semiconductor layer disposed to contact the second main surface 20B of the multiplication layer 20. The first electric field control layer 31 has a first main surface 31A and a second main surface 31B located on the opposite side of the first main surface 31A in the thickness direction. The first electric field control layer 31 is in contact with the second main surface 20B of the multiplication layer 20 at the first main surface 31A. The first electric field control layer 31 is composed of a III-V compound semiconductor. As the III-V compound semiconductor constituting the first electric field control layer 31, for example, InP can be adopted. Specifically, for example, InP (n-InP) having a conductivity type of n-type is adopted as the compound semiconductor constituting the first electric field control layer 31. The first electric field control layer 31 is a semiconductor layer having a second conductivity type. The concentration of the n-type impurity (an impurity that generates electrons as the majority carriers) contained in the compound semiconductor constituting the first electric field control layer 31 can be, for example, 5×10 17 cm -3 or so. The concentration of the impurity that generates the majority carriers is lower in the first electric field control layer 31 than in the buffer layer 12. The thickness of the first electric field control layer 31 can be, for example, about 100 nm.

[0027] The light absorption layer 40 is a semiconductor layer arranged to be in contact with the second main surface 31B of the first electric field control layer 31. The light absorption layer 40 has a first main surface 40A and a second main surface 40B that is located on the opposite side of the first main surface 40A in the thickness direction. The light absorption layer 40 is in contact with the second main surface 31B of the first electric field control layer 31 at the first main surface 40A. The light absorption layer 40 is composed of a III-V compound semiconductor. As the III-V compound semiconductor constituting the light absorption layer 40, for example, InGaAs can be adopted. Specifically, for example, undoped InGaAs (ud-InGaAs) is adopted as the compound semiconductor constituting the light absorption layer 40. The thickness of the light absorption layer 40 can be, for example, about 3.0 μm. The thickness of the light absorption layer 40 can be appropriately adjusted according to the desired characteristics of the light receiving element to be manufactured. Specifically, high sensitivity can be obtained by increasing the thickness of the light absorption layer 40. The operating speed can be improved by reducing the thickness of the light absorption layer 40.

[0028] The cap layer 51 is a semiconductor layer arranged to be in contact with the second main surface 40B of the light absorption layer 40. The cap layer 51 has a first main surface 51A and a second main surface 51B that is located on the opposite side of the first main surface 51A in the thickness direction. The cap layer 51 is in contact with the second main surface 40B of the light absorption layer 40 at the first main surface 51A. The cap layer 51 is composed of a III-V compound semiconductor. As the III-V compound semiconductor constituting the cap layer 51, for example, InP can be adopted. Specifically, for example, InP with an n-type conductivity (n-InP) is adopted as the compound semiconductor constituting the cap layer 51. The concentration of the n-type impurity (an impurity that generates electrons, which are the majority carriers) contained in the compound semiconductor constituting the cap layer 51 can be, for example, 1×10 18 cm -3 or so. In the present embodiment, the concentration of the impurity that generates the majority carriers is lower in the first electric field control layer 31 than in the cap layer 51. The thickness of the cap layer 51 can be, for example, about 500 nm.

[0029] The contact layer 52 is a semiconductor layer disposed to contact the second main surface 51B of the cap layer 51. The contact layer 52 has a first main surface 52A and a second main surface 52B located on the opposite side of the first main surface 52A in the thickness direction. The contact layer 52 is in contact with the second main surface 51B of the cap layer 51 at the first main surface 52A. The contact layer 52 is composed of a III-V compound semiconductor. As the III-V compound semiconductor constituting the contact layer 52, for example, InGaAs can be adopted. Specifically, for example, InGaAs (n-InGaAs) having an n-type conductivity type is adopted as the compound semiconductor constituting the contact layer 52. The concentration of the n-type impurity (an impurity that generates electrons which are the majority carriers) contained in the compound semiconductor constituting the contact layer 52 can be, for example, 2×10 19 cm -3 or so. The concentration of the impurity that generates the majority carriers is higher in the contact layer 52 than in the cap layer 51. The thickness of the contact layer 52 can be, for example, about 200 nm. The cap layer 51 and the contact layer 52 constitute a second conductivity type layer 50 having a second conductivity type.

[0030] In the semiconductor laminate 1 of the present embodiment, as the n-type impurity, for example, Si (silicon) or the like can be adopted. As the p-type impurity, for example, Zn (zinc) or the like can be adopted.

[0031] Next, an avalanche photodiode, which is an example of a light-receiving element fabricated using the semiconductor laminate 1, will be described. FIG. 3 is a schematic cross-sectional view showing the structure of the avalanche photodiode. Referring to FIG. 3, the avalanche photodiode 100 in the present embodiment is fabricated using the semiconductor laminate 1 of the present embodiment, and includes a substrate 11 laminated in the same manner as the semiconductor laminate 1, a buffer layer 12, a multiplication layer 20, a first electric field control layer 31, a light absorption layer 40, a cap layer 51, and a contact layer 52. A trench 99 is formed in the avalanche photodiode 100, penetrating through the contact layer 52, the cap layer 51, the light absorption layer 40, the first electric field control layer 31, and the multiplication layer 20 to reach the buffer layer 12. That is, on the sidewall 99A of the trench 99, the contact layer 52, the cap layer 51, the light absorption layer 40, the first electric field control layer 31, and the multiplication layer 20 are exposed. Also, the bottom wall 99B of the trench 99 is located within the buffer layer 12. That is, the buffer layer 12 is exposed at the bottom wall 99B of the trench 99.

[0032] Furthermore, the avalanche photodiode 100 includes a passivation film 80, a first electrode 91, and a second electrode 92. The passivation film 80 is disposed so as to cover the bottom wall 99B of the trench 99, the sidewall 99A of the trench 99, and the second main surface 52B of the contact layer 52. The passivation film 80 is composed of an insulator such as silicon nitride or silicon oxide.

[0033] An opening is formed in the passivation film 80 covering the bottom wall 99B of the trench 99 so as to penetrate the passivation film 80 in the thickness direction. The first electrode 91 is disposed so as to fill this opening. The first electrode 91 is disposed so as to contact the buffer layer 12 exposed from the opening. The first electrode 91 is made of a conductor such as metal. More specifically, the first electrode 91 can be made of, for example, Ti (titanium) / Pt (platinum) / Au (gold). The first electrode 91 makes an ohmic contact with the buffer layer 12.

[0034] An opening is formed in the passivation film 80 that covers the second main surface 52B of the contact layer 52 so as to penetrate the passivation film 80 in the thickness direction. And the second electrode 92 is disposed so as to fill this opening. The second electrode 92 is disposed so as to contact the contact layer 52 exposed from the opening. The second electrode 92 is made of a conductor such as metal. More specifically, the second electrode 92 can be made of, for example, Ti / Pt / Au. The second electrode 92 makes an ohmic contact with the contact layer 52.

[0035] Next, the operation of the avalanche photodiode 100 of the present embodiment will be described. During operation, a reverse bias is applied to the avalanche photodiode 100. Specifically, in the present embodiment, a voltage is applied such that the first electrode 91 is the negative electrode and the second electrode 92 is the positive electrode. When light is incident on the avalanche photodiode 100, the light is absorbed in the light absorption layer 40, and a pair of electrons and holes is generated. The generated electrons and holes are taken out of the avalanche photodiode 100 as a photocurrent signal, whereby the light is detected.

[0036] Here, the holes generated in the light absorption layer 40 travel toward the first electrode 91 side, which is the negative electrode, and reach the multiplication layer 20 through the first electric field control layer 31. As described above, the multiplication layer 20 of the present embodiment is a superlattice layer in which a first element layer 21 made of InP and a second element layer 22 made of GaAs 1-x Sb x (x is 0.3 or more and 1 or less) are alternately stacked. In this superlattice layer, InP constituting the first element layer 21 and GaAs 1-x Sb xBetween them, the difference ΔEv in the energy level between valence bands is larger than the difference ΔEc in the energy level between conduction bands. Therefore, the ionization rate ratio, which is the value of ΔEc / ΔEv, is small. In such a superlattice layer, when carriers fall from the first element layer 21 (barrier layer) to the second element layer (well layer) 22, the ionization coefficient of holes becomes larger than that of electrons. As a result, the number of holes in the multiplication layer 20 increases significantly compared to electrons. As a result, even if the number of electron-hole pairs generated in the light absorption layer 40 is small, the photocurrent signal can be easily detected. Thus, the avalanche photodiode 100 of the present embodiment is a light receiving element having high sensitivity. Further, the semiconductor laminate 1 of the present embodiment is a semiconductor laminate suitable for manufacturing the avalanche photodiode 100, and is a semiconductor laminate capable of obtaining a light receiving element having high sensitivity.

[0037] In the present embodiment, the ionization rate ratio in the multiplication layer 20 can be less than 0.05. The ionization rate ratio in the multiplication layer 20 can be calculated by fabricating an avalanche photodiode in which the p-type semiconductor layer in the avalanche photodiode 100 of the present embodiment is an n-type semiconductor layer and the n-type semiconductor layer is a p-type semiconductor layer, and evaluating the electrical characteristics of both. Further, in the semiconductor laminate 1 and the avalanche photodiode 100 of the present embodiment, the presence of the first electric field control layer 31 is not essential, but by adopting this, it becomes easy to stably apply a strong electric field to the multiplication layer.

[0038] (Embodiment 2) Next, Embodiment 2, which is another embodiment of the semiconductor laminate and the avalanche photodiode of the present disclosure, will be described. FIG. 4 is a schematic cross-sectional view showing the structure of the semiconductor laminate. Referring to FIGS. 4 and 1, the semiconductor laminate 1 of Embodiment 2 further includes a second electric field control layer 32 in addition to the structure of the semiconductor laminate 1 of Embodiment 1. Further, the avalanche photodiode 100 of Embodiment 2 further includes a second electric field control layer 32 in addition to the structure of the avalanche photodiode 100 of Embodiment 1.

[0039] The second electric field control layer 32 is disposed between the multiplication layer 20 and the buffer layer 12. The second electric field control layer 32 has a first main surface 32A and a second main surface 32B located on the opposite side of the first main surface 32A in the thickness direction. The second electric field control layer 32 is in contact with the second main surface 12B of the buffer layer 12 at the first main surface 32A and is in contact with the first main surface 20A of the multiplication layer 20 at the second main surface 32B.

[0040] The second electric field control layer 32 is composed of a III-V compound semiconductor. As the III-V compound semiconductor constituting the second electric field control layer 32, for example, InP can be adopted. Specifically, for example, InP (p-InP) having a p-type conductivity type is adopted as the compound semiconductor constituting the second electric field control layer 32. The second electric field control layer 32 is a semiconductor layer having a first conductivity type. The concentration of the p-type impurity (an impurity that generates holes as the majority carrier) contained in the compound semiconductor constituting the second electric field control layer 32 is, for example, 5×10 17 cm -3 or the like. The concentration of the impurity that generates the majority carrier is lower in the second electric field control layer 32 than in the buffer layer 12. The thickness of the second electric field control layer 32 can be, for example, about 100 nm.

[0041] In the present embodiment, in addition to the first electric field control layer 31 described in the above Embodiment 1, a second electric field control layer 32 is adopted. Thereby, it becomes easier to stably apply a strong electric field to the multiplication layer 20.

[0042] (Embodiment 3) Next, Embodiment 3, which is yet another embodiment of the semiconductor laminate and the avalanche photodiode of the present disclosure, will be described. FIG. 5 is a schematic cross-sectional view showing the structure of the semiconductor laminate. Referring to FIGS. 5 and 4, the semiconductor laminate 1 of Embodiment 3 further includes a composition gradient layer 60 in addition to the structure of the semiconductor laminate 1 of Embodiment 2. Further, the avalanche photodiode 100 of Embodiment 3 further includes a composition gradient layer 60 in addition to the structure of the avalanche photodiode 100 of Embodiment 2.

[0043] The composition gradient layer 60 is disposed between the first electric field control layer 31 and the optical absorption layer 40. The composition gradient layer 60 has a first main surface 60A and a second main surface 60B that is located on the opposite side of the first main surface 60A in the thickness direction. The composition gradient layer 60 is in contact with the second main surface 31B of the first electric field control layer 31 at the first main surface 60A and is in contact with the first main surface 40A of the optical absorption layer 40 at the second main surface 60B.

[0044] The composition gradient layer 60 is composed of a III-V compound semiconductor. The energy level of the band edge of the composition gradient layer 60 has a value between the energy level of the band edge of the first electric field control layer 31 and the energy level of the band edge of the optical absorption layer 40. As the III-V compound semiconductor constituting the composition gradient layer 60, for example, InGaAsP can be adopted. The composition of InGaAsP constituting the composition gradient layer 60 may be constant in the composition gradient layer 60, but the energy level of the band edge of the composition gradient layer 60 may change stepwise or continuously so as to approach the energy level of the band edge of the optical absorption layer 40 as it approaches the second main surface 60B from the first main surface 60A.

[0045] In this embodiment, a compositionally graded layer 60 is employed. As a result, carrier movement between the first field control layer 31 and the optical absorption layer 40 is facilitated. Consequently, the semiconductor laminate 1 and the avalanche photodiode 100 of this embodiment are a semiconductor laminate and an avalanche photodiode capable of improving the operating speed of the avalanche photodiode.

[0046] (Embodiment 4) Next, Embodiment 4, which is yet another embodiment of the semiconductor laminate and avalanche photodiode of the present disclosure, will be described. Referring to FIGS. 1 to 3, the semiconductor laminate 1 and the avalanche photodiode 100 in Embodiment 4 have the same laminated structure as the semiconductor laminate 1 and the avalanche photodiode 100 in Embodiment 1, while being different from Embodiment 1 in terms of the materials constituting the multiplication layer 20 and the first field control layer 31 and the conductivity type of each layer.

[0047] Specifically, referring to FIG. 2, the first element layer 21 in Embodiment 4 is composed of Al u Ga 1-u As 1-x Sb x . The second element layer 22 is composed of In y Ga 1-y As. Here, u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, and y is 0.3 or more and 1 or less. Both the lowermost layer and the uppermost layer of the multiplication layer 20 are composed of Al u Ga 1-u As 1-x Sb x . Also, referring to FIGS. 1 and 3, as the III-V compound semiconductor constituting the first field control layer 31 in Embodiment 4, for example, AlGaAsSb can be employed. Further, unlike Embodiment 1, while the conductivity type of the buffer layer 12 is n-type, the conductivity types of the first field control layer 31, the cap layer 51, and the contact layer 52 are p-type. The thickness of each layer and the concentration of the impurity generating the majority carriers can adopt the same values as in Embodiment 1.

[0048] Next, the operation of the avalanche photodiode 100 of the present embodiment will be described. During operation, a reverse bias is applied to the avalanche photodiode 100. Specifically, in the present embodiment, a voltage is applied so that the first electrode 91 is the positive electrode and the second electrode 92 is the negative electrode. That is, a voltage opposite to that in the case of the first embodiment is applied to the avalanche photodiode 100. When light is incident on the avalanche photodiode 100, the light is absorbed in the light absorption layer 40, and a pair of electrons and holes is generated. When the generated electrons and holes are taken out of the avalanche photodiode 100 as a photocurrent signal, the light is detected.

[0049] Here, the electrons generated in the light absorption layer 40 travel toward the first electrode 91, which is the positive electrode, and reach the multiplication layer 20 through the first electric field control layer 31. As described above, the multiplication layer 20 of the present embodiment is a superlattice layer in which a first element layer 21 composed of Al u Ga 1-u As 1-x Sb x (u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less) and a second element layer 22 composed of In y Ga 1-y As (y is 0.3 or more and 1 or less) are alternately laminated. In this superlattice layer, Al u Ga 1-u As 1-x Sb x constituting the first element layer 21 and In y Ga 1-yBetween As, the difference ΔEv in the energy levels between valence bands is small with respect to the difference ΔEc in the energy levels between conduction bands. Therefore, the ionization rate ratio, which is the value of ΔEv / ΔEc, is small. In such a superlattice layer, when carriers fall from the first element layer 21 (barrier layer) to the second element layer (well layer) 22, the ionization coefficient of electrons becomes larger than that of holes. As a result, the number of electrons in the multiplication layer 20 increases significantly compared to holes. As a result, even if the number of electron-hole pairs generated in the light absorption layer 40 is small, the photocurrent signal can be easily detected. Thus, the avalanche photodiode 100 of the present embodiment is a light receiving element having high sensitivity. Further, the semiconductor laminate 1 of the present embodiment is a semiconductor laminate suitable for manufacturing the avalanche photodiode 100 and is a semiconductor laminate capable of obtaining a light receiving element having high sensitivity.

[0050] In the present embodiment, the ionization rate ratio in the multiplication layer 20 can be less than 0.05. Further, in the semiconductor laminate 1 and the avalanche photodiode 100 of the present embodiment, the presence of the first electric field control layer 31 is not essential, but by adopting this, it becomes easy to stably apply a strong electric field to the multiplication layer.

[0051] <Modification Example 1> Next, Modification Example 1 of Embodiment 4 will be described. Referring to FIGS. 4 and 1, the semiconductor laminate 1 of Modification Example 1 further includes a second electric field control layer 32 in addition to the structure of the semiconductor laminate 1 of Embodiment 4 above, in the same manner as in the case of Embodiment 2 above. Further, the avalanche photodiode 100 of Modification Example 1 further includes a second electric field control layer 32 in addition to the structure of the avalanche photodiode 100 of Embodiment 4 above, in the same manner as in the case of Embodiment 2 above.

[0052] The second electric field control layer 32 is composed of a III-V compound semiconductor. As the III-V compound semiconductor constituting the second electric field control layer 32, for example, AlGaAsSb can be adopted. Specifically, for example, AlGaAsSb (n-AlGaAsSb) having an n-type conductivity type is adopted as the compound semiconductor constituting the second electric field control layer 32. Regarding the thickness of the second electric field control layer 32 and the concentration of impurities that generate majority carriers, the same values as those in the case of the second embodiment can be adopted.

[0053] In this modification, in addition to the first electric field control layer 31 described in the fourth embodiment, a second electric field control layer 32 is adopted. Thereby, it becomes even easier to stably apply a strong electric field to the multiplication layer 20.

[0054] <Modification 2> Next, a second modification of the fourth embodiment will be described. Referring to FIGS. 5 and 4, the semiconductor laminate 1 of the second modification further includes a composition gradient layer 60 in addition to the structure of the semiconductor laminate 1 of the first modification, in the same manner as in the case of the third embodiment. Further, the avalanche photodiode 100 of the second modification further includes a composition gradient layer 60 in addition to the structure of the avalanche photodiode 100 of the first modification, in the same manner as in the case of the third embodiment.

[0055] The compositional gradient layer 60 is composed of a group III-V compound semiconductor. The energy level of the band edge of the compositional gradient layer 60 has a value between the energy level of the band edge of the first electric field control layer 31 and the energy level of the band edge of the light absorption layer 40. As the group III-V compound semiconductor constituting the compositional gradient layer 60, for example, AlGaAsSb can be adopted. The ratio of the contents of Al and Ga in the AlGaAsSb constituting the compositional gradient layer 60 is set so that the energy level of the band edge in the compositional gradient layer 60 becomes a value between the energy level of the band edge of the first electric field control layer 31 and the energy level of the band edge of the light absorption layer 40. The composition of the AlGaAsSb constituting the compositional gradient layer 60 may be constant in the compositional gradient layer 60. However, the energy level of the band edge of the compositional gradient layer 60 may change stepwise or continuously so as to approach the energy level of the band edge of the light absorption layer 40 as it approaches the second main surface 60B from the first main surface 60A.

[0056] In this modification, the compositional gradient layer 60 is adopted. As a result, the movement of carriers between the first electric field control layer 31 and the light absorption layer 40 is facilitated. As a result, the semiconductor laminate 1 and the avalanche photodiode 100 of this modification are a semiconductor laminate and an avalanche photodiode capable of improving the operating speed of the avalanche photodiode.

[0057] (Embodiment 5) Next, Embodiment 5, which is still another embodiment of the semiconductor laminate and the avalanche photodiode of the present disclosure, will be described. Referring to FIGS. 1 to 3, the semiconductor laminate 1 and the avalanche photodiode 100 in Embodiment 5 have the same laminated structure as the semiconductor laminate 1 and the avalanche photodiode 100 in Embodiment 1, while being different from the case of Embodiment 1 in terms of the materials constituting the multiplication layer 20 and the first electric field control layer 31 and the conductivity type of each layer.

[0058] Specifically, referring to FIG. 2, the first element layer 21 of Embodiment 5 is Alu Ga 1-u As 1-x Sb x It is composed of. The second element layer 22 is composed of GaAs 1-z Sb z Here, u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, and z is 0.3 or more and 1 or less. The bottom layer and the top layer of the multiplication layer 20 are both made of Al u Ga 1-u As 1-x Sb x Moreover, referring to FIGS. 1 and 3, as the III-V compound semiconductor constituting the first electric field control layer 31 of Embodiment 5, for example, AlGaAsSb can be adopted. Further, unlike the case of Embodiment 1, while the conductivity type of the buffer layer 12 is set to n-type, the conductivity types of the first electric field control layer 31, the cap layer 51, and the contact layer 52 are set to p-type. Regarding the thickness of each layer and the concentration of impurities that generate majority carriers, the same values as in the case of Embodiment 1 can be adopted.

[0059] Next, the operation of the avalanche photodiode 100 of the present embodiment will be described. During operation, a reverse bias is applied to the avalanche photodiode 100. Specifically, in the present embodiment, a voltage is applied such that the first electrode 91 is the positive electrode and the second electrode 92 is the negative electrode. That is, a voltage opposite to that in the case of Embodiment 1 is applied to the avalanche photodiode 100. When light is incident on the avalanche photodiode 100, the light is absorbed in the light absorption layer 40, and a pair of electrons and holes is generated. The generated electrons and holes are taken out of the avalanche photodiode 100 as a photocurrent signal, whereby the light is detected.

[0060] Here, the electrons generated in the light absorption layer 40 travel toward the first electrode 91, which is the positive electrode, and reach the multiplication layer 20 through the first electric field control layer 31. As described above, the multiplication layer 20 of the present embodiment is made of Al u Ga 1-u As 1-x Sb xThe first element layer 21 composed of (u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less) and GaAs 1-z Sb z The superlattice layer in which the second element layer 22 composed of (z is 0.3 or more and 1 or less) is alternately laminated. In this superlattice layer, Al that constitutes the first element layer 21 u Ga 1-u As 1-x Sb x and GaAs that constitutes the second element layer 22 1-z Sb z There is a small difference ΔEv in the energy level between valence bands with respect to the difference ΔEc in the energy level between conduction bands. Therefore, the ionization rate ratio, which is the value of ΔEv / ΔEc, is small. In such a superlattice layer, when carriers fall from the first element layer 21 (barrier layer) to the second element layer (well layer) 22, the ionization coefficient of electrons becomes larger than that of holes. As a result, the number of electrons in the multiplication layer 20 increases significantly compared to holes. As a result, even if the number of pairs of electrons and holes generated in the light absorption layer 40 is small, the photocurrent signal can be easily detected. Thus, the avalanche photodiode 100 of the present embodiment is a light receiving element having high sensitivity. Further, the semiconductor laminate 1 of the present embodiment is a semiconductor laminate suitable for manufacturing the avalanche photodiode 100, and is a semiconductor laminate capable of obtaining a light receiving element having high sensitivity.

[0061] In the present embodiment, the ionization rate ratio in the multiplication layer 20 can be less than 0.05. Further, in the semiconductor laminate 1 and the avalanche photodiode 100 of the present embodiment, the presence of the first electric field control layer 31 is not essential, but by adopting this, it becomes easy to stably apply a strong electric field to the multiplication layer.

[0062] <Modification 1> Next, a modification example 1 of Embodiment 5 will be described. Referring to FIGS. 4 and 1, in addition to the structure of the semiconductor laminate 1 of Embodiment 5, the semiconductor laminate 1 of Modification Example 1 further includes a second electric field control layer 32, similar to the case of Embodiment 2. Further, the avalanche photodiode 100 of Modification Example 1 further includes a second electric field control layer 32 in addition to the structure of the avalanche photodiode 100 of Embodiment 5, similar to the case of Embodiment 2.

[0063] The second electric field control layer 32 is composed of a III-V compound semiconductor. As the III-V compound semiconductor constituting the second electric field control layer 32, for example, AlGaAsSb can be adopted. Specifically, for example, AlGaAsSb (n-AlGaAsSb) having an n-type conductivity type is adopted as the compound semiconductor constituting the second electric field control layer 32. Regarding the thickness of the second electric field control layer 32 and the concentration of impurities that generate majority carriers, the same values as those in the case of Embodiment 2 can be adopted.

[0064] In this modification example, in addition to the first electric field control layer 31 described in Embodiment 5, a second electric field control layer 32 is adopted. As a result, it becomes even easier to stably apply a strong electric field to the multiplication layer 20.

[0065] <Modification Example 2> Next, a modification example 2 of Embodiment 5 will be described. Referring to FIGS. 5 and 4, in addition to the structure of the semiconductor laminate 1 of Modification Example 1, the semiconductor laminate 1 of Modification Example 2 further includes a composition gradient layer 60, similar to the case of Embodiment 3. Further, the avalanche photodiode 100 of Modification Example 2 further includes a composition gradient layer 60 in addition to the structure of the avalanche photodiode 100 of Modification Example 1, similar to the case of Embodiment 3.

[0066] The composition gradient layer 60 is composed of a group III-V compound semiconductor. The energy level of the band edge of the composition gradient layer 60 has a value between the energy level of the band edge of the first field control layer 31 and the energy level of the band edge of the light absorption layer 40. As the group III-V compound semiconductor constituting the composition gradient layer 60, for example, AlGaAsSb can be adopted. The ratio of the contents of Al and Ga in the AlGaAsSb constituting the composition gradient layer 60 is set so that the energy level of the band edge in the composition gradient layer 60 becomes a value between the energy level of the band edge of the first field control layer 31 and the energy level of the band edge of the light absorption layer 40. The composition of the AlGaAsSb constituting the composition gradient layer 60 may be constant in the composition gradient layer 60, but the energy level of the band edge of the composition gradient layer 60 may change stepwise or continuously so as to approach the energy level of the band edge of the light absorption layer 40 as it approaches the second main surface 60B from the first main surface 60A.

[0067] In this modification, the composition gradient layer 60 is adopted. As a result, the movement of carriers between the first field control layer 31 and the light absorption layer 40 is facilitated. As a result, the semiconductor laminate 1 and the avalanche photodiode 100 of this modification are a semiconductor laminate and an avalanche photodiode capable of improving the operating speed of the avalanche photodiode.

[0068] It should be understood that the embodiments disclosed this time are illustrative in all respects and not restrictive in any way. The scope of the present invention is defined not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Industrial Applicability

[0069] The semiconductor laminate and the light receiving element of the present disclosure can be particularly advantageously applied to a light receiving element that requires high sensitivity and a semiconductor laminate used in the manufacture of a light receiving element.

Explanation of Reference Numerals

[0070] 1 Semiconductor laminate 11 Substrate 11A First main surface 11B Second main surface 12 Buffer layer 12A First main surface 12B Second main surface 20 Multiplication layer 20A First main surface 20B Second main surface 21 First element layer 22 Second element layer 31 First electric field control layer 31A First main surface 31B Second main surface 32 Second electric field control layer 32A First main surface 32B Second main surface 40 Light absorption layer 40A First main surface 40B Second main surface 50 Second conductivity type layer 51 Cap layer 51A First main surface 51B Second main surface 52 Contact layer 52A First main surface 52B Second main surface 60 Composition gradient layer 60A First main surface 60B Second main surface 80 Passivation film 91 First electrode 92 Second electrode 99 Trench 99A Side wall 99B Bottom wall 100 Avalanche photodiode

Claims

1. a first conductivity type layer composed of a group III-V compound semiconductor and having a first conductivity type; a multiplication layer composed of a group III-V compound semiconductor; an optical absorption layer composed of a group III-V compound semiconductor; a second conductivity type layer composed of a group III-V compound semiconductor and having a second conductivity type different from the first conductivity type, and comprising: the first conductivity type layer, the multiplication layer, the optical absorption layer, and the second conductivity type layer are laminated in this order; the multiplication layer is a superlattice layer including a first element layer and a second element layer disposed in contact with the first element layer; The first element layer is an InP layer, and the second element layer is a GaAs １－ｘ Sb ｘ layer, and x is 0.3 or more and 1 or less, or or The first element layer is Al ｕ Ga １－ｕ As １－ｘ Sb ｘ layer, and the second element layer is In ｙ Ga １－ｙ As layer, where u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, y is 0.3 or more and 1 or less, or or The first element layer is Al ｕ Ga １－ｕ As １－ｘ Sb ｘ layer, and the second element layer is a GaAs １－ｚ Sb ｚ layer, where u is 0.2 or more and 1 or less, x is 0.3 or more and 1 or less, and z is 0.3 or more and 1 or less, a semiconductor laminate.

2. The semiconductor laminate according to claim 1, wherein main surfaces on the first conductivity layer side and the optical absorption layer side of the multiplication layer are both composed of the first element layer.

3. The first element layer is an InP layer, and the second element layer is a GaAs １－ｘ Sb ｘ layer, and x is 0.3 or more and 1 or less. The semiconductor laminate according to claim 2.

4. The semiconductor laminate according to claim 1, further comprising a first electric field control layer composed of a group III-V compound semiconductor, disposed between the multiplication layer and the optical absorption layer, and having a second conductivity type.

5. The semiconductor laminate according to claim 4, further comprising a second electric field control layer composed of a group III-V compound semiconductor, disposed between the multiplication layer and the first conductivity type layer, and having a first conductivity type.

6. The semiconductor laminate according to claim 4, further comprising a composition gradient layer composed of a group III-V compound semiconductor, disposed between the first electric field control layer and the optical absorption layer, and having an energy level of a band edge between those of the first electric field control layer and the optical absorption layer.

7. The composition gradient layer includes a first main surface that is a main surface on the first electric field control layer side, and a second main surface that is a main surface on the optical absorption layer side, and the composition of the composition gradient layer changes stepwise such that the energy level of the band edge of the composition gradient layer approaches the energy level of the band edge of the optical absorption layer as it approaches the second main surface from the first main surface. The semiconductor laminate according to claim 6.

8. The composition gradient layer includes a first main surface that is a main surface on the first electric field control layer side, and a second main surface that is a main surface on the optical absorption layer side, and the composition of the composition gradient layer changes continuously such that the energy level of the band edge of the composition gradient layer approaches the energy level of the band edge of the optical absorption layer as it approaches the second main surface from the first main surface. The semiconductor laminate according to claim 6.

9. A semiconductor laminate according to any one of claims 1 to 8, and an electrode disposed on the semiconductor laminate, a light receiving element comprising.

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