Vertical nonvolatile memory device including memory cell string

Abstract

To provide a vertical nonvolatile memory device including a memory cell string.SOLUTION: There is disclosed a vertical nonvolatile memory device including a memory cell string. The vertical nonvolatile memory device includes a plurality of memory cell strings arranged two-dimensionally. Each of the memory cell strings includes: a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers alternately arranged in a first direction and each extending in a second direction crossing the first direction; a gate insulating film extending in the first direction and disposed between the channel layer and the plurality of gate electrodes; and a resistance change layer extending in the first direction along a surface of the channel layer. The resistance change layer may include a material capable of switching between a first state (LVS) having a first threshold voltage and a second state (HVS) having a second threshold voltage higher than the first threshold voltage.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a vertical non-volatile memory device including a memory cell string.

Background Art

[0002] Non-volatile memory devices such as semiconductor memory devices include a plurality of memory cells that can maintain information even when the power is turned off and can use the stored information again when power is supplied. Non-volatile memory devices may be used in mobile phones, digital cameras, personal digital assistants (PDAs), mobile computer devices, stationary computer devices, and other devices.

[0003] As an example of a non-volatile memory device, there is a vertical NAND (Not AND) (VNAND). VNAND is a memory device in which a large number of memory cells are stacked vertically to increase the integration density. Various techniques have been proposed to increase the number of VNAND stacks and implement high capacity in the same area. For example, various techniques such as a method using charge trapping, a method using a phase change material, a method using a resistive change material, and a method using a ferroelectric have been proposed to implement VNAND. In addition, various materials for improving the performance of non-volatile memory devices, such as improving data reliability, improving drive speed, reducing power consumption, and increasing integration density, have been studied.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a vertical non-volatile memory device including a memory cell string.

Means for Solving the Problems

[0005] A vertical non-volatile memory device according to an embodiment includes a plurality of memory cell strings arranged two-dimensionally. Each memory cell string includes a channel layer extending along a first direction, a plurality of gate electrodes respectively extending along a second direction intersecting the first direction and alternately arranged with each other along the first direction, and a plurality of spacers, a gate insulating film extending along the first direction and disposed between the channel layer and the plurality of gate electrodes, and a resistance change layer extending along the first direction along the surface of the channel layer. The resistance change layer may include a material that is switched between a first state having a first threshold voltage and a second state having a second threshold voltage higher than the first threshold voltage.

[0006] When the resistance change layer is in the first state, if a voltage lower than the first threshold voltage is applied to the resistance change layer, no current flows through the resistance change layer, and if a voltage higher than the first threshold voltage is applied to the resistance change layer, current may flow.

[0007] When the resistance change layer is in the second state, if a voltage lower than the second threshold voltage is applied to the resistance change layer, no current flows through the resistance change layer, and if a voltage higher than the second threshold voltage is applied to the resistance change layer, current may flow.

[0008] When the resistance change layer is in the first state, if a negative bias voltage is applied to the resistance change layer, the resistance change layer may be converted to the second state.

[0009] When the resistance change layer is in the second state, if a positive bias voltage higher than the second threshold voltage is applied to the resistance change layer, the resistance change layer may be converted to the first state.

[0010] In a read operation, a read voltage between the first threshold voltage and the second threshold voltage may be applied to the resistance change layer.

[0011] The resistance change layer may have a single-layer structure including at least one amorphous multi-component chalcogenide material such as GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeSbIn, GeAsSeTe, GeAsSeTeIn, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeSbSeIn, GeSbSeN, GeSbSeNIn, CTe, GeCTe, NGeCTe, BTe, SiTe, GeAsTe, GeSbSe, GeSbSeN.

[0012] For example, the ratio of germanium (Ge) in the resistance change layer may be 10 at% or more and 30 at% or less.

[0013] For example, the ratio of arsenic (As) in the resistance change layer may be 10 at% or more and 50 at% or less.

[0014] For example, the ratio of selenium (Se) in the resistance change layer may be 40 at% or more and 80 at% or less.

[0015] For example, the ratio of indium (In) in the resistance change layer may be 1 at% or more and 10 at% or less.

[0016] The resistance change layer may include a plurality of drive regions provided alternately along a first direction and a plurality of initial state regions.

[0017] Each drive region may be provided opposite to a corresponding gate electrode among a plurality of gate electrodes in a second direction, and each initial state region may be provided opposite to a corresponding insulating spacer among a plurality of insulating spacers in the second direction.

[0018] When a voltage equal to or higher than a first threshold voltage is applied, the resistance of the initial state region may be higher than that of the drive region.

[0019] Each drive region may include a first region and a second region having different active trap densities from each other.

[0020] In the first state, the density of active traps in the second region may be higher than the density of active traps in the first region, and in the second state, the density of active traps in the second region may be lower than the density of active traps in the first region.

[0021] The thickness of the second region along the first direction may be thinner than the thickness of the first region along the first direction.

[0022] The thickness of the first region along the first direction may be at least twice and at most ten times the thickness of the second region along the first direction.

[0023] During switching between the first state and the second state, the elemental composition distribution may be kept constant in the first region and the second region.

[0024] For example, the thickness of the resistance change layer in the second direction may be from 5 nm to 100 nm.

[0025] Each memory cell string further includes a barrier layer extending along the first direction between the channel layer and the resistance change layer. The barrier layer is a carbon-based or nitrogen-based insulator, and the thickness of the barrier layer in the second direction may be greater than 0 nm and at most 10 nm.

[0026] An electronic device according to another embodiment includes a processing circuit and a vertical non-volatile memory device including a plurality of memory cell strings arranged in a two-dimensional array. Each memory cell string includes a channel layer extending along the first direction, a plurality of gate electrodes respectively extending along a second direction intersecting the first direction and alternately arranged with each other along the first direction, and a plurality of spacers, a gate insulating film extending along the first direction and disposed between the channel layer and the plurality of gate electrodes, and a resistance change layer extending along the first direction along the surface of the channel layer. The resistance change layer may include a material that switches between a first state having a first threshold voltage and a second state having a second threshold voltage higher than the first threshold voltage.

Advantages of the Invention

[0027] The vertical non-volatile memory device according to an embodiment of the present application uses a substance having an ovonic threshold switching characteristic in which a threshold voltage is shifted depending on the polarity and intensity of an applied voltage as a resistance change layer. The vertical non-volatile memory device according to an embodiment of the present application has the characteristics of a voltage-driven element and can improve the speed compared to the existing CTF (charge trap flash)-VNAND while operating similarly to the existing CTF-VNAND. In addition, the vertical non-volatile memory device according to an embodiment of the present application has almost no interference between adjacent cells and can have high reliability. Also, the interval between cells can be reduced, and a vertical non-volatile memory device can be manufactured with a high integration degree. Therefore, the capacity of the vertical non-volatile memory device can be improved.

Brief Description of the Drawings

[0028]

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DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, with reference to the accompanying drawings, a vertical non-volatile memory device including a memory cell string will be described in detail. In the following drawings, the same reference numerals refer to the same components, and in the drawings, the size of each component may be exaggerated for clarity and convenience of explanation. Also, the embodiments described below are merely exemplary, and various modifications are possible from such embodiments.

[0030] Hereinafter, when described as "upper" or "above", it may include not only what is in direct contact and directly above but also what is above without contact. Singular expressions include plural expressions unless otherwise specified in the context. Also, when a part "includes" a certain component, it means that it does not exclude other components and may further include other components unless there is a special contrary description.

[0031] The use of the term "the foregoing" and similar directional terms may apply to both the singular and plural. For steps constituting a method, if the order is not explicitly stated or is stated to be contrary, such steps are performed in an appropriate order and are not necessarily limited to the order in which they are described.

[0032] Also, terms such as "… part" and "module" described in the specification mean a unit that processes at least one function or operation, which may be embodied by hardware or software, or by a combination of hardware and software.

[0033] The line connections or connection members between the components illustrated in the drawings exemplarily show functional connections and / or physical or circuit connections, and in an actual device, they may be alternative and shown as various functional, physical, or circuit connections that are added or replaceable.

[0034] All examples or the use of exemplary terms are merely for explaining the technical idea in detail, and as long as they are not limited by the claims, the scope is not limited by such examples or exemplary terms.

[0035] FIG. 1 is a block diagram showing a memory system according to an embodiment. Referring to FIG. 1, a memory system 10 according to an embodiment may include a memory controller 100 and a memory device 200. The memory controller 100 performs control operations on the memory device 200. As an example, the memory controller 100 may perform program (or write), read, and erase operations on the memory device 200 by providing an address ADD and a command CMD to the memory device 200. Also, data for a program operation and read data may be transmitted and received between the memory controller 100 and the memory device 200. The memory device 200 provides a pass / fail signal to the memory controller 100 based on a read result of the read data, and the memory controller 100 may control write / read operations of the memory cell array 210 with reference to the pass / fail signal.

[0036] The memory device 200 may include a memory cell array 210 and a voltage generation unit 220. The memory cell array 210 may include a plurality of memory cells disposed in a region where a plurality of word lines and a plurality of bit lines intersect. The memory cell array 210 may include non-volatile memory cells that store data non-volatily. As the non-volatile memory cells, the memory cell array 210 may include flash memory cells such as a NAND flash memory cell array 210 or a NOR flash memory cell array 210. In the following, it is assumed that the memory cell array 210 includes a flash memory cell array 210, and thus the memory device 200 is a non-volatile memory device, and embodiments of the present disclosure will be described in detail.

[0037] The memory controller 100 may include a write / read control unit 110, a voltage control unit 120, and a data discrimination unit 130.

[0038] The write / read control unit 110 may generate an address ADD and a command CMD for performing a program / read operation and an erase operation on the memory cell array 210. Further, the voltage control unit 120 may generate a voltage control signal for controlling at least one voltage level used within the nonvolatile memory device 200. For example, the voltage control unit 120 may generate a voltage control signal for controlling the voltage level of a word line for reading data from the memory cell array 210 or for programming data into the memory cell array 210.

[0039] The data discrimination unit 130 may perform a discrimination operation on the data read from the memory device 200. For example, the data read from the memory cell may be discriminated, and the number of on cells and / or off cells in the memory cell may be discriminated. As an example of an operation, if a program is performed on a plurality of memory cells, a predetermined read voltage may be used to discriminate the data state of the memory cells, whereby it may be discriminated whether the program has been completed normally for all cells.

[0040] As described above, the memory cell array 210 may include nonvolatile memory cells. For example, the memory cell array 210 may include flash memory cells. Further, the flash memory cells may be implemented in various forms. For example, the memory cell array 210 may include three-dimensional (or vertical) NAND (VNAND) memory cells.

[0041] FIG. 2 is a block diagram showing an example of the memory device 200 illustrated in FIG. 1. Referring to FIG. 2, the memory device 200 may further include a row decoder 230, an input / output circuit 240, and control logic 250.

[0042] The memory cell array 210 is connected to one or more string selection lines SSL, a plurality of word lines WL1 to WLm, and one or more common source lines CSLs, and may also be connected to a plurality of bit lines BL1 to BLn. The voltage generation unit 220 may generate one or more word line voltages V1 to Vi, and the word line voltages V1 to Vi may be provided to the row decoder 230. Signals for program / read / erase operations may be applied to the memory cell array 210 via the bit lines BL1 to BLn.

[0043] Also, the data to be programmed may be provided to the memory cell array 210 via the input / output circuit 240, and the read data may be provided to the outside (e.g., a memory controller) via the input / output circuit 240. The control logic 250 may provide various control signals related to the memory operation to the row decoder 230 and the voltage generation unit 220.

[0044] By the decoding operation of the row decoder 230, the word line voltages V1 to Vi may be provided to various lines SSLs, WL1 to WLm, CSLs. For example, the word line voltages V1 to Vi may include a string selection voltage, a word line voltage, and a ground selection voltage. The string selection voltage may be provided to one or more string selection lines SSLs, the word line voltage may be provided to one or more word lines WL1 to WLm, and the ground selection voltage may be provided to one or more common source lines CSLs.

[0045] FIG. 3 is a block diagram showing the memory cell array illustrated in FIG. 1. Referring to FIG. 3, the memory cell array 210 includes a plurality of memory blocks BLK1 to BLKz. Each memory block BLK has a three-dimensional structure (or a vertical structure). For example, each memory block BLK may include a structure extending along a first direction to a third direction. For example, each memory block BLK may include a plurality of memory cell strings extending along a first direction (Z direction). Also, the plurality of memory cell strings may be two-dimensionally arranged along a second direction (X direction) and a third direction (Y direction). Each memory cell string is connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL. Accordingly, each of the memory blocks BLK1 to BLKz may be connected to a plurality of bit lines BL, a plurality of string selection lines SSLs, a plurality of word lines WL, and a plurality of common source lines CSL. Such memory blocks BLK1 to BLKz will be described in more detail with reference to FIG. 4.

[0046] FIG. 4 is a drawing showing an equivalent circuit corresponding to a memory block according to an embodiment. Exemplarily, one of the memory blocks BLK1 to BLKz of the memory cell array 210 in FIG. 3 is illustrated in FIG. 4. Referring to FIGS. 3 and 4, the memory blocks BLK1 to BLKz each include a plurality of memory cell strings CS11 to CSkn. The plurality of memory cell strings CS11 to CSkn may be two-dimensionally arranged along a row direction and a column direction to form rows and columns. Each of the memory cell strings CS11 to CSkn includes a plurality of memory cells MC and a plurality of string selection transistors SST. The memory cells MC and the string selection transistors SST of each of the memory cell strings CS11 to CSkn may be stacked in a height direction.

[0047] Rows of a plurality of memory cell strings CS11 to CSkn are respectively connected to different string selection lines SSL1 to SSLk. For example, string selection transistors SST of memory cell strings CS11 to CS1n are commonly connected to string selection line SSL1. String selection transistors SST of memory cell strings CSk1 to CSkn are commonly connected to string selection line SSLk.

[0048] Also, columns of a plurality of memory cell strings CS11 to CSkn are respectively connected to different bit lines BL1 to BLn. For example, memory cells MC and string selection transistors SST of memory cell strings CS11 to CSk1 may be commonly connected to bit line BL1, and memory cells MC and string selection transistors SST of memory cell strings CS1n to CSkn may be commonly connected to bit line BLn.

[0049] Also, rows of a plurality of memory cell strings CS11 to CSkn may be respectively connected to different common source lines CSL1 to CSLk. For example, string selection transistors SST of a plurality of memory cell strings CS11 to CS1n may be commonly connected to common source line CSL1, and string selection transistors SST of a plurality of memory cell strings CSk1 to CSkn may be commonly connected to common source line CSLk.

[0050] Memory cells MC located at the same height from a substrate (or string selection transistor SST) are commonly connected to one word line WL, and memory cells MC located at different heights may be respectively connected to different word lines WL1 to WLm.

[0051] The memory blocks illustrated in FIG. 4 are exemplary. The technical idea disclosed in the present application is not limited to the memory blocks illustrated in FIG. 4. For example, the number of rows of the plurality of memory cell strings CS11 to CSkn may be increased or decreased. By changing the number of rows of the plurality of memory cell strings CS11 to CSkn, the number of string selection lines connected to the rows of the memory cell strings CS11 to CSkn and the number of memory cell strings CS11 to CSkn connected to one bit line may also be changed. By changing the number of rows of the memory cell strings CS11 to CSkn, the number of common source lines connected to the rows of the memory cell strings CS11 to CSkn may also be changed. Also, the number of columns of the memory cell strings CS11 to CSkn may be increased or decreased. By changing the number of columns of the memory cell strings CS11 to CSkn, the number of bit lines connected to the columns of the memory cell strings CS11 to CSkn and the number of memory cell strings CS11 to CSkn connected to one string selection line may also be changed.

[0052] The height of each of the memory cell strings CS11 to CSkn may be increased or decreased. For example, the number of memory cells MC stacked in each of the memory cell strings CS11 to CSkn may be increased or decreased. By changing the number of memory cells MC stacked in each of the memory cell strings CS11 to CSkn, the number of word lines WL may also be changed. For example, the number of string selection transistors provided for each of the memory cell strings CS11 to CSkn may be increased. By changing the number of string selection transistors provided for each of the memory cell strings CS11 to CSkn, the number of string selection lines or common source lines may also be changed. If the number of string selection transistors increases, the string selection transistors may be stacked in a form such as that of the memory cell MC.

[0053] Exemplarily, writing and reading may be performed in units of rows of the memory cell strings CS11 to CSkn. The common source lines CSLs may be used to select the memory cell strings CS11 to CSkn in units of rows, and the string selection lines SSLs may be used to select the memory cell strings CS11 to CSkn in units of rows. Then, in the selected rows of the memory cell strings CS11 to CSkn, writing and reading may be performed in units of pages. For example, a page may be one row of memory cells MC connected to one word line WL. In the selected rows of the memory cell strings CS11 to CSkn, the memory cells MC may be selected in units of pages by the word line WL.

[0054] Note that the memory cells MC in each of the memory cell strings CS11 to CSkn may correspond to a circuit in which a transistor and a resistor are connected in parallel. For example, FIG. 5 is a vertical cross-sectional view schematically showing the structure of each memory cell string according to an embodiment. Referring to FIG. 5, the memory cell string CS may include a plurality of insulating spacers 311 alternately stacked along the vertical direction intersecting so as to be orthogonal to the second direction (X direction), in other words, along the first direction (Z direction), and a plurality of gate electrodes 312. The plurality of insulating spacers 311 and the plurality of gate electrodes 312 may extend along the horizontal direction, in other words, the second direction. Each gate electrode 312 may be connected to the word line WL, or each gate electrode 312 may itself be the word line WL.

[0055] The insulating spacer 311 may include, but is not limited to, one of various insulating dielectric materials such as silicon oxide, aluminum oxide, and silicon nitride. The gate electrode 312 may include, for example, at least one conductive material among tungsten (W), molybdenum (Mo), ruthenium (Ru), polysilicon, TiN, and metallic two-dimensional materials, or a combination thereof. The metallic two-dimensional material may include, for example, at least one material among graphene, TaS2, TaSe2, NbS2, NbSe2, PdTe2, PtTe2, NbTe2, TiSe2, VSe2, AuSe, and MoTe2. In one embodiment, although not shown, the gate electrode 312 may include a gate layer (e.g., W, Mo, Ru, polysilicon), and a gate barrier layer (e.g., a two-dimensional material such as TiN or graphene) covering at least one of the side, lower surface, and upper surface of the gate layer.

[0056] Further, the memory cell string CS may include a channel hole penetrating through a plurality of insulating spacers 311 and a plurality of gate electrodes 312 in a first direction. A plurality of layers for forming a channel and a resistor may be disposed in the channel hole. For example, the memory cell string CS may include an insulating support 324 disposed at the center of the channel hole and extending in the first direction, a resistive change layer 323 surrounding the insulating support 324 and extending in the first direction, a channel layer 322 surrounding the resistive change layer 323 and extending in the first direction, and a gate insulating film 321 surrounding the channel layer 322 and extending in the first direction. The gate insulating film 321 may be disposed between the channel layer 322 and the plurality of gate electrodes 312, and between the channel layer 322 and the plurality of insulating spacers 311.

[0057] FIG. 6 is a horizontal cross-sectional view schematically showing the structure of a memory cell string CS according to an embodiment. Referring to FIG. 6, in order from the center, an insulating support 324, a resistive change layer 323, a channel layer 322, and a gate insulating film 321 may be arranged in a concentric form. The gate insulating film 321 may have a cylindrical form surrounding the channel layer 322, the channel layer 322 may have a cylindrical form surrounding the resistive change layer 323, and the resistive change layer 323 may have a cylindrical form surrounding the insulating support 324. Although not shown in FIG. 6, a plurality of insulating spacers 311 and a plurality of gate electrodes 312 may be alternately laminated in a first direction while surrounding the gate insulating film 321. Although not shown in FIG. 6, a barrier (see the barrier layer 325 in FIG. 16) may be arranged in a concentric form between the resistive change layer 323 and the channel layer 322.

[0058] Therefore, the gate insulating film 321 may be conformally deposited on the plurality of insulating spacers 311 and the plurality of gate electrodes 312 and extended along the first direction. The channel layer 322 may be conformally deposited along the surface of the gate insulating film 321 and extended along the vertical direction. The resistive change layer 323 may be conformally deposited along the surface of the channel layer 322 and extended along the vertical direction. The insulating support 324 may be arranged to fill the remaining space at the center of the channel hole and extended along the vertical direction.

[0059] As a result, the resistive change layer 323 faces the plurality of insulating spacers 311 and the plurality of gate electrodes 312 and has a form extended in the first direction, the channel layer 322 has a form extended in the first direction between the resistive change layer 323 and the plurality of gate electrodes 312, and the gate insulating film 321 has a form extended in the first direction between the channel layer 322 and the plurality of gate electrodes 312.

[0060] Although not shown, a drain may be disposed on the uppermost surface of the memory cell string CS so as to cover at least the channel layer 322. The drain may include a doped silicon material. A bit line may be connected to such a drain.

[0061] The channel layer 322 may include, for example, polysilicon (poly-Si), but is not limited thereto, and may include various other conductive semiconductor materials. For example, the channel layer 322 may include a two-dimensional semiconductor material having electrically p-type characteristics. The channel layer 322 may include, for example, at least one two-dimensional semiconductor material among tellurene, black phosphorus, and WSe2. Also, the gate insulating film 321 and the insulating support 324 may include, for example, at least one material among silicon oxide (SiO), aluminum oxide (Al2O3), magnesium oxide (MgO), aluminum nitride (AlN), hafnium oxide (HfO), and gallium nitride (GaN), but are not necessarily limited thereto.

[0062] Referring again to FIG. 5, as shown in the dotted box, any one of the gate electrodes 312, and a portion of the gate insulating film 321, a portion of the channel layer 322, and a portion of the resistance change layer 323 adjacent to the one gate electrode 312 in the horizontal direction, in other words, the second direction, are components of one memory cell MC. In particular, one gate electrode 312, a portion of the gate insulating film 321 adjacent to it in the horizontal direction, and a portion of the channel layer 322 form a transistor, and a portion of the resistance change layer 323 may form a resistor. Therefore, each memory cell MC may correspond to a circuit in which a transistor and a resistor are connected in parallel. Such a plurality of memory cells MC may be arranged in a vertical stacked structure to form each memory cell string CS. The thickness of one memory cell MC is determined by the height t1 of one gate electrode 312 in the first direction, and the interval between two adjacent memory cells MC in the first direction may be determined by the height t2 of one insulating spacer 311 in the first direction. By reducing the height t1 of one gate electrode 312 in the first direction and the height t2 of one insulating spacer 311 in the first direction, the integration degree of the memory cell MC can be increased. For example, the height t1 of one gate electrode 312 in the first direction may be about 20 nm or less, and the height t2 of one insulating spacer 311 in the first direction may be about 20 nm or less.

[0063] Note that the thickness d1 of the gate insulating film 321 in the second direction may be, for example, about 5 nm to about 50 nm. The thickness d2 of the channel layer 322 in the second direction may be, for example, about 2.5 nm to 20 nm. Also, the thickness d3 of the resistance change layer 323 in the second direction may be, for example, about 5 nm to about 100 nm, or about 5 nm to about 40 nm.

[0064] According to one embodiment, the resistance change layer 323 may include a material having an ovonic threshold switching (OTS, optical tracking system) characteristic in which a high resistance state is obtained when a voltage lower than the threshold voltage is applied, and a low resistance state is obtained when a voltage higher than the threshold voltage is applied. Further, the resistance change layer 323 may have a characteristic in which the threshold voltage is shifted according to the polarity and intensity of the applied bias voltage. For example, the resistance change layer 323 may be switched between a first state (LVS, low Vth state) having a relatively low first threshold voltage and a second state (HVS, high Vth state) having a second threshold voltage higher than the first threshold voltage. For this purpose, the resistance change layer 323 may include an amorphous multi-component chalcogenide material. The resistance change layer 323 may have, for example, a single layer structure including at least one material among GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeSbIn, GeAsSeTe, GeAsSeTeIn, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeSbSeIn, GeSbSeN, GeSbSeNIn, CTe, GeCTe, NGeCTe, BTe, SiTe, GeAsTe, GeSbSe, and GeSbSeN.

[0065] When the resistance change layer 323 contains germanium (Ge), the ratio of germanium (Ge) in the resistance change layer 323 may be about 10 at% or more and about 30 at% or less. When the resistance change layer 323 contains arsenic (As), the ratio of arsenic (As) in the resistance change layer 323 may be about 10 at% or more and about 50 at% or less. When the resistance change layer 323 contains selenium (Se), the ratio of selenium (Se) in the resistance change layer 323 may be about 40 at% or more and about 80 at% or less. Further, when the resistance change layer 323 contains indium (In), the ratio of indium (In) in the resistance change layer 323 may be about 1 at% or more and about 10 at% or less, about 1 at% or more and about 8 at% or less, or about 3 at% or more and about 5 at% or less. The ratio of a specific element (e.g., Ge, As, Se) in the resistance change layer 323 may mean the ratio of the specific element to all the elements in the resistance change layer 323. In other words, in the case of GeAsSe, the ratio of Ge may indicate the amount of Ge compared to the total amount of Ge, As, and Se in the compound.

[0066] FIG. 7 is a graph exemplarily showing the voltage-current characteristics of the resistive change layer 323 of the memory cell string CS according to one embodiment. Referring to FIG. 7, the resistive change layer 323 may have either one of a first state (LVS) with a relatively low threshold voltage and a second state (HVS) with a relatively high threshold voltage. For example, in the first state (LVS), the first threshold voltage of the resistive change layer 323 is the first voltage V1, and in the second state (HVS), the second threshold voltage of the resistive change layer 323 may be a second voltage V2 higher than the first voltage V1. When the resistive change layer 323 is in the first state (LVS), if a voltage lower than the first voltage V1 is applied to the resistive change layer 323, almost no current flows through the resistive change layer 323, and if a voltage equal to or higher than the first voltage V1 is applied to the resistive change layer 323, the resistive change layer 323 is turned on and current flows through the resistive change layer 323. Also, when the resistive change layer 323 is in the second state (HVS), if a voltage lower than the second voltage V2 which is the second threshold voltage is applied to the resistive change layer 323, almost no current flows through the resistive change layer 323, and if a voltage equal to or higher than the second voltage V2 is applied to the resistive change layer 323, the resistive change layer 323 is turned on and current flows through the resistive change layer 323.

[0067] Therefore, a voltage between the first voltage V1 and the second voltage V2 may be selected as the read voltage VR. When the resistive change layer 323 is in the first state (LVS), if the read voltage VR is applied to the resistive change layer 323, current flows through the resistive change layer 323, and at this time, the data value stored in the resistive change layer 323 may be defined as "1". When the resistive change layer 323 is in the second state (HVS), if the read voltage VR is applied to the resistive change layer 323, almost no current flows through the resistive change layer 323, and at this time, the data value stored in the resistive change layer 323 may be defined as "0". In other words, by measuring the current flowing through the resistive change layer 323 while applying the read voltage VR to the resistive change layer 323, the data value stored in the resistive change layer 323 can be read.

[0068] Note that when the resistance change layer 323 is in the first state (LVS), if a negative (-) bias voltage is applied to the resistance change layer 323, the threshold voltage of the resistance change layer 323 may increase, and the resistance change layer 323 may be converted to the second state (HVS). For example, if a negative third voltage V3 is applied to the resistance change layer 323, the resistance change layer 323 may be converted to the second state (HVS). Such an operation may be referred to as a "reset" operation. Also, when the resistance change layer 323 is in the second state (HVS), if a positive (+) bias voltage higher than the second voltage V2 is applied to the resistance change layer 323, the resistance change layer 323 may be converted to the first state (LVS) while the threshold voltage of the resistance change layer 323 decreases. Such an operation may be referred to as a "set" operation.

[0069] FIG. 8A is a graph exemplarily showing bias voltages for a set operation and a read operation in the resistance change layer 323 of a memory cell string CS according to an embodiment. Referring to FIG. 8A, in the set operation, a positive bias voltage equal to or higher than the second voltage V2 may be applied to the resistance change layer 323. Thereby, the threshold voltage of the resistance change layer 323 may be shifted to the first voltage V1. Thereafter, in the read operation, a positive read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the resistance change layer 323. When the read voltage VR is applied, the resistance change layer 323 may be turned on.

[0070] FIG. 8B is a graph exemplarily showing bias voltages for a reset operation and a read operation in the resistance change layer 323 of the memory cell string CS according to an embodiment. Referring to FIG. 8B, in the reset operation, a negative bias voltage, i.e., a third voltage V3, may be applied to the resistance change layer 323. The absolute value of the third voltage V3 may be substantially the same as the second voltage V2, or may be slightly larger or smaller than this. Thereby, the threshold voltage of the resistance change layer 323 may be shifted to the second voltage V2, which is higher than the first voltage V1. Thereafter, in the read operation, a positive read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the resistance change layer 323. When the read voltage VR is applied, the resistance change layer 323 may be turned off.

[0071] As described above, the resistance change layer 323 including the amorphous multi-component chalcogenide material having the aforementioned composition may have ovonic threshold switching characteristics and, at the same time, may have the characteristics of a memory in which the threshold voltage changes. In particular, the threshold voltage of the resistance change layer 323 may be shifted depending on the polarity of the bias voltage applied to the resistance change layer 323. In this regard, the resistance change layer 323 according to an embodiment may be regarded as having polarity-dependent threshold voltage shift characteristics.

[0072] Such polarity-dependent threshold voltage shift behavior may be explained through changes in trap states within the material of the resistive change layer 323. FIGS. 9A through 11C are for conceptually explaining changes in trap states within the material of the resistive change layer 323. In particular, FIG. 9A is a conceptual diagram exemplarily showing trap states within the resistive change layer material 23 in the initial (pristine) state of the resistive change layer material, and FIG. 9B schematically shows an energy band diagram for the resistive change layer material 23 in the initial state. FIG. 10A is a conceptual diagram exemplarily showing trap states within the resistive change layer material 23 after applying a positive (+) bias voltage for first-firing to the resistive change layer material 23 in the initial state, FIG. 10B schematically shows an energy band diagram for the resistive change layer material 23 near the first end after first-firing, and FIG. 10C schematically shows an energy band diagram for the resistive change layer material 23 near the second end after first-firing. FIG. 11A is a conceptual diagram exemplarily showing trap states within the resistive change layer material 23 after applying a negative (-) bias voltage to the resistively changed layer material 23 that has been first-fired, FIG. 11B schematically shows an energy band diagram for the resistive change layer material 23 near the first end after applying the negative bias voltage, and FIG. 11C schematically shows an energy band diagram for the resistive change layer material 23 near the second end after applying the negative bias voltage.

[0073] Referring to FIG. 9A, in the initial state immediately after fabrication, mainly de-activated traps exist within the resistive change layer material 23. For the sake of convenience of explanation, in FIG. 9A, the de-activated traps are indicated by dotted circles. For example, the de-activated traps may be mainly formed by covalent bonds (Se-Se) between adjacent selenium (Se) atoms within the resistive change layer material 23.

[0074] Also, in the graph of FIG. 9B, "CB" represents the conduction band, "VB" represents the valence band, and the horizontal axis represents the density of state. Referring to FIG. 9B, the energy band formed by the non-active traps is indicated by the thin dashed line. The energy band indicated by the solid line in FIG. 9B is formed by materials other than selenium (Se) in the resistance change layer material 23. The energy band formed by the non-active traps may be distributed around the Fermi level Ef.

[0075] To initially drive the resistance change layer material 23 in the initial state, a positive (+) bias voltage may be applied. For example, a bias voltage may be applied to the resistance change layer material 23 such that a current flows from the first end E1 to the second end E2 of the resistance change layer material 23. Referring to FIG. 10A, due to the initial drive, some of the non-active traps may be activated, and activated traps may be formed. The activated traps may be mainly formed by selenium ions (Se 2- ) generated while the covalent bonds between selenium (Se) atoms are broken. Such activated traps form a percolation path in the resistance change layer material 23, and the formation of the percolation path may lower the threshold voltage of the resistance change layer material 23.

[0076] In FIG. 10A, the active traps are indicated by the circles with a hatched pattern and the circles with a mesh pattern. As shown in FIG. 10A, in the resistive change layer material 23, the amount of active traps may increase from the second end portion E2 toward the first end portion E1. In particular, a large amount of active traps may be generated in the region of the resistive change layer material 23 near the first end portion E1. Therefore, after the initial drive, the resistive change layer material 23 may include a first region 23a where the density of active traps is relatively low and a second region 23b where the density of active traps is relatively high. The length of the second region 23b may be shorter than the length of the first region 23a. For example, the length of the first region 23a may be two times or more and ten times or less the length of the second region 23b.

[0077] The first region 23a is a region adjacent to the second end portion E2 to which a negative (-) voltage is applied during the initial drive. The active traps in the first region 23a are indicated by the circles with a hatched pattern. In the first region 23a, the density of the active traps may increase little by little as it approaches the boundary with the second region 23b, but the amount of increase may be relatively small. The second region 23b is a region adjacent to the first end portion E1 to which a positive (+) voltage is applied during the initial drive. Also, the second region 23b may be in direct contact with the first region 23a and may be disposed between the first region 23a and the first end portion E1. The active traps in the second region 23b are indicated by the circles with a mesh pattern. In the second region 23b, the density of the active traps may increase relatively largely as it approaches the first end portion E1. Therefore, the density of the active traps in the second region 23b may be higher than the density of the active traps in the first region 23a. In this case, the resistive change layer material 23 is in a first state (LVS) where the threshold voltage is relatively low. In other words, when the resistive change layer material 23 is in the first state (LVS), the density of the active traps in the second region 23b is higher than the density of the active traps in the first region 23a.

[0078] Referring to FIG. 10B, within the first region 23a, the energy band formed by the active traps is shown by the dotted line. The energy band formed by the active traps may be located at an energy level slightly lower than the Fermi level Ef. Also, referring to FIG. 10C, within the second region 23b, the energy band formed by the active traps is shown by the thick dashed line. Comparing FIGS. 10B and 10C, it can be seen that the energy band formed by the active traps in the second region 23b has a slightly wider energy distribution than the energy band formed by the active traps in the first region 23a. Also, in the second region 23b, it can be seen that the state density of the active traps is higher than the state density of the active traps in the first region 23a. Therefore, in the second region 23b, it can be seen that the amount of active traps is larger than the amount of active traps in the first region 23a.

[0079] Such a high density of active traps in the vicinity of the first end E1 after the first drive may have a great influence on the threshold voltage shift behavior of the resistive change layer material 23. For example, depending on the polarity of the bias voltage, the density of active traps in the second region 23b can be changed relatively easily, whereby the threshold voltage of the resistive change layer material 23 may be shifted relatively easily.

[0080] If a negative (-) bias voltage is applied to the initially driven resistive change layer material 23, that is, if a bias voltage is applied in the reverse direction to the resistive change layer material 23 so that current flows from the second end E2 to the first end E1, in the second region 23b close to the first end E1, a part of the active traps will change to non-active traps while being annihilated. It may be explained that adjacent selenium ions (Se 2- ) are further bonded to form a covalent bond (Se-Se). As a result, the density of active traps in the resistive change layer material 23 decreases.

[0081] Comparing FIGS. 10A and 11A, after applying a negative bias voltage to the resistance change layer material 23, the density of active traps may be reduced in both the first region 23a and the second region 23b. In particular, in the second region 23b, the density of active traps may be further significantly reduced. Note that in the first region 23a, the amount of change in the density of active traps is smaller than the amount of change in the density of active traps in the second region 23b. Thereby, after applying a negative bias voltage to the resistance change layer material 23, the density of active traps in the second region 23b becomes lower than the density of active traps in the first region 23a. Thereby, an ITB (interface tunneling barrier) may be formed near the boundary between the first region 23a and the second region 23b.

[0082] Further, comparing FIGS. 10B and 11B, after applying a negative bias voltage to the resistance change layer material 23, the density of states of active traps may be slightly reduced in the first region 23a. Note that comparing FIGS. 10C and 11C, after applying a negative bias voltage to the resistance change layer material 23, the density of states of active traps may be relatively significantly reduced in the second region 23b. Also, comparing FIGS. 11B and 11C, it can be seen that after applying a negative bias voltage to the resistance change layer material 23, the density of states of active traps in the second region 23b is lower than the density of states of active traps in the first region 23a.

[0083] In the resistance change layer material 23, particularly in the second region 23b near the first end E1, if the amount of active traps is reduced, a higher bias voltage will be required to form a conductive path, and thus the threshold voltage of the resistance change layer material 23 may increase. At this time, the resistance change layer material 23 is in a second state (HVS) with a relatively high threshold voltage. In other words, when the resistance change layer material 23 is in the second state (HVS), the density of active traps in the second region 23b is lower than the density of active traps in the first region 23a. Also, when the resistance change layer material 23 is in the second state (HVS), the density of active traps in the first region 23a and the density of active traps in the second region 23b are lower than the density of active traps in the first region 23a and the density of active traps in the second region 23b when the resistance change layer material 23 is in the first state (LVS), respectively.

[0084] Thereafter, if a positive bias voltage equal to or higher than the threshold voltage is applied to the resistance change layer material 23, in the resistance change layer material 23, particularly in the second region 23b, the amount of active traps increases while the threshold voltage of the resistance change layer material 23 can become low again. Thereby, the resistance change layer material 23 can return to the first state (LVS). In this way, in the resistance change layer material 23, through the state change of active traps, particularly through the large state change of active traps in the second region 23b near the first end E1, the threshold voltage shift behavior may be realized. Note that in the initial state, since the density of active traps is lower than the density of active traps in the state where a negative bias voltage is applied after the first drive, the positive bias voltage required for the first drive is higher than the positive bias voltage for further lowering the threshold voltage of the resistance change layer material 23 after the negative bias voltage.

[0085] As described above, in the resistive change layer material 23, the threshold voltage shift may occur not due to the ion migration phenomenon but due to the change in the state of the active trap or the change in the density of the active trap. Therefore, in the state before the first drive, the state after the first drive, and the state after the first drive with a negative bias voltage applied, almost no change in the composition occurs within the resistive change layer material 23, and the elemental composition distribution may be substantially maintained constant inside the resistive change layer material 23. Here, the expression "substantially maintained constant" for the elemental composition distribution may mean that there is no significant change in the concentration of each element contained, for example, in the first region 23a and the second region 23b of the resistive change layer material 23 inside the resistive change layer material 23. More specifically, the expression "substantially maintained constant" for the elemental composition distribution may include the case where the concentration difference of each element contained in the first region 23a and the second region 23b of the resistive change layer material 23 is within 10% when the resistive change layer material 23 is in the first state (LVS) and when the resistive change layer material 23 is in the second state (HVS).

[0086] In other words, when the resistive change layer material 23 changes from the first state (LVS) to the second state (HVS) or from the second state (HVS) to the first state (LVS), the ratios of components such as germanium (Ge), arsenic (As), and selenium (Se) may be maintained constant within the first region 23a and the second region 23b of the resistive change layer material 23. For example, when the resistive change layer material 23 contains selenium (Se), there is almost no difference between the selenium concentration in the first region 23a when the resistive change layer material 23 is in the first state (LVS) and the selenium concentration in the first region 23a when the resistive change layer material 23 is in the second state (HVS).

[0087] When the resistive change layer material 23 including the amorphous multi-component chalcogenide material having the foregoing composition is used as the resistive change layer 323 of the memory cell string CS, the memory device 200 may have a relatively high driving speed. For example, the resistive change layer 323 including the amorphous multi-component chalcogenide material having the foregoing composition can perform threshold voltage switching even when a voltage having a pulse width of about 1 nsec or less is applied. Therefore, the memory device 200 may have a relatively high driving speed, for example, of about 1 nsec or less.

[0088] In the memory cell string CS including the resistive change layer 323 having the foregoing characteristics, the set operation and the reset operation may be performed independently for each memory cell MC of the memory cell string CS. FIG. 12A illustratively shows the set operation of the memory cell string CS according to an embodiment, and FIG. 12B illustratively shows the reset operation of the memory cell string CS according to an embodiment.

[0089] Referring to FIG. 12A, a gate voltage less than the threshold voltage may be applied to the gate electrode 312 of the selected memory cell sMC for which the set operation is performed via the word line WL. Alternatively, the gate voltage may not be applied. Here, the threshold voltage means the threshold voltage of a transistor formed by one gate electrode 312, a part of the gate insulating film 321 adjacent thereto in the horizontal direction (i.e., the second direction or the third direction), and a part of the channel layer 322. Then, a gate voltage equal to or higher than the threshold voltage may be applied to the gate electrodes 312 of all the remaining non-selected memory cells nMC for which the set operation is not performed via the word line WL. Therefore, all the transistors of the non-selected memory cells nMC are turned on, current flows through the channel layer 322 of the non-selected memory cells nMC, the transistor of the selected memory cell sMC is turned off, and current cannot flow in the channel layer 322 of the selected memory cell sMC.

[0090] A positive bias voltage higher than the second voltage V2 described with reference to FIGS. 7 and 8A may be applied to the channel layer 322 via the bit line. Thereby, in the non-selected memory cell nMC, most of the current flows through the channel layer 322, and in the selected memory cell sMC, most of the current flows through the resistive change layer 323. Accordingly, a partial region of the resistive change layer 323 in the selected memory cell sMC may be converted to the first state (LVS). In the entire resistive change layer 323 of the memory cell string CS, the portion converted to the first state (LVS) is only the portion within the selected memory cell sMC. In other words, in the entire resistive change layer 323, only a partial region horizontally adjacent to the gate electrode 312 to which a gate voltage less than the threshold voltage is applied may be converted to the first state (LVS).

[0091] Referring to FIG. 12B, a gate voltage less than the threshold voltage may be applied to the gate electrode 312 of the selected memory cell sMC in which the reset operation is performed, and a gate voltage equal to or higher than the threshold voltage may be applied to the gate electrodes 312 of all the remaining non-selected memory cells nMC. Then, the third voltage V3 described with reference to FIGS. 7 and 8B, or a negative bias voltage lower than that, may be applied to the channel layer 322 via the bit line. Thereby, a partial region of the resistive change layer 323 in the selected memory cell sMC may be converted to the second state (HVS).

[0092] The read operation may be performed by applying a positive read voltage VR between the first voltage V1 which is the first threshold voltage and the second voltage V2 which is the second threshold voltage to the channel layer 322 in a state where a gate voltage less than the threshold voltage is applied only to the gate electrode 312 of the selected memory cell sMC and a gate voltage equal to or higher than the threshold voltage is applied to the gate electrodes 312 of all the non-selected memory cells nMC.

[0093] Such set operation, reset operation, and read operation may be performed after initially driving the resistive change layer 323. The initial driving may also be performed independently for each memory cell MC. In other words, after manufacturing the memory cell string CS, the initial driving may be sequentially performed one by one for a plurality of memory cells MC in the memory cell string CS. For example, while applying a gate voltage less than the threshold voltage only to the gate electrode 312 of the selected memory cell sMC and applying a gate voltage equal to or higher than the threshold voltage to the gate electrodes 312 of all non-selected memory cells nMC, an initial driving voltage higher than the positive bias voltage during the set operation may be applied to the channel layer 322. Then, the initial driving may be performed while sequentially changing the selected memory cell sMC until the regions of the resistive change layer 323 corresponding to all the memory cells MC in the memory cell string CS are initially driven.

[0094] For all the memory cells MC in the memory cell string CS, even after the initial driving is completed, the regions of the resistive change layer 323 corresponding to two adjacent memory cells MC along the vertical direction (i.e., the first direction) may remain in the initial state. In other words, only a partial region of the resistive change layer 323 adjacent to the gate electrode 312 along the second direction or the third direction is in the state of being initially driven, and a partial region of the resistive change layer 323 adjacent to the insulating spacer 311 along the second direction or the third direction may remain in the initial state. Therefore, within one memory cell string CS, the resistive change layer 323 may have a plurality of driven regions and a plurality of initial state regions along the vertical direction (i.e., the first direction).

[0095] FIG. 13 exemplarily shows a region formed in the resistive change layer 323 after the first driving of the memory cell string CS according to one embodiment. Referring to FIG. 13, the resistive change layer 323 in one memory cell string CS may include a plurality of driving regions 323F alternately provided along a first direction and a plurality of initial state regions 323P. Each driving region 323F may be provided opposite to a corresponding gate electrode 312 among the plurality of gate electrodes 312 in a second direction, and each initial state region 323P may be provided opposite to a corresponding insulating spacer 311 among the plurality of insulating spacers 311 in the second direction. The concentration of active traps in the initial state region 323P may be lower than the concentration of active traps in the driving region 323F. Further, when a voltage equal to or higher than the first threshold voltage is applied, the resistance of each initial state region 323P may be higher than the resistance of each driving region 323F.

[0096] As described with reference to FIG. 10A, each driving region 323F may include a first region 323a and a second region 323b having different densities of active traps from each other. The distance or thickness of the second region 323b along the first direction may be smaller than the distance or thickness of the first region 323a along the first direction. For example, the distance or thickness of the first region 323a along the first direction may be two times or more and ten times or less the distance or thickness of the second region 323b along the first direction. When the driving region 323F of the resistive change layer 323 is in the first state (LVS), the density of active traps in the second region 323b is higher than the density of active traps in the first region 323a. Note that when the driving region 323F of the resistive change layer 323 is in the second state (HVS), the density of active traps in the second region 323b may be lower than the density of active traps in the first region 23a. Further, when the driving region 323F of the resistive change layer 323 is in the second state (HVS), the density of active traps in the first region 323a and the density of active traps in the second region 323b may be lower than the density of active traps in the first region 323a and the density of active traps in the second region 323b, respectively, when the driving region 323F of the resistive change layer 323 is in the first state (LVS).

[0097] Also, as described above, in the initial state region 323P, the first region 323a of the drive region 323F, and the second region 323b of the drive region 323F, even if almost no change occurs in the elemental composition within the resistance change layer 323, it may be acceptable. Therefore, in the initial state region 323P, the first region 323a, and the second region 323b, the elemental composition distribution may be substantially the same.

[0098] FIG. 14 is a vertical cross-sectional view showing a structure fabricated to confirm the actual operation of a memory cell string CS according to an embodiment. Referring to FIG. 14, along the first direction, polysilicon, silicon oxide, and polysilicon are sequentially laminated, and a threshold switching memory material TSM (threshold switching memory) is formed along the sidewalls of the laminated polysilicon, silicon oxide, and polysilicon. The two polysilicons may correspond to the channels of non-selective memory cells nMC (FIGS. 12A and 12B), and the silicon oxide may correspond to the channel of a selective memory cell sMC (FIGS. 12A and 12B). The threshold switching memory material TSM corresponds to the resistance change layer 323 and may include the material of the resistance change layer 323 described above. In the structure illustrated in FIG. 14, a first drive voltage, a reset voltage, and a set voltage were applied to the polysilicon.

[0099] FIG. 15 is a graph exemplarily showing the voltage-current characteristics of the structure illustrated in FIG. 14 in the initial state, the set state, and the reset state. In FIG. 15, the graph labeled (a) shows the voltage-current characteristics in the initial state, the graph labeled (b) shows the voltage-current characteristics in the set state, and the graph labeled (c) shows the voltage-current characteristics in the reset state. Referring to FIG. 15, in the initial state, the resistance of the threshold switching memory material TSM is the highest, and no threshold voltage is observed. After the first drive, the resistance of the threshold switching memory material TSM becomes low. In the set state, a threshold voltage at which the current suddenly increases is observed at about 6.9V. In the reset state, a threshold voltage at which the current suddenly increases is observed at about 8V. At the applied voltage between about 6.9V and about 8V, the resistance of the switching memory material TSM in the set state was lower than the resistance of the switching memory material TSM in the reset state. Therefore, in the example illustrated in FIG. 15, the first voltage V1 which is the first threshold voltage may be about 6.9V, and the second voltage V2 which is the second threshold voltage may be about 8V.

[0100] FIG. 16 is a vertical cross-sectional view schematically showing the structure of a memory cell string according to another embodiment. Referring to FIG. 16, a memory cell string CS' according to another embodiment may further include a barrier layer 325 provided between a channel layer 322 and a resistive change layer 323. The barrier layer 325 is conformally deposited along the surface of the channel layer 322 and extends along a first direction, and the resistive change layer 323 may be conformally deposited along the surface of the barrier layer 325 and extend along a vertical direction. The barrier layer 325 may reduce or prevent diffusion of materials between the channel layer 322 and the resistive change layer 323. The barrier layer 325 may be a carbon-based or nitrogen-based insulator. For example, the barrier layer 325 may include at least one material of C, CN, and SiN. However, when forming the resistive change layer 323 along the surface of the barrier layer 325, if the probability of oxidation of the material of the resistive change layer 323 is low, the barrier layer 325 may include an oxide such as Al2O3. In order to reduce or minimize power loss due to the barrier layer 325, the barrier layer 325 may be formed as thin as possible. For example, the second-direction thickness d4 of the barrier layer 325 may be greater than 0 nm and about 10 nm or less.

[0101] As described above, since the memory device 200 according to one embodiment has the characteristics of a voltage-driven element, it may operate similarly to a CTF (charge trap flash)-VNAND. Also, the memory device 200 according to one embodiment may have a relatively fast driving speed. In particular, the memory device 200 according to one embodiment can have high reliability with almost no interference between adjacent memory cells MC in the memory cell string CS. For example, since the resistance change layer 323 includes the initial state region 323P where the concentration of active traps is the lowest between adjacent memory cells MC, almost no interference may occur between the two driving regions 323F adjacent in the first direction. Therefore, the interval between adjacent memory cells MC, in other words, the thickness (or the height in the first direction) of the insulating spacer 311 can be reduced, and the memory device 200 can be manufactured with a high degree of integration, and thus the capacity of the memory device 200 can be improved.

[0102] The memory device 200 described above may be used for data storage in various electronic devices. FIG. 17 is a conceptual diagram schematically showing an element architecture that may be applied to an electronic device according to an exemplary embodiment. Referring to FIG. 17, the electronic device 400 may include a main memory 410, an auxiliary storage 420, a CPU (central processing unit) 430, and an input / output device 440. The CPU 430 may include a cache memory 431, an ALU (arithmetic logic unit), and a control unit 433. The cache memory 431 may include SRAM (static random access memory). The main memory 410 may include DRAM (dynamic random access memory) elements, and the auxiliary storage 420 may include a memory device 200 according to one embodiment. Alternatively, the cache memory 431, the main memory 410, and the auxiliary storage 420 may all include a memory device 100, 200 according to one embodiment. In some cases, the electronic device 400 may be embodied in a form in which a computing unit element and a memory unit element are adjacent to each other by one chip without the above-described division of sub-units.

[0103] Also, the memory device 200 may be used as a neuromorphic computing platform. For example, FIG. 18 schematically shows a neuromorphic device including a memory device 200 according to one embodiment. Referring to FIG. 18, the neuromorphic device 1000 may include a processing circuit 1010 and / or a memory 1020. The memory 1020 of the neuromorphic device 1000 may include a memory device 200 according to one embodiment.

[0104] The processing circuit 1010 may be configured to control the functions for driving the neuromorphic device 1000. For example, the processing circuit 1010 may control the neuromorphic device 1000 by causing it to execute a program stored in the memory 1020 of the neuromorphic device 1000. The processing circuit 1010 may include hardware such as a logic circuit, a combination of hardware and software such as a processor for executing software, or a combination thereof. For example, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) within the neuromorphic device 1000, an arithmetic logic unit (ALU), a digital processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like. Further, the processing circuit 1010 may read various data from / to the external device 1030, utilize the data, and cause the neuromorphic device 1000 to execute. The external device 1030 may include an external memory and / or a sensor array having an image sensor (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor circuit).

[0105] The neuromorphic device 1000 illustrated in FIG. 18 may be applied to a machine learning system. The machine learning system may utilize various artificial neural network organizations and processing models including, for example, convolutional neural network (CNN), deconvolutional neural network, long short-term memory (LSTM) and / or gated recurrent unit (GRU) selectively included recurrent neural network (RNN), stacked neural network (SNN), state-space dynamic neural network (SSDNN), deep belief network (DBN), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBM), etc.

[0106] Such a machine learning system may include a combination of, for example, linear regression and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and other types of machine learning models such as expert systems, and / or ensemble techniques such as random forest. Such machine learning models are used to provide a variety of services, such as video classification services, user authentication services based on biometric information or biometric data, advanced driver-assistance systems (ADAS), voice assistant services, and automatic speech recognition (ASR) services, and may be installed on and executed by other electronic devices.

[0107] At least one of the aforementioned components may include hardware including a logic circuit, a hardware / software combination such as a processor that executes software, or a processing circuit such as a combination thereof, or may be embodied in such a processing circuit. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, an FPGA, an SoC, a programmable logic unit (PLC), a microprocessor, an ASIC, etc.

[0108] The vertical non-volatile memory device including the foregoing memory cell string has been described with reference to the embodiments illustrated in the drawings, but these are merely exemplary, and those having ordinary knowledge in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the disclosed embodiments should be considered from an illustrative rather than a limiting perspective. The scope of rights is shown not in the foregoing description but in the claims, and all differences within the scope equivalent thereto should be construed as being included in the scope of rights.

Explanation of Reference Numerals

[0109] 10 Memory system 100 Memory controller 110 Write / read control unit 120 Voltage control unit 130 Data discrimination unit 200 Memory device 210 Memory cell array 220 Voltage generation unit 230 Row decoder 240 Input / output circuit 250 Control logic 311 Insulating spacer 312 Gate electrode 321 Gate insulating film 322 Channel layer 323 Resistance change layer 324 Insulating support 325 Barrier layer

Claims

1. A plurality of memory cell strings arranged in a two-dimensional array; Each memory cell string is A channel layer extending along a first direction; a plurality of gate electrodes and a plurality of spacers each extending along a second direction intersecting the first direction and alternately arranged along the first direction; a gate insulating film extending along the first direction and disposed between the channel layer and the gate electrodes; a resistance change layer extending in the first direction along a surface of the channel layer, The resistive layer includes a material that switches between a first state (LVS) having a first threshold voltage and a second state (HVS) having a second threshold voltage higher than the first threshold voltage.

2. When the variable resistance layer is in the first state (LVS), if a voltage lower than the first threshold voltage is applied to the variable resistance layer, no current flows through the variable resistance layer, and if a voltage higher than the first threshold voltage is applied to the variable resistance layer, a current flows through the variable resistance layer; 2. The vertical nonvolatile memory device of claim 1, wherein when the resistance change layer is in a second state (HVS), if a voltage lower than the second threshold voltage is applied to the resistance change layer, no current flows through the resistance change layer, and if a voltage higher than the second threshold voltage is applied to the resistance change layer, a current flows through the resistance change layer.

3. When the resistance change layer is in the first state (LVS), if a negative bias voltage is applied to the resistance change layer, the resistance change layer is transformed to the second state (HVS); 3. The vertical nonvolatile memory device of claim 2, wherein when the resistance change layer is in the second state (HVS), if a positive bias voltage higher than the second threshold voltage is applied to the resistance change layer, the resistance change layer is converted to the first state (LVS).

4. The vertical nonvolatile memory device according to claim 1 , wherein in a read operation, a read voltage between the first threshold voltage and the second threshold voltage is applied to the resistance change layer.

5. 2. The vertical nonvolatile memory device of claim 1, wherein the resistance change layer has a single layer structure including at least one amorphous multi-element chalcogenide material selected from the group consisting of GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeSbIn, GeAsSeTe, GeAsSeTeIn, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeSbSeIn, GeSbSeN, GeSbSeNIn, CTe, GeCTe, NGeCTe, BTe, SiTe, GeAsTe, GeSbSe, and GeSbSeN.

6. The vertical nonvolatile memory device of claim 5 , wherein a ratio of germanium (Ge) in the resistance change layer is 10 at % to 30 at %.

7. The vertical nonvolatile memory device of claim 5 , wherein a ratio of arsenic (As) in the resistance change layer is 10 at % or more and 50 at % or less.

8. The vertical nonvolatile memory device of claim 5 , wherein a ratio of selenium (Se) in the resistance change layer is 40 at % or more and 80 at % or less.

9. The vertical nonvolatile memory device of claim 5 , wherein a ratio of indium (In) in the resistance change layer is 1 at % to 10 at %.

10. The vertical nonvolatile memory device of claim 1 , wherein the resistance change layer includes a plurality of driving regions and a plurality of initial state regions alternately provided along the first direction.

11. Each driving region is provided to face a corresponding one of the plurality of gate electrodes in the second direction, The vertical nonvolatile memory device of claim 10 , wherein each initial state region is disposed opposite a corresponding one of a plurality of insulating spacers in the second direction.

12. The vertical nonvolatile memory device of claim 10 , wherein a resistance of the initial state region is higher than a resistance of the driving region when a voltage equal to or greater than the first threshold voltage is applied.

13. 11. The vertical non-volatile memory device of claim 10, wherein each drive region includes a first region and a second region having different densities of active traps.

14. In the first state (LVS), a density of active traps in the second region is higher than a density of active traps in the first region; 14. The vertical non-volatile memory device of claim 13, wherein in the second state (HVS), a density of active traps in the second region is lower than a density of active traps in the first region.

15. 14. The vertical nonvolatile memory device of claim 13, wherein a thickness of the second region along the first direction is less than a thickness of the first region along the first direction.

16. 14. The vertical nonvolatile memory device of claim 13, wherein a thickness of the first region along the first direction is between two and ten times a thickness of the second region along the first direction.

17. 2. The vertical non-volatile memory device of claim 1, wherein an elemental composition distribution is maintained constant in the first region and the second region while switching between the first state (LVS) and the second state (HVS).

18. The vertical nonvolatile memory device of claim 1 , wherein the thickness of the variable resistance layer in the second direction is from 5 nm to 100 nm.

19. Each memory cell string further includes a barrier layer extending along the first direction between the channel layer and the resistance change layer, the barrier layer is a carbon-based or nitrogen-based non-conductor; The vertical nonvolatile memory device of claim 1 , wherein the barrier layer has a thickness in the second direction greater than 0 nm and less than or equal to 10 nm.

20. A processing circuit; a vertical non-volatile memory device including a plurality of memory cell strings arranged in a two-dimensional array and coupled to the processing circuit; Each memory cell string is A channel layer extending along a first direction; a plurality of gate electrodes and a plurality of spacers each extending along a second direction intersecting the first direction and alternately arranged along the first direction; a gate insulating film extending along the first direction and disposed between the channel layer and the gate electrodes; a resistance change layer extending in the first direction along a surface of the channel layer, An electronic device, wherein the resistive layer comprises a material that is switched between a first state (LVS) having a first threshold voltage and a second state (HVS) having a second threshold voltage higher than the first threshold voltage.

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