Semiconductor device

Abstract

To provide a semiconductor device with a smaller occupied area.SOLUTION: A semiconductor device includes a first transistor including a first oxide semiconductor, a second transistor including a second oxide semiconductor, a capacitor element, a first insulator, and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are disposed so as to be embedded in the first insulator. The second conductor is disposed in contact with an upper surface of the first conductor and an upper surface of a gate of the first transistor. The second insulator is disposed on the second conductor and the first insulator and the third conductor is disposed covering the second conductor through the second insulator.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Note that in this specification and the like, the semiconductor device refers to all things that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, a display device, a light-emitting device, a lighting device, an electro-optical device, a storage device, an imaging device, a communication device, and an electronic device may include semiconductor elements or semiconductor circuits. Further, a display device, a light-emitting device, a lighting device, an electro-optical device, a storage device, an imaging device, a communication device, and an electronic device may also be called a semiconductor device.

Background Art

[0004] In recent years, transistors using an oxide semiconductor or a metal oxide in a channel formation region (Oxide Semiconductor transistor, hereinafter referred to as an OS transistor) have attracted attention (Patent Document 1).

[0005] The off-current of the OS transistor is very small. By utilizing this, Patent Documents 2 and 3 disclose non-volatile memories using an OS transistor. The non-volatile memory using an OS transistor has no limit on the number of times of data rewriting, and further has low power consumption when rewriting data. In addition, Patent Document 3 discloses an example in which a memory cell of a non-volatile memory is configured only by an OS transistor.

[0006] In this specification, the non-volatile memory using an OS transistor may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation of "Nonvolatile Oxide Semiconductor RAM" and refers to a RAM having a gain cell type (2T type, 3T type) memory cell.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a semiconductor device with a small occupation area as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device capable of high integration as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with a large storage capacity as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with a low manufacturing cost as one of the problems. Or, one aspect of the present invention is to provide a highly reliable semiconductor device as one of the problems. Or, one aspect of the present invention is to provide a novel semiconductor device as one of the problems.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become clear from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention has a first transistor, a second transistor, a capacitive element, a first insulator, and a first conductor. The first transistor has a first oxide semiconductor, a first gate, and a first gate insulator. The second transistor has a second oxide semiconductor, a second gate, and a second gate insulator. The capacitive element has a second conductor, a third conductor, and a second insulator. The first insulator is disposed over the first oxide semiconductor and the second oxide semiconductor. The first insulator has a first opening reaching the first oxide semiconductor and a second opening reaching the second oxide semiconductor, and a third opening reaching one of the source or drain of the second transistor. In the first opening, the first gate insulator and the first gate are disposed. In the second opening, the second gate insulator and the second gate are disposed. In the third opening, the first conductor is disposed. The second conductor is disposed in contact with the upper surface of the first conductor and the upper surface of the first gate. The second insulator is disposed over the second conductor and the first insulator. The third conductor is disposed covering the second conductor via the second insulator. It is a semiconductor device.

[0011] In the above, it is preferable that the second conductor is disposed covering the first gate.

[0012] Also, in the above, a part of the first gate may be exposed from the second conductor and a part of the first gate may be in contact with the second insulator.

[0013] Also, in the above, it is preferable that the channel length direction of the first transistor and the channel length direction of the second transistor are substantially parallel. Also, in the above, it is preferable that the extending direction of the third conductor is substantially perpendicular to the channel length direction of the first transistor.

[0014] Further, in the above, it is preferable that a fourth conductor is provided in contact with the upper surface of the second gate, and the extending direction of the fourth conductor is substantially perpendicular to the channel length direction of the second transistor. Further, in the above, it is preferable that the fourth conductor overlaps with the first oxide semiconductor via the first insulator.

[0015] Another aspect of the present invention includes a first to fourth transistors, a first oxide semiconductor, a second oxide semiconductor, a first capacitive element, a second capacitive element, a first insulator, a second insulator, a first conductor, and a second conductor. The first transistor and the third transistor are formed on the first oxide semiconductor, the second transistor and the fourth transistor are formed on the second oxide semiconductor. The first transistor has a first gate and a first gate insulator, the second transistor has a second gate and a second gate insulator, the third transistor has a third gate and a third gate insulator, and the fourth transistor has a fourth gate and a fourth gate insulator. The first capacitive element has a third conductor and a fourth conductor, and the second capacitive element has a fifth conductor and a sixth conductor. The first insulator is disposed over the first oxide semiconductor and the second oxide semiconductor, and first and second openings reaching the first oxide semiconductor and third and fourth openings reaching the second oxide semiconductor are formed therein. A fifth opening reaching one of the source or drain of the second transistor and a sixth opening reaching one of the source or drain of the fourth transistor are formed. The first gate insulator and the first gate are disposed in the first opening, the third gate insulator and the third gate are disposed in the second opening, the second gate insulator and the second gate are disposed in the third opening, the fourth gate insulator and the fourth gate are disposed in the fourth opening, the first conductor is disposed in the fifth opening, and the second conductor is disposed in the sixth opening. The third conductor is disposed in contact with the upper surface of the first conductor and the upper surface of the first gate, the fifth conductor is disposed in contact with the upper surface of the second conductor and the upper surface of the third gate, the second insulator is disposed over the third conductor, the fifth conductor, and the first insulator, the fourth conductor is disposed to cover the third conductor with the second insulator interposed therebetween, and the sixth conductor is disposed to cover the fifth conductor with the second insulator interposed therebetween. It is a semiconductor device.

[0016] In the above, it is preferable that the first oxide semiconductor and the second oxide semiconductor have indium, one or more elements M (M is selected from gallium, aluminum, yttrium, and tin), and zinc.

Advantages of the Invention

[0017] According to one aspect of the present invention, a semiconductor device with a small occupied area can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of high integration can be provided. Or, according to one aspect of the present invention, a semiconductor device with a large storage capacity can be provided. Or, according to one aspect of the present invention, a semiconductor device with low manufacturing cost can be provided. Or, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0018] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be naturally apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0019]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0020] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and the repeated description thereof will be omitted.

[0021] In addition, the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. in order to facilitate the understanding of the invention. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but this may not be reflected in the drawing for the sake of easy understanding.

[0022] In addition, in the drawings and the like, for the sake of easy understanding of the description, the description of some components may be omitted.

[0023] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0024] In addition, in this specification and the like, the "terminal" in an electric circuit refers to a part where input or output of current, input or output of voltage, or reception or transmission of a signal is performed. Therefore, a part of a wiring or an electrode may function as a terminal.

[0025] In addition, in this specification and the like, terms such as "upper" and "lower" do not limit the positional relationship of components to be directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed in direct contact on insulating layer A, and components other than insulating layer A and electrode B are not excluded.

[0026] Also, since the functions of the source and drain are interchangeable depending on operating conditions such as when transistors of different polarities are employed or when the direction of current changes in circuit operation, it is difficult to limit which one is the source or drain. Therefore, in this specification, the terms source and drain can be used interchangeably.

[0027] In addition, in this specification and the like, "electrically connected" includes cases of direct connection and cases of connection via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only wiring extends.

[0028] In addition, in this specification and the like, when referring to count values and measurement values as "identical", "the same", "equal", or "uniform", etc., unless otherwise specified, they shall include an error of plus or minus 20%.

[0029] Also, voltage often indicates the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and the like, unless otherwise specified, voltage and potential can be used interchangeably.

[0030] Even when referred to as a "semiconductor," for example, if its conductivity is sufficiently low, it has the characteristics of an "insulator." Therefore, it is also possible to use it by replacing "semiconductor" with "insulator." In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification may be interchangeable with each other.

[0031] Also, even when referred to as a "semiconductor," for example, if its conductivity is sufficiently high, it has the characteristics of a "conductor." Therefore, it is also possible to use it by replacing "semiconductor" with "conductor." In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification may be interchangeable with each other.

[0032] Note that the ordinal numbers such as "first," "second," etc. in this specification and the like are attached to avoid confusion of components, and do not indicate any order or rank such as the process order or the stacking order. Also, even for a term without an ordinal number in this specification and the like, an ordinal number may be attached in the claims to avoid confusion of components. Also, even for a term with an ordinal number in this specification and the like, a different ordinal number may be attached in the claims. Also, even for a term with an ordinal number in this specification and the like, the ordinal number may be omitted in the claims and the like.

[0033] Note that in this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as the "conducting state"). Also, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as the "non-conducting state").

[0034] In addition, in this specification and the like, the "on-current" may refer to the current flowing between the source and the drain when the transistor is in the on-state. Also, the "off-current" may refer to the current flowing between the source and the drain when the transistor is in the off-state.

[0035] In addition, in this specification and the like, the high power supply potential VDD (hereinafter, also simply referred to as "VDD", "H potential", or "H") indicates a power supply potential having a potential higher than the low power supply potential VSS (hereinafter, also simply referred to as "VSS", "L potential", or "L"). Also, VSS indicates a power supply potential having a potential lower than VDD. Further, the ground potential (hereinafter, also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0036] In addition, unless otherwise specified, the transistors shown in this specification and the like are enhancement-type (normally-off type) n-channel field-effect transistors. Therefore, its threshold voltage (also referred to as "Vth") is greater than 0V. Also, unless otherwise specified, "supplying an H potential to the gate of the transistor" may be synonymous with "turning on the transistor". Also, unless otherwise specified, "supplying an L potential to the gate of the transistor" may be synonymous with "turning off the transistor".

[0037] In addition, in this specification and the like, the gate refers to a gate electrode and part or all of the gate wiring. The gate wiring refers to the wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0038] In addition, in this specification and the like, the source refers to a source region, a source electrode, and part or all of a source wiring. The source region refers to a region in the semiconductor layer where the resistivity is equal to or less than a certain value. The source electrode refers to a conductive layer of a portion connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0039] In addition, in this specification and the like, the drain refers to a drain region, a drain electrode, and part or all of a drain wiring. The drain region refers to a region in the semiconductor layer where the resistivity is equal to or less than a certain value. The drain electrode refers to a conductive layer of a portion connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0040] In addition, in drawings and the like, in order to make the potentials of wirings and electrodes, etc. easier to understand, an "H" indicating an H potential or an "L" indicating an L potential may be added adjacent to the wirings and electrodes, etc. Further, for wirings and electrodes, etc. where a potential change has occurred, an "H" or "L" may be added in enclosed characters. Further, when a transistor is in an off state, an "×" symbol may be added over the transistor.

[0041] Generally, a "capacitor" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification and the like, the "capacitor element" includes the case where it is the aforementioned "capacitor". That is, in this specification and the like, the "capacitor element" includes those having a configuration in which two electrodes face each other with an insulator in between, those having a configuration in which two wirings face each other with an insulator in between, or those in which two wirings are arranged with an insulator in between.

[0042] In addition, in this specification and the like, when the same reference numeral is used for a plurality of elements, particularly when it is necessary to distinguish them, the reference numeral may be described with a distinguishing reference numeral such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring CL may be described as wiring CL[2].

[0043] Note that the channel length is, for example, in the top view of the transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be a single value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0044] The channel width is, for example, in the top view of the transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the length of the channel formation region in the vertical direction with respect to the channel length direction in the channel formation region. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0045] In the present specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and the influence may become non-negligible. For example, in a fine transistor in which the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

[0046] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0047] In the present specification, when simply described as the channel width, it may refer to the apparent channel width. Alternatively, in the present specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

[0048] Note that impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are included, for example, the density of defect levels in the semiconductor may increase, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components of the oxide semiconductor, and for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Note that water may also function as an impurity. Further, for example, due to the incorporation of impurities, oxygen vacancies (V O : also referred to as oxygen vacancy) may be formed in the oxide semiconductor.

[0049] Note that in this specification and the like, an oxynitride has a composition with a higher oxygen content than nitrogen. Further, a nitride oxide has a composition with a higher nitrogen content than oxygen.

[0050] Also, in this specification and the like, the term "insulator" can be rephrased as an insulating film or an insulating layer. Further, the term "conductor" can be rephrased as a conductive film or a conductive layer. Also, the term "semiconductor" can be rephrased as a semiconductor film or a semiconductor layer.

[0051] Also, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0052] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0053] Also, in this specification and the like, normally-off means that when no potential is applied to the gate or when the gate is given a ground potential, the drain current per 1 μm of channel width flowing through the transistor is -20 A or less at room temperature, 1 × 10 -18 A or less at 85°C, or 1 × 10 -16 A or less at 125°C.

[0054] (Embodiment 1) In this embodiment, as an example of a semiconductor device according to an aspect of the present invention, the configuration of the memory cell 10 will be described with reference to FIGS. 1 to 8. The memory cell 10 functions as part of a storage device and includes a transistor 11, a transistor 12, and a capacitor element 13, and is electrically connected to a wiring CL, a wiring WL, a wiring RBL, a wiring SL, a wiring WBL, a wiring BGL1, and a wiring BGL2.

[0055] FIG. 1A is a circuit diagram of the memory cell 10, and FIG. 1B is a top view of the memory cell 10. FIG. 2A is a top view excluding the wiring CL from FIG. 1B. FIG. 2B is a top view excluding the wiring CL, the wiring WL, the conductor 207, the dashed-dotted line A1 - A2 - A3, and the dashed-dotted line A4 - A5 - A6 from FIG. 1B. In the top views of FIGS. 1B, 2A, and 2B, some elements are omitted for clarity of the figure.

[0056] FIG. 3A is a cross-sectional view of the portion indicated by the one-dot chain line A1-A2-A3 in FIGS. 1B and 2A. Here, the cross-sectional view indicated by A1-A2 is a cross-sectional view in the channel length direction of transistor 12, and the cross-sectional view indicated by A2-A3 is a cross-sectional view in the channel width direction of transistor 11. Further, FIG. 3B is a cross-sectional view of the portion indicated by the one-dot chain line A4-A5-A6 in FIGS. 1B and 2A. Here, the cross-sectional view indicated by A4-A5 is a cross-sectional view in the channel width direction of transistor 12, and the cross-sectional view indicated by A5-A6 is a cross-sectional view in the channel length direction of transistor 11.

[0057] Note that in drawings and the like, arrows indicating the x-direction, y-direction, and z-direction may be attached. The x-direction, y-direction, and z-direction are directions that are orthogonal to each other. In this specification and the like, one of the x-direction, y-direction, or z-direction may be referred to as the "first direction" or "first direction". Also, one of the other two may be referred to as the "second direction" or "second direction". Also, the remaining one may be referred to as the "third direction" or "third direction".

[0058] <Configuration Example of Semiconductor Device> First, a circuit configuration example of memory cell 10 will be described. As shown in FIG. 1A, memory cell 10 includes transistor 11, transistor 12, and capacitor element 13. One of the source or drain of transistor 11 is electrically connected to wiring RBL, and the other is electrically connected to wiring SL. The back gate of transistor 11 is electrically connected to wiring BGL1. One of the source or drain of transistor 12 is electrically connected to wiring WBL, and the other is electrically connected to the gate of transistor 11. Note that in this specification and the like, the node or wiring that electrically connects the gate of transistor 11 and the other of the source or drain of transistor 12 may be referred to as node FN. The gate of transistor 12 is electrically connected to wiring WL, and the back gate is electrically connected to wiring BGL2.

[0059] As shown in FIG. 1A, it is preferable that the transistor 11 and the transistor 12 are provided on the same plane, and the capacitor element 13 is provided on the transistor 11 and the transistor 12. In other words, the capacitor element 13 is preferably arranged so as to overlap the transistor 11 and the transistor 12 in the z-axis direction. By adopting such a configuration, the capacitor element 13 can be provided for the transistor 11 and the transistor 12 without substantially increasing the area. Therefore, the occupied area of the memory cell 10 can be reduced. As a result, high integration of the semiconductor device can be achieved, and a semiconductor device with a large storage capacity can be provided. In addition, a semiconductor device with a low manufacturing cost per storage capacity can be provided.

[0060] The wiring CL is arranged on the capacitor element 13. Here, the wiring CL functions as the upper electrode of the capacitor element 13. On the contrary, the node FN functions as the lower electrode of the capacitor element 13. That is, the capacitor element 13 constitutes a MIM (Metal-Insulator-Metal) capacitor. In addition, it can also be said that the memory cell 10 includes the capacitor element 13 between the node FN and the wiring CL.

[0061] The memory cell 10 has a function of holding the potential (charge) written in the node FN and storing data. Specifically, a potential for turning on the transistor 12 is supplied to the wiring WL, and the wiring WBL and the node FN are brought into a conductive state. Then, the charge for setting the node FN to a predetermined potential is supplied to the node FN via the wiring WBL. Thereafter, a potential for turning off the transistor 12 is supplied to the gate of the transistor 12. By turning off the transistor 12, the charge written in the node FN is held.

[0062] Also, when reading the data stored in the memory cell 10, a constant potential (hereinafter sometimes referred to as a read potential) may be applied to the wiring CL. When the read potential is supplied to the wiring CL, the transistor 11 becomes on or off according to the potential written to the node FN. That is, the data stored in the node FN of the memory cell 10 can be read as the on or off state of the transistor 11.

[0063] The semiconductor layers of the transistor 12 and the transistor 11 can be used singly or in combination, such as single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor. As the semiconductor material, for example, silicon, germanium, etc. can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductor, and nitride semiconductor may be used.

[0064] Note that the semiconductor layers used for the transistor may be laminated. When laminating the semiconductor layers, semiconductors having different crystal states may be used, or different semiconductor materials may be used.

[0065] In particular, the transistor 12 is preferably an OS transistor. Since the oxide semiconductor has a band gap of 2 eV or more, the off-current is extremely small. When an OS transistor is used for the transistor 12, the charge written to the node FN can be held for a long time. Therefore, the capacitance required for the capacitive element 13 can be reduced. For this reason, by using an OS transistor for the transistor 12, the occupied area of the capacitive element 13 can be reduced. Thereby, it becomes easier to arrange the capacitive element 13 on the transistors 11 and 12, so that the occupied area of the memory cell 10 can be reduced. When an OS transistor is used for the transistor 12, the memory cell 10 can be called an "OS memory".

[0066] The OS memory can retain the information written for a period of one year or more, and even for a period of ten years or more, even when the power supply is stopped. Therefore, the OS memory can also be regarded as a non-volatile memory.

[0067] In addition, since the amount of charge written in the OS memory hardly changes over a long period of time, the OS memory can retain not only binary (1-bit) but also multi-valued (multi-bit) information.

[0068] In addition, since the OS memory writes charges to the node via the OS transistor, the high voltage required in the conventional flash memory is not necessary, and a high-speed writing operation can be realized. Also, the erasing operation before data rewriting performed in the flash memory is not necessary in the OS memory. Also, since charge injection and extraction into the floating gate or charge trapping layer are not performed, in the OS memory, the number of times of writing and reading data can be made substantially unlimited. The OS memory has less degradation and higher reliability compared to the conventional flash memory.

[0069] In addition, the OS memory does not involve structural changes at the atomic level like phase change memory (PCM), magnetoresistive random access memory (MRAM), or resistive random access memory (ReRAM). Therefore, the OS memory is more resistant to rewriting than phase change memory, magnetoresistive memory, and resistive change memory.

[0070] In addition, the OS transistor has almost no increase in the off-current even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Also, the on-current is less likely to decrease even in a high-temperature environment. A storage device including the OS memory operates stably even in a high-temperature environment and can obtain high reliability. Therefore, when configuring the OS memory, it is preferable to use transistors 11 and 12 as OS transistors. Further, the OS transistor has a high breakdown voltage between the source and the drain. By using the OS transistor as the transistor constituting the semiconductor device, a semiconductor device with stable operation and good reliability can be realized even in a high-temperature environment.

[0071] As shown in FIGS. 3A and 3B, etc., the memory cell 10 includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, an insulator 216 on the insulator 214, an insulator 222 on the insulator 216, an insulator 224 on the insulator 222, an insulator 275 on the insulator 224, an insulator 280 on the insulator 275, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282. The insulators 212, 214, 216, 222, 224, 275, 280, 282, and 283 function as interlayer insulating films. Transistors 11 and 12 are provided in a layer between the insulator 214 and the insulator 282, and a capacitor element 13 is provided on the insulator 280. Openings reaching the other of the source or drain of the transistor 12 are formed in the insulator 280 and the insulator 275, and a conductor 240 is provided so as to be embedded in the openings. Further, it is preferable that an insulator 241 is provided in contact with the side surface of the conductor 240.

[0072] Transistor 11 has a conductor 205 (conductor 205a, conductor 205b, and conductor 205c) arranged to be embedded in an insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 230c, an oxide 243a, and an oxide 243b on the oxide 230b, a conductor 242a on the oxide 243a, a conductor 242b on the oxide 243b, an insulator 250 on the oxide 230c, and a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping a part of the oxide 230b. Hereinafter, the oxides 230a, 230b, and 230c may be collectively referred to as oxide 230. Also, the oxides 243a and 243b may be collectively referred to as oxide 243. Also, the conductors 242a and 242b may be collectively referred to as conductor 242.

[0073] Here, the conductor 260 functions as a top gate, and the conductor 205 functions as a back gate (wiring BGL1). Also, the insulator 250 functions as a gate insulator of the top gate, and the insulators 222 and 224 function as gate insulators of the back gate. Also, the conductor 242a functions as one of the source or drain, and the conductor 242b functions as the other of the source or drain. Also, at least a part of the region of the oxide 230 that overlaps the conductor 260 functions as a channel formation region.

[0074] Also, an insulator 275 covers the insulator 224, the oxides 230a, 230b, 243, and the conductor 242, and an insulator 280 is provided in contact with the upper surface of the insulator 275. Openings reaching the oxide 230b and the insulator 224 are provided in the insulator 280 and the insulator 275, and the openings are provided to overlap the region between the conductor 242a and the conductor 242b.

[0075] As shown in FIGS. 2B, 3A, and 3B, an oxide 230c, an insulator 250, and a conductor 260 are disposed in the opening. Thus, the oxide 230c is provided in contact with the upper surface of the insulator 224, the side surface of the oxide 230a, the upper surface and side surface of the oxide 230b, the side surfaces of the oxides 243a and 243b, the side surfaces of the conductors 242a and 242b, the side surface of the insulator 275, and the side surface of the insulator 280. Further, the insulator 250 is provided in contact with the upper surface and side surface of the oxide 230c, and the conductor 260 is provided in contact with the upper surface and side surface of the insulator 250. Also, the upper surface of the conductor 260, the uppermost surface of the insulator 250, and the uppermost surface of the oxide 230c are arranged to substantially coincide with the upper surface of the insulator 280.

[0076] With such a structure, the conductor 260, the insulator 250, and the oxide 230c can be self-alignedly formed so as to be embedded in the opening formed in the insulator 280 or the like. By forming the conductor 260 or the like in this way, the conductor 260 can be disposed in the region between the conductors 242a and 242b without alignment.

[0077] Further, the transistor 12 includes conductors 206 (conductors 206a, 206b, and 206c) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductors 206, an insulator 224 on the insulator 222, an oxide 231a on the insulator 224, an oxide 231b on the oxide 231a, oxides 231c, 245a, and 245b on the oxide 231b, a conductor 244a on the oxide 245a, a conductor 244b on the oxide 245b, an insulator 251 on the oxide 231c, and conductors 261 (conductors 261a and 261b) located on the insulator 251 and overlapping a part of the oxide 231b. Hereinafter, the oxides 231a, 231b, and 231c may be collectively referred to as the oxide 231. Also, the oxides 245a and 245b may be collectively referred to as the oxide 245. Further, the conductors 244a and 244b may be collectively referred to as the conductor 244.

[0078] Note that the transistor 12 has the same configuration as the transistor 11. Therefore, the conductor 206 and the conductor 205, the oxide 231 and the oxide 230, the insulator 251 and the insulator 250, and the conductor 261 and the conductor 260 are formed in the same layer and have the same configuration. Therefore, in the following, the description of the conductor 206 as that of the conductor 205, the oxide 231 as that of the oxide 230, the insulator 251 as that of the insulator 250, and the conductor 261 as that of the conductor 260 can be referred to.

[0079] Here, the conductor 261 functions as a top gate, and the conductor 206 functions as a back gate (wiring BGL2). Also, the insulator 251 functions as a gate insulator of the top gate, and the insulators 222 and 224 function as gate insulators of the back gate. Further, the conductor 244a functions as one of a source or a drain, and the conductor 244b functions as the other of the source or the drain. Also, at least a part of the region of the oxide 231 that overlaps with the conductor 261 functions as a channel formation region.

[0080] Also, the insulator 275 covers the insulator 224, the oxides 231a, 231b, 245, and the conductor 244, and the insulator 280 is provided in contact with the upper surface of the insulator 275. Openings reaching the oxide 231b and the insulator 224 are provided in the insulator 280 and the insulator 275, and the openings are provided to overlap with the region between the conductor 244a and the conductor 244b.

[0081] As shown in FIGS. 2B, 3A, and 3B, an oxide 231c, an insulator 251, and a conductor 261 are disposed in the opening. Thus, the oxide 231c is provided in contact with the upper surface of the insulator 224, the side surface of the oxide 231a, the upper and side surfaces of the oxide 231b, the side surfaces of the oxides 245a and 245b, the side surfaces of the conductors 244a and 244b, the side surface of the insulator 275, and the side surface of the insulator 280. Further, the insulator 251 is provided in contact with the upper and side surfaces of the oxide 231c, and the conductor 261 is provided in contact with the upper and side surfaces of the insulator 251. Also, the upper surface of the conductor 261, the uppermost surface of the insulator 251, and the uppermost surface of the oxide 231c are disposed substantially flush with the upper surface of the insulator 280.

[0082] With such a structure, the conductor 261, the insulator 251, and the oxide 231c can be self-alignedly formed so as to be embedded in the opening formed in the insulator 280 or the like. By forming the conductor 261 and the like in this way, the conductor 261 can be disposed in the region between the conductors 244a and 244b without alignment.

[0083] The capacitor element 13 includes a conductor 207 disposed in contact with the upper surface of the conductor 240 and the upper surface of the conductor 260, an insulator 282 disposed on the insulator 280 and the conductor 207, and a conductor 208 disposed on the insulator 282 and at least partially overlapping the conductor 207.

[0084] Here, the conductor 207 functions as a node FN, and the conductor 208 functions as a wiring CL. In other words, the conductor 207 functions as a lower electrode of the capacitor element 13, and the conductor 208 functions as an upper electrode of the capacitor element 13. Also, the insulator 282 functions as a dielectric of the capacitor element 13.

[0085] As shown in FIG. 2A, in a top view, the conductor 207 preferably includes the conductor 260. In other words, the conductor 207 is preferably disposed to cover the conductor 260. Also, in a top view, the conductor 207 may also include the conductor 240. With such a configuration, the capacitor element 13 can be disposed to cover the top gate of the transistor 11 and overlap with the other of the source or drain of the transistor 12. Therefore, the area of the capacitor element 13 can be increased without substantially increasing the area of the transistors 11 and 12.

[0086] Also, as shown in FIGS. 1B, 3A, and 3B, the insulator 282 is preferably disposed to cover the conductor 207, and the conductor 208 is preferably disposed to cover the conductor 207 via the insulator 282. Thereby, the conductor 208 is also disposed via the insulator 282 on the side surface of the conductor 207. Therefore, the entire region where the conductor 208 and the conductor 207 overlap and the side surface of the conductor 207 can function as the capacitor element 13.

[0087] With the above configuration, the occupied area of the memory cell 10 can be reduced and the capacitor element 13 can be provided. Thereby, high integration of the semiconductor device can be achieved, and a semiconductor device with a large storage capacity can be provided. Also, a semiconductor device with a low manufacturing cost per storage capacity can be provided.

[0088] Also, the conductor 209 is disposed in contact with the upper surface of the conductor 261. The conductor 209 can be formed in the same layer as the conductor 207 and is covered by the insulator 282. The conductor 209 functions as the wiring WL.

[0089] Note that a memory cell array can be formed by arranging a plurality of memory cells 10 in a matrix. In this case, the wiring connecting each memory cell 10 is preferably provided to extend in one direction. For example, as shown in FIGS. 1A and 1B, the wiring CL (conductor 208), the wiring WL (conductor 209), the wiring BGL1 (conductor 205), and the wiring BGL2 (conductor 206) may be provided to extend in the y direction. At this time, each memory cell 10 arranged in the y direction will be connected to the common wiring CL (conductor 208), the wiring WL (conductor 209), the wiring BGL1 (conductor 205), and the wiring BGL2 (conductor 206).

[0090] Also, for example, if the conductor 261 is provided to extend as the wiring WL, a parasitic transistor will be formed at the location where the wiring WL and the oxide 230b overlap. However, in this embodiment, the conductor 209 disposed on the conductor 261 functions as the wiring WL. As a result, as shown at A5 in FIG. 3B, the conductor 209 and the oxide 230b overlap via an insulator 280 or the like. Therefore, it is possible to suppress the formation of a parasitic transistor at the location where the conductor 209 and the oxide 230b overlap.

[0091] Also, when arranging a plurality of memory cells 10 in the x direction, one of the source or drain of the transistor 11 of the memory cell 10 is connected to the other of the source or drain of the transistor 11 of the adjacent memory cell 10. Also, one of the source or drain of the transistor 12 of the memory cell 10 is connected to the other of the source or drain of the transistor 12 of the adjacent memory cell 10. That is, the sources and drains of the plurality of transistors 11 are connected in series, and the sources and drains of the plurality of transistors 12 are also connected in series. In other words, in the memory cell 10, one of the source or drain of the transistor 12 is electrically connected to the wiring WBL via another transistor 12, one of the source or drain of the transistor 11 is electrically connected to the wiring RBL via another transistor 11, and the other of the source or drain of the transistor 11 is electrically connected to the wiring SL via another transistor 11.

[0092] In this case, the node FN of the memory cell 10 is connected to the other of the source or drain of the transistor 12 of the memory cell 10 and one of the source or drain of the transistor 12 of the adjacent memory cell 10. Therefore, the potential (charge) written to the node FN can be held by turning off the transistor 12 of each memory cell 10 and turning off the transistor 12 of the adjacent memory cell 10.

[0093] When adopting the above configuration, as shown in FIG. 1B, the oxide 230b and the oxide 230a, and the oxide 231b and the oxide 231a may be provided so as to extend in the x direction, respectively. Thereby, the transistor 11 can be formed at the overlapping portion of the oxide 230b and the conductor 208, and the transistor 12 can be formed at the overlapping portion of the oxide 231b and the conductor 209. Here, the channel length direction of the transistor 11 and the channel length direction of the transistor 12 are substantially parallel. Also, the channel length direction of the transistor 11 and the extension direction of the conductor 208 are substantially perpendicular. Also, the channel length direction of the transistor 12 and the extension direction of the conductor 209 are substantially perpendicular.

[0094] Also, although the region overlapping with the conductor 260 is removed, the oxide 243 and the conductor 242 may be arranged to extend in the x direction in the same manner as the oxide 230b. Also, although the region overlapping with the conductor 261 is removed, the oxide 245 and the conductor 244 may be arranged to extend in the x direction in the same manner as the oxide 231b.

[0095] Note that the configuration of the memory cell 10 is not limited to the above. For example, in each memory cell 10, the wiring RBL and the wiring SL may be connected to the transistor 11, and the transistor 12 may be connected to the wiring WBL. In this case, the oxide 230b, the oxide 231b, etc. are not provided to extend, but are provided by being patterned in an island shape in each memory cell 10. Therefore, the potential (charge) written to the node FN can be held only by turning off the transistor 12 of each memory cell 10.

[0096] Also, details of the memory cell array in which a plurality of memory cells 10 are arranged in a matrix will be described in a later embodiment.

[0097] Next, FIG. 4 shows an enlarged view of the vicinity of the channel formation region of the transistor 11 in FIG. 3B. In the following, the oxide 230 of the transistor 11 will be described, but the description can also be referred to for the oxide 231 of the transistor 12. As shown in FIG. 4, the oxide 230 has a region 232c that functions as the channel formation region of the transistor 11, a region 232a that is provided so as to sandwich the region 232c and functions as the source region or the drain region of the transistor 11, and a region 232b.

[0098] At least a part of the region 232c overlaps with the conductor 260. In other words, the region 232c is provided in the region between the conductor 242a and the conductor 242b. The region 232a is provided to overlap with the conductor 242a, and the region 232b is provided to overlap with the conductor 242b.

[0099] The region 232c that functions as a channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the regions 232a and 232b. Therefore, the region 232c can be said to be of i-type (intrinsic) or substantially i-type.

[0100] Also, the regions 232a and 232b that function as a source region or a drain region are regions with an increased carrier concentration and a lower resistance due to a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, or a metal element. That is, the regions 232a and 232b are n-type regions with a higher carrier concentration and a lower resistance compared to the region 232c.

[0101] Here, the carrier concentration of the region 232c that functions as a channel formation region is preferably 18 cm -3 or less, more preferably 17 cm -3 less than, even more preferably 16 cm -3 less than, even more preferably 13 cm -3 less than, even more preferably 12 cm -3 less than. Note that the lower limit value of the carrier concentration of the region 232c that functions as a channel formation region is not particularly limited, but for example, it can be -9 cm -3 .

[0102] Also, a region may be formed between region 232c and region 232a or region 232b, where the carrier concentration is equal to or lower than the carrier concentrations of regions 232a and 232b and equal to or higher than the carrier concentration of region 232c. That is, the region functions as a junction region between region 232c and region 232a or region 232b. The hydrogen concentration in the junction region may be equal to or lower than the hydrogen concentrations of regions 232a and 232b and equal to or higher than the hydrogen concentration of region 232c. Also, the oxygen deficiency in the junction region may be equal to or less than the oxygen deficiencies of regions 232a and 232b and equal to or more than the oxygen deficiency of region 232c.

[0103] Also, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes from region to region but may also change continuously within each region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0104] For the transistor 11, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 including the channel formation region. The oxide 230 preferably has oxide 230a disposed on the insulator 224, oxide 230b disposed on oxide 230a, and oxide 230c disposed on oxide 230b. In the following, the oxide 230 of the transistor 11 will be described, but the description can also be referred to for the oxide 231 of the transistor 12.

[0105] In addition, as the metal oxide functioning as a semiconductor, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced. By using a metal oxide with a large band gap, the off-currents of transistor 11 and transistor 12 can be reduced. In particular, by reducing the off-current of transistor 12, when transistors 11 and 12 are used as memory cells of a memory device, it is possible to hold the stored content for a long time. That is, the memory device does not require a refresh operation, or the frequency of the refresh operation can be extremely low. Also, thereby, the power consumption of the memory device can be sufficiently reduced.

[0106] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. For example, as the oxide 230, an In-Ga-Zn oxide may be used, or an oxide obtained by adding tin to the In-Ga-Zn oxide may also be used. Also, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0107] The above metal oxide can be formed on a substrate using a sputtering method or the like. Therefore, transistors 11 and 12 can be provided on top of peripheral circuits such as a drive circuit formed on a silicon substrate. Thus, when transistors 11 and 12 are used as memory cells of a memory device, the occupied area of a memory cell array that can be provided on one chip can be increased, so that the storage capacity of the memory device can be increased. Further, by forming a plurality of the above metal oxide films stacked, a memory cell array can be provided in a stacked manner. Thereby, cells can be integrated and arranged without increasing the occupied area of the memory cell array. That is, a stacked structure of a memory cell array (hereinafter, may be referred to as a 3D cell array) can be configured. As described above, high integration of memory cells can be achieved, and a semiconductor device with a large storage capacity can be provided.

[0108] Note that the method for forming the above metal oxide is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. may be appropriately used.

[0109] Here, it is preferable that the atomic number ratio of In to element M in the metal oxide used for oxide 230b is larger than the atomic number ratio of In to element M in the metal oxide used for oxide 230a. Oxide 230c may use the metal oxide that can be used for oxide 230b or the metal oxide that can be used for oxide 230a.

[0110] Specifically, as the oxide 230a, a metal oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof may be used. Further, as the oxide 230b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 5:1:3 [atomic ratio] or in the vicinity thereof may be used. Note that the vicinity of the composition includes a range of ±30% of the desired atomic ratio. Further, as the element M, it is preferable to use gallium.

[0111] Note that when forming a film of the metal oxide by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, and may be the atomic ratio of the sputtering target used for forming the metal oxide.

[0112] By disposing the oxide 230a under the oxide 230b, diffusion of impurities and oxygen from the structure formed below the oxide 230a to the oxide 230b can be suppressed. Further, by disposing the oxide 230c on the oxide 230b, diffusion of impurities and oxygen from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

[0113] However, the oxide 230 is not limited to a configuration in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, or a configuration having a stacked structure of four or more layers may be provided, or each of the oxide 230a, the oxide 230b, or the oxide 230c may have a stacked structure. For example, the oxide 230c may have a two-layer stacked structure. In this case, as the oxide 230c, a metal oxide that can be used for the oxide 230b may be provided, and a metal oxide that can be used for the oxide 230a may be provided thereon.

[0114] In addition, since the oxide 230a, the oxide 230b, and the oxide 230c have a common element other than oxygen (as the main component), the density of defect levels at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced. Since the density of defect levels at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced, the influence on carrier conduction due to interface scattering is small, and a high on-current can be obtained.

[0115] Here, at the junction between the oxide 230a and the oxide 230b and at the junction between the oxide 230b and the oxide 230c, the lower end of the conduction band changes smoothly. In other words, it can also be said that the lower end of the conduction band at the junction between the oxide 230a and the oxide 230b and at the junction between the oxide 230b and the oxide 230c changes continuously or is continuously joined. To achieve this, it is preferable to reduce the density of defect levels in the mixed layer formed at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c.

[0116] The oxide 230b preferably has crystallinity respectively. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 230b. Also, CAAC-OS may be used for the oxide 230a or the oxide 230c.

[0117] CAAC-OS has a highly crystalline and dense structure, and is a metal oxide with few impurities and defects (for example, oxygen vacancies (also referred to as V O :oxygen vacancy)). In particular, by performing heat treatment at a temperature at which the metal oxide does not polycrystallize (for example, 400°C or higher and 600°C or lower) after the formation of the metal oxide, CAAC-OS can be made to have a more highly crystalline and dense structure. In this way, by increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0118] On the one hand, since it is difficult to confirm distinct crystal grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0119] In a transistor using an oxide semiconductor, when impurities and oxygen deficiencies are present in the region where the channel in the oxide semiconductor is formed, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Further, hydrogen near the oxygen deficiency may form a defect in which hydrogen enters the oxygen deficiency (hereinafter sometimes referred to as VH).) and generate electrons serving as carriers even when no voltage is applied to the gate electrode of the transistor. For this reason, when the region where the channel in the oxide semiconductor is formed contains oxygen deficiencies, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists without applying a voltage to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, it is preferable that impurities, oxygen deficiencies, and VH are reduced as much as possible. In other words, the region where the channel in the oxide semiconductor is formed has a reduced carrier concentration in a state where no voltage is applied to the gate electrode of the transistor, and is preferably i-type (intrinsic) or substantially i-type. O H is sometimes called.) and may generate electrons serving as carriers even when no voltage is applied to the gate electrode of the transistor. For this reason, when the region where the channel in the oxide semiconductor is formed contains oxygen deficiencies, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists without applying a voltage to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, impurities, oxygen deficiencies, and VH O H are preferably reduced as much as possible. In other words, the region where the channel in the oxide semiconductor is formed has a reduced carrier concentration in a state where no voltage is applied to the gate electrode of the transistor, and is preferably i-type (intrinsic) or substantially i-type.

[0120] On the other hand, by providing an insulator containing oxygen that desorbs by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen deficiencies and VH O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, there is a risk of causing a decrease in the on-current or a decrease in the field-effect mobility of transistors 11 and 12. Further, if the oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0121] Therefore, in the oxide semiconductor, the region 232c that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 232a and 232b that function as a source region or a drain region preferably have a high carrier concentration and are n-type. That is, it is preferable to reduce the oxygen deficiency and VH in the region 232c of the oxide semiconductor, and not to supply an excessive amount of oxygen to the regions 232a and 232b. O O It is preferable to reduce the oxygen deficiency and VH in the region 232c of the oxide semiconductor, and not to supply an excessive amount of oxygen to the regions 232a and 232b.

[0122] Therefore, with the conductors 242a and 242b provided on the oxide 230b, it is preferable to perform microwave treatment in an oxygen-containing atmosphere to reduce the oxygen deficiency and VH in the region 232c. Here, the microwave treatment refers to, for example, a treatment using a device having a power source for generating high-density plasma using microwaves. At the same time, in the transistor 12 as well, microwave treatment is performed in an oxygen-containing atmosphere with the conductors 244a and 244b provided. O O By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 232c. By the action of plasma, microwaves, etc., the VH in the region 232c is segmented, hydrogen H is removed from the region 232c, and the oxygen deficiency V can be filled with oxygen. That is, in the region 232c, the reaction "VH → H + V" occurs, and the hydrogen concentration in the region 232c can be reduced. Therefore, the oxygen deficiency and VH in the region 232c can be reduced, and the carrier concentration can be decreased.

[0123] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 232c. By the action of plasma, microwaves, etc., the VH in the region 232c is segmented, hydrogen H is removed from the region 232c, and the oxygen deficiency V can be filled with oxygen. That is, in the region 232c, the reaction "VH → H + V" occurs, and the hydrogen concentration in the region 232c can be reduced. Therefore, the oxygen deficiency and VH in the region 232c can be reduced, and the carrier concentration can be decreased. O O By the action of plasma, microwaves, etc., the VH in the region 232c is segmented, hydrogen H is removed from the region 232c, and the oxygen deficiency V can be filled with oxygen. O O That is, in the region 232c, the reaction "VH → H + V" occurs, and the hydrogen concentration in the region 232c can be reduced. O O That is, in the region 232c, the reaction "VH → H + V" occurs, and the hydrogen concentration in the region 232c can be reduced. O O That is, in the region 232c, the reaction "VH → H + V" occurs, and the hydrogen concentration in the region 232c can be reduced. O O Therefore, the oxygen deficiency and VH in the region 232c can be reduced, and the carrier concentration can be decreased.

[0124] In addition, when performing microwave treatment in an oxygen-containing atmosphere, the actions of microwaves, high frequencies such as RF, and oxygen plasma are shielded by the conductors 242a and 242b and do not reach the regions 232a and 232b. Furthermore, the action of the oxygen plasma can be reduced by the insulators 275 and 280 provided to cover the oxide 230b and the conductor 242. As a result, during microwave treatment, in the regions 232a and 232b, O reduction of V O H and excessive oxygen supply do not occur, so a decrease in carrier concentration can be prevented.

[0125] In this way, oxygen deficiency and V O H can be selectively removed in the region 232c of the oxide semiconductor, and the region 232c can be made into an i-type or substantially i-type. Furthermore, supply of excessive oxygen to the regions 232a and 232b that function as a source region or a drain region can be suppressed, and the n-type can be maintained. Thereby, variations in the electrical characteristics of the transistor 11 can be suppressed, and variations in the electrical characteristics of the transistor 11 within the substrate surface can be suppressed. Note that the same effect can be obtained for the transistor 12. O By adopting the above configuration, a semiconductor device with little variation in transistor characteristics can be provided. In addition, a semiconductor device having good electrical characteristics can be provided. In addition, a semiconductor device with good reliability can be provided.

[0126] In FIGS. 3A, 3B, etc., the side surface of the opening for embedding the conductor 260 etc. is substantially perpendicular to the formation surface of the oxide 230b including the groove portion of the oxide 230b, but the present embodiment is not limited to this. For example, the bottom of the opening may have a gentle curved surface and may have a U-shaped form. Further, for example, the side surface of the opening may be inclined with respect to the formation surface of the oxide 230b.

[0127]

[0128] ​Also, as shown in FIG. 3A, in a cross-sectional view in the channel width direction of the transistor 11, a curved surface may be provided between the side surface and the upper surface of the oxide 230b. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter also referred to as round).

[0129] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half of the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. By adopting such a shape, the covering properties of the insulator 250 and the conductor 260 on the oxide 230b can be improved.

[0130] At least one of the insulator 212, the insulator 214, the insulator 275, the insulator 282, and the insulator 283 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistors 11 and 12 into the transistors 11 and 12. Therefore, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms (the above impurities are difficult to permeate) for at least one of the insulator 212, the insulator 214, the insulator 275, the insulator 282, and the insulator 283. Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate).

[0131] In this specification, the barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier property refers to a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability). Alternatively, it refers to a function of capturing and fixing the corresponding substance (also referred to as gettering).

[0132] As the insulator 212, insulator 214, insulator 275, insulator 282, and insulator 283, for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, as the insulator 212 and the insulator 283, it is preferable to use silicon nitride or the like which has a higher hydrogen barrier property. Further, for example, as the insulator 214, the insulator 275, and the insulator 282, it is preferable to use aluminum oxide or magnesium oxide or the like which has a high function of capturing hydrogen and fixing hydrogen. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 11 and the transistor 12 side through the insulator 212 and the insulator 214. Or, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed above the insulator 283 to the transistor 11 and the transistor 12 side. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 212 and the insulator 214. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 280 or the like above the transistor 11 and the transistor 12 through the insulator 282 or the like. In this way, it is preferable to form a structure in which the transistors 11 and 12 are surrounded by the insulator 212, the insulator 214, the insulator 275, the insulator 282, and the insulator 283 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0133] Here, when using aluminum oxide or the like as the insulator 212, the insulator 214, the insulator 275, the insulator 282, and the insulator 283, it is preferable to use an oxide having an amorphous structure. For example, AlO x (x is an arbitrary number greater than 0), or MgO yIt is preferable to use a metal oxide such as (where y is any number greater than 0). In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of transistors 11 and 12 or by providing it around transistors 11 and 12, hydrogen contained in transistors 11 and 12 or hydrogen existing around transistors 11 and 12 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation regions of transistors 11 and 12. By using a metal oxide having an amorphous structure as a component of transistors 11 and 12 or by providing it around transistors 11 and 12, transistors 11 and 12 and a semiconductor device having good characteristics and high reliability can be fabricated.

[0134] Also, when using aluminum oxide or the like, the insulators 212, 214, 275, 282, and 283 preferably have an amorphous structure, but a region having a polycrystalline structure may be formed partially. Further, the insulators 212, 214, 275, 282, and 283 may have a multilayer structure in which an amorphous structure layer and a polycrystalline structure layer are laminated. For example, a laminated structure in which a polycrystalline structure layer is formed on an amorphous structure layer may be used.

[0135] The film formation of the insulators 212, 214, 275, 282, and 283 may be performed, for example, using a sputtering method. Since the sputtering method does not require hydrogen to be used as a film formation gas, the hydrogen concentration of the insulators 212, 214, 275, 282, and 283 can be reduced. Note that the film formation method is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.

[0136] Also, it may be preferable to lower the resistivity of the insulator 212 and the insulator 283. For example, by setting the resistivity of the insulator 212 and the insulator 283 to approximately 1×10 13 Ωcm, in a process using plasma or the like in the semiconductor device manufacturing process, the insulator 212 and the insulator 283 may be able to mitigate the charge-up of the conductor 205, the conductor 242, or the conductor 260. The resistivity of the insulator 212 and the insulator 283 is preferably 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.

[0137] Also, the insulator 216 and the insulator 280 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 216 and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide having pores, etc. may be appropriately used.

[0138] In the transistor 11, the conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. The conductor 205 may be provided to extend in the y direction as shown in FIG. 1B or the like. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. In the following, the conductor 205 of the transistor 11 will be described, but the description can also be referred to for the conductor 206 of the transistor 12.

[0139] The conductor 205 includes a conductor 205a, a conductor 205b, and a conductor 205c. The conductor 205a is provided in contact with the bottom surface and the side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is substantially the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. That is, the conductor 205b is configured to be wrapped by the conductor 205a and the conductor 205c.

[0140] Here, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms for the conductor 205a and the conductor 205c. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0141] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 through the insulator 224 or the like. In addition, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a and the conductor 205c, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, as the conductor 205a, the above conductive material may be used as a single layer or a laminate. For example, titanium nitride may be used for the conductor 205a.

[0142] In addition, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0143] The conductor 205 may function as a back gate electrode. In that case, the threshold voltage (Vth) of the transistor 11 can be controlled by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 11 can be made larger and the off-current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no negative potential is applied.

[0144] Also, the electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. Also, the film thickness of the insulator 216 becomes almost the same as that of the conductor 205. Here, it is preferable to reduce the film thicknesses of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the film thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that the diffusion of the impurities into the oxide 230 can be reduced.

[0145] Note that, as shown in FIGS. 3A and 3B, the conductor 205 may be provided to be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, the conductor 205 preferably extends also in a region outside the end portions intersecting with the channel width direction of the oxides 230a and 230b. That is, outside the side surfaces in the channel width direction of the oxide 230, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator. By having such a configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as a top gate electrode and the electric field of the conductor 205 functioning as a back gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the top gate and the back gate is referred to as a surrounded channel (S-channel) structure.

[0146] Note that, in this specification and the like, an S-channel structure transistor refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Also, the S-channel structure disclosed in this specification and the like is different from a Fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to increase the resistance to the short channel effect, in other words, to make a transistor in which the short channel effect hardly occurs.

[0147] Also, as shown in FIG. 1B and the like, the conductor 205 is extended to function also as a wiring. However, it is not limited thereto, and a configuration may be adopted in which a conductor functioning as a wiring is provided under the conductor 205. Also, the conductor 205 does not necessarily need to be provided one by one for each transistor. For example, a configuration may be adopted in which the conductor 205 is shared by a plurality of transistors.

[0148] Note that, although a configuration in which the conductor 205 is formed by laminating the conductor 205a, the conductor 205b, and the conductor 205c is shown, the present invention is not limited to this. The conductor 205 may be provided in a single-layer, two-layer, or four-layer or more laminated structure. For example, when the conductor 205 has a two-layer laminated structure, the conductor 205c may be omitted, and the upper surface of the conductor 205a and the upper surface of the conductor 205b may be made to coincide with each other.

[0149] The insulator 222 and the insulator 224 function as gate insulators corresponding to the back gates of the transistor 11 and the transistor 12.

[0150] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). Further, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0151] As the insulator 222, an insulator containing one or both of oxides of aluminum and hafnium, which are insulating materials, may be used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and the oxide 231 to the substrate side and the diffusion of impurities such as hydrogen from the peripheral portions of the transistor 11 and the transistor 12 to the oxide 230 and the oxide 231. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen to the inside of the transistor 11 and the transistor 12, and to suppress the generation of oxygen vacancies in the oxide 230 and the oxide 231. Further, it is possible to suppress the reaction between the conductor 205 and the conductor 206 and the oxygen possessed by the insulator 224 and the oxide 230 and the oxide 231.

[0152] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Further, the insulator 222 may be used by laminating silicon oxide, silicon oxynitride or silicon nitride on these insulators.

[0153] Further, the insulator 222 may be used in a single layer or in a laminate of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator functioning as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0154] The insulator 224 in contact with the oxide 230 and the oxide 231 preferably contains excess oxygen (oxygen is desorbed by heating). For example, the insulator 224 may be appropriately silicon oxide, silicon oxynitride, etc. By providing an oxygen-containing insulator in contact with the oxide 230 and the oxide 231, oxygen deficiency in the oxide 230 and the oxide 231 can be reduced, and the reliability of the transistors 11 and 12 can be improved.

[0155] Specifically, as the insulator 224, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating, in other words, an insulator material having an excess oxygen region. An oxide from which oxygen is desorbed by heating means that in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, more preferably 2.0×1019 molecules / cm 3 or more than, or 3.0×10 20 molecules / cm 3 The oxide film is the one with the above or more. Note that as the surface temperature of the film during the above TDS analysis, a range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less is preferable.

[0156] Also, during the manufacturing process of transistor 11 and transistor 12, it is preferable to perform heat treatment with the surfaces of oxide 230 and oxide 231 exposed. The heat treatment may be performed, for example, at 100°C or more and 600°C or less, more preferably 350°C or more and 550°C or less. Note that the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. Thereby, oxygen can be supplied to oxide 230 and oxide 231 to reduce oxygen vacancies (V O ). Also, the heat treatment may be performed under reduced pressure. Or, after performing heat treatment in an atmosphere of nitrogen gas or inert gas, in order to supplement the desorbed oxygen, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. Or, after performing heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or inert gas.

[0157] Note that by performing an oxygen addition treatment on oxide 230 and oxide 231, oxygen vacancies in oxide 230 and oxide 231 are repaired by the supplied oxygen, in other words, the reaction of "V O +O→null" can be promoted. Further, by reacting the oxygen supplied to the hydrogen remaining in oxide 230 and oxide 231, the hydrogen can be removed (dehydrated) as H2O. Thereby, it is possible to suppress the recombination of the hydrogen remaining in oxide 230 and oxide 231 with oxygen vacancies to form V O H.

[0158] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. Further, the insulator 224 may be formed in an island shape so as to overlap with the oxide 230a and the oxide 231a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the upper surface of the insulator 222.

[0159] The oxide 243a and the oxide 243b are provided on the oxide 230b. The oxide 243a and the oxide 243b are provided so as to be separated from each other with the conductor 260 interposed therebetween. In the following, the oxide 243 of the transistor 11 will be described, but the description can also be referred to for the oxide 245 of the transistor 12.

[0160] The oxide 243 (the oxide 243a and the oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. With such a configuration, the electrical characteristics and the reliability of the transistor 11 can be improved. Note that, when the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0161] As the oxide 243, a metal oxide containing an element M may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. It is preferable that the concentration of the element M in the oxide 243 is higher than that in the oxide 230b. Further, gallium oxide may be used as the oxide 243. Also, a metal oxide such as an In-M-Zn oxide may be used as the oxide 243. Specifically, in the metal oxide used for the oxide 243, it is preferable that the atomic ratio of the element M to In is larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, the film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and still more preferably 1 nm or more and 2 nm or less. Also, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, the release of oxygen in the oxide 230 can be preferably suppressed. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal, the release of oxygen in the oxide 230 may be suppressed.

[0162] The conductor 242a is preferably provided in contact with the upper surface of the oxide 243a, and the conductor 242b is preferably provided in contact with the upper surface of the oxide 243b. The conductors 242a and 242b are arranged in the A5-A6 direction and are provided separately with the conductor 260 interposed therebetween. Hereinafter, the conductor 242 of the transistor 11 will be described, but the description can also be referred to for the conductor 244 of the transistor 12.

[0163] As the conductor 242 (conductor 242a and conductor 242b), for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one aspect of the present invention, nitrides containing tantalum are particularly preferred. Also, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. These materials are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen.

[0164] Note that hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a and the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b or the like diffuses into the conductor 242a and the conductor 242b, and the diffused hydrogen may combine with nitrogen that the conductor 242a and the conductor 242b have. That is, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a and the conductor 242b.

[0165] Also, a configuration may be adopted in which a curved surface is not formed between the side surface and the upper surface of the conductor 242. By making the conductor 242 without the formation of the curved surface, the cross-sectional area of the conductor 242 in the cross-section in the channel width direction can be increased. Thereby, the conductivity of the conductor 242 can be increased, and the on-current of the transistor 11 can be increased.

[0166] Insulator 275 is provided to cover insulator 224, oxide 230, oxide 231, oxide 243, oxide 245, conductor 242, and conductor 244, and an opening is formed in the region where conductor 260, conductor 261, conductor 240, etc. are provided. Insulator 275 is preferably provided in contact with the upper surface of insulator 224, the side surface of oxide 230, the side surface of oxide 243, the side surface of conductor 242, the upper surface of conductor 242, the side surface of oxide 231, the side surface of oxide 245, the side surface of conductor 244, and the upper surface of conductor 244. Also, insulator 275 preferably functions as a barrier insulating film that suppresses oxygen permeation. Further, insulator 275 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to insulator 224, oxide 230, or oxide 231, and preferably has a function of capturing impurities such as hydrogen. As insulator 275, for example, an insulator such as aluminum oxide or silicon nitride may be used.

[0167] By providing insulator 275, which has a function of capturing impurities such as hydrogen and is in contact with insulator 280 and insulator 224, within the region sandwiched between insulator 212 and insulator 283, impurities such as hydrogen contained in insulator 280 and insulator 224 can be captured, and the amount of hydrogen in the region can be made constant. In this case, it is preferable to use aluminum oxide or the like as insulator 275.

[0168] In addition, a barrier insulating film having the same shape as conductor 242 and conductor 244 in top view may be provided between insulator 275 and conductor 242 and conductor 244. For the barrier insulating film, an insulator that can be used for insulator 275 may be used.

[0169] Insulator 250 functions as the gate insulator of the top gate of transistor 11. In transistor 11, insulator 250 is preferably disposed to overlap oxide 230b. In the following, insulator 250 of transistor 11 will be described, but the description can also be referred to for insulator 251 of transistor 12.

[0170] The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, etc. In particular, silicon oxide and silicon oxynitride are preferred because they are stable against heat.

[0171] Similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0172] In FIGS. 3A and 3B, the insulator 250 is shown as a single layer, but it may have a laminated structure of two or more layers. When the insulator 250 has a two-layer laminated structure, the lower layer of the insulator 250 is preferably formed using an insulator that releases oxygen upon heating, and the upper layer of the insulator 250 is preferably formed using an insulator having a function of suppressing oxygen diffusion. With such a configuration, it is possible to suppress the diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. Further, it is possible to suppress the oxidation of the conductor 260 by oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be provided using the materials that can be used for the above-described insulator 250, and the upper layer of the insulator 250 can be provided using the same materials as the insulator 222.

[0173] When silicon oxide, silicon oxynitride, etc. are used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material that is a high-k material having a high relative permittivity. By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high relative permittivity can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it is possible to thin the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0174] As the upper layer of the insulator 250, specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230 can be used. In particular, it is preferable to use an insulator containing one or both of aluminum and hafnium oxides. For example, as the insulator 250, a laminated structure including silicon oxide and hafnium oxide on the silicon oxide may be used.

[0175] Also, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Also, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0176] Note that the metal oxide may be configured to have a function as a part of the top gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming the conductor 260a by sputtering, the electrical resistance value of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0177] By having the above metal oxide, it is possible to improve the on-current of the transistor 11 without weakening the influence of the electric field from the conductor 260. Further, by maintaining the distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the above metal oxide, the leakage current between the conductor 260 and the oxide 230 can be suppressed. Further, by providing a laminated structure of the insulator 250 and the above metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted appropriately.

[0178] The conductor 260 functions as the top gate electrode of the transistor 11. In the transistor 11, the conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. Hereinafter, the conductor 260 of the transistor 11 will be described, but the description can also be referred to for the conductor 261 of the transistor 12.

[0179] For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 260b. Further, as shown in FIGS. 3A and 3B, the upper surface of the conductor 260 substantially coincides with the uppermost surface of the insulator 250 and the uppermost surface of the oxide 230c. In FIGS. 3A and 3B, the conductor 260 is shown as a two-layer structure of a conductor 260a and a conductor 260b, but it may be a single-layer structure or a laminated structure of three or more layers.

[0180] For the conductor 260a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0181] In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250 and the resulting decrease in conductivity. As the conductive material having the function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0182] In addition, since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, as the conductor 260b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material.

[0183] Also, as shown in FIG. 3A, in the channel width direction of the transistor 11, when the bottom surface of the insulator 222 is used as a reference, the height of the bottom surface of the region of the conductor 260 where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260 that functions as a gate electrode to cover the side surface and the upper surface of the channel formation region of the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 can easily act on the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 11 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap when the bottom surface of the insulator 222 is used as a reference is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0184] The insulator 280 is provided on the insulator 275, and an opening is formed in a region where the conductor 260, the conductor 261, the conductor 240, etc. are provided. Also, the upper surface of the insulator 280 may be planarized.

[0185] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably provided using, for example, the same material as the insulator 216. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because regions containing oxygen that desorb upon heating can be easily formed.

[0186] The insulator 280 preferably has an excess oxygen region or excess oxygen, similar to the insulator 224. Also, the concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, the insulator 280 may appropriately use oxides containing silicon such as silicon oxide and silicon oxynitride. By providing an insulator having excess oxygen in contact with the oxides 230 and 231, the oxygen deficiency in the oxides 230 and 231 can be reduced, and the reliability of the transistors 11 and 12 can be improved.

[0187] The conductor 240 provided between the transistor 12 and the capacitor element 13 has its lower surface in contact with the conductor 244b and its upper surface in contact with the conductor 207. Further, it is preferable that an insulator 241 is provided in contact with the side surface of the conductor 240 that functions as a plug.

[0188] The insulator 241 is provided in contact with the inner walls of the openings of the insulator 275 and the insulator 280. A first conductor of the conductor 240 is provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 is further provided inside. Note that in FIG. 3A, a configuration in which the first conductor and the second conductor of the conductor 240 are stacked is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers.

[0189] The conductor 240 preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. Further, the conductor 240 may have a laminated structure. When the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the insulators 275 and the conductor in contact with the insulator 280. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Further, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. Thereby, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 from mixing into the oxide 231 through the conductor 240.

[0190] As the insulator 241, for example, insulators such as silicon nitride, aluminum oxide, and silicon oxynitride may be used. Since the insulator 241 is provided in contact with the insulators 275 and 280, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 from mixing into the oxide 230 through the conductor 240. In particular, silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0191] Further, a conductor 207 is provided in contact with the upper surface of the conductor 240 and the upper surface of the conductor 260. Here, the conductor 207 functions as a node FN. That is, the conductor 244b that functions as the other of the source or drain of the transistor 12 is electrically connected to the conductor 260 that functions as the gate of the transistor 11 through the conductor 240 and the conductor 207.

[0192] Further, in the same layer as the conductor 207, a conductor 209 is provided in contact with the upper surface of the conductor 261. Here, the conductor 209 functions as a wiring WL.

[0193] The conductor 207 and the conductor 209 may be formed by patterning the same conductive film. It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 207 and the conductor 209. Further, the conductor 207 and the conductor 209 may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor 207 and the conductor 209 may be formed so as to be embedded in an opening provided in an insulator.

[0194] The insulator 282 covers the conductor 207 and the conductor 209 and is disposed in contact with the upper surface of the insulator 280. Since the insulator 282 functions as a dielectric of the capacitor element 13, it is preferable to use an insulator having a thin equivalent oxide thickness (EOT). Examples of the insulator 282 include aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, a oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, a oxynitride having silicon and hafnium, or a nitride having silicon and hafnium. Note that in this specification, the equivalent oxide thickness refers to a value obtained by converting a physical film thickness into an electrical film thickness equivalent to silicon oxide or silicon oxynitride.

[0195] For example, when aluminum oxide having a relative dielectric constant of 8.5 is used as the insulator 282 and the area of the capacitor element 13 is 61800 nm 2 then, by setting the film thickness of the insulator 282 to 5 nm or less, the capacitance value of the capacitor element 13 can be made 0.9 fF or more. Here, when the film thickness of the insulator 282 is represented using an EOT with a relative dielectric constant of 3.9, the film thickness of the insulator 282 is 2.3 nm.

[0196] If the capacitance value of the capacitor element 13 is 0.9 fF or more, since it is sufficiently larger than the gate capacitance of the transistor 12, data writing and reading of the memory cell 10 can be sufficiently performed. That is, by setting the film thickness of the insulator 282 to about 5 nm or less, the memory cell 10 can function sufficiently as a memory device.

[0197] Further, the insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 280, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, for example, an insulator such as aluminum oxide may be used. By providing the insulator 282 having a function of capturing impurities such as hydrogen in contact with the insulator 280 within the region sandwiched between the insulator 212 and the insulator 283, impurities such as hydrogen contained in the insulator 280 and the like can be captured, and the amount of hydrogen in the region can be made constant.

[0198] Further, the insulator 282 is preferably formed by a sputtering method. For example, film formation may be performed by a sputtering method in an atmosphere containing oxygen. By forming the insulator 282 by a sputtering method, oxygen can be added to the insulator 280. Thereby, the oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230 or the oxide 231 via the oxide 230c or the oxide 231c, so that the oxygen deficiency in the oxide 230 and the oxide 231 can be reduced, and the electrical characteristics and reliability of the transistors 11 and 12 can be improved. However, the film formation method of the insulator 282 is not limited to the sputtering method, and CVD method, MBE method, PLD method, ALD method, etc. may be appropriately used.

[0199] Further, a conductor 208 is provided on the insulator 282 such that at least a part thereof overlaps with the conductor 207. Here, the conductor 208 functions as a wiring CL. The conductor 208 may be a conductor that can be used for the conductor 209 or the like. Note that the conductor 208 may be formed so as to be embedded in an opening provided in the insulator.

[0200] An insulator 283 is provided to cover the insulator 282 and the conductor 208. The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 280. As the insulator 283, it is preferable to use a nitride containing silicon, such as silicon nitride or silicon oxynitride. For example, silicon nitride formed by a sputtering method may be used as the insulator 283. By forming the insulator 283 by a sputtering method, a silicon nitride film with high density and difficult to form voids or the like can be formed. Further, as the insulator 283, silicon nitride formed by a CVD method may be laminated on silicon nitride formed by a sputtering method.

[0201] <Constituent Materials of Semiconductor Device> Hereinafter, the constituent materials that can be used for a semiconductor device will be described.

[0202] Note that the formation of the insulator, conductor, and oxide shown below can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0203] Note that the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD (Photo CVD) method that uses light, and the like. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.

[0204] In addition, as the ALD method, a thermal ALD (Thermal Atomic Layer Deposition) method that performs the reaction of the precursor and the reactant only with thermal energy, a PEALD (Plasma Enhanced Atomic Layer Deposition) method that uses a plasma-excited reactant, etc. can be used.

[0205] <<Substrate>> As the substrate on which the transistor 11 and the transistor 12 are formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), a resin substrate, etc. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. Or, a substrate having a metal nitride, a substrate having a metal oxide, etc. Furthermore, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, etc. Or, those in which elements are provided on these substrates may also be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, etc.

[0206] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties.

[0207] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it becomes possible to reduce the operating voltage of the transistor while maintaining the physical film thickness. On the other hand, for the insulator that functions as the interlayer film, by using a material with a low relative permittivity, the parasitic capacitance generated between the wirings can be reduced. Therefore, materials may be selected according to the function of the insulator.

[0208] In addition, examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0209] Examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin.

[0210] In addition, a transistor using a metal oxide can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a laminated form. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, silicon nitride can be used.

[0211] In addition, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated.

[0212] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Also, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Further, a semiconductor having a high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0213] In addition, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen may be used. Also, a laminated structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0214] In addition, when an oxide is used in the channel formation region of the transistor, it is preferable to use a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen as the conductor functioning as the gate electrode. In this case, it is advisable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is easily supplied to the channel formation region.

[0215] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen included in the metal oxide in which the channel is formed. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0216] <<Metal Oxide>> As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described.

[0217] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Further, in addition to them, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0218] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like. However, there may be cases where a plurality of the aforementioned elements are combined as element M.

[0219] Note that in this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0220] <Classification of Crystal Structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 5A. FIG. 5A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0221] As shown in FIG. 5A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Also, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Also, "Crystal" includes single crystal and poly crystal.

[0222] Note that the structure within the thick frame shown in FIG. 5A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, this structure can be described as a structure that is energetically unstable "Amorphous" and completely different from "Crystal".

[0223] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, FIG. 5B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 5B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 5B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 5B is 500 nm.

[0224] In FIG. 5B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [a.u.]. As shown in FIG. 5B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected in the vicinity of 2θ = 31°. Note that, as shown in FIG. 5B, the peak in the vicinity of 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0225] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 5C. FIG. 5C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 5C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0226] As shown in FIG. 5C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0227] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 5A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. The non-single crystal oxide semiconductor also includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0228] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0229] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor having c-axis orientation and no clear orientation in the a-b plane direction.

[0230] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be about several tens of nm.

[0231] Also, in an In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. Thus, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0232] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0233] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0234] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0235] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to the capture of carriers. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0236] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to crystal grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation, defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0237] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Note that since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as restricted-view electron beam diffraction) using an electron beam with a probe diameter larger than the nanocrystals (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0238] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0239] [[Constitution of Oxide Semiconductor]] Next, the details of the above-mentioned CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0240] [CAC-OS] The CAC-OS is, for example, a constituent of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0241] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0242] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0243] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0244] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0245] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0246] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0247] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor of one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0248] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0249] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0250] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 18 cm -3 or less, more preferably 1×10 17 cm -3 or less, even more preferably 1×10 16 cm -3 or less, even more preferably 1×10 13 cm -3 or less, even more preferably 1×10 12 cm-3 It is more preferable that it is less than. In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. In some cases, an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0251] In addition, since the oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0252] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

[0253] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0254] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0255] In the oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface between the channel formation region of the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3Hereinafter, it is preferably 2×10 17 atoms / cm 3 or less.

[0256] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0257] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 5×10 19 atoms / cm 3 less than, preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0258] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, thereby forming oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 less than, preferably less than 5×10 19 atoms / cm 3 less than, more preferably less than 1×10 19 atoms / cm 3 less than, still more preferably less than 5×10 18 atoms / cm 3 less than, still more preferably less than 1×10 18 atoms / cm 3 less than.

[0259] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0260] <<Other semiconductor materials>> The semiconductor materials that can be used for the oxide 230 are not limited to the above-described metal oxides. As the oxide 230, a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) as the semiconductor material. In particular, it is suitable to use a layer material that functions as a semiconductor as the semiconductor material.

[0261] Here, in this specification and the like, the layer material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer material has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0262] Examples of the layer material include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing a chalcogen. Further, chalcogens are a general term for elements belonging to Group 16 and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0263] As the oxide 230, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide applicable as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0264] <Modification Example of Semiconductor Device> Hereinafter, an example of a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 6, 7A, 7B, 8A, and 8B.

[0265] FIG. 6 is a top view of the memory cell 10. FIG. 7A is a cross-sectional view of the portion indicated by the one-dot chain line A1-A2-A3 in FIG. 6. Here, the cross-sectional view shown by A1-A2 is a cross-sectional view in the channel length direction of the transistor 12, and the cross-sectional view shown by A2-A3 is a cross-sectional view in the channel width direction of the transistor 11. Further, FIG. 7B is a cross-sectional view of the portion indicated by the one-dot chain line A4-A5-A6 in FIG. 6. Here, the cross-sectional view shown by A4-A5 is a cross-sectional view in the channel width direction of the transistor 12, and the cross-sectional view shown by A5-A6 is a cross-sectional view in the channel length direction of the transistor 11. In the top view of FIG. 6, some elements (for example, the wiring CL) are omitted for clarity of the figure.

[0266] In the semiconductor devices shown in FIGS. 6, 7A, and 7B, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that also in this section, the description of the components of the semiconductor device in <Configuration Example of Semiconductor Device> can be referred to.

[0267] The semiconductor devices shown in FIGS. 6, 7A, and 7B are modified examples of the semiconductor devices shown in FIGS. 1B, 2A, 2B, 3A, and 3B. The memory cell 10 shown in FIGS. 6, 7A, and 7B is different from the memory cell 10 shown in FIGS. 1B, 2A, 2B, 3A, and 3B in that a part of the conductor 260 is exposed from the conductor 207.

[0268] Here, a part of the conductor 260 is in contact with the insulator 282. Therefore, in the memory cell 10 shown in FIGS. 6, 7A, and 7B, the conductors 207 and 260 function as the lower electrode of the capacitor element 13.

[0269] Further, the region where the conductor 260 is in contact with the insulator 282 includes a region overlapping with the vicinity of the channel formation region of the transistor 11. That is, in the memory cell 10 shown in FIGS. 6, 7A, and 7B, in the vicinity of the upper part of the channel formation region of the transistor 11, the insulator 282, the insulator 280, the oxide 230c, the insulator 250, and the conductor 260 are in contact with each other.

[0270] By adopting such a configuration, a barrier insulating film against impurities such as water and hydrogen can be provided near the upper part of the channel formation region of the transistor 11, so that the diffusion of the impurities into the oxide 230 through the oxide 230c, the insulator 250, etc. can be more effectively reduced. Also, by forming the insulator 282 by sputtering, oxygen can be added to the region closer to the channel formation region of the transistor 11 in the insulator 280. As a result, the oxygen contained in the insulator 280 can be more efficiently supplied to the oxide 230 through the oxide 230c or the insulator 250, so that the oxygen deficiency in the oxide 230 can be reduced, and the electrical characteristics and reliability of the transistor 11 can be improved.

[0271] Also, in FIG. 1A etc., an example in which the wirings BGL1 and BGL2 extend in the y direction is shown, but the semiconductor device according to the present invention is not limited to this. For example, as shown in FIG. 8A, a configuration may be adopted in which the transistors 11 and 12 are not provided with back gates. Also, for example, as shown in FIG. 8B, a configuration may be adopted in which the wirings BGL1 and BGL2 are extended and provided in the x direction.

[0272] Also, in FIG. 1A etc., an example in which when reading the memory cell 10, the wiring CL for applying the read potential is connected to the upper electrode of the capacitive element 13 is shown, but the semiconductor device according to the present invention is not limited to this. For example, a configuration may be adopted in which the wiring CL is connected to the back gate electrode of the transistor 11. In this case, a low power supply potential VSS may be applied to the wiring connected to the upper electrode of the capacitive element 13. That is, the conductor 205 may be used as the wiring CL for applying the read potential when reading the memory cell 10, and the conductor 208 may be used as the wiring to which the low power supply potential VSS is applied.

[0273] According to one aspect of the present invention, a semiconductor device with a small occupied area can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of high integration can be provided. Or, according to one aspect of the present invention, a semiconductor device with a large memory capacity can be provided. Or, according to one aspect of the present invention, a semiconductor device with a low manufacturing cost can be provided. Or, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0274] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with other configurations, methods shown in this embodiment, or configurations, methods shown in other embodiments.

[0275] (Embodiment 2) In this embodiment, a configuration example of a semiconductor device 500 including the memory cell 10 shown in the previous embodiment will be described.

[0276] FIG. 9A shows a block diagram illustrating a configuration example of a semiconductor device 500 according to one aspect of the present invention. The semiconductor device 500 shown in FIG. 9A includes a drive circuit 510 and a memory cell array 520. The memory cell array 520 is a NAND-type memory cell array having a plurality of memory cell strings 20. The memory cell string 20 has a plurality of memory cells 10. In FIG. 9A, an example is shown in which the memory cell array 520 has n (n is an integer of 2 or more) memory cell strings 20[1] to 20[n]. However, the present invention is not limited to this, and for example, n memory cell strings 20 may be regarded as one block, and the memory cell array 520 may have a configuration having a plurality of blocks.

[0277] The drive circuit 510 includes a PSW 541 (power switch), a PSW 542, and a peripheral circuit 515. The peripheral circuit 515 includes a peripheral circuit 511, a control circuit 512, and a voltage generation circuit 528.

[0278] In the semiconductor device 500, each circuit, each signal, and each voltage can be appropriately selected or discarded as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0279] Also, the signals BW, CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. Note that the signals PON1 and PON2 may be generated by the control circuit 512.

[0280] The control circuit 512 is a logic circuit having a function of controlling the overall operation of the semiconductor device 500. For example, the control circuit 512 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 500. Alternatively, the control circuit 512 generates a control signal for the peripheral circuit 511 so that this operation mode is executed.

[0281] The voltage generation circuit 528 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 528. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 528, and the voltage generation circuit 528 generates a negative voltage.

[0282] The peripheral circuit 511 is a circuit for writing and reading data to and from the memory cell 10. The peripheral circuit 511 includes a row decoder 521, a column decoder 522, a row driver 523, a column driver 524, an input circuit 525, an output circuit 526, and a sense amplifier 527.

[0283] The row decoder 521 and the column decoder 522 have the function of decoding the signal ADDR. The row decoder 521 is a circuit for specifying the row to be accessed, and the column decoder 522 is a circuit for specifying the column to be accessed. The row driver 523 has the function of selecting the wiring WL specified by the row decoder 521. The column driver 524 has functions such as writing data to the memory cell 10, reading data from the memory cell 10, and holding the read data.

[0284] The input circuit 525 has the function of holding the signal WDA. The data held by the input circuit 525 is output to the column driver 524. The output data of the input circuit 525 is the data (Din) to be written to the memory cell 10. The data (Dout) read by the column driver 524 from the memory cell 10 is output to the output circuit 526. The output circuit 526 has the function of holding Dout. Also, the output circuit 526 has the function of outputting Dout to the outside of the semiconductor device 500. The data output from the output circuit 526 is the signal RDA.

[0285] The PSW 541 has the function of controlling the supply of V DD to the peripheral circuit 515. The PSW 542 has the function of controlling the supply of V HM to the row driver 523. Here, the high power supply voltage of the semiconductor device 500 is V DD , and the low power supply voltage is GND (ground potential). Also, V HM is the high power supply voltage used to set the word line to a high level and is higher than V DD . The on / off of the PSW 541 is controlled by the signal PON1, and the on / off of the PSW 542 is controlled by the signal PON2. In FIG. 9A, in the peripheral circuit 515, the number of power supply domains to which V DD is supplied is set to 1, but it can also be made plural. In this case, a power switch may be provided for each power supply domain.

[0286] The drive circuit 510 and the memory cell array 520 may be provided on the same plane. Also, as shown in FIG. 9B, the drive circuit 510 and the memory cell array 520 may be provided in an overlapping manner. By providing the drive circuit 510 and the memory cell array 520 in an overlapping manner, the signal propagation distance can be shortened. Also, miniaturization of the semiconductor device 500 can be achieved.

[0287] FIG. 10 shows a circuit diagram for explaining an arrangement example of the memory cells 10 in the memory cell array 520. The memory cell array 520 has n memory cell strings 20[1] to 20[n] extending in the x direction. Each memory cell string 20 has m memory cells 10 (m is an integer of 2 or more) arranged in the x direction, a transistor 14, and a transistor 15. Therefore, in the memory cell array 520, m×n memory cells 10 are arranged in an n-row and m-column matrix. Also, n transistors 14[1] to 14[n] and n transistors 15[1] to 15[n] are arranged in the y direction, respectively. Note that the circuit configuration of each memory cell 10 is the same as the configuration shown in FIG. 1A, and the wiring connections and the like are also the same. Thus, the description of the previous embodiment can be referred to.

[0288] In each memory cell string 20, the sources and drains of a plurality of transistors 11 are connected in series, and the sources and drains of a plurality of transistors 12 are also connected in series. Also, at one end of each memory cell string 20, one of the source or drain of the transistor 11 is electrically connected to one of the source or drain of the transistor 14. Also, at the other end of each memory cell string 20, the other of the source or drain of the transistor 11 is electrically connected to one of the source or drain of the transistor 15.

[0289] In FIG. 10, the memory cell 10 in the first row and first column is denoted as memory cell 10[1,1], and the memory cell 10 in the n-th row and m-th column is denoted as memory cell 10[n,m]. Also, the memory cell 10 in the j-th row and i-th column (where j is an integer from 1 to n, and i is an integer from 1 to m) is denoted as memory cell 10[j,i].

[0290] Note that the rows and columns extend in directions orthogonal to each other. In the present embodiment, the x-direction is defined as the "row" and the y-direction is defined as the "column", but the x-direction may be defined as the "column" and the y-direction may be defined as the "row".

[0291] Also, the memory cell array 520 includes m wirings CL[1] to CL[m] extending in the y-direction, m wirings WL[1] to WL[m] extending in the y-direction, m wirings BGL1[1] to BGL1[m] extending in the y-direction, m wirings BGL2[1] to BGL2[m] extending in the y-direction, and two wirings SEL[1] and SEL[2] extending in the y-direction. Here, the wiring SEL[1] is electrically connected to the gates of transistors 14[1] to 14[n], and the wiring SEL[2] is electrically connected to the gates of transistors 15[1] to 15[n].

[0292] The memory cell array 520 also includes n wirings RBL[1] to RBL[n], n wirings SL[1] to SL[n], and n wirings WBL[1] to WBL[n]. In each memory cell string 20, the wiring WBL is electrically connected to the transistor 12 at one end, the wiring RBL is electrically connected to the transistor 14 at one end, and the wiring SL is electrically connected to the transistor 15 at the other end.

[0293] For example, in the memory cell string 20[1], the wiring RBL[1] is electrically connected to one of the source or drain of the transistor 11 of the memory cell 10[1,1] via the transistor 14[1]. Also, the wiring SL[1] is electrically connected to the other of the source or drain of the transistor 11 of the memory cell 10[1,m] via the transistor 15[1]. Further, the wiring WBL[1] is electrically connected to one of the source or drain of the transistor 12 of the memory cell 10[1,1].

[0294] FIG. 11 shows a top view of the memory cell array 520 corresponding to the circuit diagram of FIG. 10. Note that in the top view of FIG. 11, some elements are omitted for clarity of the figure. Also, for clarity of the figure, conductors 207 and the like are shown by solid lines instead of hidden lines for some elements. Here, the structure of each memory cell 10 is the same as the structure shown in FIGS. 1B, 2A, 2B, 3A, 3B, etc., and the description of the previous embodiments can be referred to.

[0295] As shown in FIG. 11, the memory cell array 520 has m conductors 208[1] to 208[m] that extend in the y direction and function as the wiring CL, m conductors 209[1] to 209[m] that function as the wiring WL, m conductors 205[1] to 205[m] that function as the wiring BGL1, m conductors 206[1] to 206[m] that function as the wiring BGL2, a conductor 210[1] that functions as the wiring SEL[1], and a conductor 210[2] that functions as the wiring SEL[2]. Also, the conductors 210 that function as the wiring SEL[1] and the wiring SEL[2] may be formed using the same conductive material as the conductor 209.

[0296] Also, as shown in FIG. 11, the memory cell array 520 extends in the x direction and has n oxide 230b[1] to oxide 230b[n] and n oxide 231b[1] to oxide 231b[n]. One oxide 230b and one oxide 231b are arranged one by one in each memory cell string 20. A plug electrically connected to the wiring RBL is provided at one end of the oxide 230b, and a plug electrically connected to the wiring SL is provided at the other end of the oxide 230b. Also, a plug electrically connected to the wiring WBL is provided at one end of the oxide 231b. Although not shown, similar to the oxide 230b and the oxide 231b, the oxide 230a, the oxide 231a, the oxide 243, the oxide 245, the conductor 242, and the conductor 244 are also appropriately extended and arranged.

[0297] In the oxide 230b, the transistor 11 is formed in a portion overlapping with the conductor 208. Also, in the oxide 231b, the transistor 12 is formed in a portion overlapping with the conductor 209, the transistor 14 is formed in a portion overlapping with the conductor 210[1], and the transistor 15 is formed in a portion overlapping with the conductor 210[2]. Here, the transistor 14 and the transistor 15 may have the same structure as the transistor 11. However, the upper surface of the top gate of the transistor 14 is in contact with the conductor 210[1], and the upper surface of the top gate of the transistor 15 is in contact with the conductor 210[2].

[0298] Further, the memory cell array 520 has an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, an insulator 216 on the insulator 214, an insulator 222 on the insulator 216, an insulator 224 on the insulator 222, an insulator 275 on the insulator 224, an insulator 280 on the insulator 275, an insulator 282 on the insulator 280, and an insulator 283 on the insulator 282, similar to the structure shown in FIGS. 3A and 3B. Also, m conductors 205 and m conductors 206 are arranged in the same layer as the insulator 216, n oxides 230b and n oxides 231b are arranged on the insulator 224, m conductors 209 are arranged on the insulator 280, and m conductors 208 are arranged on the insulator 282. Further, in each memory cell 10, a transistor 11 and a transistor 12 are provided in a layer between the insulator 214 and the insulator 282, a capacitor element 13 is provided on the insulator 280, and a conductor 240 connecting the transistor 11 and the transistor 12 is provided.

[0299] For example, the memory cells 10[1,1] and 10[1,2] that make up the memory cell array 520 also have the structures shown in FIGS. 3A and 3B, respectively. However, both the transistor 11 of the memory cell 10[1,2] and the transistor 11 of the memory cell 10[1,2] are formed in the oxide 230b[1]. Also, both the transistor 12 of the memory cell 10[1,2] and the transistor 12 of the memory cell 10[1,2] are formed in the oxide 231b[1].

[0300] As shown in FIG. 11, in the NAND-type memory cell array 520, it is not necessary to form contact plugs connected to wirings such as the WBL and RBL in each memory cell 10. Therefore, it is not necessary to provide space for forming unnecessary contact holes in the memory cell 10. Thus, by designing the shape of the memory cell 10 based on the rectangle surrounded by the oxide 230b, the oxide 231b, the conductor 208 (wiring CL), and the conductor 209 (wiring WL), the occupied area of the memory cell 10 can be minimized.

[0301] Here, the layouts of the oxide 230b, the oxide 231b, the conductor 208, and the conductor 209 are preferably designed so that the area of the memory cell 10 is as narrow as possible based on the parasitic capacitance between wirings, the minimum processing dimension, and the like. As a result, the area occupied by the conductor 208 that functions as the upper electrode of the capacitive element 13 in the memory cell 10, that is, the maximum value of the area that the capacitive element 13 can take, is also limited. For this reason, it is preferable that the area where the conductor 207 overlaps with the designed conductor 208 is as large as possible.

[0302] In the memory cell 10 described in the present embodiment and the like, the conductor 207 that functions as the node FN is disposed so as to overlap the oxide 230b and the oxide 231b. Thereby, in the memory cell 10, the area where the conductor 208 and the conductor 207 overlap can be expanded in the y direction.

[0303] By adopting such a configuration, the capacitance of the capacitive element 13 can be increased without substantially increasing the area with respect to the limited area of the memory cell 10. Therefore, the occupied area of the memory cell 10 can be reduced. As a result, high integration of the semiconductor device can be achieved, and a semiconductor device with a large storage capacity can be provided. In addition, a semiconductor device with a low manufacturing cost per storage capacity can be provided.

[0304] Next, an example of the data writing operation and the data reading operation of the memory cell array 520 will be described with reference to FIGS. 12A and 12B. Hereinafter, the operation will be described using the memory cell string 20[1] in the case of m = 4 as a model.

[0305] First, an example of writing data to the memory cell string 20[1] in periods T1 to T4 will be described using the timing chart shown in FIG. 12A. Here, FIG. 12A shows the potential V of the wiring WBL[1] WBL[1] [V], the potential V of the wiring WL[4] WL[4] [V], the potential V of the wiring WL[3] WL[3] [V], the potential V of the wiring WL[2] WL[2][V], potential V of wiring WL[1] WL[1] [V] is shown. During periods T1 to T4, the potentials of wiring RBL[1], wiring SL[1], wiring CL[1] to wiring CL[4], wiring BGL1[1] to wiring BGL1[4], and wiring BGL2[1] to wiring BGL2[4] are set to 0V.

[0306] During period T1, data 0 is written into memory cell 10[1,4]. Potential V WBL[1] is set to the potential of data 0 (e.g., 0V), and potential V WL[4] to potential V WL[1] are set to the potentials at which transistors 11 of memory cells 10[1,4] to 10[1,1] turn on (e.g., 4V). As a result, wiring WBL[1] and node FN of memory cell 10[1,4] are connected, and the potential of data 0 is applied to node FN. When switching from period T1 to period T2, potential V WL[4] is set to the potential at which transistor 11 turns off (e.g., -4V). Thereby, node FN of memory cell 10[1,4] becomes a floating state, and the potential corresponding to data 0 applied to node FN can be retained.

[0307] During period T2, data 1 is written into memory cell 10[1,3]. Potential V WBL[1] is set to the potential of data 1 (e.g., 2V), and potential V WL[3] to potential V WL[1] are set to the potentials at which transistors 11 of memory cells 10[1,3] to 10[1,1] turn on (e.g., 4V). As a result, wiring WBL[1] and node FN of memory cell 10[1,3] are connected, and the potential of data 1 is applied to node FN. At this time, since transistor 11 of memory cell 10[1,4] is in an off state, the data 0 written into memory cell 10[1,4] during period T1 is retained. When switching from period T2 to period T3, potential V WL[3] is set to the potential at which transistor 11 turns off (e.g., -4V). Thereby, node FN of memory cell 10[1,3] becomes a floating state, and the potential corresponding to data 1 applied to node FN can be retained.

[0308] Hereinafter, in period T3, data 0 is written into memory cells 10[1,2] in the same manner as in period T1, and in period T4, data 1 is written into memory cell 10[1,1] in the same manner as in period T2.

[0309] Next, an example of reading data from the memory cell string 20[1] into which data has been written in periods T1 to T4 will be described using the timing chart shown in FIG. 12B. Here, FIG. 12B shows the potential V CL[4] [V] of wiring CL[4], the potential V CL[3] [V] of wiring CL[3], the potential V CL[2] [V] of wiring CL[2], the potential V CL[1] [V] of wiring CL[1], and the current value I RBL[1] [μA] of wiring RBL[1]. Note that in periods T5 to T8, the potentials of wirings WL[1] to WL[4] are -4V, the potential of wiring RBL[1] is 1.2V, and the potentials of wirings SL[1], WBL[1], BGL1[1] to BGL1[4], and BGL2[1] to BGL2[4] are 0V. Also, transistors 14[1] and 15[1] are in the on state.

[0310] In period T5, the data 0 in memory cell 10[1,4] is read. The potential V CL[4] is set as the read potential (for example, 0V), and the potentials V CL[3] to V CL[1] are set to potentials (for example, 4V) at which the transistors 11 of memory cells 10[1,3] to 10[1,1] are turned on regardless of the data they hold. As a result, the conduction state between wiring RBL[1] and wiring SL[1] will be determined by the conduction state of the transistor 11 of memory cell 10[1,4]. Here, when the read potential is applied to wiring CL, the transistor 11 of memory cell 10 is turned off if data 0 is held and turned on if data 1 is held. As shown in FIG. 12B, I RBL[1]is 0 μA, and since the wiring RBL[1] and the wiring SL[1] are in a non-conductive state, it can be read that the memory cell 10[1,4] holds the data 0.

[0311] In period T6, the data 1 of the memory cell 10[1,3] is read. The potential V CL[3] is set as the read potential (for example, 0 V), and the potential V CL[4]、 The potential V CL[2] , and the potential V CL[1] are set to a potential (for example, 4 V) at which the transistors 11 of the memory cell 10[1,4], the memory cell 10[1,2], and the memory cell 10[1,1] are turned on regardless of the data they hold. As a result, the conduction state of the wiring RBL[1] and the wiring SL[1] will be determined by the conduction state of the transistor 11 of the memory cell 10[1,3]. As shown in FIG. 12B, I RBL[1] takes a positive value, and since the wiring RBL[1] and the wiring SL[1] are in a conductive state, it can be read that the memory cell 10[1,3] holds the data 1.

[0312] Hereinafter, in period T7, the data 0 of the memory cell 10[1,2] can be read in the same manner as in period T5, and in period T8, the data 1 of the memory cell 10[1,1] can be read in the same manner as in period T6.

[0313] In the above manner, the writing and reading of the data of the memory cell string 20[1] can be performed. In the above, the writing and reading were performed for one memory cell string 20, but the writing and reading of the data of a plurality of memory cell strings 20 can be performed simultaneously in the same manner. For example, in the memory cell array 520 shown in FIG. 10, the writing and reading of the data of the memory cell strings 20[1] to 20[n] can be performed simultaneously.

[0314] Note that the data writing operation and data reading operation of the memory cell array 520 described above are merely examples, and the present invention is not limited thereto. For example, as described in the previous embodiment, during the data reading operation, the conductor 205 may function as a wiring CL for applying a read potential, and the conductor 208 may be a wiring to which a low power supply potential VSS is applied.

[0315] Also, the layout of the memory cell array 520 described above is merely an example, and the present invention is not limited thereto. For example, the wiring WBL may be provided not only at one end of the memory cell string 20 but also at the other end, that is, a configuration in which two wirings WBL are connected to one memory cell string 20 may be adopted. By adopting such a configuration, in the above-described data writing operation, data can be written simultaneously from two directions of the memory cell string 20, so that the data writing speed can be improved.

[0316] Further, for example, the wirings BGL1 and BGL2 may not be provided, or the wirings BGL1 and BGL2 may be configured to extend in the x direction. Also, the transistors 14 and 15 may be configured to be provided with a back gate and the wiring BGL1.

[0317] Also, although the memory cell array 520 is a NAND-type memory cell array, the present invention is not limited thereto. For example, oxides 230b, oxides 231b, etc. may be formed in an island pattern on each memory cell 10 to form a NOR-type memory cell array.

[0318] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with other configurations, methods shown in the present embodiment, or configurations, methods shown in other embodiments.

[0319] (Embodiment 3) In the present embodiment, an application example of a storage device according to an aspect of the present invention will be described.

[0320] Generally, in semiconductor devices such as computers, various storage devices are used according to the application. Fig. 13 shows various storage devices by layer. The storage devices located in the upper layer are required to have a faster access speed, and the storage devices located in the lower layer are required to have a larger storage capacity and a higher recording density. In Fig. 13, from the top layer in order, it shows the memory integrated as a register in an arithmetic processing unit such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0321] The memory integrated as a register in an arithmetic processing unit such as a CPU is used for temporarily storing calculation results, etc., so the access frequency from the arithmetic processing unit is high. Therefore, a faster operating speed is required rather than the storage capacity. Also, the register has a function of holding the setting information of the arithmetic processing unit, etc.

[0322] SRAM is used, for example, for caches. A cache has a function of replicating and holding a part of the information held in the main memory. By replicating frequently used data in the cache, the access speed to the data can be increased.

[0323] DRAM is used, for example, for main memories. A main memory has a function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0324] 3D NAND memory is used, for example, for storage. A storage has a function of holding data that needs to be stored long - term and various programs used in the arithmetic processing unit, etc. Therefore, a larger storage capacity and a higher recording density are required for storage rather than the operating speed. The recording density of the storage device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0325] The memory device according to one aspect of the present invention has a large storage capacity, a high operating speed, and can retain data for a long period of time. The memory device according to one aspect of the present invention can be suitably used as a memory device located in a boundary region 901 including both a layer where a cache is located and a layer where a main memory is located. Further, the memory device according to one aspect of the present invention can be suitably used as a memory device located in a boundary region 902 including both a layer where a main memory is located and a layer where a storage is located.

[0326] The memory device according to one aspect of the present invention can be applied to, for example, memory devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game machines, etc.). It can also be used for image sensors, IoT (Internet of Things), healthcare, etc. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large computers such as server systems.

[0327] Further, the memory device according to one aspect of the present invention is applied to various removable memory devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). Some configuration examples of the removable memory device are schematically shown in FIGS. 14A to 14E. For example, the memory device according to one aspect of the present invention is processed into a packaged memory chip and used for various storage devices and removable memories.

[0328] FIG. 14A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 etc. of the substrate 1104.

[0329] FIG. 14B is a schematic diagram of the appearance of an SD card, and FIG. 14C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1114 etc. on the substrate 1113.

[0330] FIG. 14D is a schematic diagram of the appearance of an SSD, and FIG. 14E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1154 etc. on the substrate 1153.

[0331] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with other configurations, methods shown in the present embodiment, or configurations, methods shown in other embodiments.

[0332] (Embodiment 4) FIG. 15 shows a specific example of an electronic device including a semiconductor device according to an aspect of the present invention.

[0333] <Electronic device·System> A semiconductor device according to an aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, television devices, monitors for desktop or notebook information terminals, digital signage, large game machines such as pachinko machines, and other electronic devices having a relatively large screen, as well as digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, audio playback devices, and the like. Further, a semiconductor device according to an aspect of the present invention can be applied as a component of artificial intelligence. By using the semiconductor device according to an aspect of the present invention, artificial intelligence can be mounted on an electronic device.

[0334] An electronic device according to an aspect of the present invention may have an antenna. By receiving a signal with the antenna, display of video, information, etc. can be performed on the display unit. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

[0335] An electronic device according to an aspect of the present invention may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0336] An electronic device according to an aspect of the present invention can have various functions. For example, functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, touch panel function, displaying a calendar, date, or time, executing various software (programs), wireless communication function, and reading a program or data recorded on a recording medium can be provided.

[0337] [Information Terminal] FIG. 15A shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101.

[0338] The information terminal 5100 can execute an application using artificial intelligence by using a semiconductor device according to an aspect of the present invention. Examples of applications using artificial intelligence include, for example, an application that recognizes a conversation and displays the conversation content on the display unit 5102, an application that recognizes characters, figures, etc. input by a user on the touch panel provided on the display unit 5102 and displays them on the display unit 5102, and an application that performs biometric authentication such as fingerprint and voiceprint.

[0339] FIG. 15B shows a notebook information terminal 5200. The notebook information terminal 5200 has a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0340] Similar to the above-described information terminal 5100, the notebook information terminal 5200 can execute an application using artificial intelligence by using a semiconductor device according to an aspect of the present invention. Examples of applications using artificial intelligence include, for example, design support software, text proofreading software, and recipe automatic generation software. Further, by using the notebook information terminal 5200, new artificial intelligence can be developed.

[0341] In the above description, a smartphone and a notebook information terminal are illustrated in FIGS. 15A and 15B, respectively, as examples of electronic devices, but information terminals other than smartphones and notebook information terminals can be applied. Examples of information terminals other than smartphones and notebook information terminals include, for example, PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0342] [Game machine] FIG. 15C shows a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided on the housing 5301 to another housing (not shown), the video output to the display unit 5304 can be output to another video device (not shown). At this time, the housing 5302 and the housing 5303 can each function as an operation unit. Thereby, a plurality of players can play games simultaneously. A semiconductor device according to one aspect of the present invention can be incorporated into chips etc. provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

[0343] Also, FIG. 15D shows a stationary game machine 5400 which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

[0344] By applying the GPU or chip of one aspect of the present invention to game machines such as the portable game machine 5300 and the stationary game machine 5400, a game machine with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0345] Furthermore, by using a semiconductor device according to one aspect of the present invention in the portable game machine 5300, a portable game machine 5300 having artificial intelligence can be realized.

[0346] Originally, expressions such as the progress of the game, the actions and words of the creatures appearing in the game, and the phenomena occurring in the game are defined by the program of that game. However, by applying artificial intelligence to the portable game machine 5300, expressions not limited to the game program become possible. For example, expressions such as the content queried by the player, the progress of the game, the time, and the changes in the actions and words of the characters appearing in the game become possible.

[0347] Also, when playing a game that requires multiple players on the portable game machine 5300, since the game players can be anthropomorphically configured by artificial intelligence, a game can be played even by one person by using an artificial intelligence-based game player as the opponent.

[0348] In FIGS. 15C and 15D, a portable game machine and a stationary game machine are illustrated as examples of game machines, but the game machines to which the semiconductor device according to one aspect of the present invention can be applied are not limited thereto. Examples of game machines to which the semiconductor device according to one aspect of the present invention can be applied include, for example, arcade game machines installed in entertainment facilities (such as game centers and amusement parks), and pitching machines for batting practice installed in sports facilities.

[0349] [Large computer] The semiconductor device according to one aspect of the present invention can be applied to a large computer.

[0350] FIG. 15E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 15F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0351] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. Further, a plurality of substrates 5504 are provided on the computer 5502, and the semiconductor device according to one aspect of the present invention can be mounted on the substrate.

[0352] The supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, since a huge number of operations need to be processed at high speed, the power consumption is high and the heat generation of the chips is large. By applying the semiconductor device according to one aspect of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. In addition, due to the low power consumption, the heat generation from the circuit can be reduced, so that the influence on the circuit itself, the peripheral circuit, and the module due to heat generation can be minimized.

[0353] In FIGS. 15E and 15F, a supercomputer is illustrated as an example of a large computer, but the large computer to which the semiconductor device according to one aspect of the present invention is applied is not limited thereto. Examples of the large computer to which the semiconductor device according to one aspect of the present invention is applied include, for example, a computer (server) that provides services, a large general-purpose computer (mainframe), and the like.

[0354] [Mobile object] The semiconductor device according to one aspect of the present invention can be applied to an automobile, which is a mobile object, and the periphery of the driver's seat of the automobile.

[0355] FIG. 15G is a view showing the periphery of the windshield in the interior of an automobile 5600, which is an example of a mobile object. In FIG. 15G, in addition to the display panels 5601, 5602, and 5603 attached to the dashboard, a display panel 5604 attached to the pillar is illustrated.

[0356] The display panels 5601 to 5603 can provide various information by displaying a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, an air conditioner setting, and the like. In addition, the display items, layout, and the like displayed on the display panel can be appropriately changed according to the user's preference, and the designability can be enhanced. The display panels 5601 to 5603 can also be used as lighting devices.

[0357] The display panel 5604 can complement the field of view (blind spot) blocked by a pillar by displaying an image from an imaging device (not shown) provided in a vehicle. That is, by displaying an image from an imaging device provided outside the vehicle, the blind spot can be supplemented and safety can be enhanced. Further, by displaying an image that complements the invisible part, it is possible to perform safety confirmation more naturally without a sense of discomfort. The display panel 5604 can also be used as an illumination device.

[0358] Since the semiconductor device according to one aspect of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of a vehicle. Further, the chip can be used in a system that performs road guidance, danger prediction, and the like. The display panels 5601 to 5604 may be configured to display information such as road guidance and danger prediction.

[0359] In the above description, a vehicle is described as an example of a moving body, but the moving body is not limited to a vehicle. For example, examples of the moving body include a train, a monorail, a ship, and an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), and a semiconductor device according to one aspect of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0360] [Home Appliance] FIG. 15H shows an electric refrigerator-freezer 5700 which is an example of a home appliance. The electric refrigerator-freezer 5700 includes a housing 5701, a refrigerator door 5702, a freezer door 5703, and the like.

[0361] By using the semiconductor device according to one aspect of the present invention in the electric refrigerator 5700, an electric refrigerator 5700 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator 5700 can have functions such as automatically generating a menu based on the foodstuffs stored in the electric refrigerator 5700 and the expiration dates of those foodstuffs, and automatically adjusting the temperature according to the foodstuffs stored in the electric refrigerator 5700.

[0362] Although the electric refrigerator has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, and the like.

[0363] The electronic devices described in this embodiment, the functions of those electronic devices, application examples of artificial intelligence, and the effects thereof can be appropriately combined with the descriptions of other electronic devices.

[0364] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with other configurations, methods shown in this embodiment, or configurations, methods shown in other embodiments.

Description of Reference Numerals

[0365] BGL1: Wiring, BGL2: Wiring, CL: Wiring, RBL: Wiring, SL: Wiring, SEL: Wiring, T1: Period, T2: Period, T3: Period, T4: Period, T5: Period, T6: Period, T7: Period, T8: Period, WBL: Wiring, WL: Wiring, 10: Memory Cell, 11: Transistor, 12: Transistor, 13: Capacitor Element, 14: Transistor, 15: Transistor, 20: Memory Cell String, 205: Conductor, 205a: Conductor, 205b: Conductor, 205c: Conductor, 206: Conductor, 206a: Conductor, 206b: Conductor, 206c: Conductor, 207: Conductor, 208: Conductor, 209: Conductor, 210: Conductor, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230b: Oxide, 230c: Oxide, 231: Oxide, 231a: Oxide, 231b: Oxide, 231c: Oxide, 232a: Region, 232b: Region, 232c: Region, 240: Conductor, 241: Insulator, 242: Conductor, 242a: Conductor, 242b: Conductor, 243: Oxide, 243a: Oxide, 243b: Oxide, 244: Conductor, 244a: Conductor, 244b: Conductor, 245: Oxide, 245a: Oxide, 245b: Oxide, 250: Insulator, 251: Insulator, 260: Conductor, 260a: Conductor, 260b: Conductor, 261: Conductor, 261a: Conductor, 261b: Conductor, 275: Insulator, 280: Insulator, 282: Insulator, 283: Insulator, 500: Semiconductor Device, 510: Driving Circuit, 511: Peripheral Circuit, 512: Control Circuit, 515: Peripheral Circuit, 520: Memory Cell Array, 521: Row Decoder, 522: Column Decoder, 523: Row Driver, 524: Column Driver, 525: Input Circuit, 526: Output Circuit, 527: Sense Amplifier, 528: Voltage Generation Circuit, 541: PSW, 542: PSW, 901: Boundary Region, 902: Boundary Region, 1100: USB Memory, 1101: Housing, 1102: Cap, 1103: USB Connector, 1104: Substrate, 1105: Memory Chip, 1106: Controller Chip, 1110: SD Card, 1111: Housing, 1112: Connector, 1113: Substrate, 1114: Memory Chip, 1115: Controller Chip, 1150: SSD, 1151: Housing, 1152: Connector, 1153: Substrate, 1154: Memory Chip,1155: Memory chip, 1156: Controller chip, 5100: Information terminal, 5101: Housing, 5102: Display unit, 5200: Notebook information terminal, 5201: Main body, 5202: Display unit, 5203: Keyboard, 5300: Portable game console, 5301: Housing, 5302: Housing, 5303: Housing, 5304: Display unit, 5305: Connection part, 5306: Operation key, 5400: Type game console, 5402: Controller, 5500: Supercomputer, 5501: Rack, 5502: Computer, 5504: Substrate, 5600: Automobile, 5601: Display panel, 5602: Display panel, 5603: Display panel, 5604: Display panel, 5700: Electric refrigerator-freezer, 5701: Housing, 5702: Door for refrigerator compartment, 5703: Door for freezer compartment,

Claims

[Claim 1] a first transistor, a second transistor, a capacitor, a first insulator, and a first conductor; the first transistor includes a first oxide semiconductor, a first gate, and a first gate insulator; the second transistor includes a second oxide semiconductor, a second gate, and a second gate insulator; the capacitance element includes a second conductor, a third conductor, and a second insulator; the first insulator is disposed on the first oxide semiconductor and the second oxide semiconductor; the first insulator has a first opening formed therein, the first opening reaching the first oxide semiconductor, a second opening formed therein, the second oxide semiconductor, and a third opening formed therein, the third opening reaching one of a source or a drain of the second transistor; the first gate insulator and the first gate are disposed in the first opening; the second gate insulator and the second gate are disposed in the second opening; the first conductor is disposed in the third opening; the second conductor is disposed in contact with an upper surface of the first conductor and an upper surface of the first gate; the second insulator is disposed on the second conductor and the first insulator; The third conductor is disposed to cover the second conductor with the second insulator interposed therebetween.

Images