Trench under-shield method and approach for trenched semiconductor device structure

Abstract

To provide a power semiconductor device having a gate trench and a method for manufacturing such a device.SOLUTION: A semiconductor device including a polysilicon layer 450 includes a wide bandgap semiconductor layer structure including a drift region 420 having a first conductivity type, and a plurality of gate trenches 480 in an upper portion of the semiconductor layer structure, each having a lower surface, a first sidewall, a second sidewall, and a top opening. The polysilicon layer includes a plurality of polysilicon layers on the second sidewall of the gate trenches.SELECTED DRAWING: Figure 4B

Description

Technical Field

[0001] This application claims the benefit of priority to U.S. Patent Application No. 17 / 018,305, filed on September 11, 2020, with the United States Patent and Trademark Office, and the entire contents of the above application are incorporated by reference for all purposes.

[0002] The present invention relates to power semiconductor devices, and more particularly, to power semiconductor devices having gate trenches and methods of fabricating such devices.

Background Art

[0003] A metal-insulator-semiconductor field effect transistor (referred to as "MISFET: Metal Insulating Semiconductor Field Effect Transistor") is a well-known type of semiconductor transistor that can be used as a switching device. The MISFET is a three-terminal device having a gate, a drain, and a source terminal, and a semiconductor body. The source region and the drain region are formed in the semiconductor body separated by a channel region, and the gate electrode (which acts as the gate terminal or can be electrically connected to the gate terminal) is disposed adjacent to the channel region. The MISFET can be turned on or off by applying a bias voltage to the gate electrode. When the MISFET is turned on (i.e., the MISFET is in its "on-state"), current is conducted through the channel region of the MISFET between the source region and the drain region. When the bias voltage is removed from the gate electrode (or reduced below the threshold level), the current stops conducting through the channel region. As an example, an n-type MISFET has an n-type source and drain regions and a p-type channel. Therefore, the n-type MISFET has an "n-p-n" design. The n-type MISFET turns on when a gate-bias voltage sufficient to create a conductive n-type inversion layer within the p-type channel region that electrically connects the n-type source and drain regions is applied to the gate electrode, thereby enabling majority carrier conduction between the source region and the drain region. The gate electrode of a power MISFET is typically separated from the channel region by a thin gate dielectric layer.

[0004] In some applications, a MISFET may need to carry large currents and / or be able to block high voltages. Such MISFETs are often referred to as "power" MISFETs. For example, various other power semiconductor devices are known in the art, including bipolar junction transistors ("BJTs"), insulated gate bipolar transistors ("IGBTs"), junction barrier Schottky diodes, gate turn-off transistors ("GTOs"), MOS controlled thyristors, and various other devices. These power semiconductor devices are often fabricated from wide bandgap semiconductor materials such as silicon carbide ("(SiC)") or gallium nitride ("(GaN)") based semiconductor materials. As used herein, a wide bandgap semiconductor material refers to a semiconductor material having a bandgap greater than 1.40 eV.

[0005] Power semiconductor devices can have a lateral or vertical structure. In a device having a lateral structure, the device's terminals (e.g., drain, gate, and source terminals for a power MOSFET device) are on the same major (i.e., top or bottom) surface of the semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source can be on the top surface of the semiconductor layer structure and the drain can be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include a substrate. As used herein, the term "semiconductor layer structure" refers to a structure that includes one or more semiconductor layers such as a semiconductor substrate and / or semiconductor epitaxial layers.

[0006] Conventional power semiconductor devices typically have a semiconductor substrate such as a silicon carbide substrate having a first conductivity type (e.g., an n-type substrate), and an epitaxial layer structure having a first conductivity type (e.g., n-type) is formed on the substrate. A portion of this epitaxial layer structure (which can comprise one or more separate layers) functions as the drift region of the power semiconductor device. The device typically includes an “active region” that includes one or more power semiconductor devices having a junction such as a p-n junction. The active region can be formed on and / or within the drift region. The active region serves as the main junction for blocking a voltage in the reverse bias direction and providing a current in the forward bias direction. The power semiconductor device can also have an edge termination within a termination region adjacent to the active region. One or more power semiconductor devices can be formed on the substrate, and each power semiconductor device will typically have its own edge termination. After the substrate is fully processed, the resulting structure can be diced to separate the individual edge-terminated power semiconductor devices. The power semiconductor device can have a unit cell structure, in which the active region of each power semiconductor device includes a plurality of individual “unit cell” devices, and the plurality of individual “unit cell” devices are arranged parallel to each other and function together as a single power semiconductor device.

[0007] Power semiconductor devices are designed to block (in forward or reverse blocking states) or pass (in forward operating states) high voltages and / or large currents. For example, in a blocking state, a power semiconductor device can be designed to maintain a potential of hundreds or thousands of volts. However, when the applied voltage approaches or exceeds the voltage level at which the device is designed to block, a non-negligible level of current may begin to flow through the power semiconductor device. Typically, such current, called "leakage current," can be highly undesirable. Leakage current can begin to flow when the voltage increases beyond the designed voltage blocking capability of the device, which can be a function of, among other things, the doping and thickness of the drift region. Leakage current can also occur for other reasons, such as device edge termination and / or failure of the primary junction. When the voltage applied to the device increases beyond the breakdown voltage and reaches a critical level, the increase in the electric field can result in an uncontrollable and undesirable runaway generation of charge carriers within the semiconductor device, leading to a state known as avalanche breakdown.

[0008] Power semiconductor devices can also begin to allow a non-negligible amount of leakage current to flow at voltage levels lower than the designed breakdown voltage of the device. In particular, leakage current can begin to flow at the edges of the active regions where high electric fields can occur due to the electric field crowding effect. To reduce this electric field crowding (and the resulting increase in leakage current), the edge terminations described above that surround part or all of the active region of the power semiconductor device can be provided. These edge terminations can spread the electric field over a wider area, thereby reducing the electric field crowding.

[0009] A vertical power semiconductor device including a MOSFET transistor can have a standard gate electrode design in which the gate electrode of the transistor is formed on top of the semiconductor layer structure or alternatively can have a gate electrode embedded in a trench within the semiconductor layer structure. A MOSFET having an embedded gate electrode is typically referred to as a gate-trench MOSFET. By the standard gate electrode design, the channel region of each unit cell transistor is disposed horizontally under the gate electrode. In contrast, in the gate-trench MOSFET design, the channel is disposed vertically. The gate-trench MOSFET can provide improved performance but typically requires a more complex manufacturing process. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0010] According to some embodiments of the concepts of the present invention, a device can be provided. The device can include a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches within an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, and a plurality of polysilicon layers, each polysilicon layer being on the second sidewall of a respective gate trench.

[0011] In some embodiments, the device can include an oxide layer on each polysilicon layer. In some embodiments, the device can include a gate structure in each gate trench, and each gate structure includes a gate oxide. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device can include a first source / drain contact on a first main surface of the semiconductor layer structure and a second source / drain contact on a second main surface of the semiconductor layer structure opposite the first main surface. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each polysilicon layer extends by the length of each gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each gate trench includes a first length portion with each polysilicon layer and a second length portion without each polysilicon layer.

[0012] In some embodiments, the device can include a channel region in a first sidewall of the gate trench and in a second sidewall of the second length portion of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region. In some embodiments, each gate trench includes a third length portion with a polysilicon layer on a first sidewall of each gate trench. In some embodiments, the device can include a channel region in a first sidewall of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region. In some embodiments, the wide bandgap semiconductor includes silicon carbide. In some embodiments, the device can include a lower oxide layer on a lower surface, a first sidewall, and a second sidewall of each gate trench. In some embodiments, the device can include an upper oxide layer on the polysilicon layer.

[0013] According to some embodiments of the concepts of the present invention, a device may be provided. The device can include a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches within an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, and a plurality of polysilicon layers, each polysilicon layer being below a respective one of the plurality of gate trenches.

[0014] In some embodiments, the plurality of gate trenches include a first gate trench having a respective polysilicon layer below its lower surface, and a second gate trench having no polysilicon layer below its lower surface. In some embodiments, the device can include a gate structure within each second gate trench. In some embodiments, each gate trench of the device can include each polysilicon layer of the plurality of polysilicon layers. In some embodiments, the device can include a gate structure within each gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each polysilicon layer extends for the length of its respective gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each gate trench includes a first length portion having its respective polysilicon layer and a second length portion having no respective polysilicon layer. In some embodiments, the device can include a channel region within the first sidewall of the gate trench and within the second sidewall of the second length portion of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region. In some embodiments, the device can include an oxide layer on each polysilicon layer. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device can include a first source / drain contact on the first major surface of the semiconductor layer structure and a second source / drain contact on the second major surface of the semiconductor layer structure opposite the first major surface. In some embodiments, the device can include a channel region within the first sidewall of each gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region. In some embodiments, the wide bandgap semiconductor includes silicon carbide.

[0015] According to some embodiments of the concepts of the present invention, a device may be provided. The device includes a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, and a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, and each gate trench including a plurality of alternating first length portions and a plurality of second length portions along the length of the gate trench, a plurality of gate trenches, and a plurality of polysilicon layers, each polysilicon layer being on the second sidewall of each gate trench in the first length portion. The second length portion of each gate trench may be free of polysilicon layers.

[0016] In some embodiments, the device may include an oxide layer in each gate trench. In some embodiments, the oxide layer includes a first cross-section in the first length portion of each gate trench and a second cross-section in the second length portion of each gate trench. In some embodiments, the device may include a gate structure in each gate trench, the gate structure including a gate electrode. In some embodiments, the gate electrode includes a first cross-section in the first length portion of each gate trench and a second cross-section in the second length portion of each gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device may include a first source / drain contact on a first main surface of the semiconductor layer structure and a second source / drain contact on a second main surface of the semiconductor layer structure opposite the first main surface. In some embodiments, the wide-bandgap semiconductor includes silicon carbide.

[0017] According to some embodiments of the concepts of the present invention, a device may be provided. The device includes a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, the plurality of gate trenches including first and second gate trenches, a plurality of polysilicon layers, each polysilicon layer being below a respective first gate trench of the plurality of gate trenches, and a plurality of gate electrodes, each gate electrode being disposed within a respective second gate trench of the plurality of gate trenches. A second length portion of each gate trench may be free of a polysilicon layer.

[0018] In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each polysilicon layer extends only as long as the length of its respective first gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure. In some embodiments, the device may include a channel region within a first sidewall of the second gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region may be within the well region. In some embodiments, the wide-bandgap semiconductor includes silicon carbide.

[0019] According to some embodiments of the concept of the present invention, a method of forming a semiconductor device is provided. The method comprises forming a wide-bandgap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region having a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches being spaced apart from each other and each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening; and forming a polysilicon layer along the second sidewall of each gate trench.

[0020] In some embodiments, the method can include forming an oxide layer on the polysilicon layer. In some embodiments, the method can include forming a lower oxide layer on the lower surface, the first sidewall, and the second sidewall of each gate trench, and forming the polysilicon layer includes forming a polysilicon layer on the lower oxide layer. In some embodiments, the method can include forming an upper oxide layer on the polysilicon layer. In some embodiments, the method can include forming a gate structure in each gate trench, and each gate structure includes a gate electrode. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the method can include forming a first source / drain contact on the first main surface of the semiconductor layer structure and a second source / drain contact on the second main surface of the semiconductor layer structure opposite the first main surface. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each polysilicon layer extends by the length of each gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each gate trench includes a first length portion with each polysilicon layer and a second length portion without each polysilicon layer. In some embodiments, the channel region is formed in the first sidewall of the gate trench and in the second sidewall of the second length portion of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region can be within the well region. In some embodiments, the channel region is formed in the first sidewall of the gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region can be within the well region. In some embodiments, the wide-bandgap semiconductor includes silicon carbide.

[0021] According to some embodiments of the present disclosure, a method of forming a semiconductor device may be provided. The method includes forming a wide-bandgap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region having a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches being spaced apart from each other and each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening; and forming a polysilicon layer at least at some of the lower portions of the gate trenches.

[0022] In some embodiments, the plurality of gate trenches includes a first gate trench having a respective polysilicon layer on its lower surface and a second gate trench having no polysilicon layer on its lower surface. In some embodiments, the method may include forming a gate structure in each second gate trench. In some embodiments, the polysilicon layer is formed in each gate trench of the semiconductor device. In some embodiments, the method may include forming a gate structure in each gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each polysilicon layer extends for the length of its respective gate trench. In some embodiments, each gate trench extends a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each gate trench includes a first length portion having a respective polysilicon layer and a second length portion having no respective polysilicon layer. In some embodiments, the method may include forming an oxide layer on each polysilicon layer. In some embodiments, the method may include forming a first source / drain contact on a first main surface of the semiconductor layer structure and a second source / drain contact on a second main surface of the semiconductor layer structure opposite the first main surface. In some embodiments, the wide-bandgap semiconductor includes silicon carbide.

[0023] According to some embodiments of the present disclosure, a method of forming a semiconductor device may be provided. The method includes forming a wide-bandgap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region having a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, and each gate trench including a plurality of alternating first length portions and a plurality of second length portions along the length of the gate trench; and forming a plurality of polysilicon layers, each polysilicon layer being on the second sidewall of each gate trench in the first length portion. The second length portion of each gate trench may be free of polysilicon layers.

[0024] In some embodiments, the method may further include forming an oxide layer in each gate trench. In some embodiments, the oxide layer includes a first cross-section in the first length portion of each gate trench and a second cross-section in the second length portion of each gate trench. In some embodiments, the method may include forming a gate structure in each gate trench, the gate structure including a gate electrode. In some embodiments, the gate electrode includes a first cross-section in the first length portion of each gate trench and a second cross-section in the second length portion of each gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the method may include forming a first source / drain contact on a first main surface of the semiconductor layer structure and a second source / drain contact on a second main surface of the semiconductor layer structure opposite the first main surface. In some embodiments, the wide-bandgap semiconductor includes silicon carbide.

[0025] According to some embodiments of the present disclosure, a device is provided. The device may include a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, a plurality of source trenches in an upper portion of the semiconductor layer structure, each source trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, a plurality of gate trenches in the upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, and a plurality of polysilicon layers, each polysilicon layer being below a respective one of the plurality of source trenches.

[0026] In some embodiments, the plurality of source trenches includes a first source trench, each having a respective polysilicon layer below its lower surface, and each gate trench has no polysilicon layer below its lower surface. In some embodiments, the device may include a gate structure in each gate trench. In some embodiments, each gate trench and each source trench extend a predetermined length in a direction parallel to the upper surface of the semiconductor layer structure, and each polysilicon layer extends only as long as the respective source trench. In some embodiments, the device may include a channel region in the first and second sidewalls of each gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region. In some embodiments, the device may include a first source / drain contact on a first main surface of the semiconductor layer structure and a second source / drain contact on a second main surface of the semiconductor layer structure opposite the first main surface.

[0027] According to some embodiments of the present disclosure, a device is provided. The device includes a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, and a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, each gate trench including a plurality of first length portions, a plurality of second length portions, and a plurality of third length portions, a plurality of first polysilicon layers, each first polysilicon layer being on the first sidewall of each gate trench in the first length portion, and a plurality of second polysilicon layers, each second polysilicon layer being on the second sidewall of each gate trench in the second length portion. The first and second sidewalls of each gate trench in the third length portion can be without the first and second polysilicon layers.

[0028] In some embodiments, the device can include an oxide layer in each gate trench. The oxide layer can have a first cross-section in the first length portion of each gate trench, a second cross-section in the second length portion of each gate trench, and a third cross-section in the third length portion of each gate trench. In some embodiments, the device can include a gate structure in each gate trench, the gate structure including a gate electrode. The gate electrode can have a first cross-section in the first length portion of each gate trench, a second cross-section in the second length portion of each gate trench, and a third cross-section in the third length portion of each gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device can include a first source / drain contact on a first main surface of the semiconductor layer structure and a second source / drain contact on a second main surface of the semiconductor layer structure opposite the first main surface. In some embodiments, the wide-bandgap semiconductor includes silicon carbide.

[0029] According to some embodiments of the present disclosure, a device is provided. The device includes a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, and a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, each gate trench including a plurality of first length portions and a plurality of second length portions, a plurality of polysilicon layers, each first polysilicon layer being on the first and second sidewalls of each respective gate trench within the first length portion. The first and second sidewalls of each gate trench within the second length portion can be without a polysilicon layer.

[0030] In some embodiments, the device can include an oxide layer within each gate trench. The oxide layer can have a first cross-section within the first length portion of each gate trench and a second cross-section within the second length portion of each gate trench. In some embodiments, the device can include a gate structure within each respective gate trench, the gate structure including a gate electrode. The gate electrode can have a first cross-section within the first length portion of each gate trench and a second cross-section within the second length portion of each gate trench. In some embodiments, the semiconductor layer structure includes a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device can include a first source / drain contact on a first main surface of the semiconductor layer structure and a second source / drain contact on a second main surface of the semiconductor layer structure opposite the first main surface. In some embodiments, the wide-bandgap semiconductor includes silicon carbide.

[0031] According to some embodiments of the present disclosure, a device is provided. The device includes a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, and a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, each gate trench exposing a side surface of the drift region, and a plurality of polysilicon layers, each polysilicon layer being on at least a portion of the first and second sidewalls of a respective gate trench.

[0032] In some embodiments, the device can include an oxide layer in each gate trench. In some embodiments, the device can include a gate structure in each gate trench, the gate structure comprising a gate electrode. In some embodiments, the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type. In some embodiments, the device can include a first source / drain contact on a first main surface of the semiconductor layer structure and a second source / drain contact on a second main surface of the semiconductor layer structure opposite the first main surface. In some embodiments, the wide-bandgap semiconductor includes silicon carbide.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0034] In most cases, a MISFET includes a gate dielectric layer formed as an oxide layer (e.g., a silicon oxide layer). A MISFET having an oxide gate dielectric layer is called a metal oxide semiconductor field effect transistor or "MOSFET: Metal Oxide Semiconductor Field Effect Transistor". As will be discussed in more detail below, the oxide gate dielectric layers in these devices can be susceptible to damage when exposed to high electric fields. Therefore, power MOSFETs (and other power semiconductor devices) that include gate trenches often have a shield region that is formed under the gate trench and serves to reduce the electric field level in the oxide gate dielectric layer during reverse blocking operation. Since oxide gate dielectric layers are almost always used because of their excellent electrical properties, the discussion of the embodiments of the present invention below will focus on MOSFETs as opposed to MISFETs, although it will be recognized that the techniques according to the embodiments of the present invention described herein are equally applicable to devices having gate dielectric layers formed of materials other than oxides.

[0035] SiC gate trenches in MOSFET vertical power devices are attractive due to their inherently low specific on-resistance, which can result in more efficient operation for power switching operations that require mild to moderate reverse blocking voltage levels (e.g., 650 - 1200V). Since the channel is formed on the sidewalls of the gate trench and the trench design reduces the overall pitch of the device, enabling high integration, trench MOSFET vertical power devices can exhibit low specific resistance during on-state operation. Furthermore, the carrier mobility in the sidewall channels of trench MOSFETs has been found to be 2 - 4 times higher than the corresponding carrier mobility in the channels of planar (e.g., lateral structure) devices. This increased carrier mobility also increases the current density. However, SiC gate trench MOSFET vertical power devices can suffer from oxide reliability issues due to the presence of steep high electric field corners at the lower edges of the trenches, which can break down the gate oxide over time and ultimately lead to device failure.

[0036] FIG. 1A is a schematic cross-sectional view of a first wide bandgap power MOSFET 100A. As shown in FIG. 1A, the power MOSFET 100A includes an (n + ) n-type silicon carbide substrate 110 doped at a high concentration. A lightly doped (n - ) silicon carbide drift region 120 is provided on the substrate 110. A moderately doped p-type silicon carbide layer 170 is formed on the upper surface of the n-type drift region 120. The moderately doped p-type silicon carbide layer 170 can be formed, for example, by epitaxial growth. This moderately doped p-type silicon carbide layer 170 can provide a p-well 172 for the device 100. A transistor channel can be formed within the p-well 172, as discussed below. A highly doped n + silicon carbide source layer 160 can be formed within the upper region of the p-type silicon carbide layer 170. A highly doped n +The silicon carbide source layer 160 can be formed, for example, by ion implantation.

[0037] The substrate 110, the drift region 120, the moderately doped p-type layer 170, and the highly doped n + The silicon carbide source layer 160, together with the various regions / patterns formed therein, constitutes the semiconductor layer structure 106 of the MOSFET 100A.

[0038] The gate trench 180 is formed within the semiconductor layer structure 106. The gate trench 180 is highly doped n + The silicon carbide source layer 160 and the moderately doped p-type layer 170 can extend into the drift region 120. The gate insulating layer 182 can be formed on the lower surface and sidewalls of each gate trench 180. The gate electrode 184 can be formed on each gate insulating layer 182 to fill each gate trench 180. The vertical channel region 178 is provided in the p-well 172 adjacent to the gate insulating layer 182.

[0039] The source contact (not shown) can be formed on the highly doped n-type source region 160. The drain contact (not shown) can be formed on the lower surface of the substrate 110. The gate contact (not shown) can be formed on the gate electrode 184.

[0040] Typically, when the gate insulating layer 182, implemented as a silicon oxide layer, is subjected to an overly high electric field, the gate insulating layer 182 deteriorates over time and ultimately fails to insulate the gate electrode 184 from the semiconductor layer structure, which can lead to device failure. The corners of the gate insulating layer 182 (e.g., the area where the gate insulating layer 182 transitions from a vertical surface to a horizontal surface) are particularly susceptible to such high electric fields. To improve the reliability of the gate insulating layer 182, the power MOSFET 100 includes a deep shield pattern 140 under the gate trench 180. The deep shield pattern 140 is a highly doped (p formed in the upper surface of the n-type drift region 120 by ion implantation.+ ) It can be made into a silicon carbide pattern.

[0041] The deep shield pattern 140 can be considered to be very effective in protecting the corners of the gate insulating layer 182 from high electric fields during the reverse blocking operation. The deep shield pattern 140 can provide a shield for the gate insulating layer 182 and can provide the desired device performance resulting from the utilization of two sidewall surfaces for current conduction.

[0042] The deep shield pattern 140 of the power MOSFET 100A can be formed following the formation of the gate trench 180 and prior to the formation of the gate insulating layer 182 and the gate electrode 184 therein. Ion implantation can be used to form the deep shield pattern 140. The depth at which ions are implanted is directly related to the energy of the implant, i.e., ions implanted into the semiconductor layer at higher energies tend to penetrate deeper into the layer. Therefore, forming a deep shield pattern (which may have a thickness of 1 to 5 microns) by ion implantation requires high energy implantation.

[0043] When dopant ions are implanted into a semiconductor layer, the ions damage the crystal lattice of the semiconductor layer, and this damage can typically only be partially repaired by thermal annealing. Further, the amount of lattice damage is also directly related to the implant energy, and higher energy implants tend to cause more lattice damage than lower energy implants, and the uniformity of the ion implant also tends to decrease with increasing implant depth. Therefore, in order to form an implanted region having good doping uniformity with depth and / or an acceptable level of lattice damage, it may be necessary to perform a plurality of successive epitaxial growth / ion implantation steps to form a deep implant. This can significantly increase the complexity and cost of the manufacturing process and, in many cases, may not be a commercially viable option.

[0044] Further, the formation of the deep shield pattern 140 can be a problem due to the anisotropic etching of the silicon carbide layers 160, 170, and 120 during the formation of the gate trench 180. While FIG. 1A shows an ideal trench 180 and deep shield pattern 140, FIG. 1B is a schematic cross-sectional view of the power MOSFET 100B during the formation of the deep shield pattern 140 by ion implantation 190, which may result from current formation techniques. As can be seen, the sidewalls of the trench 180B are angled (i.e., not vertical) by anisotropic etching. Due to the angling of the sidewalls and the ion scattering effect, p-type ions are implanted into the semiconductor region, and p + Form the sidewalls of the gate trench 180 during the formation of the deep shield pattern 140. The implantation of p-type ions into these regions of the device changes the effective doping levels of these regions. Further, the drift region 120 is lightly doped (n - ) region (e.g., heavily doped (p +) is several orders of magnitude lower than the deep shield pattern 140), the n-type dopants in the upper portion of the drift region 120 can be at least partially compensated by the unintentional doping of p-type dopants into the trench sidewalls that can occur during the ion implantation step used to form the deep shield pattern 140. This can result in an increase in JEFT resistance (since the effective n-type doping level is reduced by the implantation of compensating p-type ions), and in some cases, as shown in FIG. 1B, the p-type dopants can completely overwhelm the background n-type doping of the drift region 120, resulting in the formation of a p-type pinch region 144, which is a p-type layer highly doped with (p + ) is connected to a p-type layer 170 doped to a medium concentration with the deep shield pattern 140. When this occurs, the current is pinched off, rendering the power MOSFET 100B inoperable or with significantly degraded performance.

[0045] The approach of ensuring that the sidewalls of the drift region 120 exposed by the trench 180 between the p-well 172 and the deep shield pattern 140 are not unintentionally doped with p-type dopants during the formation of the deep shield pattern 140 will be described below with reference to FIGS. 2A - 3C. FIGS. 2A - 2C show operations 200A - 200C, respectively, of a first related art approach for forming a power MOSFET that addresses the problems presented by the gate trench power MOSFET of FIG. 1B. Prior to operation 200A shown in FIG. 2A, a trench etch oxide mask 210 can be formed on the upper surface of the device, and the gate trench 180 can be formed by etching. In operation 200A of FIG. 2A, with the trench etch oxide mask 210 still present, a sidewall oxide mask 220 is formed on the highly doped n-type exposed by the gate trench 180 + silicon carbide source layer 160, a p-type layer 170 doped to a medium concentration, and an n-type doped to a low concentration -It can be formed by oxidizing a portion of the silicon carbide drift region 120. This sidewall oxide mask can be formed by thermal oxidation.

[0046] In operation 200B shown in FIG. 2B, ion implantation 190 is performed at a low concentration doped n exposed at the bottom of trench 180 - into a portion of the silicon carbide drift region 120 doped at a high concentration with (p + ) to implant a deep shield pattern 240 of silicon carbide. Ion implantation 190 can also be performed on the exposed surfaces of trench etch oxide mask 210 and sidewall oxide mask 220, resulting in portions 211 of trench etch oxide mask 210 and portions 221 of sidewall oxide mask 220 being implanted with p-type dopants.

[0047] In operation 200C shown in FIG. 2C, oxide masks 210 and 220 can be removed, along with portions 211 and 221, respectively, that received ion implantation in operation 200B. The removal of oxide masks 210 and 220 ensures that the portion 120S of the low-concentration doped n silicon carbide drift region 120 exposed by the trench is not substantially counter-doped with p-type dopants, thus avoiding the problems of the power MOSFET 100B of FIG. 1B. -

[0048] ​One advantage of the approach of FIGS. 2A-2C is that when a device is formed on a SiC wafer having an exposed (0001) plane, due to the crystal orientation effect, the sidewall oxide mask 220 is formed much more rapidly than the oxide formed on the portion of the drift region 120 exposed at the bottom of the gate trench 180. On the other hand, a disadvantage of the approach of FIGS. 2A-2C is that the resulting gate trench 180W formed subsequent to operation 200C is wider and deeper than the original gate trench 180 formed prior to operation 200A of FIG. 2A. As a result, the width of the deep shield pattern 240 is narrower than the width of the gate trench 180, which means that the deep shield pattern 240 does not extend to cover the lower corners of the gate insulating layer subsequently formed within the gate trench 180W, and thus the deep shield pattern provides insufficient protection for the most vulnerable portions of the gate insulating layer. Similarly, the formation of the sidewall oxide mask 220 in operation 200A may result in a ledge surface 220L (see FIG. 2A), and the ledge surface 220L may scatter in an unintended direction during operation 200B, for example, resulting in a higher concentration of p-type doping in the channel region (requiring a thicker sidewall oxide mask 220 and making the resulting gate trench 180W even wider).

[0049] FIGS. 3A-3C illustrate a second related art approach for forming a power MOSFET that addresses the problems presented by the gate trench power MOSFET of FIG. 1B. Prior to operation 300A shown in FIG. 3A, a trench etch oxide mask 210 is formed on the upper surfaces of the highly doped n + silicon carbide source layer 160 and the moderately doped p-type layer 170, and the gate trench 180 is formed by etching. In operation 300A of FIG. 3A, and with the trench etch oxide mask 210 still present, a sidewall oxide mask 320 is formed on the highly doped n +Silicon carbide source layer 160, a p-type layer 170 doped at a medium concentration, and an n doped at a low concentration - It can be formed by depositing a mask material (e.g., SiO2) on a portion of the silicon carbide drift region 120 and on the upper surface of the trench etch oxide mask 210.

[0050] In operation 300B shown in FIG. 3B, the ion implantation 190 is an n doped at a low concentration - Highly doped (p) in the silicon carbide drift region 120 + ) It can be carried out to implant a deep shield pattern 340 of silicon carbide. The ion implantation 190 can also be carried out on the exposed surfaces of the trench etch oxide mask 210 and the sidewall oxide mask 320, resulting in the portions of the trench etch oxide mask 210 and the portion 321 of the sidewall oxide mask 220 being implanted with ions.

[0051] In operation 300C shown in FIG. 3C, the oxide masks 210 and 320, together with their portions that received ion implantation in operation 300B, can be removed. Similar to the operations in FIGS. 2A - 2C, the removal of the oxide masks 210 and 320 results in a portion 120S of the low-concentration n-doped silicon carbide drift region 120 that is substantially unaffected by the deep shield pattern 340 of the highly doped (p + ) silicon carbide, and thus the problems of the power MOSFET 100B in FIG. 1B can be avoided. -

[0052] ​The approach of FIGS. 3A - 3C offers an advantage in that the resulting gate trench following operation 300C in FIG. 3C has the same width as the original gate trench 180 etched prior to operation 300A in FIG. 3A. This is because, unlike operations 200A - C, none of the materials of the drift region 120, p-type layer 170, and source layer 160 are thermally oxidized. A ledge surface similar to surface 200L is also preferably avoided. However, a drawback of the approach of FIGS. 3A - 3C is that the deposition of the sidewall mask material to form the sidewall oxide mask 320 may result in a thicker mask being applied to the lower part of the gate trench 180 (e.g., on the upper surface of the drift region 120 exposed by the gate trench 180) compared to along the sidewalls of the gate trench 180. This thicker mask at the lower part of the gate trench 180 can potentially prevent the implantation of ions used to form the deep shield pattern 340 of highly doped (p + ) silicon carbide from being accepted. Thinning the sidewall oxide mask 320 (e.g., by depositing less material), on the other hand, may potentially require re-etching of the gate trench 180 to remove the implanted material within the sidewalls of the drift region 120, p-type layer 170, and source layer 160, and also results in a gate trench that is wider and deeper than the original gate trench 180 formed prior to operation 300A in FIG. 3A.

[0053] As discussed above, the formation of deep shield regions can be time-consuming and can result in implantation damage to the semiconductor device structure. According to embodiments of the present invention, gate-trench wide-bandgap power semiconductor devices such as power MOSFETs and power IGBTs lacking deep trench shield patterns under the gate trenches are provided. Instead, the doped polysilicon material can be used as a shield material to shield a portion of the lower part of the gate trench and a plurality of portions of one sidewall of the gate trench. Using highly doped polysilicon as a blocking material can simplify the operation of forming the gate-trench wide-bandgap power semiconductor device and can reduce the implantation damage to the device. Thus, the exemplary embodiments of the present disclosure can reduce or avoid the drawbacks of the approaches of FIGS. 1B, 2A-2C, and 3A-3C. Further, in some embodiments, the doped polysilicon region can be connected to the source of the power semiconductor device, which can be advantageous when the device is in a blocking mode of operation.

[0054] The new approach for forming the doped polysilicon blocking region can even reduce or eliminate the implanted p-type dopants within the portion of the drift region that is between the p-well channel and the deep shield pattern. Therefore, the devices according to embodiments of the present invention can show improved performance compared to devices formed using the techniques discussed above with respect to the power MOSFET 100B of FIG. 1B. Further, the approach according to embodiments of the present invention can avoid the difficulties in forming deeper and / or wider gate trenches similar to those in FIGS. 2A-2C, or deep shield patterns that occur as in FIGS. 3A-3C.

[0055] Embodiments of the present invention are described herein with reference to FIGS. 4A - 13. It will be recognized that the features of the different embodiments disclosed herein can be combined in any way to provide many further embodiments. Thus, for example, the features of any MOSFET embodiment described herein can be incorporated within an IGBT embodiment and vice versa. Thus, while various features of the inventive concept are described below with respect to specific examples, it will be recognized that these features can be added to other embodiments and / or used in place of exemplary features of other embodiments to provide many further embodiments. Thus, it should be understood that the present invention encompasses these different combinations.

[0056] FIGS. 4A - 4D are schematic diagrams showing a gate - trench - power MOSFET according to an embodiment of the inventive concept. More specifically, FIG. 4A is a plan view of the upper surface of a semiconductor layer structure of a gate - trench - power MOSFET device. FIG. 4B is a cross - sectional view taken along line B - B of FIG. 4A, and FIG. 4C is a corresponding perspective view. FIG. 4D is a cross - sectional view taken along line B - B in FIG. 4A, showing the device after a gate material 490 (not shown in FIGS. 4A - 4C) is formed within the gate trench. Further, for better illustration and description of the gate - trench - power MOSFET device, an oxide layer 455 (discussed below) is omitted in FIGS. 4A and 4C.

[0057] Referring to FIGS. 4A - 4D, a gate - trench - power MOSFET device 400 can include a semiconductor layer structure 406. The semiconductor device can include a highly doped (n + ) n - type silicon carbide substrate 410. A lightly doped (n - ) silicon carbide drift region 420 can be formed on the substrate 410 by epitaxial growth. A moderately doped p - type layer is formed on the upper surface of the n - type silicon carbide drift region 420. A highly doped (n +)The n-type silicon carbide region is formed within the upper region of a p-type layer doped at a medium concentration by ion implantation. The (n doped at a high concentration + )n-type silicon carbide region can serve as a source region. All of the layers described above can be grown in a single epitaxial growth process, and the single epitaxial growth process has a process stop for switching between n-type doping and p-type doping (within the upper region of the p-type layer doped at a medium concentration, the (n doped at a high concentration + )subsequent ion implantation step for forming the n-type silicon carbide region). The layers described above include a semiconductor layer structure 406.

[0058] The gate trench 480 can be etched into the upper surface of the semiconductor layer structure 406. Only one gate trench 480 is shown in FIGS. 4B - 4D, but a plurality of gate trenches 480 are typically provided, and each gate trench 480 extends in a first direction (e.g., from the upper surface of the n-type silicon carbide layer towards the substrate 410), and it will be recognized that the gate trenches 480 are spaced apart from each other in a second direction so as to extend a predetermined length parallel to each other. The gate trench 480 can be perpendicular to the first direction and can extend a predetermined length in a third direction parallel to the upper surface of the substrate 410.

[0059] Each gate trench 480 can extend through the n-type silicon carbide layer doped at a high concentration and convert this silicon carbide layer into a plurality of spaced regions 464 that will ultimately serve as the source region of the power MOSFET. Each gate trench 480 can also extend through the p-type silicon carbide layer doped at a medium concentration and convert this layer into a plurality of p-wells 472. Each gate trench 480 can also extend within the upper surface of the n-type drift region 420.

[0060] As can be seen in FIG. 4B, the etching of the gate trench 480 can result in its non-parallel sidewall surfaces. In other words, the sidewalls can be angled with respect to a normal (perpendicular) line to the upper surface of the substrate 410.

[0061] After the etching of the gate trench 480, the polysilicon layer 450 can be deposited on top of the upper surface of the semiconductor layer structure 406. The polysilicon layer 450 can be a p-type polysilicon layer doped at a high concentration. The polysilicon layer 450 can be deposited along one sidewall of the gate trench 480 and can conform to the sidewall of the gate trench 480. The polysilicon layer 450 can be a continuous layer extending parallel to the length direction of the gate trench 480. The polysilicon layer 450 can be formed, for example, by blanket-forming a polysilicon layer on the device and using an etch mask to selectively etch the blanket polysilicon layer. Alternatively, the mask can be formed first, and the polysilicon layer can be selectively deposited within the opening in the mask. Other techniques can also be used.

[0062] In other words, the polysilicon layer 450 can be deposited on the sidewalls of the n-type drift region 420 and the sidewalls of the p-type silicon carbide layer that are both exposed by the etched gate trench 480. In some embodiments, an optical process can be used to define the polysilicon layer 450 on the sidewalls of the gate trench 480. In some exemplary embodiments, and as seen in FIG. 4B, the polysilicon layer 450 can also be deposited on a portion of the lower part of the gate trench 480 (e.g., on the upper surface of the n-type drift region 420 exposed by the gate trench 480) and on the upper part of the p-well 472. In some embodiments, the thickness of the polysilicon layer 450 can be in the range of 100 nanometers (nm) to 500 nm, but the present disclosure is not limited thereto.

[0063] Referring to FIGS. 4A and 4C, the gate trench 480 and the polysilicon layer 450 can extend continuously along the length of the device 400 and / or the length of the semiconductor layer structure 406.

[0064] After the polysilicon layer 450 is deposited, an oxide layer 455 can be formed. The oxide layer 455 can be formed both on and in the upper surface of the polysilicon layer and on the exposed portion of the silicon carbide semiconductor layer structure 406, as shown in FIG. 4B. In some embodiments, the oxide layer 455 can be formed by annealing in an oxygen-containing environment to oxidize the polysilicon layer 450 and the exposed silicon carbide. When the oxide layer 455 is formed by thermal oxidation, the polysilicon layer 450 can oxidize more rapidly than the exposed silicon carbide surface (and the exposed silicon carbide surface can also oxidize at different rates depending on which plane of the crystal structure is exposed), and thus it will be recognized that the oxide layer 455 may not have a uniform thickness. Additionally or alternatively, the oxide layer 455 can be formed by deposition. Any unnecessary portions of the oxide layer 455 (e.g., the oxidized silicon carbide surface outside the gate trench 480) can be removed. After the formation of the polysilicon layer 450 and the oxide layer 455, further processing (e.g., forming a gate insulating layer, a gate electrode, and contacts) can be performed to form a power MOSFET. For example, the gate electrode 490 shown in FIG. 4D can be formed.

[0065] The devices of FIGS. 4A - 4D avoid the drawbacks of FIGS. 2A - 3C discussed above and also avoid possible problems that may arise from the implantation of ions into the n-type drift region 420. The formation of the polysilicon layer 450 can also provide a reduction in the number of operations and / or a simplified manufacturing of the device.

[0066] Figures 4E and 4F are schematic diagrams showing a gate-trench power MOSFET according to an embodiment of the concept of the present invention. Figure 4E is a cross-sectional view, and Figure 4F is a corresponding perspective view. Figures 4E and 4F show that in some embodiments, a polysilicon layer 450 can be formed on both sides of the gate trench 480. In fact, in some embodiments, some of the gate trenches 480 can have a polysilicon layer 450 formed on the "right" sidewall, while other gate trenches 480 in the device can have a polysilicon layer 450 formed on the "left" sidewall (i.e., some of the gate trenches can have the design of Figures 4B - 4D, while other gate trenches can have the design of Figures 4E - 4F). Therefore, the gate trenches 480 of these devices can have a first sidewall that does not include the polysilicon layer 450 (which can be the left sidewall for some gate trenches and the right sidewall for other gate trenches) and a second sidewall on which the polysilicon layer 450 is formed (which can also be the left sidewall for some gate trenches and the right sidewall for other gate trenches).

[0067] Figure 14 is a schematic diagram showing a gate-trench power MOSFET 1400 according to a further embodiment of the concept of the present invention. Figure 14 shows that in some embodiments, the gate trench 480 can be etched to extend deeper into the n-type drift region 420 from the upper surface of the n-type drift region 420. The polysilicon layer 1450 can be formed or deposited to completely cover the first sidewall of the gate trench 480 and partially cover the second sidewall of the gate trench 480. The polysilicon layer 1450 can also completely cover the lower surface of the gate trench 480. The gate trench 480 and the polysilicon layer 1450 can extend continuously along the length of the device 400 and / or the length of the semiconductor layer structure 406.

[0068] Figures 5A - 5E are schematic diagrams showing a gate - trench power MOSFET according to an embodiment of the concept of the present invention. More specifically, FIG. 5A is a plan view of the upper surface of a gate - trench power MOSFET device, and FIGS. 5B, 5C, 5D, and 5E are cross - sectional views. FIG. 5B is taken along line B - B of FIG. 5A. FIG. 5C is taken along line C - C of FIG. 5A. FIGS. 5D and 5E respectively correspond to FIGS. 5B and 5C, and also include gate material 590 excluded from FIGS. 5A - 5C to better show the polysilicon layer within the gate - trench. Further, to better show and explain the gate - trench power MOSFET device, oxide layer 555 is omitted in FIGS. 5A, 5B, and 5C.

[0069] Referring to FIGS. 5A - 5E, the gate - trench power MOSFET device 500 can include a semiconductor layer structure 506. When formed, the semiconductor layer structure 506 can be the same as the semiconductor layer structure 406 of FIGS. 4A - 4D, and thus further description thereof is omitted here.

[0070] The gate - trench 480 can be etched within the upper surface of the semiconductor layer structure 506. The gate - trench 480 can be the same as the gate - trench 480 of FIGS. 4A - 4D, and thus further description thereof is omitted here.

[0071] The polysilicon layer 550 can be deposited on top of the upper surface of the semiconductor layer structure 506. The polysilicon layer 550 can be a p-type polysilicon layer doped at a high concentration. The polysilicon layer 550 can be deposited in a discontinuous region along one sidewall of the gate trench 480, and each of the discontinuous regions can coincide with the sidewall of the gate trench 480. In other words, there can be a first region 480-1 of the gate trench 480 where the polysilicon layer 550 is deposited, and there can be a second region 480-2 of the gate trench 480 where there is no polysilicon layer 550. The first region 480-1 of the gate trench 480 can alternate with the second region 480-2 of the gate trench 480 in a third direction (e.g., the direction in which the gate trench 480 extends for a predetermined length). Each first region 480-1 of the gate trench 480 can be between a pair of adjacent second regions 480-2 of the gate trench 480, and / or each second region 480-1 of the gate trench 480 can be between a pair of adjacent first regions 480-1 of the gate trench 480. In some exemplary embodiments, a patterned mask layer and / or a photolithography process can be used to deposit the polysilicon layer 550 within the first region 480-1 of the gate trench 480.

[0072] The polysilicon layer 550 within the first region 480-1 can be deposited on one sidewall of the sidewall of the trench 480. For example, as shown in FIG. 5B, each sidewall of the gate trench 480 is formed by an exposed portion of the n-type drift region 420 and one p-well 472 of the p-well 472. In some exemplary embodiments, as seen in FIG. 5B, the polysilicon layer 550 can be on a portion of the lower part of the first portion 480-1 of the gate trench 480 (e.g., on the upper surface of the n-type drift region 420 exposed by the gate trench 480), and also on the upper part of the p-well 472 adjacent to the first portion 480-1 of the gate trench 480. In some embodiments, the thickness of the polysilicon layer 450 can be in the range of 100 nanometers (nm) to 500 nm, but the present disclosure is not limited thereto.

[0073] After the polysilicon layer 550 is deposited in the first region 480-1 of the etched gate trench 480, an oxide layer 555 can be formed. The oxide layer 555 can be formed on the polysilicon layer 550, or in other words, can include a first portion 555-1 formed on the polysilicon layer 550 within the first region 480-1 of the etched gate trench 480. The oxide layer 555 can also include a second portion 555-2 formed on the surfaces of components of the semiconductor layer structure 506, such as the drift region 420, the p-well 472, and the highly doped n-type silicon carbide region 464, which are exposed within the second region 480-2 of the gate trench 480. For example, within the first region 480-1 of the gate trench, the polysilicon layer 550 can be oxidized by annealing in an oxygen-containing environment, resulting in the first portion 555-1 of the oxide layer 555. Within the second region 480-2 of the gate trench, the surfaces of the drift region 420, the p-type silicon carbide layer 470, and the highly doped n-type silicon carbide region 464, which are exposed within the second region 480-2, can be oxidized by annealing in an oxygen-containing environment, resulting in the second portion 555-2 of the oxide layer 555. Additionally or alternatively, the oxide layer 455 can be formed by deposition. The first portion 555-1 of the oxide layer 555 can have a cross-section different from that of the second portion 555-2 of the oxide layer. The oxide layer 555 can have different thicknesses in different regions for the same reasons discussed above with respect to the embodiments of FIGS. 4A-4D.

[0074] After the formation of the polysilicon layer 450 and the oxide layer 555, further processing (e.g., forming a gate insulating layer, a gate electrode, and contacts) can be performed to form a power MOSFET. For example, a gate electrode 590 as shown in FIGS. 5D and 5E can be formed. Similar to the case of the oxide layer 555, the gate electrode 590 can have a different cross-section 590-1 within the first region 480-1 of the gate trench compared to the cross-section 590-2 within the second region 480-2.

[0075] The exemplary embodiments of FIGS. 5A-5E can provide that the sidewall of the gate trench 480 is in a second region 480-2 without the polysilicon layer 550, and the channel can conduct current along the sidewall thereof, for example, by a p-well formed in the sidewall. Note that in FIG. 5A, the polysilicon layers in adjacent gate trenches are shown as being aligned. It will be recognized that embodiments of the present invention are not limited to such an arrangement configuration. For example, in other embodiments, the polysilicon layers 455 in adjacent trenches can be completely offset from each other (i.e., as a result, no portion of the polysilicon layer is aligned in the horizontal direction of the figure in FIG. 5A), or can be partially offset from each other.

[0076] Figures 5F and 5G are schematic diagrams showing a gate-trench power MOSFET according to a further embodiment of the concept of the present invention. Figure 5F is a cross-sectional view, and Figure 5G includes gate material 590 removed from Figure 5F to better show the polysilicon layer within the gate-trench of Figure 5F. Figures 5F and 5G show that, in some embodiments, the polysilicon layer 550 can be formed on both sides of the gate-trench 480. Further, in some embodiments, the gate-trench 480 can comprise a first region 480-1 (seen in Figure 5B), a second region 480-2 (seen in Figure 5C), and a third region 480-3 (seen in Figure 5G). Within the first region 480-1 of the gate-trench 480, the polysilicon layer 550 can be formed on the first sidewall 480-R of the gate-trench 480. Within the third region 480-3 of the gate-trench 480, the polysilicon layer 550 can be formed on the second sidewall 480-L of the gate-trench 480. Within the second region 480-2, both the first and second sidewalls 480-R, 480-L of the gate-trench can be assumed to be without the polysilicon layer 550. Within the first and third regions 480-1 and 480-3, the channel can conduct current by the sidewall without the polysilicon layer 550, and in the second region 480-2 (where both sidewalls of the gate-trench 480 are without the polysilicon layer 550), the channel can conduct current along both sidewalls, for example, by a p-well formed in the sidewalls.

[0077] Figures 15A and 15B are schematic diagrams showing a gate trench power MOSFET 1500 according to a further embodiment of the concept of the present invention. Figures 15A and 15B show that in some embodiments, within a first region 480-1, a polysilicon layer 1550 can be formed on both sides of the gate trench 480, and within a second region 480-2, it can be assumed that there is no polysilicon layer 1550 on both the first and second sidewalls of the gate trench. Within the first region 480-1, since both sidewalls are covered by the polysilicon layer 1550, current cannot be conducted. Within the second region 480-2 (where there is no polysilicon layer 1550 on both sidewalls of the gate trench 480), the channel can conduct current along both sidewalls, for example, by means of a p-well formed on the sidewalls.

[0078] Figures 6A-6B are schematic cross-sectional views showing a gate trench power MOSFET device 600 according to an embodiment of the concept of the present invention. Figures 6C and 6D are cross-sectional views of a gate trench power MOSFET device 600', showing regions of the device having a cross-section different from that shown in Figures 6A and 6B.

[0079] Referring to Figures 6A and 6B, the gate trench power MOSFET device 600 can be made similar to the gate trench power MOSFET device 400 described with reference to Figures 4A-4D, except that the MOSFET device 600 further includes an additional oxide layer 654 between the sidewall of the gate trench 480 and the polysilicon layer 450.

[0080] The gate trench power MOSFET device 600 can include a semiconductor layer structure 406 having an internally formed gate trench 480. The semiconductor layer structure 406 and the gate trench 480 can be the same as those of the semiconductor layer structure 406 and the gate trench in the embodiments of Figures 4A-4D, and thus, further description thereof is omitted here.

[0081] Prior to the deposition of the polysilicon layer 450, the underlying oxide layer 654 can be formed. For example, the surfaces of the drift region 420, p-type well 472, and highly doped n-type silicon carbide region 464 that are exposed within the gate trench 480 can be oxidized by annealing in an oxygen-containing environment, resulting in the underlying oxide layer 654. Additionally or alternatively, the underlying oxide layer 654 can be formed by deposition.

[0082] The polysilicon layer 450 can be deposited on top of the upper surface of the semiconductor layer structure 506 and / or on the upper surface of the underlying oxide layer 654. The polysilicon layer 450 can be the same as the polysilicon layer 450 discussed above with reference to the embodiments of FIGS. 4A - 4D, except that in the embodiments of FIGS. 6A - 6B, the polysilicon layer 450 is formed on the underlying oxide layer 654 as opposed to being formed directly on the underlying semiconductor layer structure 606. Accordingly, further description of the polysilicon layer 450 is omitted here.

[0083] After the polysilicon layer 450 is deposited, the upper oxide layer 655 can be formed. For example, the exposed surfaces of the polysilicon layer 450 and the semiconductor layer structure 606 can be oxidized by annealing in an oxygen-containing environment. Additionally or alternatively, the upper oxide layer 655 can be formed by deposition. The upper oxide layer 655 can be formed by a process different from that of the underlying oxide layer 654. After the formation of the polysilicon layer 450 and the upper oxide layer 655, further processing (e.g., forming a gate insulating layer, gate electrode, and contacts) can be performed to form a power MOSFET. For example, the gate electrode 490 shown in FIG. 6B can be formed.

[0084] The gate-trench power MOSFET device 600 corresponds to the gate-trench power MOSFET device 400 of FIGS. 4A - 4D by the addition of the lower oxide layer 654. It will be recognized that the gate-trench power MOSFET device 500 of FIGS. 5A - 5D can be similarly modified to include the lower oxide layer 654 in order to provide the gate-trench power MOSFET device 600'. FIGS. 6A - 6D show such a gate-trench power MOSFET device 600'. In particular, FIGS. 6A - 6B discussed above show a cross-section of the device 600' including the polysilicon layer 450 (thus corresponding to the cross-sections of FIGS. 5B and 5D). FIGS. 6C and 6D show cross-sections of the device 600' without the polysilicon layer 450 (thus corresponding to the cross-sections of FIGS. 5C and 5E).

[0085] As shown in FIGS. 6C - 6D, the lower oxide layer is formed throughout the entire gate-trench 480 (including the portion 480-2 of the gate-trench 480 that does not include the polysilicon layer 550).

[0086] After the lower oxide layer 654 is formed, the polysilicon layer 550 can be deposited in a discontinuous region along one sidewall of the gate trench 480, and each of the discontinuous regions can coincide with the sidewall of the gate trench 480. In other words, there can be a first region 480-1 of the gate trench 480 where the polysilicon layer 550 is deposited, and there can be a second region 480-2 of the gate trench 480 where the polysilicon layer 550 is absent. The first region 480-1 of the gate trench 480 can alternate with the second region 480-2 of the gate trench 480 in a third direction (e.g., the direction in which the gate trench 480 extends a predetermined length). Each first region 480-1 of the gate trench 480 can be between a pair of adjacent second regions 480-2 of the gate trench 480, and / or each second region 480-1 of the gate trench 480 can be between a pair of adjacent first regions 480-1 of the gate trench 480. In some exemplary embodiments, the patterned mask layer and / or the optical process can be used to deposit the polysilicon layer 550 within the first region 480-1 of the gate trench 480.

[0087] As described above, the portion of the gate trench power MOSFET 650 having the first region 480-1 of the gate trench 480 can be the same as the gate trench power MOSFET 600 shown in FIGS. 6A-6B, and reference is made to the description thereof above. After the polysilicon layer is deposited within the first region 480-1 of the etched gate trench 480, the upper oxide layer 655 can be formed. The upper oxide layer 655 can be formed on the polysilicon layer 550, or in other words, can include a first portion formed on the polysilicon layer within the first region 480-1 of the etched gate trench 480. The upper oxide layer 655 can also include a second portion formed on the surfaces of components of the semiconductor layer structure, such as the drift region 420, the p-type well 472, and the highly doped n-type silicon carbide region 464, which are exposed within the second region 480-2 of the gate trench 480.

[0088] The addition of the lower oxide layer 655 can provide an additional benefit of preventing hole injection into the polysilicon layer 450 when a high voltage is applied to the drain.

[0089] FIG. 7 is a schematic cross-sectional view showing a gate-trench power MOSFET 700 according to an embodiment of the concept of the present invention.

[0090] The gate-trench power MOSFET device 700 can include a semiconductor layer structure 706. The semiconductor layer structure 706 can be similar to the semiconductor layer structure 406 of FIGS. 4A - 4D. For example, the semiconductor layer structure 706 can include a highly doped (n + ) n-type silicon carbide substrate 410, a lightly doped (n - ) silicon carbide drift region 420 formed on the substrate 410 by epitaxial growth, a moderately doped p-well 472 formed on the upper surface of the n-type silicon carbide drift region 420, and a highly doped (n + ) n-type silicon carbide region 464 formed within the upper region of each of the moderately doped p-wells 472 by ion implantation.

[0091] The gate trench 480 can be etched into the upper surface of the semiconductor layer structure 706. Only one gate trench 480 is shown in FIG. 7, but a plurality of gate trenches 480 are typically provided, each gate trench 480 extending in a first direction (e.g., from the upper surface of the n-type silicon carbide layer towards the substrate 410), and it will be recognized that the gate trenches 480 are spaced apart from each other in a second direction so as to extend parallel to each other. The gate trench 480 can be substantially the same as the gate trench 480 of the embodiments of FIGS. 4A - 4D, except that the gate trench of this embodiment can extend deeper into the semiconductor layer structure 706. Each gate trench 480 can also extend into the upper surface of the n-type drift region 420.

[0092] The polysilicon layer 750 can be deposited below the gate trench 480. The polysilicon layer 750 can fill the lower portion of the gate trench 480. The polysilicon layer 750 can be a continuous layer extending parallel to the length direction of the gate trench 480. In other words, the polysilicon layer 750 can be deposited on the upper surface of the n-type drift region 420 exposed by the gate trench 480, but the side walls of the p-well 472 can be assumed to have no polysilicon layer 750. The optical process can be used to define the polysilicon layer 750 at the lower part of the gate trench 480.

[0093] In some embodiments, referring to FIGS. 5B - 5E, the polysilicon layer 750 can also be deposited along one side wall of the gate trench 480 and within at least a first region 480-1 of the gate trench 480.

[0094] After the polysilicon layer 750 is deposited, an oxide layer 755 can be formed. For example, the exposed surfaces of the polysilicon layer 750 and the semiconductor layer structure 606 can be oxidized by annealing in an oxygen-containing environment. Additionally or alternatively, the oxide layer 755 can be formed by deposition. After the formation of the polysilicon layer 750 and the oxide layer 755, further processing (e.g., forming a gate insulating layer, a gate electrode, and contacts) can be performed to form a power MOSFET. For example, as seen in FIG. 7, an intermetal dielectric layer 785, a source contact 796, a drain contact 765, and a gate electrode 490 can be formed.

[0095] FIG. 8 is a schematic cross-sectional view showing a gate trench power MOSFET according to an embodiment of the concept of the present invention. The gate trench power MOSFET device 800 can include a semiconductor layer structure 806. The semiconductor layer structure 806 can be similar to the semiconductor layer structure 406 of FIGS. 4A - 4D. For example, the semiconductor layer structure 806 can be a highly doped (n + ) n-type silicon carbide substrate 410, a lowly doped (n -)Silicon carbide drift region 420, a p-type layer doped at a medium concentration formed on the upper surface of the n-type silicon carbide drift region 420, and a highly doped (n formed in the upper region of the p-type layer 470 doped at a medium concentration by ion implantation + )can include an n-type silicon carbide layer. The silicon carbide region 464 can be used as a source region. All of the layers described above can be grown in a single epitaxial growth process having a process stop that switches between n-type doping and p-type doping.

[0096] A plurality of gate trenches 480 can be etched in the upper surface of the semiconductor layer structure 806 (only one gate trench 480 is shown in FIG. 8). Each gate trench 480 extends in a first direction (e.g., from the upper surface of the n-type silicon carbide layer toward the substrate 410), and the gate trenches 480 are spaced apart from each other in a second direction so as to extend parallel to each other. The gate trenches 480 can be perpendicular to the first direction and can extend a predetermined length in a third direction that can be parallel to the upper surface of the substrate 410. Further, a plurality of source trenches 481 can be etched in the upper surface of the semiconductor layer structure 806 (two source trenches 481 are shown in FIG. 8). The source trenches 481 can be formed by the same etching process used to form the gate trenches 480, or can be at least partially formed by a different etching process. For example, since the source trenches 481 can be formed deeper than the gate trenches 480, a polysilicon layer (described below) formed within the lower portion of the source trenches 481 can provide better protection against the lower portion of the gate trenches 480. The trenches 480, 481 extend through the highly doped n-type silicon carbide layer and can convert the highly doped n-type silicon carbide layer into a plurality of spaced-apart regions 464 that will ultimately serve as the source region 460 of the power MOSFET. The trenches 480, 481 similarly extend through the moderately doped p-type silicon carbide layer and can convert the moderately doped p-type silicon carbide layer into a plurality of p-wells 472. The trenches 480, 481 can also extend within the upper surface of the n-type drift region 420.

[0097] The oxide layer 855 can be formed within each gate trench 480. For example, the exposed surface of the semiconductor layer structure 706 can be oxidized by annealing in an oxygen-containing environment. Additionally or alternatively, the oxide layer 855 can be formed by deposition. After the formation of the oxide layer 855, the gate electrode 890 can be formed within the gate trench 480, and the intermetal dielectric layer 785 can be formed to cover the gate electrode. The corresponding oxide layer 855 can also be formed within the source trench 481 (not shown), and the oxide layer 855 can then be optionally removed. Next, the polysilicon layer 850 can be deposited within the lower portion of each source trench 481. The polysilicon layer 850 can be a continuous layer extending parallel to the length direction of the source trench 481. The source metal coating 796 can then be deposited to cover the upper portion of the device within the source trench to form the source contact.

[0098] Figures 9 to 13 are flowcharts showing a method of manufacturing a gate trench power semiconductor device according to an embodiment of the concept of the present invention.

[0099] Referring to FIGS. 9 and 4A - 4D, the operation can begin with the formation of a wide - bandgap semiconductor layer structure (block 900). The semiconductor layer structure can include a substrate and a plurality of semiconductor layers, and the plurality of semiconductor layers can grow on the substrate by epitaxial growth and / or be formed by ion implantation. The semiconductor layer structure can include a drift region having a first conductivity type. The semiconductor layer structure can further include a well region having a second conductivity type on the drift region, and a source region having the first conductivity type within an upper portion of the well region. In some embodiments, the semiconductor layer structure can include a current diffusion layer having the first conductivity type. A plurality of gate trenches are formed within the upper surface of the semiconductor layer structure (block 910). The gate trenches can extend in a first direction and be spaced from each other in a second direction perpendicular to the first direction. Each gate trench can extend a predetermined length in a third direction perpendicular to the first direction. Each gate trench can have a lower surface, a first sidewall extending in the first direction, and a second sidewall extending in the first direction. A polysilicon layer can be formed on the sidewall (e.g., the second sidewall) of the gate trench (block 920). In some embodiments, the polysilicon layer can be deposited on one or more upper surfaces of the semiconductor layer structure. The polysilicon layer and / or one or more upper surfaces of the semiconductor layer structure can be oxidized, or an oxide can be deposited, resulting in an oxide layer (block 930). Further components such as a gate insulating layer, a gate electrode, and contacts can be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 940).

[0100] Referring to FIGS. 10 and 5A - 5E, the operation can begin with the formation of a wide - bandgap semiconductor layer structure (block 1000). The semiconductor layer structure can be formed in the same manner as described above with reference to block 900 of FIG. 9, and thus, further description thereof is omitted. A plurality of gate trenches are formed in the upper surface of the semiconductor layer structure (block 1010). The gate trenches can be formed in the same manner as described above with reference to block 910 of FIG. 9, and thus, further description thereof is omitted. A polysilicon layer can be formed on a first region of the sidewall (e.g., the second sidewall) of the gate trench (block 1020). In other words, the polysilicon layer can be formed within a first region of the gate trench. The sidewall and a second region of the gate trench can be assumed to be without the polysilicon layer. The polysilicon layer can be deposited on one or more upper surfaces of the semiconductor layer structure. One or more upper surfaces of the polysilicon layer and / or the semiconductor layer structure can be oxidized, or an oxide can be deposited, resulting in an oxide layer (block 1030). The oxide layer can have a first cross - section within a first portion of the gate trench and a second different cross - section within a second portion of the gate trench. Further components such as a gate insulating layer, a gate electrode, and contacts can be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 1040). The gate electrode can have a first cross - section within a first portion of the gate trench and a second different cross - section within a second portion of the gate trench.

[0101] Referring to FIGS. 11 and 6A - 6D, the operation can begin with the formation of a wide - bandgap semiconductor layer structure (block 1100). The semiconductor layer structure can be formed in the same manner as described above with reference to block 900 of FIG. 9, and thus, further description thereof is omitted. A plurality of gate trenches are formed in the upper surface of the semiconductor layer structure (block 1110). The gate trenches can be formed in the same manner as described above with reference to block 910 of FIG. 9, and thus, further description thereof is omitted. One or more upper surfaces of the semiconductor layer structure can be oxidized or an oxide can be deposited, resulting in a lower oxide layer (block 1120). A polysilicon layer can be formed on the sidewalls (e.g., the second sidewalls) of the gate trenches (block 1130). The polysilicon layer can be deposited on one or more upper surfaces of the semiconductor layer structure. In some embodiments, the polysilicon layer can be a continuous region extending in a third direction by the length of the gate trenches. In other embodiments, the polysilicon layer can be formed within a first region of the gate trenches, and a second region of the gate trenches can be without the polysilicon layer. One or more upper surfaces of the polysilicon layer and / or the semiconductor layer structure can be oxidized, resulting in an upper oxide layer (block 1140). Further components such as gate insulating layers, gate electrodes, and contacts can be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 1150).

[0102] Referring to FIGS. 12 and 7, the operation can begin with the formation of a wide-bandgap semiconductor layer structure (block 1200). The semiconductor layer structure can be formed in the same manner as described above with reference to block 900 of FIG. 9, and thus further description thereof is omitted. A plurality of gate trenches are formed in the upper surface of the semiconductor layer structure (block 1210). The gate trenches can be formed in the same manner as described above with reference to block 910 of FIG. 9, and thus further description thereof is omitted. A polysilicon layer can be formed at the bottom (e.g., the second sidewall) of each gate trench (block 1220). In some embodiments, the polysilicon layer can be deposited. One or more upper surfaces of the polysilicon layer and / or the semiconductor layer structure can be oxidized, or an oxide can be deposited, resulting in an oxide layer (block 1230). Further components such as a gate insulating layer, a gate electrode, and contacts can be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 1240).

[0103] Referring to FIGS. 13 and 8, the operation can begin with the formation of a wide-bandgap semiconductor layer structure (block 1300). The semiconductor layer structure can include a substrate and a plurality of semiconductor layers, and the plurality of semiconductor layers can grow on the substrate by epitaxial growth and / or be formed by ion implantation. The semiconductor layer structure can include a drift region having a first conductivity type. The semiconductor layer structure can further include a well region having a second conductivity type on the drift region, and a source region having the first conductivity type in the upper portion of the well region. In some embodiments, the semiconductor layer structure can include a current diffusion layer having the first conductivity type. A plurality of gate trenches are formed in the upper surface of the semiconductor layer structure (block 1310). The gate trenches can extend in a first direction and be spaced apart from each other in a second direction perpendicular to the first direction. Each gate trench can extend a predetermined length in a third direction perpendicular to the first direction. Each gate trench can have a lower surface, a first sidewall extending in the first direction, and a second sidewall extending in the first direction. The plurality of gate trenches can include a first gate trench and a second gate trench that can alternate in the second direction. A polysilicon layer can be formed at the bottom (e.g., the second sidewall) of each first gate trench (block 1320). In some embodiments, the polysilicon layer can be deposited. One or more upper surfaces of the polysilicon layer and / or the semiconductor layer structure can be oxidized, or an oxide can be deposited, resulting in an oxide layer (block 1330). Further components such as a gate insulating layer, a gate electrode, and contacts can be formed on the upper and lower surfaces of the semiconductor layer structure to complete the device (block 1340). For example, the gate electrode can be formed in each second gate trench.

[0104] In the above description, each of the exemplary embodiments has a specific conductivity type. It will be recognized that opposite conductivity type devices can be formed in each of the above embodiments by simply inverting the conductivity of the n-type and p-type layers. Therefore, it will be recognized that the present invention covers both n-channel and p-channel devices for each different device structure (e.g., MOSFET, IGBT, etc.). Herein, when a contact can be either a source contact or a drain contact, that contact can be referred to as a "source / drain contact".

[0105] The present invention has been described above with respect to power MOSFET and IGBT implementation aspects, but it will be recognized that the techniques described herein will also be equally well applicable to other similar vertical power devices having gate trenches. Therefore, embodiments of the present invention are not limited to MOSFETs and IGBTs, and the techniques disclosed herein can be used for any suitable gate trench device.

[0106] The present invention has been mainly discussed above with respect to silicon carbide-based power semiconductor devices. However, it will be recognized that silicon carbide is used herein as an example, and that the devices discussed herein can be formed of any suitable wide bandgap semiconductor material system. By way of example, gallium nitride-based semiconductor materials (e.g., gallium nitride, aluminum gallium nitride, etc.) can be used in place of silicon carbide in any of the embodiments described above.

[0107] It will also be recognized that the different features of the different embodiments described herein can be combined to provide further embodiments. For example, it was discussed above with respect to one embodiment that a junction termination extension could be used instead of a guard ring. This is true for each embodiment disclosed herein. Similarly, the shield region under the gate trench can be included or omitted in any of the embodiments. Any of the embodiments can also include well regions having various dopant concentrations including a channel region doped at a low concentration.

[0108] Embodiments of the present invention have been described above with reference to the accompanying drawings in which embodiments of the invention are shown. However, it will be recognized that the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numerals refer to like elements throughout.

[0109] The terms, first, second, etc. are used throughout the specification to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element could be termed the second element and, similarly, the second element could be termed the first element. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0110] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used in this specification, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", and / or "including", when used in this specification, specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0111] When an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be understood that it can be directly on or extend directly onto the other element, or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, no intervening elements are present. When an element is referred to as being "connected" or "coupled" to another element, it can be understood that it can be directly connected or directly coupled to the other element, or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0112] Relative terms such as "below", "above", "upper", "lower", "top", or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0113] Embodiments of the present invention are described herein with reference to schematic illustrations, which are cross-sectional illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Further, variations from the illustrated shapes as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present invention are also described with reference to flowcharts. It will be recognized that the steps shown in the flowcharts need not be performed in the order shown.

[0114] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions having a conductivity type, such as n-type or p-type, that refers to the majority carrier concentration within the layer and / or region. Thus, an n-type material has a majority equilibrium concentration of negatively charged electrons, while a p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated as "+" or "-" (similar to the cases of n+, n-, p+, p-, n++, n--, p++, p--, or the like) to indicate a relatively high ("+") or low ("-") concentration of majority carriers compared to another layer or region. However, such notations do not imply the presence of a specific concentration of majority or minority carriers within the layer or region.

[0115] In the drawings and the specification, typical embodiments of the present invention are disclosed, and specific terms are used. However, the specific terms are used for general and illustrative purposes only, not for limitation, and the scope of the present invention is set forth in the appended claims.

Claims

1. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening; a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench; A device comprising:

2. The device of claim 1 further comprising an oxide layer on each polysilicon layer.

3. The device of claim 1 or claim 2, further comprising a gate structure in each gate trench, each gate structure comprising a gate oxide.

4. 4. The device of claim 1, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

5. 5. The device of claim 1 , further comprising a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

6. 6. A device as claimed in claim 1, wherein each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective gate trench.

7. 7. The device of claim 1, wherein each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each gate trench has a first length portion comprising the respective polysilicon layer and a second length portion free of the respective polysilicon layer.

8. 8. The device of claim 7, further comprising a channel region in the first sidewall of the gate trench and in the second sidewall of the second length of the gate trench.

9. 9. The device of claim 8, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, the channel region being within the well region.

10. 10. The device of claim 7, wherein each gate trench comprises a third length comprising a polysilicon layer on the first sidewall of each gate trench.

11. The device of claim 1 , further comprising a channel region in the first sidewall of the gate trench.

12. 12. The device of claim 11, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region.

13. 13. The device of claim 1, wherein the wide bandgap semiconductor comprises silicon carbide.

14. 14. The device of claim 1, further comprising a bottom oxide layer on the lower surface, the first sidewall, and the second sidewall of each gate trench, the polysilicon layer being on the bottom oxide layer.

15. The device of claim 14 further comprising a top oxide layer on the polysilicon layer.

16. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening; a plurality of polysilicon layers, each polysilicon layer underlying a respective one of the plurality of gate trenches; A device comprising:

17. 17. The device of claim 16, wherein the plurality of gate trenches comprises first gate trenches each having a respective polysilicon layer below the lower surface thereof, and second gate trenches free of a polysilicon layer below the lower surface of the second gate trench.

18. 18. The device of claim 16 or claim 17, further comprising a gate structure in each second gate trench.

19. 19. The device of claim 16, wherein each gate trench of the device comprises a respective polysilicon layer of the plurality of polysilicon layers.

20. 20. The device of claim 19, further comprising a gate structure in each gate trench.

21. 21. A device as claimed in claim 19 or claim 20, wherein each gate trench extends a length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective gate trench.

22. 22. The device of claim 16, wherein each gate trench extends a length in a direction parallel to an upper surface of the semiconductor layer structure, and each gate trench comprises a first length portion comprising the respective polysilicon layer and a second length portion free of the respective polysilicon layer.

23. 23. The device of claim 16, further comprising a channel region in the first sidewall of the gate trench and in the second sidewall of the second length of the gate trench.

24. 24. The device of claim 23, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, the channel region being within the well region.

25. 25. The device of claim 16, further comprising an oxide layer on each polysilicon layer.

26. 26. A device as claimed in any of claims 16 to 25, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

27. 27. The device of claim 16, further comprising a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

28. 28. The device of claim 16, further comprising a channel region in the first sidewall of each gate trench.

29. 30. The device of claim 28, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, the channel region being within the well region.

30. 30. The device of any of claims 16 to 29, wherein the wide bandgap semiconductor comprises silicon carbide.

31. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, each gate trench comprising a plurality of first length portions and a plurality of second length portions alternating along a length of the gate trench; a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench within the first length; the second length of each gate trench being free of the polysilicon layer.

32. 32. The device of claim 31 further comprising an oxide layer in each gate trench.

33. 33. The device of claim 31 or claim 32, wherein the oxide layer comprises a first cross-section within the first length of each gate trench and a second cross-section within the second length of each gate trench.

34. 34. The device of claim 32 or claim 33, further comprising a gate structure in each gate trench, the gate structure comprising a gate electrode.

35. 35. The device of claim 34, wherein the gate electrode comprises a first cross-section within the first length of each gate trench and a second cross-section within the second length of each gate trench.

36. 36. A device as claimed in any of claims 31 to 35, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

37. 37. The device of claim 31, further comprising a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

38. 38. The device of any of claims 31 to 37, wherein the wide bandgap semiconductor comprises silicon carbide.

39. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, the plurality of gate trenches comprising first and second gate trenches; a plurality of polysilicon layers, each polysilicon layer underlying a respective first gate trench of the plurality of gate trenches; a plurality of gate electrodes, each gate electrode being disposed within a respective second gate trench of the plurality of gate trenches; the second length of each gate trench being free of the polysilicon layer.

40. 40. The device of claim 39, wherein each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective first gate trench.

41. 42. A device as claimed in claim 40 or claim 41, wherein each gate trench extends a predetermined length in a direction parallel to a top surface of the semiconductor layer structure.

42. 42. The device of any of claims 39 to 41, further comprising a channel region in the first sidewall of the second gate trench.

43. 43. The device of claim 42, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, the channel region being within the well region.

44. 44. The device of any of claims 39 to 43, wherein the wide bandgap semiconductor comprises silicon carbide.

45. 1. A method of forming a semiconductor device, comprising: forming a wide bandgap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region having a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches being spaced apart from one another, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening; forming a polysilicon layer along the second sidewall of each gate trench; A method comprising:

46. 46. ​​The method of claim 45, further comprising forming an oxide layer on the polysilicon layer.

47. forming an under oxide layer on the lower surface, the first sidewall, and the second sidewall of each gate trench; forming the polysilicon layer includes forming the polysilicon layer on the under oxide layer. A method according to claim 45 or claim 46.

48. 48. The method of claim 47, further comprising forming a top oxide layer on the polysilicon layer.

49. 49. The method of any of claims 45 to 48, further comprising forming a gate structure in each gate trench, each gate structure comprising a gate electrode.

50. 50. The method of any of claims 45 to 49, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

51. 51. The method of any of claims 45 to 50, further comprising forming a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

52. 52. The method of any of claims 45 to 51, wherein each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective gate trench.

53. 53. The method of any of claims 45 to 52, wherein each gate trench extends a length in a direction parallel to an upper surface of the semiconductor layer structure, each gate trench having a first length comprising the respective polysilicon layer and a second length free of the respective polysilicon layer.

54. 54. The method of claim 53, wherein a channel region is formed in the first sidewall of the gate trench and in the second sidewall of the second length of the gate trench.

55. 55. The method of claim 54, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region.

56. 56. The method of any of claims 45 to 55, further comprising a channel region formed in the first sidewall of the gate trench.

57. 57. The method of claim 56, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, and the channel region is within the well region.

58. 58. The method of any of claims 45 to 57, wherein the wide bandgap semiconductor comprises silicon carbide.

59. 1. A method of forming a semiconductor device, comprising: forming a wide bandgap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region having a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches being spaced apart from one another, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening; forming a polysilicon layer beneath at least some of said gate trenches; A method comprising:

60. 60. The method of claim 59, wherein the plurality of gate trenches comprises first gate trenches each having a respective polysilicon layer on the lower surface thereof, and second gate trenches free of a polysilicon layer on the lower surface of the second gate trench.

61. 61. The method of claim 59 or claim 60, further comprising forming a gate structure in each second gate trench.

62. 62. The method of any of claims 59 to 61, wherein a polysilicon layer is formed within each gate trench of the semiconductor device.

63. 63. The method of claim 62, further comprising forming a gate structure in each gate trench.

64. 64. The method of any of claims 59 to 63, wherein each gate trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of the respective gate trench.

65. 65. The method of any of claims 59 to 64, wherein each gate trench extends a length in a direction parallel to an upper surface of the semiconductor layer structure, each gate trench having a first length comprising the respective polysilicon layer and a second length free of the respective polysilicon layer.

66. 66. The method of any of claims 59 to 65, further comprising forming an oxide layer on each polysilicon layer.

67. 67. The method of any of claims 59 to 66, further comprising forming a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

68. 68. The method of any of claims 59 to 67, wherein the wide bandgap semiconductor comprises silicon carbide.

69. 1. A method comprising: forming a wide bandgap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region having a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, each gate trench comprising a plurality of first length portions and a plurality of second length portions alternating along a length of the gate trench; forming a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench within the first length; the second length of each gate trench being free of the polysilicon layer.

70. 70. The method of claim 69, further comprising forming an oxide layer in each gate trench.

71. 71. The method of claim 69 or claim 70, wherein the oxide layer comprises a first cross-section within the first length of each gate trench and a second cross-section within the second length of each gate trench.

72. 72. The method of any of claims 69 to 71, further comprising forming a gate structure in each gate trench, the gate structure comprising a gate electrode.

73. 73. The method of claim 72, wherein the gate electrode comprises a first cross-section within the first length of each gate trench and a second cross-section within the second length of each gate trench.

74. 74. The method of any of claims 69 to 73, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

75. 75. The method of any of claims 69 to 74, further comprising forming a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

76. 76. The method of any of claims 69 to 75, wherein the wide bandgap semiconductor comprises silicon carbide.

77. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of source trenches in an upper portion of the semiconductor layer structure, each source trench having a lower surface, a first sidewall, a second sidewall, and a top opening; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening; a plurality of polysilicon layers, each polysilicon layer underlying a respective one of the plurality of source trenches; A device comprising:

78. 78. The device of claim 77, wherein the plurality of source trenches comprises first source trenches each having a respective polysilicon layer below the lower surface thereof, and each gate trench is free of a polysilicon layer below the lower surface of each gate trench.

79. 79. The device of claim 77 or claim 78, further comprising a gate structure in each gate trench.

80. 80. A device as claimed in any of claims 77 to 79, wherein each gate trench and each source trench extends a predetermined length in a direction parallel to an upper surface of the semiconductor layer structure, and each polysilicon layer extends the length of its respective source trench.

81. 81. The device of any of claims 77-80, further comprising a channel region in the first and second sidewalls of each gate trench.

82. 82. The device of claim 81, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type, the channel region being within the well region.

83. 83. The device of any of claims 77 to 82, further comprising a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

84. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and a top opening, each gate trench comprising a plurality of first lengths, a plurality of second lengths, and a plurality of third lengths; a plurality of first polysilicon layers, each first polysilicon layer on the first sidewall of a respective gate trench within the first length; a plurality of second polysilicon layers, each second polysilicon layer on the second sidewall of a respective gate trench within the second length; the first and second sidewalls of each gate trench within the third length are free of the first and second polysilicon layers.

85. 85. The device of claim 84, further comprising an oxide layer in each gate trench.

86. 86. The device of claim 84 or claim 85, wherein the oxide layer comprises a first cross-section within the first length of each gate trench, a second cross-section within the second length of each gate trench, and a third cross-section within the third length of each gate trench.

87. 87. The device of any of claims 84 to 86, further comprising a gate structure in each gate trench, the gate structure comprising a gate electrode.

88. 88. The device of claim 87, wherein the gate electrode comprises a first cross-section within the first length of each gate trench, a second cross-section within the second length of each gate trench, and a third cross-section within the third length of each gate trench.

89. 89. The device of any of claims 84 to 88, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

90. 90. The method of any of claims 84 to 89, further comprising a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

91. 91. The device of any of claims 84 to 90, wherein the wide bandgap semiconductor comprises silicon carbide.

92. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, each gate trench comprising a plurality of first lengths and a plurality of second lengths; a plurality of first polysilicon layers, each first polysilicon layer on the first and second sidewalls of a respective gate trench within the first length; the first and second sidewalls of each gate trench within the second length are free of the polysilicon layer.

93. 93. The device of claim 92, further comprising an oxide layer in each gate trench.

94. 94. The device of claim 93, wherein the oxide layer comprises a first cross-section within the first length of each gate trench and a second cross-section within the second length of each gate trench.

95. 95. The device of any of claims 92 to 94, further comprising a gate structure in each gate trench, the gate structure comprising a gate electrode.

96. 96. The device of claim 95, wherein the gate electrode comprises a first cross-section within the first length of each gate trench and a second cross-section within the second length of each gate trench.

97. 97. The device of any of claims 92 to 96, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

98. 98. The device of any of claims 92 to 97, further comprising a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

99. 99. The device of any of claims 92 to 98, wherein the wide bandgap semiconductor comprises silicon carbide.

100. A device, comprising: a wide bandgap semiconductor layer structure including a drift region having a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a lower surface, a first sidewall, a second sidewall, and an upper opening, each gate trench exposing a side of the drift region; a plurality of polysilicon layers, each polysilicon layer on at least a portion of each of the first and second sidewalls of a respective gate trench; A device comprising:

101. 101. The device of claim 100, further comprising an oxide layer in each gate trench.

102. 102. The device of claim 100 or claim 101, further comprising a gate structure in each gate trench, the gate structure comprising a gate electrode.

103. 103. A device according to any of claims 100 to 102, wherein the semiconductor layer structure comprises a well region having a second conductivity type different from the first conductivity type.

104. 104. The device of any of claims 100 to 103, further comprising a first source / drain contact on a first major surface of the semiconductor layer structure and a second source / drain contact on a second major surface of the semiconductor layer structure opposite the first major surface.

105. 105. The device of any of claims 100 to 104, wherein the wide bandgap semiconductor comprises silicon carbide.

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