SiC SEMICONDUCTOR DEVICE

Abstract

To provide an SiC semiconductor device capable of suppressing wet spreading of a conductive joining material in an SiC semiconductor layer including a side surface having a rough surface region.SOLUTION: An SiC semiconductor device 1 includes: an SiC semiconductor layer 2 (SiC chip) having a stacked structure including an SiC semiconductor substrate 6 (SiC substrate) and an SiC epitaxial layer 7, and including a first main surface 3 at the SiC epitaxial layer 7 side, a second main surface 4 of the SiC semiconductor substrate 6, and side surfaces 5A to 5D; first rough surface regions 20A to 20D formed in a portion composed of the SiC semiconductor substrate 6 among the side surfaces 5A to 5D; second rough surface regions 20A to 20D formed in a portion composed of the SiC epitaxial layer 7 among the side surfaces 5A to 5D; and smooth surface regions 21A to 21D formed in a portion composed of the SiC semiconductor substrate 6 among the side surfaces 5A to 5D.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a SiC semiconductor device.

Background Art

[0002] In recent years, a method for processing a SiC semiconductor wafer called the stealth dicing method has attracted attention. In the stealth dicing method, after a SiC semiconductor wafer is selectively irradiated with a laser beam, the SiC semiconductor wafer is cut along the portion irradiated with the laser beam. According to this method, a SiC semiconductor wafer having a relatively high hardness can be cut without using a cutting member such as a dicing blade, so that the manufacturing time can be shortened.

[0003] Patent Document 1 discloses a method for manufacturing a SiC semiconductor device using the stealth dicing method. In the manufacturing method of Patent Document 1, a rough surface region composed of a plurality of rows of laser irradiation marks formed by laser irradiation is formed over the entire area of each side surface of the SiC semiconductor layer cut out from the SiC semiconductor wafer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] A SiC semiconductor device is mounted on an object to be connected via a conductive bonding material such as solder. Examples of the object to be connected include a lead frame, a circuit board, and an electronic component. In a SiC semiconductor layer having a rough surface region on the side surface, the conductive bonding material wets and spreads on the side surface of the SiC semiconductor layer due to capillary action occurring in the rough surface region.

[0006] In a structure in which a rough surface region is formed over the entire side surface of the SiC semiconductor layer, there is a risk that most of the SiC semiconductor layer may be covered by the conductive bonding material. In this case, there is a risk of short circuit occurring in the SiC semiconductor layer and / or between the SiC semiconductor layer and the object to be connected.

[0007] One embodiment provides a SiC semiconductor device capable of suppressing the wetting spread of a conductive bonding material in a SiC semiconductor layer including a side surface having a rough surface region.

Means for Solving the Problems

[0008] One embodiment provides a SiC semiconductor device including a SiC semiconductor layer containing a SiC single crystal, having a mounting surface, a non-mounting surface opposite to the mounting surface, and a side surface connecting the mounting surface and the non-mounting surface and including a rough surface region and a smooth surface region formed in a region different from the rough surface region.

[0009] According to this SiC semiconductor device, the capillary phenomenon occurring in the rough surface region can be suppressed by the smooth surface region. Therefore, the wetting spread of the conductive bonding material on the side surface of the SiC semiconductor layer can be suppressed.

[0010] One embodiment provides a SiC semiconductor device having a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer, the SiC semiconductor layer having an element formation surface composed of the SiC epitaxial layer, a first rough surface region formed in a portion composed of the SiC semiconductor substrate on the side surface of the SiC semiconductor layer, and a smooth surface region formed in a portion composed of the SiC semiconductor substrate on the side surface of the SiC semiconductor layer. The rough surface region may further include a second rough surface region formed in a portion of the side surface composed of the SiC epitaxial layer.

[0011] According to this SiC semiconductor device, the capillary phenomenon occurring in the rough surface region can be suppressed by the smooth surface region. Therefore, the wetting spread of the conductive bonding material on the side surface of the SiC semiconductor layer can be suppressed.

Brief Description of the Drawings

[0012]

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Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0014] In the embodiments of the present invention, a hexagonal SiC (silicon carbide) single crystal is applied. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal according to the period of the atomic arrangement. In the embodiments of the present invention, an example in which a 4H-SiC single crystal is applied will be described, but other polytypes are not excluded from the present invention.

[0015] Hereinafter, the crystal structure of the 4H-SiC single crystal will be described. FIG. 1 is a diagram showing a unit cell (hereinafter simply referred to as "unit cell") of the 4H-SiC single crystal applied to the embodiment of the present invention. FIG. 2 is a plan view showing the silicon plane of the unit cell shown in FIG. 1.

[0016] Referring to FIGS. 1 and 2, the unit cell includes a tetrahedral structure in which four C atoms are bonded to one Si atom in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which the tetrahedral structure is stacked four times. The unit cell has a hexagonal prism structure having a regular hexagonal silicon plane, a regular hexagonal carbon plane, and six side faces connecting the silicon plane and the carbon plane.

[0017] The silicon plane is a termination plane terminated by Si atoms. In the silicon plane, one Si atom is located at each of the six vertices of the regular hexagon, and one Si atom is located at the center of the regular hexagon.

[0018] The carbon plane is a termination plane terminated by C atoms. In the carbon plane, one C atom is located at each of the six vertices of a regular hexagon, and one C atom is located at the center of the regular hexagon.

[0019] The crystal planes of the unit cell are defined by four coordinate axes (a1, a2, a3, c) including the a1 axis, a2 axis, a3 axis and c axis. The value of a3 among the four coordinate axes takes the value of -(a1 + a2). Hereinafter, the crystal planes of the 4H-SiC single crystal will be described with reference to the silicon plane as an example of the termination plane of the hexagonal crystal.

[0020] The a1 axis, a2 axis and a3 axis are respectively set along the arrangement direction of the nearest Si atoms (hereinafter simply referred to as the "nearest neighbor atom direction") with respect to the Si atom located at the center in the plan view of the silicon plane seen from the c axis. The a1 axis, a2 axis and a3 axis are respectively set with an angle shift of 120° each following the arrangement of the Si atoms.

[0021] The c axis is set in the normal direction of the silicon plane with respect to the Si atom located at the center. The silicon plane is the (0001) plane. The carbon plane is the (000-1) plane.

[0022] The side faces of the hexagonal prism include six crystal planes along the nearest neighbor atom direction in the plan view of the silicon plane seen from the c axis. More specifically, the side faces of the hexagonal prism include six crystal planes each containing two nearest Si atoms in the plan view of the silicon plane seen from the c axis.

[0023] The side faces of the hexagonal prism include the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane and (10-10) plane in a clockwise direction from the tip of the a1 axis in the plan view of the silicon plane seen from the c axis.

[0024] The diagonal plane along the diagonal of the hexagonal prism includes six crystal planes along the intersection direction that intersects the nearest neighbor atom direction in a plan view of the silicon plane looking from the c-axis. More specifically, the diagonal plane of the hexagonal prism includes six crystal planes each containing two non-nearest neighbor Si atoms in a plan view of the silicon plane looking from the c-axis. When viewed with respect to the Si atom located at the center, the intersection direction in the nearest neighbor atom direction becomes the orthogonal direction orthogonal to the nearest neighbor atom direction.

[0025] The diagonal plane of the hexagonal prism includes the (11-20) plane, (1-210) plane, (-2110) plane, (-1-120) plane, (-12-10) plane, and (2-1-10) plane in a plan view of the silicon plane looking from the c-axis.

[0026] The crystal direction of the unit cell is defined by the normal direction of the crystal plane. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

[0027] The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

[0028] The hexagonal crystal has six-fold symmetry, and there are equivalent crystal planes and equivalent crystal directions every 60°. For example, the (1-100) plane, (0-110) plane, (-1010) plane, (-1100) plane, (01-10) plane, and (10-10) plane form equivalent crystal planes.

[0029] In addition, the [1-100] direction, [0-110] direction, [-1010] direction, [-1100] direction, [01-10] direction, and [10-10] direction form equivalent crystal directions. Also, the [11-20] direction, [1-210] direction, [-2110] direction, [-1-120] direction, [-12-10] direction, and [2-1-10] direction form equivalent crystal directions.

[0030] The c-axis is the

[0001] direction ([000-1] direction). The a1-axis is the [2-1-10] direction ([-2110] direction). The a2-axis is the [-12-10] direction ([1-210] direction). The a3-axis is the [-1-120] direction ([11-20] direction).

[0031] (0001) plane and (000-1) plane are collectively referred to as the c-plane. The

[0001] direction and [000-1] direction are collectively referred to as the c-axis direction. (11-20) plane and (-1-120) plane are collectively referred to as the a-plane. [11-20] direction and [-1-120] direction are collectively referred to as the a-axis direction. (1-100) plane and (-1100) plane are collectively referred to as the m-plane. [1-100] direction and [-1100] direction are collectively referred to as the m-axis direction.

[0032] FIG. 3 is a perspective view of the SiC semiconductor device 1 according to the first embodiment of the present invention viewed from one angle, and is a perspective view showing a first form example of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. FIG. 4 is a perspective view of the SiC semiconductor device 1 shown in FIG. 3 viewed from another angle.

[0033] FIG. 5 is an enlarged view of the region V shown in FIG. 3. FIG. 6 is an enlarged view of the region VI shown in FIG. 3. FIG. 7 is a plan view of the SiC semiconductor device 1 shown in FIG. 3. FIG. 8 is a cross-sectional view taken along the line VIII-VIII shown in FIG. 7.

[0034] Referring to FIGS. 3 to 8, the SiC semiconductor device 1 includes a SiC semiconductor layer 2. The SiC semiconductor layer 2 includes a 4H-SiC single crystal as an example of a SiC single crystal composed of a hexagonal crystal. The SiC semiconductor layer 2 is formed in a rectangular parallelepiped chip shape.

[0035] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (a square shape in this form) in a plan view (hereinafter simply referred to as "plan view") as viewed from the normal direction Z thereof.

[0036] The first main surface 3 is an element formation surface on which a semiconductor element is formed. The second main surface 4 of the SiC semiconductor layer 2 is a ground surface having grinding marks. The side surfaces 5A to 5D are cleavage surfaces each facing a crystal plane of a SiC single crystal. The side surfaces 5A to 5D do not have grinding marks.

[0037] In this form, the first main surface 3 of the SiC semiconductor layer 2 is formed as a non-mounting surface. In this form, the second main surface 4 of the SiC semiconductor layer 2 is formed as a mounting surface. When the SiC semiconductor layer 2 is mounted on an object to be connected, the SiC semiconductor layer 2 is mounted on the object to be connected with the second main surface 4 facing it. Examples of the object to be connected include electronic components, lead frames, circuit boards, etc.

[0038] The thickness TL of the SiC semiconductor layer 2 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

[0039] In this form, the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the (0001) plane (silicon plane). The second main surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0040] The first major surface 3 and the second major surface 4 have an off-angle θ that is inclined at an angle of 10° or less with respect to the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0041] The off-angle θ may be 0° or more and 5.0° or less. The off-angle θ may be set in the range of an angle of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. It is preferable that the off-angle θ exceeds 0°. The off-angle θ may be less than 4.0°.

[0042] The off-angle θ may be set in the range of an angle of 3.0° or more and 4.5° or less. In this case, it is preferable that the off-angle θ is set in the range of an angle of 3.0° or more and 3.5° or less or 3.5° or more and 4.0° or less.

[0043] The off-angle θ may be set in the range of an angle of 1.5° or more and 3.0° or less. In this case, it is preferable that the off-angle θ is set in the range of an angle of 1.5° or more and 2.0° or less or 2.0° or more and 2.5° or less.

[0044] The lengths of the side surfaces 5A to 5D may each be 0.5 mm or more and 10 mm or less. The surface areas of the side surfaces 5A to 5D are equal to each other in this form. When the first major surface 3 and the second major surface 4 are formed in a rectangular shape in plan view, the surface areas of the side surfaces 5A and 5C may be less than the surface areas of the side surfaces 5B and 5D, or may exceed the surface areas of the side surfaces 5B and 5D.

[0045] The side surfaces 5A and 5C extend along the first direction X and face each other in the second direction Y that intersects the first direction X in this form. The side surfaces 5B and 5D extend along the second direction Y and face each other in the first direction X in this form. More specifically, the second direction Y is a direction orthogonal to the first direction X.

[0046] In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0047] The side surfaces 5A and 5C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. The side surface 5A is formed by the (-1-120) plane of the SiC single crystal. The side surface 5C is formed by the (11-20) plane of the SiC single crystal.

[0048] The side surfaces 5B and 5D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. The side surface 5B is formed by the (-1100) plane of the SiC single crystal. The side surface 5D is formed by the (1-100) plane of the SiC single crystal.

[0049] The side surfaces 5A and 5C may form inclined surfaces that are inclined in the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal of the first main surface 3 of the SiC semiconductor layer 2.

[0050] In this case, when the normal of the first main surface 3 of the SiC semiconductor layer 2 is set to 0°, the side surfaces 5A and 5C may be inclined at an angle corresponding to the off-angle θ with respect to the normal of the first main surface 3 of the SiC semiconductor layer 2. The angle corresponding to the off-angle θ may be equal to the off-angle θ or may be an angle greater than 0° and less than the off-angle θ.

[0051] On the other hand, the side surfaces 5B and 5D extend planar along the normal of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the side surfaces 5B and 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0052] SiC semiconductor layer 2 has a laminated structure including an n + -type SiC semiconductor substrate 6 and an n-type SiC epitaxial layer 7 in this embodiment. The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 6.

[0053] The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 7. The side surfaces 5A to 5D of the SiC semiconductor layer 2 are formed by the SiC semiconductor substrate 6 and the SiC epitaxial layer 7.

[0054] The n-type impurity concentration of the SiC epitaxial layer 7 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 6. More specifically, the n-type impurity concentration of the SiC epitaxial layer 7 is less than the n-type impurity concentration of the SiC semiconductor substrate 6. The n-type impurity concentration of the SiC semiconductor substrate 6 is 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the SiC epitaxial layer 7 may be 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less.

[0055] The thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 6, it is possible to reduce the resistance value due to shortening of the current path.

[0056] The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

[0057] An active region 8 and an outer region 9 are set in the SiC semiconductor layer 2. The active region 8 is a region where a Schottky barrier diode D as an example of a semiconductor element is formed. The outer region 9 is a region outside the active region 8.

[0058] The active region 8 is set in the central portion of the SiC semiconductor layer 2 at a distance from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in the inward region in a plan view. The active region 8 is set in a rectangular shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0059] The outer region 9 is set in the region between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the periphery of the active region 8. The outer region 9 is set in an endless shape (in this form, a square ring shape) surrounding the active region 8 in a plan view.

[0060] A main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 selectively covers the active region 8 and the outer region 9. The main surface insulating layer 10 may have a single-layer structure made of a silicon oxide (SiO2) layer or a silicon nitride (SiN) layer.

[0061] The main surface insulating layer 10 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this form, the main surface insulating layer 10 has a single-layer structure made of a silicon oxide layer.

[0062] The main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D that are exposed from the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are continuous with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are cleavage surfaces.

[0063] The thickness of the main surface insulating layer 10 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 10 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0064] A first main surface electrode layer 12 is formed on the main surface insulating layer 10. The first main surface electrode layer 12 is formed at the center of the SiC semiconductor layer 2 with a space from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in the inner region in a plan view.

[0065] A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10. The passivation layer 13 may have a single-layer structure made of a silicon oxide layer or a silicon nitride layer.

[0066] The passivation layer 13 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this form, the passivation layer 13 has a single-layer structure made of a silicon nitride layer.

[0067] The side surfaces 14A, 14B, 14C, and 14D of the passivation layer 13 are formed at intervals from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in an inner region in a plan view. The passivation layer 13 exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 in a plan view. The passivation layer 13 exposes the main surface insulating layer 10.

[0068] A sub-pad opening 15 for exposing a part of the first main surface electrode layer 12 as a pad region is formed in the passivation layer 13. The sub-pad opening 15 is formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0069] The thickness of the passivation layer 13 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 13 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0070] A resin layer 16 (insulating layer) is formed on the passivation layer 13. The passivation layer 13 and the resin layer 16 form one insulating laminated structure (insulating layer). In FIG. 7, the resin layer 16 is shown by hatching.

[0071] The resin layer 16 may contain a negative-type or positive-type photosensitive resin. In this form, the resin layer 16 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 16 may contain polyimide as an example of a negative-type photosensitive resin.

[0072] The resin side surfaces 17A, 17B, 17C, and 17D of the resin layer 16 are formed at intervals from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in an inner region in a plan view. The resin layer 16 exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 in a plan view. The resin layer 16 exposes the main surface insulating layer 10 together with the passivation layer 13. In this form, the resin side surfaces 17A to 17D of the resin layer 16 are formed flush with the side surfaces 14A to 14D of the passivation layer 13.

[0073] The resin side surfaces 17A to 17D of the resin layer 16 are the portions that partitioned the dicing street when cutting out the SiC semiconductor device 1 from a single SiC semiconductor wafer. In this form, the side surfaces 14A to 14D of the passivation layer 13 are also the portions that partitioned the dicing street.

[0074] By exposing the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 from the resin layer 16 and the passivation layer 13, it becomes unnecessary to physically cut the resin layer 16 and the passivation layer 13. As a result, the SiC semiconductor device 1 can be smoothly cut out from a single SiC semiconductor wafer. Also, the insulation distance from the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be increased.

[0075] The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Of course, the side surfaces 14A to 14D of the passivation layer 13 may be formed flush with the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0076] A pad opening 18 for exposing a part of the first main surface electrode layer 12 as a pad region is formed in the resin layer 16. The pad opening 18 is formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0077] The pad opening 18 communicates with the sub-pad opening 15. The inner wall of the pad opening 18 is flush with the inner wall of the sub-pad opening 15. The inner wall of the pad opening 18 may be located on the side surfaces 5A to 5D side of the SiC semiconductor layer 2 with respect to the inner wall of the sub-pad opening 15. The inner wall of the pad opening 18 may be located in the inner region of the SiC semiconductor layer 2 with respect to the inner wall of the sub-pad opening 15. The resin layer 16 may cover the inner wall of the sub-pad opening 15.

[0078] The thickness of the resin layer 16 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 16 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0079] A second main surface electrode layer 19 is formed on the second main surface 4 of the SiC semiconductor layer 2. The second main surface electrode layer 19 forms an ohmic contact with the second main surface 4 (SiC semiconductor substrate 6) of the SiC semiconductor layer 2.

[0080] Rough surface regions 20A to 20D and smooth surface regions 21A to 21D are respectively formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2. The rough surface regions 20A to 20D are regions where a part of the side surfaces 5A to 5D is roughened by introducing a predetermined surface roughness Rr. The smooth surface regions 21A to 21D are regions having a surface roughness Rs (Rs < Rr) less than the surface roughness Rr of the rough surface regions 20A to 20D on the side surfaces 5A to 5D.

[0081] The rough surface regions 20A to 20D include the rough surface region 20A formed on the side surface 5A, the rough surface region 20B formed on the side surface 5B, the rough surface region 20C formed on the side surface 5C, and the rough surface region 20D formed on the side surface 5D. The smooth surface regions 21A to 21D include the smooth surface region 21A formed on the side surface 5A, the smooth surface region 21B formed on the side surface 5B, the smooth surface region 21C formed on the side surface 5C, and the smooth surface region 21D formed on the side surface 5D.

[0082] The rough surface regions 20A to 20D are formed in regions on the second main surface 4 side of the SiC semiconductor layer 2 on the side surfaces 5A to 5D. In this form, the rough surface regions 20A to 20D are formed from the corner portions on the second main surface 4 side to the middle portion in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D.

[0083] The rough surface regions 20A to 20D are formed at intervals from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. The rough surface regions 20A to 20D expose the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D. The rough surface regions 20A to 20D are not formed in the main surface insulating layer 10, the passivation layer 13, and the resin layer 16.

[0084] More specifically, the rough surface regions 20A to 20D are formed in the middle portion in the thickness direction of the SiC semiconductor substrate 6. More specifically, the rough surface regions 20A to 20D are formed at intervals from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4. Thereby, the rough surface regions 20A to 20D expose a part of the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2.

[0085] The rough surface regions 20A to 20D extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. The tangential direction of the first main surface 3 is a direction orthogonal to the normal direction Z. The tangential direction includes the first direction X (m-axis direction of the SiC single crystal) and the second direction Y (a-axis direction of the SiC single crystal).

[0086] The rough surface region 20A is formed in a strip shape that extends linearly along the m-axis direction on the side surface 5A. The rough surface region 20B is formed in a strip shape that extends linearly along the a-axis direction on the side surface 5B. The rough surface region 20C is formed in a strip shape that extends linearly along the m-axis direction on the side surface 5C. The rough surface region 20D is formed in a strip shape that extends linearly along the a-axis direction on the side surface 5D.

[0087] The rough surface regions 20A and 20B are connected to each other at the corner connecting the side surfaces 5A and 5B in the SiC semiconductor layer 2. The rough surface regions 20B and 20C are connected to each other at the corner connecting the side surfaces 5B and 5C in the SiC semiconductor layer 2.

[0088] The rough surface regions 20C and 20D are connected to each other at the corner connecting the side surfaces 5C and 5D in the SiC semiconductor layer 2. The rough surface regions 20D and 20A are connected to each other at the corner connecting the side surfaces 5D and 5A in the SiC semiconductor layer 2.

[0089] As a result, the rough surface regions 20A to 20D are integrally formed so as to surround the SiC semiconductor layer 2. The rough surface regions 20A to 20D form a single endless (annular) rough surface region surrounding the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0090] Regarding the normal direction Z, the thickness TR of the rough surface regions 20A to 20D is less than the thickness TL of the SiC semiconductor layer 2 (TR < TL). Preferably, the thickness TR of the rough surface regions 20A to 20D is less than the thickness TS of the SiC semiconductor substrate 6 (TR < TS).

[0091] The thickness TR of the rough surface regions 20A to 20D may be equal to or greater than the thickness TE of the SiC epitaxial layer 7 (TR ≧ TE). The thicknesses of the thickness TR of the rough surface region 20A, the thickness TR of the rough surface region 20B, the thickness TR of the rough surface region 20C, and the thickness TR of the rough surface region 20D may be equal to each other or different from each other.

[0092] Preferably, the ratio TR / TL of the thickness TR of the rough surface regions 20A to 20D to the thickness TL of the SiC semiconductor layer 2 is 0.1 or more and less than 1.0. The ratio TR / TL may be 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0.

[0093] The ratio TR / TL may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR / TL is preferably 0.2 or more and 0.5 or less.

[0094] More preferably, the ratio TR / TS of the thickness TR of the rough surface regions 20A to 20D to the thickness TS of the SiC semiconductor substrate 6 is 0.1 or more and less than 1.0. The ratio TR / TS may be 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0.

[0095] The ratio TR / TS may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR / TS is preferably 0.2 or more and 0.5 or less.

[0096] In this form, the rough surface regions 20A to 20D each include modified lines 22A to 22D (modified layers). The modified lines 22A to 22D include a layered region in which a part of the SiC single crystal forming the side surfaces 5A to 5D is modified to have properties different from those of the SiC single crystal. That is, the rough surface regions 20A to 20D are regions roughened by the modified lines 22A to 22D.

[0097] The modified lines 22A to 22D include a region in which the density, refractive index, or mechanical strength (crystal strength), or other physical properties are modified to have properties different from those of the SiC single crystal. The modified lines 22A to 22D may include at least one of a molten recrystallized layer, a defect layer, an insulating breakdown layer, or a refractive index change layer.

[0098] The melt re-hardened layer is a layer formed by re-hardening after a part of the SiC semiconductor layer 2 has melted. The defect layer is a layer containing voids, cracks, etc. formed in the SiC semiconductor layer 2. The dielectric breakdown layer is a layer in which a part of the SiC semiconductor layer 2 has undergone dielectric breakdown. The refractive index change layer is a layer in which a part of the SiC semiconductor layer 2 has changed to a refractive index different from that of the SiC single crystal.

[0099] The rough surface region 20A includes one or more (two or more layers. In this form, two layers) of modified lines 22A. The plurality of modified lines 22A, in this form, extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the plurality of modified lines 22A are each formed in a strip shape extending linearly along the m-axis direction on the side surface 5A.

[0100] The plurality of modified lines 22A are formed offset from each other in the normal direction Z. The plurality of modified lines 22A may be formed at intervals in the normal direction Z. The plurality of modified lines 22A may overlap each other in the normal direction Z. The thickness TR of the rough surface region 20A is determined by the total value of the thicknesses of the plurality of modified lines 22A. The thicknesses of the plurality of modified lines 22A may be equal to each other or different from each other.

[0101] The rough surface region 20B includes one or more (two or more layers. In this form, two layers) of modified lines 22B. The plurality of modified lines 22B, in this form, extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the plurality of modified lines 22B are each formed in a strip shape extending linearly along the a-axis direction on the side surface 5B.

[0102] The plurality of modified lines 22B are formed offset from each other in the normal direction Z. The plurality of modified lines 22B may be formed at intervals in the normal direction Z. The plurality of modified lines 22B may overlap each other in the normal direction Z. The thickness TR of the rough surface region 20B is determined by the total value of the thicknesses of the plurality of modified lines 22B. The thicknesses of the plurality of modified lines 22B may be equal to each other or different from each other.

[0103] The rough surface region 20C includes one or a plurality of (two or more layers. In this form, two layers) modified lines 22C. In this form, the plurality of modified lines 22C extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the plurality of modified lines 22C are each formed in a strip shape extending linearly along the m-axis direction on the side surface 5C.

[0104] The plurality of modified lines 22C are formed so as to be offset from each other in the normal direction Z. The plurality of modified lines 22C may be formed at intervals in the normal direction Z. The plurality of modified lines 22C may overlap each other in the normal direction Z. The thickness TR of the rough surface region 20C is determined by the total value of the thicknesses of the plurality of modified lines 22C. The thicknesses of the plurality of modified lines 22C may be equal to each other or different from each other.

[0105] The rough surface region 20D includes one or a plurality of (two or more layers. In this form, two layers) modified lines 22D. In this form, the plurality of modified lines 22D extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. More specifically, the plurality of modified lines 22D are each formed in a strip shape extending linearly along the a-axis direction on the side surface 5D.

[0106] The plurality of modified lines 22D are formed so as to be offset from each other in the normal direction Z. The plurality of modified lines 22D may be formed at intervals in the normal direction Z. The plurality of modified lines 22D may overlap each other in the normal direction Z. The thickness TR of the rough surface region 20D is determined by the total value of the thicknesses of the plurality of modified lines 22D. The thicknesses of the plurality of modified lines 22D may be equal to each other or different from each other.

[0107] The modified line 22A and the modified line 22B are connected to each other at the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. The modified line 22B and the modified line 22C are connected to each other at the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

[0108] The modified line 22C and the modified line 22D are connected to each other at the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. The modified line 22D and the modified line 22A are connected to each other at the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.

[0109] As a result, the modified lines 22A to 22D are integrally formed so as to surround the SiC semiconductor layer 2. The modified lines 22A to 22D form one endless (annular) modified line surrounding the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0110] Referring to FIG. 5, the modified line 22A includes a plurality of a-plane modified portions 28 (modified portions). In other words, the modified line 22A is formed by an aggregate of a plurality of a-plane modified portions 28. The plurality of a-plane modified portions 28 are portions where the SiC single crystal exposed from the side surface 5A is modified to have properties different from those of the SiC single crystal. The region around each a-plane modified portion 28 on the side surface 5A may be modified to have properties different from those of the SiC single crystal.

[0111] The plurality of a-plane modified portions 28 each include one end portion 28a located on the first main surface 3 side, the other end portion 28b located on the second main surface 4 side, and a connecting portion 28c connecting the one end portion 28a and the other end portion 28b.

[0112] The plurality of a-plane modified portions 28 are each linearly formed extending in the normal direction Z. As a result, the plurality of a-plane modified portions 28 are formed in a striped shape as a whole. The plurality of a-plane modified portions 28 may include a plurality of a-plane modified portions 28 formed in a tapered shape in which the width in the m-axis direction narrows from the one end portion 28a side toward the other end portion 28b side.

[0113] The plurality of a-plane modification portions 28 are formed at intervals in the m-axis direction so as to face each other in the m-axis direction. The plurality of a-plane modification portions 28 may overlap each other in the m-axis direction. One strip-shaped region extending in the m-axis direction is formed by a line connecting one end portions 28a of the plurality of a-plane modification portions 28 and a line connecting the other end portions 28b of the plurality of a-plane modification portions 28. The modification line 22A is formed by this strip-shaped region.

[0114] The plurality of a-plane modification portions 28 may each form a notch that cuts out the side surface 5A. The plurality of a-plane modification portions 28 may each form a recess that is recessed from the side surface 5A in the a-axis direction. The plurality of a-plane modification portions 28 may be formed in a dot shape according to the length in the normal direction Z and the width in the m-axis direction.

[0115] In the m-axis direction, the pitch PR between the central portions of the plurality of adjacent a-plane modification portions 28 may be greater than 0 μm and less than or equal to 20 μm. The pitch PR may be greater than 0 μm and less than or equal to 5 μm, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0116] In the m-axis direction, the width WR of each a-plane modification portion 28 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0117] Thus, the rough surface region 20A extends along the normal direction Z and is roughened by the modification line 22A including the plurality of a-plane modification portions 28 facing each other in the m-axis direction. The rough surface region 20A has a surface roughness Rr corresponding to the pitch PR and the width WR of the plurality of a-plane modification portions 28.

[0118] The rough surface region 20C (modified line 22C) has the same structure as the rough surface region 20A (modified line 22A), except that it is formed on the side surface 5C. The description of the rough surface region 20A (modified line 22A) shall apply mutatis mutandis to the description of the rough surface region 20C (modified line 22C) by reading "side surface 5A" as "side surface 5C".

[0119] Referring to FIG. 6, the modified line 22D includes a plurality of m-plane modified portions 29 (modified portions). In other words, the modified line 22D is formed by an aggregate of a plurality of m-plane modified portions 29. The plurality of m-plane modified portions 29 are portions where the SiC single crystal exposed from the side surface 5D is modified to have properties different from those of the SiC single crystal. The region around each m-plane modified portion 29 on the side surface 5D may be modified to have properties different from those of the SiC single crystal.

[0120] The plurality of m-plane modified portions 29 each include one end portion 29a located on the first main surface 3 side, the other end portion 29b located on the second main surface 4 side, and a connecting portion 29c connecting the one end portion 29a and the other end portion 29b.

[0121] The plurality of m-plane modified portions 29 are each linearly formed extending in the normal direction Z. As a result, the plurality of m-plane modified portions 29 are formed in a striped shape as a whole. The plurality of m-plane modified portions 29 may include a plurality of m-plane modified portions 29 formed in a tapered shape in which the width in the a-axis direction narrows from the one end portion 29a side toward the other end portion 29b side.

[0122] The plurality of m-plane modified portions 29 are formed at intervals in the a-axis direction so as to face each other in the a-axis direction. The plurality of m-plane modified portions 29 may overlap each other in the a-axis direction. One strip-shaped region extending in the a-axis direction is formed by a line connecting the one end portions 29a of the plurality of m-plane modified portions 29 and a line connecting the other end portions 29b of the plurality of m-plane modified portions 29. The modified line 22D is formed by this strip-shaped region.

[0123] The plurality of m-plane modified portions 29 may each form a notch that cuts out the side surface 5D. The plurality of m-plane modified portions 29 may each form a recess that is recessed from the side surface 5D in the m-axis direction. The plurality of m-plane modified portions 29 may be formed in a dot shape according to the length in the normal direction Z and the width in the a-axis direction.

[0124] In the a-axis direction, the pitch PR between the central portions of the plurality of adjacent m-plane modified portions 29 may be 0 μm or more and 20 μm or less. The pitch PR may be 0 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0125] In the a-axis direction, the width WR of each m-plane modified portion 29 may exceed 0 μm and be 20 μm or less. The width WR may exceed 0 μm and be 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0126] In this way, the rough surface region 20D extends along the normal direction Z and is roughened by the modified line 22D including the plurality of m-plane modified portions 29 facing each other along the a-axis direction. The rough surface region 20D has a surface roughness Rr according to the pitch PR and the width WR of the plurality of m-plane modified portions 29.

[0127] The rough surface region 20B (modified line 22B) has the same structure as the rough surface region 20D (modified line 22D), except for being formed on the side surface 5B. The description of the rough surface region 20D (modified line 22D) is applied mutatis mutandis to the description of the rough surface region 20B (modified line 22B) by reading "side surface 5D" as "side surface 5B".

[0128] Referring again to FIGS. 3 and 4, the smooth surface regions 21A to 21D are formed in regions different from the rough surface regions 20A to 20D on the side surfaces 5A to 5D of the SiC semiconductor layer 2. The smooth surface regions 21A to 21D are formed in regions other than the rough surface regions 20A to 20D on the side surfaces 5A to 5D.

[0129] The smooth surface regions 21A to 21D are formed in the regions on the first main surface 3 side of the SiC semiconductor layer 2 on the side surfaces 5A to 5D. The smooth surface regions 21A to 21D are formed from the first main surface 3 of the SiC semiconductor layer 2 to the middle portion in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D. More specifically, the smooth surface regions 21A to 21D are formed in the SiC epitaxial layer 7. The smooth surface regions 21A to 21D expose the SiC epitaxial layer 7.

[0130] More specifically, the smooth surface regions 21A to 21D are formed in both the SiC epitaxial layer 7 and the SiC semiconductor substrate 6 across the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7. The smooth surface regions 21A to 21D expose both the SiC epitaxial layer 7 and the SiC semiconductor substrate 6.

[0131] The smooth surface regions 21A to 21D extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. The smooth surface region 21A is formed in a strip shape that extends linearly along the m-axis direction on the side surface 5A. The smooth surface region 21B is formed in a strip shape that extends linearly along the a-axis direction on the side surface 5B. The smooth surface region 21C is formed in a strip shape that extends linearly along the m-axis direction on the side surface 5C. The smooth surface region 21D is formed in a strip shape that extends linearly along the a-axis direction on the side surface 5D.

[0132] The smooth surface region 21A and the smooth surface region 21B are continuous with each other at the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. The smooth surface region 21B and the smooth surface region 21C are continuous with each other at the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

[0133] The smooth surface region 21C and the smooth surface region 21D are continuous with each other at the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. The smooth surface region 21D and the smooth surface region 21A are continuous with each other at the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.

[0134] As a result, the smooth surface regions 21A to 21D are integrally formed so as to surround the SiC semiconductor layer 2. The smooth surface regions 21A to 21D form one endless (annular) smooth surface region surrounding the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0135] With respect to the normal direction Z, the thickness TRs of the smooth surface regions 21A to 21D is a value obtained by subtracting the thickness TR of the rough surface regions 20A to 20D from the thickness TL of the SiC semiconductor layer 2 (TRs = TL - TR). The thickness TRs of the smooth surface regions 21A to 21D can take various values according to the thickness TR of the rough surface regions 20A to 20D.

[0136] The thickness TRs of the smooth surface regions 21A to 21D is preferably equal to or greater than the thickness TR of the rough surface regions 20A to 20D (TR ≦ TRs). The ratio TRs / TL of the thickness TRs of the smooth surface regions 21A to 21D to the thickness TL of the SiC semiconductor layer 2 is preferably 0.5 or more. It is more preferable that the thickness TRs of the smooth surface regions 21A to 21D exceeds the thickness TR of the rough surface regions 20A to 20D (TR < TRs). It is more preferable that the ratio TRs / TL exceeds 0.5.

[0137] The thicknesses of the thickness TRs of the smooth surface region 21A, the thickness TRs of the smooth surface region 21B, the thickness TRs of the smooth surface region 21C, and the thickness TRs of the smooth surface region 21D may be equal to each other or may be different from each other.

[0138] Unlike the rough surface regions 20A to 20D, the smooth surface regions 21A to 21D do not have the modification lines 22A to 22D (modified layers). The smooth surface regions 21A to 21D are composed of smooth cleavage surfaces formed by the crystal planes of the SiC single crystal. The smooth surface regions 21A to 21D have a surface roughness Rs corresponding to the crystal plane (cleavage plane) of the SiC single crystal.

[0139] The smooth surface region 21A is composed of the a-plane of the SiC single crystal forming the side surface 5A. The smooth surface region 21B is composed of the m-plane of the SiC single crystal forming the side surface 5B. The smooth surface region 21C is composed of the a-plane of the SiC single crystal forming the side surface 5C. The smooth surface region 21D is composed of the m-plane of the SiC single crystal forming the side surface 5D.

[0140] In this way, on the side surfaces 5A to 5D of the SiC semiconductor layer 2, rough surface regions 20A to 20D having a surface roughness Rr corresponding to the modification of the SiC single crystal and smooth surface regions 21A to 21D having a surface roughness Rs corresponding to the crystal plane (cleavage plane) of the SiC single crystal are formed.

[0141] The insulating side surfaces 11A to 11D of the aforementioned main surface insulating layer 10 are continuous with the smooth surface regions 21A to 21D. The insulating side surfaces 11A to 11D are formed flush with the smooth surface regions 21A to 21D. The insulating side surfaces 11A to 11D are composed of smooth cleavage planes. The insulating side surfaces 11A to 11D form one smooth surface region with the smooth surface regions 21A to 21D.

[0142] Referring to FIG. 8, in the active region 8, an n-type diode region 35 is formed in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. In this form, the diode region 35 is formed in the central portion of the first main surface 3 of the SiC semiconductor layer 2. In this form, the diode region 35 is set to a rectangular shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

[0143] The n-type impurity concentration of the diode region 35 may be equal to or higher than the n-type impurity concentration of the SiC epitaxial layer 7. In this form, the diode region 35 is formed using a part of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 35 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The diode region 35 may be formed by introducing n-type impurities into the surface layer portion of the SiC epitaxial layer 7.

[0144] In the outer region 9, a p + -type guard region 36 is formed in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. The guard region 36 is formed in a strip shape extending along the diode region 35 in plan view.

[0145] The guard region 36 is more specifically formed in an endless shape (for example, a square ring shape, a chamfered square ring shape, or a circular ring shape) surrounding the diode region 35 in a plan view. As a result, the guard region 36 is formed as a guard ring region. The diode region 35 is defined by the guard region 36 in this form. Also, the active region 8 is defined by the guard region 36.

[0146] The p-type impurities in the guard region 36 may not be activated. In this case, the guard region 36 is formed as a non-semiconductor region. The p-type impurities in the guard region 36 may be activated. In this case, the guard region 36 is formed as a p-type semiconductor region.

[0147] On the first main surface 3 of the SiC semiconductor layer 2, the aforementioned main surface insulating layer 10 is formed. In the main surface insulating layer 10, a diode opening 37 for exposing the diode region 35 is formed. The diode opening 37 exposes the inner peripheral edge of the guard region 36 in addition to the diode region 35. The diode opening 37 is formed in a square shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0148] On the main surface insulating layer 10, the aforementioned first main surface electrode layer 12 is formed. The first main surface electrode layer 12 enters the diode opening 37 from above the insulating layer. The first main surface electrode layer 12 is electrically connected to the diode region 35 within the diode opening 37.

[0149] More specifically, the first main surface electrode layer 12 forms a Schottky junction with the diode region 35. As a result, a Schottky barrier diode D having the first main surface electrode layer 12 as an anode and the diode region 35 as a cathode is formed. On the main surface insulating layer 10, the aforementioned passivation layer 13 and resin layer 16 are formed.

[0150] FIG. 9 is a perspective view showing an SiC semiconductor wafer 41 used in the manufacture of the SiC semiconductor device 1 shown in FIG. 3.

[0151] The SiC semiconductor wafer 41 is a member serving as the base of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 includes a 4H-SiC single crystal as an example of a hexagonal SiC single crystal. In this form, the SiC semiconductor wafer 41 has an n-type impurity concentration corresponding to the n-type impurity concentration of the SiC semiconductor substrate 6.

[0152] The SiC semiconductor wafer 41 is formed in a plate shape or a disk shape. The SiC semiconductor wafer 41 may be formed in a disk shape. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43.

[0153] The thickness TW of the SiC semiconductor wafer 41 exceeds the thickness TS of the SiC semiconductor substrate 6 (TS < TW). The thickness TW of the SiC semiconductor wafer 41 is adjusted to the thickness TS of the SiC semiconductor substrate 6 by grinding.

[0154] The thickness TW may be more than 150 μm and 750 μm or less. The thickness TW may be more than 150 μm and 300 μm or less, 300 μm or more and 450 μm or less, 450 μm or more and 600 μm or less, or 600 μm or more and 750 μm or less. In view of the grinding time of the SiC semiconductor wafer 41, the thickness TW is preferably more than 150 μm and 500 μm or less. The thickness TW is typically 300 μm or more and 450 μm or less.

[0155] In this form, the first wafer main surface 42 and the second wafer main surface 43 face the c-plane of the SiC single crystal. The first wafer main surface 42 faces the (0001) plane (silicon plane). The second wafer main surface 43 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0156] The first wafer main surface 42 and the second wafer main surface 43 have an off-angle θ that is inclined at an angle of 10° or less with respect to the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 42 is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0157] The off-angle θ may be 0° or more and 5.0° or less. The off-angle θ may be set in the range of an angle of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. It is preferable that the off-angle θ exceeds 0°. The off-angle θ may be less than 4.0°.

[0158] The off-angle θ may be set in the range of an angle of 3.0° or more and 4.5° or less. In this case, it is preferable that the off-angle θ is set in the range of an angle of 3.0° or more and 3.5° or less or 3.5° or more and 4.0° or less.

[0159] The off-angle θ may be set in the range of an angle of 1.5° or more and 3.0° or less. In this case, it is preferable that the off-angle θ is set in the range of an angle of 1.5° or more and 2.0° or less or 2.0° or more and 2.5° or less.

[0160] The SiC semiconductor wafer 41 includes a first wafer corner portion 45 that connects the first wafer main surface 42 and the wafer side surface 44, and a second wafer corner portion 46 that connects the second wafer main surface 43 and the wafer side surface 44. The first wafer corner portion 45 has a first chamfered portion 47 that slopes downward from the first wafer main surface 42 toward the wafer side surface 44. The second wafer corner portion 46 has a second chamfered portion 48 that slopes downward from the second wafer main surface 43 toward the wafer side surface 44.

[0161] The first chamfered portion 47 may be formed in a convexly curved shape. The second chamfered portion 48 may be formed in a convexly curved shape. The first chamfered portion 47 and the second chamfered portion 48 suppress cracks in the SiC semiconductor wafer 41.

[0162] On the wafer side surface 44 of the SiC semiconductor wafer 41, one orientation flat 49 is formed as an example of a mark indicating the crystal orientation of the SiC single crystal. The orientation flat 49 is a notch formed in the wafer side surface 44 of the SiC semiconductor wafer 41. In this form, the orientation flat 49 extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

[0163] A plurality (for example, two) of orientation flats 49 indicating the crystal orientation may be formed on the wafer side surface 44 of the SiC semiconductor wafer 41. The plurality (for example, two) of orientation flats 49 may include a first orientation flat and a second orientation flat.

[0164] The first orientation flat may be a notch that extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal. The second orientation flat may be a notch that extends linearly along the m-axis direction ([1-100] direction) of the SiC single crystal.

[0165] On the first main surface 42 of the SiC semiconductor wafer 41, a plurality of device formation regions 51 corresponding to the SiC semiconductor device 1 are set. The plurality of device formation regions 51 are set in a matrix array at intervals in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).

[0166] Each device formation region 51 has four sides 52A, 52B, 52C, and 52D along the crystal orientation of the SiC single crystal. The four sides 52A to 52D respectively correspond to the four side surfaces 5A to 5D of the SiC semiconductor layer 2. The four sides 52A to 52D include two sides 52A and 52C along the m-axis direction ([1-100] direction) and two sides 52B and 52D along the a-axis direction ([11-20] direction).

[0167] The plurality of device formation regions 51 are each partitioned by a lattice-shaped planned cutting line 53 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The planned cutting line 53 includes a plurality of first planned cutting lines 54 and a plurality of second planned cutting lines 55.

[0168] The plurality of first planned cutting lines 54 each extend along the m-axis direction ([1-100] direction). The plurality of second planned cutting lines 55 each extend along the a-axis direction ([11-20] direction). After a predetermined structure is formed in the plurality of device formation regions 51, the SiC semiconductor wafer 41 is cut along the planned cutting line 53, whereby a plurality of SiC semiconductor devices 1 are cut out.

[0169] FIGS. 10A to 10M are cross-sectional views showing an example of a method for manufacturing the SiC semiconductor device 1 shown in FIG. 3. In FIGS. 10A to 10M, for the sake of convenience of explanation, only the region where three SiC semiconductor devices 1 are formed is shown, and the illustration of other regions is omitted.

[0170] Referring to FIG. 10A, in manufacturing the SiC semiconductor device 1, first, an SiC semiconductor wafer 41 is prepared (also refer to FIG. 9). Next, an n-type SiC epitaxial layer 7 is formed on the first wafer main surface 42 of the SiC semiconductor wafer 41.

[0171] In the step of forming the SiC epitaxial layer 7, SiC is epitaxially grown from the first wafer main surface 42 of the SiC semiconductor wafer 41. The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less.

[0172] As a result, a SiC semiconductor wafer structure 61 including a SiC semiconductor wafer 41 and a SiC epitaxial layer 7 is formed. The SiC semiconductor wafer structure 61 includes a first main surface 62 and a second main surface 63.

[0173] The first main surface 62 and the second main surface 63 of the SiC semiconductor wafer structure 61 respectively correspond to the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. The thickness TWS of the SiC semiconductor wafer structure 61 may be more than 150 μm and 800 μm or less. Preferably, the thickness TWS is more than 150 μm and 550 μm or less.

[0174] Next, referring to FIG. 10B, a p + -type guard region 36 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The forming process of the guard region 36 includes a process of selectively introducing p-type impurities into the surface layer portion of the first main surface 62 of the SiC semiconductor wafer structure 61 through an ion implantation mask (not shown). More specifically, the guard region 36 is formed in the surface layer portion of the SiC epitaxial layer 7.

[0175] The guard region 36 partitions an active region 8 and an outer region 9 in the SiC semiconductor wafer structure 61. An n-type diode region 35 is partitioned in the region (active region 8) surrounded by the guard region 36.

[0176] The diode region 35 may be formed by selectively introducing n-type impurities into the surface layer portion of the first main surface 62 of the SiC semiconductor wafer structure 61 through an ion implantation mask (not shown).

[0177] Next, referring to FIG. 10C, a main surface insulating layer 10 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The main surface insulating layer 10 contains silicon oxide (SiO2). The main surface insulating layer 10 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0178] Next, referring to FIG. 10D, a mask 64 having a predetermined pattern is formed on the main surface insulating layer 10. The mask 64 has a plurality of openings 65. The plurality of openings 65 respectively expose regions in the main surface insulating layer 10 where the diode openings 37 are to be formed.

[0179] Next, unnecessary portions of the main surface insulating layer 10 are removed by an etching method through the mask 64. Thereby, diode openings 37 are formed in the main surface insulating layer 10. After the formation of the diode openings 37, the mask 64 is removed.

[0180] Next, referring to FIG. 10E, a base electrode layer 66 that serves as a base for the first main surface electrode layer 12 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The base electrode layer 66 is formed over the entire first main surface 62 of the SiC semiconductor wafer structure 61 and covers the main surface insulating layer 10. The first main surface electrode layer 12 may be formed by a vapor deposition method, a sputtering method, or an electroplating method.

[0181] Next, referring to FIG. 10F, a mask 67 having a predetermined pattern is formed on the base electrode layer 66. The mask 67 has an opening 68 that exposes a region other than the region in the base electrode layer 66 where the first main surface electrode layer 12 is to be formed.

[0182] Next, unnecessary portions of the base electrode layer 66 are removed by an etching method through the mask 67. Thereby, the base electrode layer 66 is divided into a plurality of first main surface electrode layers 12. After the formation of the first main surface electrode layer 12, the mask 67 is removed.

[0183] Next, referring to FIG. 10G, a passivation layer 13 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The passivation layer 13 contains silicon nitride (SiN). The passivation layer 13 may be formed by a CVD method.

[0184] Next, referring to FIG. 10H, a resin layer 16 is applied over the passivation layer 13. The resin layer 16 collectively covers the active region 8 and the outer region 9. The resin layer 16 may contain polybenzoxazole as an example of a positive-type photosensitive resin.

[0185] Next, referring to FIG. 10I, after the resin layer 16 is selectively exposed, it is developed. Thereby, pad openings 18 are formed in the resin layer 16. Also, dicing streets 69 along the planned cutting lines 53 (sides 52A to 52D of each device formation region 51) are defined in the resin layer 16.

[0186] Next, unnecessary portions of the passivation layer 13 are removed. The unnecessary portions of the passivation layer 13 may be removed by an etching method through the resin layer 16. Thereby, sub-pad openings 15 are formed in the passivation layer 13. Also, dicing streets 69 along the planned cutting lines 53 are defined in the passivation layer 13.

[0187] Next, referring to FIG. 10J, the second main surface 63 of the SiC semiconductor wafer structure 61 (the second wafer main surface 43 of the SiC semiconductor wafer 41) is ground. Thereby, the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is thinned. Also, grinding marks are formed on the second main surface 63 of the SiC semiconductor wafer structure 61.

[0188] The SiC semiconductor wafer structure 61 is ground until it reaches a thickness TWS corresponding to the thickness TL of the SiC semiconductor layer 2. The SiC semiconductor wafer structure 61 may be ground until it reaches a thickness TWS of 40 μm or more and 200 μm or less.

[0189] That is, the SiC semiconductor wafer 41 is ground until it reaches a thickness TW corresponding to the thickness TS of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 may be ground until it reaches a thickness TW of 40 μm or more and 150 μm or less.

[0190] Next, referring to FIG. 10K, a plurality of modification lines 70 (modification layers) serving as the bases of the rough surface regions 20A to 20D (modified lines 22A to 22D) are formed. In the process of forming the modification lines 70, pulsed laser light is irradiated from the laser light irradiation device 71 toward the SiC semiconductor wafer structure 61.

[0191] In this form, the laser light is irradiated onto the SiC semiconductor wafer structure 61 from the first main surface 62 side of the SiC semiconductor wafer structure 61 through the main surface insulating layer 10. The laser light may be directly irradiated onto the SiC semiconductor wafer structure 61 from the second main surface 63 side of the SiC semiconductor wafer structure 61.

[0192] The condensing part (focus) of the laser light is set at the mid-thickness position in the thickness direction of the SiC semiconductor wafer structure 61. The irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the planned cutting line 53 (the four sides 52A to 52D of each device formation region 51).

[0193] More specifically, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the first planned cutting line 54. Also, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the second planned cutting line 55.

[0194] Thereby, a plurality of modification lines 70 are formed in the mid-thickness position in the thickness direction of the SiC semiconductor wafer structure 61, extending along the planned cutting line 53 (the four sides 52A to 52D of each device formation region 51), and modifying the crystal state of the SiC single crystal to a property different from that of other regions.

[0195] The two modification lines 70 along the sides 52A and 52C of the device formation region 51 each include an a-plane modification part 28. The two modification lines 70 along the sides 52B and 52D of the device formation region 51 each include an m-plane modification part 29.

[0196] A plurality of modified lines 70 are formed one by one or in multiple layers (two or more layers. In this embodiment, two layers) for each of the four sides 52A to 52D of each device formation region 51 in a one-to-one correspondence. The plurality of modified lines 70 are also laser processing marks formed in the middle part in the thickness direction of the SiC semiconductor wafer structure 61. More specifically, the a-plane modified portion 28 and the m-plane modified portion 29 of the modified line 70 are laser processing marks.

[0197] The condensing part (focus) of the laser beam, the laser energy, the pulse duty ratio, the irradiation speed, etc. are determined to arbitrary values according to the position, size, shape, thickness, etc. of the modified line 70 (rough surface regions 20A to 20D) to be formed.

[0198] Next, referring to FIG. 10L, a second main surface electrode layer 19 is formed on the second main surface 63 of the SiC semiconductor wafer structure 61. The second main surface electrode layer 19 may be formed by a vapor deposition method, a sputtering method, or a plating method.

[0199] Prior to the formation process of the second main surface electrode layer 19, an annealing process may be performed on the second main surface 63 (ground surface) of the SiC semiconductor wafer structure 61. The annealing process may be performed by a laser annealing method using a laser beam.

[0200] According to the laser annealing method, the SiC single crystal in the surface layer portion of the second main surface 63 of the SiC semiconductor wafer structure 61 is modified to form a Si amorphous layer. In this case, a SiC semiconductor device 1 having a Si amorphous layer in the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 is manufactured. On the second main surface 4 of the SiC semiconductor layer 2, grinding marks and a Si amorphous layer coexist. According to the laser annealing method, the ohmic property of the second main surface electrode layer 19 with respect to the second main surface 4 of the SiC semiconductor layer 2 can be enhanced.

[0201] Next, referring to FIG. 10M, a plurality of SiC semiconductor devices 1 are cut out from the SiC semiconductor wafer structure 61. In this process, a tape-shaped support member 73 is adhered to the second main surface 63 side of the SiC semiconductor wafer structure 61.

[0202] Next, an external force is applied to the planned cutting line 53 from the second main surface 63 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force applied to the planned cutting line 53 may be applied by a pressing member such as a blade.

[0203] In another form, the support member 73 may be attached to the first main surface 62 side of the SiC semiconductor wafer structure 61. In this case, an external force may be applied to the planned cutting line 53 from the first main surface 62 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force may be applied by a pressing member such as a blade.

[0204] In yet another form, a stretchable support member 73 may be attached to the first main surface 62 side or the second main surface 63 side of the SiC semiconductor wafer structure 61. In this case, the SiC semiconductor wafer structure 61 may be cleaved by stretching the stretchable support member 73 in the m-axis direction and the a-axis direction.

[0205] When cleaving the SiC semiconductor wafer structure 61 using the support member 73, it is preferable that the support member 73 is attached to the second main surface 63 side of the SiC semiconductor wafer structure 61 with few obstacles.

[0206] In this way, the SiC semiconductor wafer structure 61 is cleaved along the planned cutting line 53 starting from the modified line 70, and a plurality of SiC semiconductor devices 1 are cut out from one SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

[0207] The portion of the modified line 70 along the side 52A of each device formation region 51 becomes a rough surface region 20A (modified line 22A). The portion of the modified line 70 along the side 52B of each device formation region 51 becomes a rough surface region 20B (modified line 22B). The portion of the modified line 70 along the side 52C of each device formation region 51 becomes a rough surface region 20C (modified line 22C). The portion of the modified line 70 along the side 52D of each device formation region 51 becomes a rough surface region 20D (modified line 22D). Through the steps including the above, the SiC semiconductor device 1 is manufactured.

[0208] In this embodiment, the grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 was carried out prior to the formation process (FIG. 10K) of the modification line 70. However, the grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 can be carried out at any timing after the preparation process (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation process (FIG. 10L) of the second main surface electrode layer 19.

[0209] For example, the grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 may be carried out prior to the formation process (FIG. 10A) of the SiC epitaxial layer 7. Also, the grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 may be carried out after the formation process (FIG. 10K) of the modification line 70.

[0210] Also, the grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 may be carried out in multiple times at any timing after the preparation process (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation process (FIG. 10K) of the modification line 70. Also, the grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 may be carried out in multiple times at any timing after the preparation process (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation process (FIG. 10L) of the second main surface electrode layer 19.

[0211] FIG. 11 is a perspective view showing the semiconductor package 74 in which the SiC semiconductor device 1 is incorporated, through the encapsulation resin 79.

[0212] Referring to FIG. 11, the semiconductor package 74 is of the so-called TO-220 type in this embodiment. The semiconductor package 74 includes the SiC semiconductor device 1, the pad portion 75, the heat sink 76, a plurality (two in this embodiment) of terminals 77, a plurality (two in this embodiment) of conductive wires 78, and the encapsulation resin 79. The pad portion 75, the heat sink 76, and the plurality of terminals 77 form a lead frame as an example of an object to be connected.

[0213] The pad portion 75 includes a metal plate. The pad portion 75 may contain iron, gold, silver, copper, aluminum, etc. The pad portion 75 is formed in a square shape in a plan view. The pad portion 75 has a planar area equal to or larger than the planar area of the SiC semiconductor device 1. The SiC semiconductor device 1 is disposed on the pad portion 75.

[0214] The second main surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via a conductive bonding material 80. The conductive bonding material 80 is interposed in the region between the second main surface electrode layer 19 and the pad portion 75.

[0215] The conductive bonding material 80 may be a metal paste or solder. The metal paste may be a conductive paste containing Au (gold), Ag (silver), or Cu (copper). The conductive bonding material 80 preferably consists of solder. The solder may be lead-free solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, or SnSbNi.

[0216] The heat sink 76 is connected to one side of the pad portion 75. In this configuration, the pad portion 75 and the heat sink 76 are formed of a single metal plate. A through hole 76a is formed in the heat sink 76. The through hole 76a is formed in a circular shape.

[0217] The plurality of terminals 77 are arranged along the side of the pad portion 75 opposite to the heat sink 76. Each of the plurality of terminals 77 includes a metal plate. The terminal 77 may contain iron, gold, silver, copper, aluminum, etc.

[0218] The plurality of terminals 77 include a first terminal 77A and a second terminal 77B. The first terminal 77A and the second terminal 77B are arranged at intervals along the side of the pad portion 75 opposite to the heat sink 76. The first terminal 77A and the second terminal 77B extend in a strip shape along a direction orthogonal to their arrangement direction.

[0219] The plurality of conductive wires 78 may be bonding wires or the like. The plurality of conductive wires 78 includes a conductive wire 78A and a conductive wire 78B. The conductive wire 78A is electrically connected to the first terminal 77A and the first main surface electrode layer 12 of the SiC semiconductor device 1. Thereby, the first terminal 77A is electrically connected to the first main surface electrode layer 12 of the SiC semiconductor device 1 via the conductive wire 78A.

[0220] The conductive wire 78B is electrically connected to the second terminal 77B and the pad portion 75. Thereby, the second terminal 77B is electrically connected to the second main surface electrode layer 19 of the SiC semiconductor device 1 via the conductive wire 78B. The second terminal 77B may be integrally formed with the pad portion 75.

[0221] The encapsulating resin 79 encapsulates the SiC semiconductor device 1, the pad portion 75, and the plurality of conductive wires 78 so as to expose a part of the heat sink 76 and the plurality of terminals 77. The encapsulating resin 79 is formed in a rectangular parallelepiped shape.

[0222] The form of the semiconductor package 74 is not limited to TO-220. As the semiconductor package 74, SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package), or various forms similar to these may be applied.

[0223] FIG. 12 is a perspective view specifically showing the mounting state of the SiC semiconductor device 1 shown in FIG. 11.

[0224] Referring to FIG. 12, the SiC semiconductor device 1 is disposed on the pad portion 75 with the second main surface 4 of the SiC semiconductor layer 2 facing upward. The second main surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via a conductive bonding material 80.

[0225] The conductive bonding material 80 includes a film-shaped conductive bonding material film 80a formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2. The conductive bonding material film 80a is a region where a part of the conductive bonding material 80 wets and spreads in a film shape on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0226] When the rough surface regions 20A to 20D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2, the conductive bonding material 80 wets and spreads on the side surfaces 5A to 5D due to the capillary phenomenon occurring in the rough surface regions 20A to 20D. In this form, an example is shown in which the conductive bonding material 80 wets and spreads over the entire area of the rough surface regions 20A to 20D, and a conductive bonding material film 80a covering the entire area of the rough surface regions 20A to 20D is formed.

[0227] On the side surfaces 5A to 5D of the SiC semiconductor layer 2, smooth surface regions 21A to 21D are formed in the regions between the first main surface 3 and the rough surface regions 20A to 20D. The smooth surface regions 21A to 21D have a surface roughness Rs (Rs < Rr) that is less than the surface roughness Rr of the rough surface regions 20A to 20D.

[0228] The capillary phenomenon occurring in the rough surface regions 20A to 20D is suppressed by the smooth surface regions 21A to 21D. Therefore, the wetting and spreading of the conductive bonding material 80 on the side surfaces 5A to 5D is suppressed by the smooth surface regions 21A to 21D. In this form, the conductive bonding material film 80a has an end portion located in the middle of the thickness direction of the smooth surface regions 21A to 21D across the boundary between the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D.

[0229] Also, the smooth surface regions 21A to 21D are formed in the regions on the first main surface 3 side with respect to the rough surface regions 20A to 20D on the side surfaces 5A to 5D of the SiC semiconductor layer 2. Thereby, the smooth surface regions 21A to 21D suppress the intrusion of the conductive bonding material 80 into the first main surface 3.

[0230] Thus, in the SiC semiconductor device 1, the short circuit of the SiC semiconductor layer 2 through the conductive bonding material 80 (conductive bonding material film 80a) is suppressed by the smooth surface regions 21A to 21D. More specifically, the short circuit between the first main surface electrode layer 12 and the second main surface electrode layer 19 (pad portion 75) through the conductive bonding material 80 (conductive bonding material film 80a) is suppressed by the smooth surface regions 21A to 21D. This short circuit may include those caused by a discharge phenomenon between the conductive bonding material 80 (conductive bonding material film 80a) and the first main surface electrode layer 12.

[0231] The risk of short circuit associated with the formation of the conductive bonding material film 80a increases as the area of the side surfaces 5A to 5D of the SiC semiconductor layer 2 decreases. That is, the smaller the thickness TL of the SiC semiconductor layer 2, the higher the risk of short circuit associated with the formation of the conductive bonding material film 80a. The structure that suppresses the formation of the conductive bonding material film 80a by the smooth surface regions 21A to 21D is particularly effective when the thickness TL of the SiC semiconductor layer 2 is 40 μm or more and 200 μm or less.

[0232] As described above, according to the SiC semiconductor device 1, the capillary phenomenon occurring in the rough surface regions 20A to 20D can be suppressed by the smooth surface regions 21A to 21D, so that the wetting spread of the conductive bonding material 80 on the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be suppressed. Therefore, the short circuit caused by the wetting spread of the conductive bonding material 80 can be suppressed.

[0233] Also, according to the SiC semiconductor device 1, the rough surface regions 20A to 20D are formed in the region on the second main surface 4 side of the SiC semiconductor layer 2, and the smooth surface regions 21A to 21D are formed in the region on the first main surface 3 side of the SiC semiconductor layer 2 with respect to the rough surface regions 20A to 20D. Thereby, the intrusion of the conductive bonding material 80 around the first main surface 3 of the SiC semiconductor layer 2 can be appropriately suppressed. Therefore, the short circuit caused by the wetting spread of the conductive bonding material 80 can be appropriately suppressed.

[0234] In particular, according to the SiC semiconductor device 1, the rough surface regions 20A to 20D are formed on the SiC semiconductor substrate 6, and the smooth surface regions 21A to 21D are formed on the SiC epitaxial layer 7. The smooth surface regions 21A to 21D are preferably formed on the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 across the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7.

[0235] Thereby, the spreading of the conductive bonding material 80 on the SiC epitaxial layer 7 can be appropriately suppressed. Therefore, short circuits and variations in electrical characteristics of the semiconductor element (the Schottky barrier diode D in this embodiment) caused by the conductive bonding material 80 can be suppressed.

[0236] Further, according to the SiC semiconductor device 1, it includes a main surface insulating layer 10 and a first main surface electrode layer 12 formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 has insulating side surfaces 11A to 11D that are continuous with the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0237] In the structure in which the rough surface regions 20A to 20D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2, the main surface insulating layer 10 enhances the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12.

[0238] Thereby, while suppressing the spreading of the conductive bonding material 80, a short circuit caused by the spreading of the conductive bonding material 80 can be appropriately suppressed. Such a structure is also effective in suppressing the discharge phenomenon between the conductive bonding material 80 (conductive bonding material film 80a) and the first main surface electrode layer 12.

[0239] FIG. 13A is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a second exemplary form of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. Hereinafter, for the structure corresponding to the structure described for the SiC semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0240] The rough surface regions 20A to 20D according to the first exemplary embodiment are formed from the corner portions on the second main surface 4 side to the middle portion in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D. On the other hand, the rough surface regions 20A to 20D according to the second exemplary embodiment are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The rough surface regions 20A to 20D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

[0241] Also, in this embodiment, rough surface regions 20A to 20D including one layer of modification lines 22A to 22D are formed. The modification lines 22A to 22D are formed one by one in a one-to-one correspondence relationship with the middle portion in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D.

[0242] In this embodiment, the smooth surface regions 21A to 21D are formed not only in the regions on the first main surface 3 side but also in the regions on the second main surface 4 side on the side surfaces 5A to 5D. The smooth surface regions 21A to 21D on the second main surface 4 side are formed from the second main surface 4 to the middle portion in the thickness direction of the SiC semiconductor layer 2. The smooth surface regions 21A to 21D on the second main surface 4 side are formed on the SiC semiconductor substrate 6.

[0243] The rough surface regions 20A to 20D according to the second exemplary embodiment are formed by adjusting the condensing portion (focus) of the laser beam and the like in the formation process of the modification lines 70 (rough surface regions 20A to 20D) (see also FIG. 10K).

[0244] As described above, even when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the second exemplary embodiment are formed, the same effects as those when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary embodiment are formed can be achieved.

[0245] In particular, according to the SiC semiconductor device 1 having the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the second exemplary form, the smooth surface regions 21A to 21D are also provided in the regions on the second main surface 4 side of the side surfaces 5A to 5D. Thereby, the wetting spread of the conductive bonding material 80 can be suppressed in the regions on the second main surface 4 side of the side surfaces 5A to 5D. Therefore, a short circuit caused by the wetting spread of the conductive bonding material 80 can be appropriately suppressed.

[0246] Also, in the manufacturing process of the SiC semiconductor device 1, a grinding process (FIG. 10J) of the SiC semiconductor wafer structure 61 is performed. According to the thinned SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41), the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can be appropriately cleaved without forming a plurality of modified lines 70 (rough surface regions 20A to 20D) at intervals in the normal direction Z.

[0247] In other words, since the thinning process of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is performed, the SiC semiconductor wafer structure 61 can be appropriately cleaved by one layer of modified line 70. Thereby, the time required for the forming process of the modified line 70 can be reduced.

[0248] Thereby, it is not necessary to form a plurality of rough surface regions 20A to 20D at intervals in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D, so that the formation area of the rough surface regions 20A to 20D can be appropriately reduced. Thereby, the wetting spread of the conductive bonding material 80 caused by the rough surface regions 20A to 20D can be appropriately suppressed.

[0249] In this case, the second main surface 4 of the SiC semiconductor layer 2 is composed of a ground surface. The SiC semiconductor device 1 preferably includes a SiC semiconductor layer 2 having a thickness TL of 40 μm or more and 200 μm or less. The SiC semiconductor layer 2 having such a thickness TL can be appropriately cut out from the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

[0250] In the SiC semiconductor layer 2, the thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. In the SiC semiconductor layer 2, the thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. Thinning of the SiC semiconductor layer 2 is also effective in reducing the resistance value.

[0251] FIG. 13B is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a third exemplary form of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. Hereinafter, for the structure corresponding to the structure described for the SiC semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0252] The rough surface regions 20A to 20D according to the first exemplary form are connected to each other at the corners connecting the side surfaces 5A to 5D in the SiC semiconductor layer 2. On the other hand, the rough surface regions 20A to 20D according to the third exemplary form are formed with spaces from each other at the corners connecting the side surfaces 5A to 5D in the SiC semiconductor layer 2.

[0253] Also, in this form, the rough surface regions 20A to 20D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The rough surface regions 20A to 20D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

[0254] Also, in this form, rough surface regions 20A to 20D including one layer of modification lines 22A to 22D are formed. The modification lines 22A to 22D are formed one by one in a one-to-one correspondence relationship in the middle of the SiC semiconductor layer 2 in the thickness direction on the side surfaces 5A to 5D.

[0255] The rough surface region 20A and the rough surface region 20B are formed with spaces from each other in the normal direction Z at the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. The rough surface region 20B and the rough surface region 20C are formed with spaces from each other in the normal direction Z at the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

[0256] The rough surface regions 20C and 20D are formed at a distance from each other in the normal direction Z at the corner connecting the side surfaces 5C and 5D in the SiC semiconductor layer 2. The rough surface regions 20D and 20A are formed at a distance from each other in the normal direction Z at the corner connecting the side surfaces 5D and 5A in the SiC semiconductor layer 2.

[0257] Of course, at least one of the rough surface regions 20A to 20D may be formed at a distance from the other rough surface regions 20A to 20D at the corner connecting any of the side surfaces 5A to 5D in the SiC semiconductor layer 2. Two or three of the rough surface regions 20A to 20D may be connected to each other at the corner connecting any of the side surfaces 5A to 5D in the SiC semiconductor layer 2.

[0258] In this form, the smooth surface regions 21A to 21D are formed not only in the regions on the first main surface 3 side but also in the regions on the second main surface 4 side on the side surfaces 5A to 5D. The smooth surface regions 21A to 21D on the second main surface 4 side are formed from the second main surface 4 to the middle part in the thickness direction of the SiC semiconductor layer 2. The smooth surface regions 21A to 21D on the second main surface 4 side are formed on the SiC semiconductor substrate 6.

[0259] The rough surface regions 20A to 20D according to the third exemplary form are formed by adjusting the condensing part (focus) of the laser beam and the like in the formation process of the modified line 70 (rough surface regions 20A to 20D) (see also Fig. 10K).

[0260] As described above, even when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the third exemplary form are formed, the same effects as those when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary form and the second exemplary form are formed can be achieved.

[0261] FIG. 13C is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a fourth exemplary form of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0262] The rough surface regions 20A to 20D according to the first exemplary form are formed in a strip shape extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. On the other hand, the rough surface regions 20A to 20D according to the fourth exemplary form are formed in a strip shape extending in an inclined shape that slopes downward from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2.

[0263] Also, in this form, the rough surface regions 20A to 20D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The rough surface regions 20A to 20D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

[0264] Also, in this form, the rough surface regions 20A to 20D including one layer of modification lines 22A to 22D are formed. The modification lines 22A to 22D are formed one by one in a one-to-one correspondence relationship in the middle portion in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D.

[0265] The rough surface regions 20A to 20D according to the fourth exemplary form more specifically include a first end region 81, a second end region 82, and an inclined region 83. The first end region 81 is located on the first main surface 3 side of the SiC semiconductor layer 2 near the corner of the SiC semiconductor layer 2. The second end region 82 is located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the first end region 81 near the corner of the SiC semiconductor layer 2. The inclined region 83 slopes downward from the first main surface 3 to the second main surface 4 in the region between the first end region 81 and the second end region 82.

[0266] At the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, the first end region 81 of the rough surface region 20A and the first end region 81 of the rough surface region 20B may be located. At the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, the second end region 82 of the rough surface region 20A and the second end region 82 of the rough surface region 20B may be located.

[0267] At the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, the first end region 81 of the rough surface region 20A and the second end region 82 of the rough surface region 20B may be located. At the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, the second end region 82 of the rough surface region 20A and the first end region 81 of the rough surface region 20B may be located.

[0268] The rough surface region 20A and the rough surface region 20B may be continuous with each other or may be formed with a space therebetween at the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2.

[0269] At the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, the first end region 81 of the rough surface region 20B and the first end region 81 of the rough surface region 20C may be located. At the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, the second end region 82 of the rough surface region 20B and the second end region 82 of the rough surface region 20C may be located.

[0270] At the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, the first end region 81 of the rough surface region 20B and the second end region 82 of the rough surface region 20C may be located. At the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, the second end region 82 of the rough surface region 20B and the first end region 81 of the rough surface region 20C may be located.

[0271] The rough surface region 20B and the rough surface region 20C may be continuous with each other or may be formed with a space therebetween at the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

[0272] At the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, the first end region 81 of the rough surface region 20C and the first end region 81 of the rough surface region 20D may be located. At the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, the second end region 82 of the rough surface region 20C and the second end region 82 of the rough surface region 20D may be located.

[0273] At the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, the first end region 81 of the rough surface region 20C and the second end region 82 of the rough surface region 20D may be located. At the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, the second end region 82 of the rough surface region 20C and the first end region 81 of the rough surface region 20D may be located.

[0274] The rough surface region 20C and the rough surface region 20D may be connected to each other at the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, or may be formed with a space therebetween.

[0275] At the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, the first end region 81 of the rough surface region 20D and the first end region 81 of the rough surface region 20A may be located. At the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, the second end region 82 of the rough surface region 20D and the second end region 82 of the rough surface region 20A may be located.

[0276] At the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, the first end region 81 of the rough surface region 20D and the second end region 82 of the rough surface region 20A may be located. At the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, the second end region 82 of the rough surface region 20D and the first end region 81 of the rough surface region 20A may be located.

[0277] The rough surface regions 20D and 20A may be connected to each other at the corners connecting the side surfaces 5D and 5A in the SiC semiconductor layer 2, or may be formed with a space therebetween.

[0278] In this form, the smooth surface regions 21A to 21D are formed not only in the regions on the first main surface 3 side but also in the regions on the second main surface 4 side on the side surfaces 5A to 5D. The smooth surface regions 21A to 21D on the second main surface 4 side are formed from the second main surface 4 to the middle part in the thickness direction of the SiC semiconductor layer 2. The smooth surface regions 21A to 21D on the second main surface 4 side are formed on the SiC semiconductor substrate 6.

[0279] The rough surface regions 20A to 20D according to the fourth exemplary form are formed by adjusting the condensing part (focus) of the laser beam or the like in the formation process of the modification line 70 (rough surface regions 20A to 20D) (see also FIG. 10K).

[0280] As described above, even when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the fourth exemplary form are formed, the same effects as those when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary form and the second exemplary form are formed can be achieved.

[0281] In particular, according to the modification line 70 that is the basis of the rough surface regions 20A to 20D according to the fourth exemplary form, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). Thereby, even when forming the single-layer modification line 70 (rough surface regions 20A to 20D), the SiC semiconductor wafer structure 61 can be appropriately cleaved.

[0282] FIG. 13D is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a fifth exemplary form of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0283] The rough surface regions 20A to 20D according to the first exemplary form are formed in a strip shape that extends linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. On the other hand, the rough surface regions 20A to 20D according to the fifth exemplary form are formed in a strip shape that slopes downward from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2 and extends in a curved (curvilinear) shape.

[0284] Also, in this form, the rough surface regions 20A to 20D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The rough surface regions 20A to 20D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

[0285] Also, in this form, rough surface regions 20A to 20D including one layer of modification lines 22A to 22D are formed. The modification lines 22A to 22D are formed one by one in a one-to-one correspondence relationship in the middle part in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D.

[0286] The rough surface regions 20A to 20D according to the fifth exemplary form more specifically include a first end region 84, a second end region 85, and a curved region 86, respectively. The first end region 84 is located on the first main surface 3 side of the SiC semiconductor layer 2 near the corner of the SiC semiconductor layer 2. The second end region 85 is located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the first end region 84 near the corner of the SiC semiconductor layer 2.

[0287] The curved region 86 slopes downward in a concave curved shape from the first main surface 3 to the second main surface 4 and connects the first end region 84 and the second end region 85. The curved region 86 may slope downward in a convex curved shape from the first main surface 3 to the second main surface 4.

[0288] At the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, the first end region 84 of the rough surface region 20A and the first end region 84 of the rough surface region 20B may be located. At the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, the second end region 85 of the rough surface region 20A and the second end region 85 of the rough surface region 20B may be located.

[0289] At the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, the first end region 84 of the rough surface region 20A and the second end region 85 of the rough surface region 20B may be located. At the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, the second end region 85 of the rough surface region 20A and the first end region 84 of the rough surface region 20B may be located.

[0290] The rough surface region 20A and the rough surface region 20B may be continuous with each other at the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, or may be formed with a space therebetween.

[0291] At the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, the first end region 84 of the rough surface region 20B and the first end region 84 of the rough surface region 20C may be located. At the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, the second end region 85 of the rough surface region 20B and the second end region 85 of the rough surface region 20C may be located.

[0292] At the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, the first end region 84 of the rough surface region 20B and the second end region 85 of the rough surface region 20C may be located. At the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, the second end region 85 of the rough surface region 20B and the first end region 84 of the rough surface region 20C may be located.

[0293] The rough surface region 20B and the rough surface region 20C may be continuous with each other at the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, or may be formed with a space therebetween.

[0294] At the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, the first end region 84 of the rough surface region 20C and the first end region 84 of the rough surface region 20D may be located. At the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, the second end region 85 of the rough surface region 20C and the second end region 85 of the rough surface region 20D may be located.

[0295] At the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, the first end region 84 of the rough surface region 20C and the second end region 85 of the rough surface region 20D may be located. At the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, the second end region 85 of the rough surface region 20C and the first end region 84 of the rough surface region 20D may be located.

[0296] The rough surface region 20C and the rough surface region 20D may be connected to each other at the corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2, or may be formed with a space therebetween.

[0297] At the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, the first end region 84 of the rough surface region 20D and the first end region 84 of the rough surface region 20A may be located. At the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, the second end region 85 of the rough surface region 20D and the second end region 85 of the rough surface region 20A may be located.

[0298] At the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, the first end region 84 of the rough surface region 20D and the second end region 85 of the rough surface region 20A may be located. At the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, the second end region 85 of the rough surface region 20D and the first end region 84 of the rough surface region 20A may be located.

[0299] The rough surface region 20D and the rough surface region 20A may be connected to each other at the corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2, or may be formed with a space therebetween.

[0300] In this form, the smooth surface regions 21A to 21D are formed not only in the regions on the first main surface 3 side but also in the regions on the second main surface 4 side on the side surfaces 5A to 5D. The smooth surface regions 21A to 21D on the second main surface 4 side are formed from the second main surface 4 to the middle part in the thickness direction of the SiC semiconductor layer 2. The smooth surface regions 21A to 21D on the second main surface 4 side are formed on the SiC semiconductor substrate 6.

[0301] The rough surface regions 20A to 20D according to the fifth exemplary form are formed by adjusting the condensing part (focus) of the laser beam or the like in the forming process of the modification line 70 (rough surface regions 20A to 20D) (see also FIG. 10K).

[0302] Even when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the fifth exemplary form are formed, the same effects as those when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary form and the second exemplary form are formed can be achieved.

[0303] In particular, according to the modification line 70 that is the base of the rough surface regions 20A to 20D according to the fifth exemplary form, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). Thereby, even when forming the single-layer modification line 70 (rough surface regions 20A to 20D), the SiC semiconductor wafer structure 61 can be appropriately cleaved.

[0304] FIG. 13E is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a sixth exemplary form of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 1, the same reference numerals are given and the description thereof is omitted.

[0305] The rough surface regions 20A to 20D according to the first exemplary embodiment are formed in a strip shape extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. On the other hand, the rough surface regions 20A to 20D according to the sixth exemplary embodiment are formed in a strip shape extending in a meandering (curved) shape toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2.

[0306] Also, in this embodiment, the rough surface regions 20A to 20D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The rough surface regions 20A to 20D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

[0307] Also, in this embodiment, rough surface regions 20A to 20D including one layer of modification lines 22A to 22D are formed. The modification lines 22A to 22D are formed one by one in a one-to-one correspondence relationship in the middle portion in the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D.

[0308] More specifically, the rough surface regions 20A to 20D each include a plurality of first regions 87, a plurality of second regions 88, and a plurality of connection regions 89. The plurality of first regions 87 are located in the region on the first main surface 3 side of the SiC semiconductor layer 2. The plurality of second regions 88 are located in the region on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the plurality of first regions 87. The plurality of curved regions 86 connect the corresponding first regions 87 and second regions 88, respectively.

[0309] The rough surface region 20A and the rough surface region 20B may be connected to each other at the corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2, or may be formed at intervals from each other.

[0310] The rough surface region 20B and the rough surface region 20C may be connected to each other at the corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2, or may be formed at intervals from each other.

[0311] The rough surface regions 20C and 20D may be connected to each other at the corners connecting the side surfaces 5C and 5D in the SiC semiconductor layer 2, or may be formed with a space therebetween.

[0312] The rough surface regions 20D and 20A may be connected to each other at the corners connecting the side surfaces 5D and 5A in the SiC semiconductor layer 2, or may be formed with a space therebetween.

[0313] In this form, the smooth surface regions 21A to 21D are formed not only in the regions on the first main surface 3 side but also in the regions on the second main surface 4 side on the side surfaces 5A to 5D. The smooth surface regions 21A to 21D on the second main surface 4 side are formed from the second main surface 4 to the middle portion in the thickness direction of the SiC semiconductor layer 2. The smooth surface regions 21A to 21D on the second main surface 4 side are formed on the SiC semiconductor substrate 6.

[0314] The meandering periods of the rough surface regions 20A to 20D are arbitrary. The rough surface regions 20A to 20D may each be formed in a strip shape extending in a concave curved shape from the first main surface 3 toward the second main surface 4. In this case, the rough surface regions 20A to 20D may each include two first regions 87, one second region 88, and two connection regions 89.

[0315] Alternatively, the rough surface regions 20A to 20D may each be formed in a strip shape extending in a convex curved shape from the second main surface 4 toward the first main surface 3. In this case, the rough surface regions 20A to 20D may each include one first region 87, two second regions 88, and two connection regions 89.

[0316] The rough surface regions 20A to 20D according to the sixth exemplary form are formed by adjusting the condensing portion (focus) of the laser beam or the like in the formation process of the modified line 70 (rough surface regions 20A to 20D) (see also FIG. 10K).

[0317] Even when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the sixth embodiment are formed, the same effects as those when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first and second embodiments are formed can be achieved.

[0318] In particular, according to the modified line 70 that is the basis of the rough surface regions 20A to 20D according to the sixth embodiment, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). Thereby, even when forming the single-layer modified line 70 (rough surface regions 20A to 20D), the SiC semiconductor wafer structure 61 can be appropriately cleaved.

[0319] FIG. 13F is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a seventh embodiment of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 1, the same reference numerals are given and the description is omitted.

[0320] The rough surface regions 20A to 20D according to the first embodiment are formed in the same shape on the side surfaces 5A to 5D of the SiC semiconductor layer 2. In contrast, the rough surface regions 20A to 20D according to the seventh embodiment are formed at different occupation ratios RA, RB, RC, and RD on the side surfaces 5A to 5D of the SiC semiconductor layer 2. The occupation ratios RA to RD are the ratios of the rough surface regions 20A to 20D occupying the side surfaces 5A to 5D.

[0321] Also, in this embodiment, the rough surface regions 20A to 20D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The rough surface regions 20A to 20D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

[0322] Also, in this form, rough surface regions 20A and 20C including two layers of modified lines 22A and 22C are formed, and rough surface regions 20B and 20D including one layer of modified lines 22B and 22D are formed. The modified lines 22A to 22D may be formed one by one in a one-to-one correspondence in the middle of the thickness direction of the SiC semiconductor layer 2 on the side surfaces 5A to 5D.

[0323] The exclusive ratios RA to RD are more specifically different depending on the crystal plane of the SiC single crystal. The exclusive ratios RB and RD of the rough surface regions 20B and 20D formed on the m-plane of the SiC single crystal are less than or equal to the exclusive ratios RA and RC of the rough surface regions 20A and 20C formed on the a-plane of the SiC single crystal (RB, RD ≤ RA, RC). More specifically, the exclusive ratios RB and RD are less than the exclusive ratios RA and RC (RB, RD < RA, RC).

[0324] The exclusive ratios RA and RC of the rough surface regions 20A and 20C may be equal to each other or different from each other. The exclusive ratios RB and RD of the rough surface regions 20B and 20D may be equal to each other or different from each other.

[0325] In this form, the surface areas of the rough surface regions 20B and 20D with respect to the side surfaces 5B and 5D are each less than the surface areas of the rough surface regions 20A and 20C with respect to the side surfaces 5A and 5C. In this form, the thicknesses TR of the rough surface regions 20B and 20D are each less than the thicknesses TR of the rough surface regions 20A and 20C.

[0326] In this form, the smooth surface regions 21A to 21D are formed not only in the regions on the first main surface 3 side but also in the regions on the second main surface 4 side on the side surfaces 5A to 5D. The smooth surface regions 21A to 21D on the second main surface 4 side are formed from the second main surface 4 to the middle of the thickness direction of the SiC semiconductor layer 2. The smooth surface regions 21A to 21D on the second main surface 4 side are formed on the SiC semiconductor substrate 6.

[0327] The rough surface regions 20A to 20D according to the seventh exemplary form are formed by adjusting the condensing part (focus) of the laser beam and the like in the formation process of the modified line 70 (rough surface regions 20A to 20D) (see also FIG. 10K).

[0328] Even when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the seventh embodiment are formed, the same effects as those when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first embodiment and the second embodiment are formed can be achieved.

[0329] In particular, the rough surface regions 20A to 20D according to the seventh embodiment are respectively formed at different occupation ratios RA to RD on the side surfaces 5A to 5D of the SiC semiconductor layer 2. More specifically, the rough surface regions 20A to 20D have different occupation ratios RA to RD according to the crystal planes of the SiC single crystal.

[0330] The occupation ratios RB and RD of the rough surface regions 20B and 20D formed on the m-plane of the SiC single crystal are less than or equal to the occupation ratios RA and RC of the rough surface regions 20A and 20C formed on the a-plane of the SiC single crystal (RB, RD ≤ RA, RC).

[0331] The SiC single crystal has a physical property that it is easily cracked along the nearest neighbor atom direction (also refer to FIGS. 1 and 2 together) in a plan view of the c-plane (silicon plane) from the c-axis, and is difficult to crack along the intersection direction of the nearest neighbor atom directions. The nearest neighbor atom direction is the a-axis direction and its equivalent directions. The intersection direction of the nearest neighbor atom directions is the m-axis direction and its equivalent directions.

[0332] Therefore, in the formation process of the modified line 70 (rough surface regions 20A to 20D), since the crystal planes along the nearest neighbor atom direction of the SiC single crystal have a relatively easy cracking property, the SiC single crystal can be appropriately cut (cleaved) without forming a modified line 70 (rough surface regions 20A to 20D) having a relatively large occupation ratio (also refer to FIG. 10L together). The crystal planes along the nearest neighbor atom direction are the m-plane and its equivalent planes.

[0333] That is, in the step of forming the modified lines 70 (rough surface regions 20A to 20D), the exclusive ratio of the modified lines 70 (rough surface regions 20A to 20D) along the second planned cutting line 55 extending in the a-axis direction can be made smaller than the exclusive ratio of the modified lines 70 (rough surface regions 20A to 20D) along the first planned cutting line 54 extending in the m-axis direction.

[0334] On the other hand, modified lines 70 having a relatively large exclusive ratio are formed on the crystal planes along the intersection direction of the nearest neighbor atomic directions of the SiC single crystal. As a result, inappropriate cutting (cleavage) of the SiC semiconductor wafer structure 61 can be suppressed, and thus the generation of cracks due to the physical properties of the SiC single crystal can be appropriately suppressed. The crystal planes along the intersection direction of the nearest neighbor atomic directions are the a-plane and its equivalent planes.

[0335] As described above, according to the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the seventh exemplary form, the exclusive ratios RA to RD of the rough surface regions 20A to 20D with respect to the side surfaces 5A to 5D can be adjusted and reduced by utilizing the physical properties of the SiC single crystal.

[0336] In other words, the exclusive ratios of the smooth surface regions 21A to 21D with respect to the side surfaces 5A to 5D can be increased by utilizing the physical properties of the SiC single crystal. As a result, a short circuit caused by the wetting spread of the conductive bonding material 80 can be appropriately suppressed. Also, the time required for the step of forming the modified lines 70 can be shortened.

[0337] The exclusive ratios RA to RD may be adjusted by the surface area of the rough surface regions 20A to 20D with respect to the side surfaces 5A to 5D. The exclusive ratios RA to RD may be adjusted by the thickness TR of the rough surface regions 20A to 20D. The exclusive ratios RA to RD may be adjusted by the number of the modified lines 22A to 22D included in the rough surface regions 20A to 20D.

[0338] FIG. 13G is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing an eighth exemplary form of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D. Hereinafter, for the structure corresponding to the structure described for the SiC semiconductor device 1, the same reference numerals are given and the description thereof is omitted.

[0339] In the first exemplary form, the rough surface regions 20A to 20D are formed in the regions on the second main surface 4 side of the SiC semiconductor layer 2 on the side surfaces 5A to 5D, and the smooth surface regions 21A to 21D are formed in the regions on the first main surface 3 side of the SiC semiconductor layer 2 on the side surfaces 5A to 5D.

[0340] On the other hand, in the eighth exemplary form, the rough surface regions 20A to 20D are formed in the regions on the first main surface 3 side of the SiC semiconductor layer 2 on the side surfaces 5A to 5D, and the smooth surface regions 21A to 21D are formed in the regions on the second main surface 4 side of the SiC semiconductor layer 2 on the side surfaces 5A to 5D. In this form, the rough surface regions 20A to 20D including the two-layer modified lines 22A to 22D are formed.

[0341] More specifically, the rough surface regions 20A to 20D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2 on the side surfaces 5A to 5D. The rough surface regions 20A to 20D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

[0342] In this form, the rough surface regions 20A to 20D are formed in the SiC epitaxial layer 7. More specifically, the rough surface regions 20A to 20D are formed in both the SiC epitaxial layer 7 and the SiC semiconductor substrate 6 across the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7.

[0343] The smooth surface regions 21A to 21D are formed from the second main surface 4 to the middle portion in the thickness direction of the SiC semiconductor layer 2. In the regions on the second main surface 4 side of the side surfaces 5A to 5D, the smooth surface regions 21A to 21D are formed in the SiC semiconductor substrate 6.

[0344] In this form, the first main surface 3 of the SiC semiconductor layer 2 is formed as a mounting surface, and the second main surface 4 of the SiC semiconductor layer 2 is formed as a non-mounting surface. That is, the SiC semiconductor layer 2 is face-down mounted on the object to be connected with the first main surface 3 facing it.

[0345] The rough surface regions 20A to 20D according to the eighth exemplary form are formed by adjusting the condensing part (focus) of the laser beam or the like in the forming process of the reforming line 70 (rough surface regions 20A to 20D) (see also Fig. 10K).

[0346] As described above, when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the eighth exemplary form are formed, it is possible to suppress the wetting spread of the conductive bonding material 80 from the first main surface 3 side toward the second main surface 4 side. Therefore, the same effects as those when the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary form are formed can be achieved.

[0347] A SiC semiconductor device 1 may be formed that simultaneously includes at least two of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the first exemplary form, the second exemplary form, the third exemplary form, the fourth exemplary form, the fifth exemplary form, the sixth exemplary form, the seventh exemplary form, and the eighth exemplary form (hereinafter simply referred to as "the first to eighth exemplary forms").

[0348] Further, the features of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the first to eighth exemplary forms can be combined in any manner and in any form. That is, rough surface regions 20A to 20D (smooth surface regions 21A to 21D) having a form in which at least two features of the features of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the first to eighth exemplary forms are combined may be adopted.

[0349] In the second to seventh exemplary embodiments, the smooth surface regions 21A to 21D are formed in the regions on the side surfaces 5A to 5D closer to the second main surface 4. Therefore, the SiC semiconductor device 1 shown in the second to seventh exemplary embodiments may be face-down mounted on the object to be connected with the SiC semiconductor layer 2 facing the first main surface 3, as in the eighth exemplary embodiment. That is, in the second to seventh exemplary embodiments, the first main surface 3 of the SiC semiconductor layer 2 may be the mounting surface, and the second main surface 4 may be the non-mounting surface.

[0350] Further, the features of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the fourth exemplary embodiment may be combined with the features of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the sixth exemplary embodiment. In this case, strip-shaped rough surface regions 20A to 20D are formed that slope downward from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2 and meander in a curved shape (curved shape) toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2.

[0351] FIG. 14 is a perspective view showing an SiC semiconductor device 91 according to the second embodiment of the present invention, and is a perspective view showing a structure to which the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary embodiment are applied. Hereinafter, the structures corresponding to the structures described for the SiC semiconductor device 1 will be denoted by the same reference numerals and the description thereof will be omitted.

[0352] In this embodiment, the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary embodiment are applied. However, instead of or in addition to the rough surface regions 20A to 20D according to the first exemplary embodiment, the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the second exemplary embodiment, the third exemplary embodiment, the fourth exemplary embodiment, the fifth exemplary embodiment, the sixth exemplary embodiment, the seventh exemplary embodiment, or the eighth exemplary embodiment may be adopted.

[0353] Further, rough surface regions 20A to 20D (smooth surface regions 21A to 21D) having a form in which at least two features among the features of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the first to eighth exemplary embodiments are combined may be adopted.

[0354] Referring to FIG. 14, in this embodiment, the insulating side surfaces 11A to 11D of the main surface insulating layer 10 are formed at intervals from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in an inner region in a plan view. The main surface insulating layer 10 exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 in a plan view.

[0355] The main surface insulating layer 10, together with the resin layer 16 and the passivation layer 13, exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D of the main surface insulating layer 10 are flush with the resin side surfaces 17A to 17D of the resin layer 16 and the side surfaces 14A to 14D of the passivation layer 13 in this embodiment. In this embodiment, the insulating side surfaces 11A to 11D of the main surface insulating layer 10 also become the portions partitioning the dicing street.

[0356] This main surface insulating layer 10 is formed by performing a step of removing the main surface insulating layer 10 by an etching method after the step of removing the passivation layer 13 in the step of FIG. 10I described above.

[0357] In this case, in the step of FIG. 10K described above, laser light may be directly irradiated into the SiC semiconductor wafer structure 61 from the side of the first main surface 62 of the SiC semiconductor wafer structure 61 without passing through the main surface insulating layer 10.

[0358] As described above, the SiC semiconductor device 91 can also achieve the same effects as those described for the SiC semiconductor device 1. However, in terms of enhancing the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12, the structure of the SiC semiconductor device 1 according to the first embodiment is preferable.

[0359] FIG. 15 is a perspective view of the SiC semiconductor device 101 according to the third embodiment of the present invention, showing a structure to which the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary form are applied. FIG. 16 is a perspective view of the SiC semiconductor device 101 shown in FIG. 15 as viewed from another angle. FIG. 17 is a plan view of the SiC semiconductor device 101 shown in FIG. 15. FIG. 18 is a plan view obtained by removing the resin layer 129 from FIG. 17.

[0360] In this embodiment, the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first exemplary form are applied. That is, in the manufacturing process of the SiC semiconductor device 101, the same processes as those in FIGS. 10A to 10M described above are applied.

[0361] In the SiC semiconductor device 101, instead of or in addition to the rough surface regions 20A to 20D according to the first exemplary form, the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the second exemplary form, the third exemplary form, the fourth exemplary form, the fifth exemplary form, the sixth exemplary form, the seventh exemplary form, or the eighth exemplary form may be adopted.

[0362] Further, the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) having a form in which at least two characteristics of the characteristics of the rough surface regions 20A to 20D (smooth surface regions 21A to 21D) according to the first to eighth exemplary forms are combined may be adopted.

[0363] Referring to FIGS. 15 to 18, the SiC semiconductor device 101 includes a SiC semiconductor layer 102. The SiC semiconductor layer 102 includes a 4H-SiC single crystal as an example of a hexagonal SiC single crystal. The SiC semiconductor layer 102 is formed in a rectangular parallelepiped chip shape.

[0364] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (a rectangular shape in this form) in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal direction Z.

[0365] The first main surface 103 is an element formation surface on which a semiconductor element is formed. The second main surface 104 of the SiC semiconductor layer 102 is a ground surface having grinding marks. The side surfaces 105A to 105D are cleavage surfaces each facing a crystal plane of the SiC single crystal. The side surfaces 105A to 105D do not have grinding marks.

[0366] The thickness TL of the SiC semiconductor layer 102 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

[0367] In this form, the first main surface 103 and the second main surface 104 face the c-plane of the SiC single crystal. The first main surface 103 faces the (0001) plane (silicon plane). The second main surface 104 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0368] The first main surface 103 and the second main surface 104 have an off-angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0369] The off-angle θ may be 0° or more and 5.0° or less. The off-angle θ may be set within an angular range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. The off-angle θ preferably exceeds 0°. The off-angle θ may be less than 4.0°.

[0370] The off-angle θ may be set within an angular range of 3.0° or more and 4.5° or less. In this case, the off-angle θ is preferably set within an angular range of 3.0° or more and 3.5° or less, or 3.5° or more and 4.0° or less.

[0371] The off-angle θ may be set within an angular range of 1.5° or more and 3.0° or less. In this case, the off-angle θ is preferably set within an angular range of 1.5° or more and 2.0° or less, or 2.0° or more and 2.5° or less.

[0372] The lengths of the side surfaces 105A to 105D may each be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). In this form, the surface areas of the side surfaces 105B and 105D exceed the surface areas of the side surfaces 105A and 105C. The first main surface 103 and the second main surface 104 may be formed in a square shape in plan view. In this case, the surface areas of the side surfaces 105A and 105C are equal to those of the side surfaces 105B and 105D.

[0373] In this form, the side surfaces 105A and 105C extend along the first direction X and face each other in the second direction Y that intersects the first direction X. The side surfaces 105B and 105D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is a direction orthogonal to the first direction X.

[0374] In this embodiment, the first direction X is set in the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set in the a-axis direction ([11-20] direction) of the SiC single crystal.

[0375] The side surfaces 105A and 105C form the short sides of the SiC semiconductor layer 102 in plan view. The side surfaces 105A and 105C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. The side surface 105A is formed by the (-1-120) plane of the SiC single crystal. The side surface 105C is formed by the (11-20) plane of the SiC single crystal.

[0376] The side surfaces 105B and 105D form the long sides of the SiC semiconductor layer 102 in plan view. The side surfaces 105B and 105D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. The side surface 105B is formed by the (-1100) plane of the SiC single crystal. The side surface 105D is formed by the (1-100) plane of the SiC single crystal.

[0377] The side surfaces 105A and 105C may form inclined surfaces that are inclined in the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal of the first main surface 103 of the SiC semiconductor layer 102 when the normal of the first main surface 103 of the SiC semiconductor layer 102 is used as a reference.

[0378] In this case, when the normal of the first main surface 103 of the SiC semiconductor layer 102 is set to 0°, the side surfaces 105A and 105C may be inclined at an angle corresponding to the off-angle θ with respect to the normal of the first main surface 103 of the SiC semiconductor layer 102. The angle corresponding to the off-angle θ may be equal to the off-angle θ or may be an angle greater than 0° and less than the off-angle θ.

[0379] In this embodiment, the SiC semiconductor layer 102 is n +It has a stacked structure including a p-type SiC semiconductor substrate 106 and an n-type SiC epitaxial layer 107. The SiC semiconductor substrate 106 and the SiC epitaxial layer 107 respectively correspond to the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 according to the first embodiment. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 106.

[0380] The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 107. The side surfaces 105A to 105D of the SiC semiconductor layer 102 are formed by the SiC semiconductor substrate 106 and the SiC epitaxial layer 107.

[0381] The thickness TS of the SiC semiconductor substrate 106 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. It is preferable that the thickness TS is 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 106, it is possible to reduce the resistance value due to shortening of the current path.

[0382] The thickness TE of the SiC epitaxial layer 107 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. It is preferable that the thickness TE is 5 μm or more and 15 μm or less.

[0383] The n-type impurity concentration of the SiC epitaxial layer 107 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 106. More specifically, the n-type impurity concentration of the SiC epitaxial layer 107 is less than the n-type impurity concentration of the SiC semiconductor substrate 106. The n-type impurity concentration of the SiC semiconductor substrate 106 is 1.0×10 18 cm -3 or more and may be 1.0×10 21 cm -3 or less. The n-type impurity concentration of the SiC epitaxial layer 107 is 1.0×10 15 cm -3 or more and may be 1.0×10 18 cm -3 or less.

[0384] In this form, the SiC epitaxial layer 107 has a plurality of regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 107 includes a high-concentration region 108 having a relatively high n-type impurity concentration and a low-concentration region 109 having a lower n-type impurity concentration than the high-concentration region 108.

[0385] The high-concentration region 108 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102. The low-concentration region 109 is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the high-concentration region 108.

[0386] The n-type impurity concentration of the high-concentration region 108 is 1×10 16 cm -3 or more and may be 1×10 18 cm -3 or less. The n-type impurity concentration of the low-concentration region 109 is 1×10 15 cm -3 or more and may be 1×10 16 cm -3 or less.

[0387] The thickness of the high-concentration region 108 is equal to or less than the thickness of the low-concentration region 109. More specifically, the thickness of the high-concentration region 108 is less than the thickness of the low-concentration region 109. The thickness of the high-concentration region 108 is less than half of the total thickness of the SiC epitaxial layer 107.

[0388] In the SiC semiconductor layer 102, an active region 111 and an outer region 112 are set. The active region 111 is a region where a vertical MISFET (Metal Insulator Field Effect Transistor), which is an example of a semiconductor element, is formed. The outer region 112 is a region outside the active region 111.

[0389] The active region 111 is set at the central portion of the SiC semiconductor layer 102 with a space from the side surfaces 105A to 105D of the SiC semiconductor layer 102 in the inward region in a plan view. The active region 111 is set in a rectangular shape (a rectangular shape in this form) having four sides parallel to the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0390] The outer region 112 is set in a region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 111. The outer region 112 is set in an endless shape (a square ring shape in this form) surrounding the active region 111 in a plan view.

[0391] On the first main surface 103 of the SiC semiconductor layer 102, a main surface insulating layer 113 is formed. The main surface insulating layer 113 selectively covers the active region 111 and the outer region 112. The main surface insulating layer 113 may contain silicon oxide (SiO2).

[0392] The main surface insulating layer 113 has insulating side surfaces 114A, 114B, 114C, 114D exposed from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The insulating side surfaces 114A to 114D are continuous with the side surfaces 105A to 105D. The insulating side surfaces 114A to 114D are formed flush with the side surfaces 105A to 105D, respectively. The insulating side surfaces 114A to 114D are composed of cleavage surfaces.

[0393] The thickness of the main surface insulating layer 113 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 113 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0394] On the main surface insulating layer 113, a main surface gate electrode layer 115 as one of the first main surface electrode layers is formed. The main surface gate electrode layer 115 penetrates the main surface insulating layer 113 and is electrically connected to an arbitrary region of the SiC semiconductor layer 102.

[0395] The main surface gate electrode layer 115 includes a gate pad 116 and gate fingers 117, 118. The gate pad 116 and the gate fingers 117, 118 are disposed in the active region 111.

[0396] The gate pad 116 is formed along the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 116 is formed along the central region of the side surface 105A of the SiC semiconductor layer 102 in a plan view.

[0397] The gate pad 116 may be formed along a corner connecting any two of the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. The gate pad 116 may be formed in a rectangular shape in a plan view.

[0398] The gate fingers 117, 118 include an outer gate finger 117 and an inner gate finger 118. The outer gate finger 117 is drawn out from the gate pad 116 and extends in a strip shape along the periphery of the active region 111.

[0399] In this form, the outer gate finger 117 is formed along three side surfaces 105A, 105B, 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

[0400] The outer gate finger 117 has a pair of open ends 119, 120. The pair of open ends 119, 120 are formed in a region facing the gate pad 116 across the inner region of the active region 111. In this form, the pair of open ends 119, 120 are formed along the side surface 105C of the SiC semiconductor layer 102.

[0401] The inner gate finger 118 is drawn out from the gate pad 116 to the inner region of the active region 111. The inner gate finger 118 extends in a strip shape in the inner region of the active region 111. The inner gate finger 118 extends from the gate pad 116 toward the side surface 105C.

[0402] On the main surface insulating layer 113, a main surface source electrode layer 121 as one of the first main surface electrode layers is further formed. The main surface source electrode layer 121 penetrates the main surface insulating layer 113 and is electrically connected to an arbitrary region of the SiC semiconductor layer 102. In this form, the main surface source electrode layer 121 includes a source pad 122, a source routing wiring 123, and a source connection portion 124.

[0403] The source pad 122 is formed in the active region 111 at a distance from the gate pad 116 and the gate fingers 117, 118. The source pad 122 is formed in a C shape (an inverted C shape in FIGS. 17 and 18) in plan view so as to cover a C-shaped (an inverted C shape in FIGS. 17 and 18) region defined by the gate pad 116 and the gate fingers 117, 118.

[0404] The source routing wiring 123 is formed in the outer region 112. The source routing wiring 123 extends in a strip shape along the active region 111. In this form, the source routing wiring 123 is formed in an endless shape (a square ring shape in this form) surrounding the active region 111 in plan view. The source routing wiring 123 is electrically connected to the SiC semiconductor layer 102 in the outer region 112.

[0405] The source connection portion 124 connects the source pad 122 and the source routing wiring 123. The source connection portion 124 is provided in a region between a pair of open end portions 119 and 120 of the outer gate fingers 117. The source connection portion 124 crosses a boundary region between the active region 111 and the outer region 112 from the source pad 122 and is connected to the source routing wiring 123.

[0406] The MISFET formed in the active region 111 includes an npn-type parasitic bipolar transistor due to its structure. When an avalanche current generated in the outer region 112 flows into the active region 111, the parasitic bipolar transistor is turned on. In this case, for example, due to latch-up, the control of the MISFET may become unstable.

[0407] Therefore, in the SiC semiconductor device 101, an avalanche current absorption structure for absorbing the avalanche current generated in the outer region 112 is formed by utilizing the structure of the main surface source electrode layer 121.

[0408] More specifically, the avalanche current generated in the outer region 112 is absorbed by the source routing wiring 123 and reaches the source pad 122 through the source connection portion 124. When a conductor for external connection (for example, a bonding wire) is connected to the source pad 122, the avalanche current is taken out by this conductor.

[0409] Thereby, it is possible to suppress the parasitic bipolar transistor from being turned on by an undesired current generated in the outer region 112. Therefore, latch-up can be suppressed, and the stability of the control of the MISFET can be enhanced.

[0410] A gate voltage is applied to the main surface gate electrode layer 115. The gate voltage may be 10V or more and 50V or less (for example, about 30V). A source voltage is applied to the main surface source electrode layer 121. The source voltage may be a reference voltage (for example, GND voltage).

[0411] On the main surface insulating layer 113, a passivation layer 125 (insulating layer) is formed. The passivation layer 125 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer.

[0412] The passivation layer 125 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this form, the passivation layer 125 has a single-layer structure composed of a silicon nitride layer.

[0413] The side surfaces 126A, 126B, 126C, and 126D of the passivation layer 125 are formed at intervals from the side surfaces 105A to 105D of the SiC semiconductor layer 102 in an inner region in a plan view. The passivation layer 125 exposes the peripheral portion of the SiC semiconductor layer 102 in a plan view. The passivation layer 125 exposes the main surface insulating layer 113.

[0414] The passivation layer 125 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. Gate sub-pad openings 127 and source sub-pad openings 128 are formed in the passivation layer 125. The gate sub-pad opening 127 exposes the gate pad 116. The source sub-pad opening 128 exposes the source pad 122.

[0415] The thickness of the passivation layer 125 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 125 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0416] On the passivation layer 125, a resin layer 129 (insulating layer) is formed. The passivation layer 125 and the resin layer 129 form a single insulating laminated structure (insulating layer). In FIG. 17, the resin layer 129 is indicated by hatching.

[0417] The resin layer 129 may contain a negative-type or positive-type photosensitive resin. In this form, the resin layer 129 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 129 may contain polyimide as an example of a negative-type photosensitive resin.

[0418] The resin layer 129 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. The resin side surfaces 130A, 130B, 130C, 130D of the resin layer 129 are formed at intervals from the side surfaces 105A to 105D of the SiC semiconductor layer 102 into the inner region. The resin layer 129 exposes the main surface insulating layer 113 together with the passivation layer 125. In this form, the resin side surfaces 130A to 130D of the resin layer 129 are formed flush with the side surfaces 126A to 126D of the passivation layer 125.

[0419] The resin side surfaces 130A to 130D of the resin layer 129 are the portions that partitioned the dicing street when cutting out the SiC semiconductor device 101 from a single SiC semiconductor wafer. In this form, the side surfaces 126A to 126D of the passivation layer 125 are also the portions that partitioned the dicing street.

[0420] By exposing the peripheral portion of the SiC semiconductor layer 102 from the resin layer 129 and the passivation layer 125, it becomes unnecessary to physically cut the resin layer 129 and the passivation layer 125. As a result, the SiC semiconductor device 101 can be smoothly cut out from a single SiC semiconductor wafer. Also, the insulating distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 can be increased.

[0421] The distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Of course, the side surfaces 126A to 126D of the passivation layer 125 may be formed flush with the side surfaces 105A to 105D of the SiC semiconductor layer 102.

[0422] The gate pad opening 131 and the source pad opening 132 are formed in the resin layer 129. The gate pad opening 131 exposes the gate pad 116. The source pad opening 132 exposes the source pad 122.

[0423] The gate pad opening 131 of the resin layer 129 communicates with the gate sub-pad opening 127 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the gate sub-pad opening 127. The inner wall of the gate pad opening 131 may be located inside the inner wall of the gate sub-pad opening 127. The resin layer 129 may cover the inner wall of the gate sub-pad opening 127.

[0424] The source pad opening 132 of the resin layer 129 communicates with the source sub-pad opening 128 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the source sub-pad opening 128. The inner wall of the source pad opening 132 may be located inside the inner wall of the source sub-pad opening 128. The resin layer 129 may cover the inner wall of the source sub-pad opening 128.

[0425] The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 129 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0426] On the second main surface 104 of the SiC semiconductor layer 102, a drain electrode layer 133 as a second main surface electrode layer is connected. The maximum voltage that can be applied between the main surface source electrode layer 121 and the drain electrode layer 133 during the off state may be 1000V or more and 10000V or less.

[0427] The drain electrode layer 133 may contain at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode layer 133 may have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer.

[0428] The drain electrode layer 133 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in an arbitrary manner. The drain electrode layer 133 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in this order from the second main surface 104 of the SiC semiconductor layer 102.

[0429] The SiC semiconductor substrate 106 is formed as a drain region 134 of the MISFET. The SiC epitaxial layer 107 is formed as a drift region 135 of the MISFET.

[0430] On the side surfaces 105A to 105D of the SiC semiconductor layer 102, rough surface regions 20A to 20D and smooth surface regions 21A to 21D according to the first exemplary embodiment are formed. The structures of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the third embodiment are the same as the structures of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first embodiment, except that they are formed on the SiC semiconductor layer 102 instead of the SiC semiconductor layer 2.

[0431] The descriptions of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the first embodiment shall apply mutatis mutandis to the descriptions of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the third embodiment, and the specific descriptions of the rough surface regions 20A to 20D and the smooth surface regions 21A to 21D according to the third embodiment are omitted.

[0432] FIG. 19 is an enlarged view of the region XIX shown in FIG. 18, and is a diagram for explaining the structure of the first main surface 103 of the SiC semiconductor layer 102. FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. 19. FIG. 21 is a cross-sectional view taken along the line XXI-XXI shown in FIG. 19. FIG. 22 is an enlarged view of the region XXII shown in FIG. 20. FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII shown in FIG. 18. FIG. 24 is an enlarged view of the region XXIV shown in FIG. 23.

[0433] Referring to FIGS. 19 to 23, in the active region 111, a p-type body region 141 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The body region 141 defines the active region 111.

[0434] In this embodiment, the body region 141 is formed over the entire region of the first main surface 103 of the SiC semiconductor layer 102 where the active region 111 is formed. The p-type impurity concentration of the body region 141 may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0435] In the active region 111, a plurality of gate trenches 142 are formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 142 are each formed in a strip shape extending along the first direction X (the m-axis direction of the SiC single crystal) in a plan view, and are formed at intervals along the second direction Y (the a-axis direction of the SiC single crystal).

[0436] In this form, each gate trench 142 extends from the peripheral edge on one side (side 105B side) to the peripheral edge on the other side (side 105D side) in the active region 111. The plurality of gate trenches 142 are formed in a stripe shape as a whole in a plan view.

[0437] Each gate trench 142 crosses the middle part between the peripheral edge on one side and the peripheral edge on the other side in the active region 111. One end of each gate trench 142 is located at the peripheral edge on one side in the active region 111. The other end of each gate trench 142 is located at the peripheral edge on the other side in the active region 111.

[0438] The length of each gate trench 142 may be 0.5 mm or more. The length of each gate trench 142 is the length from the end on the connection part side of each gate trench 142 and the outer gate finger 117 to the opposite end in the cross section shown in FIG. 21.

[0439] In this form, the length of each gate trench 142 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total extension of one or more gate trenches 142 per unit area is 2 0.5 μm / μm or more 2 and 0.75 μm / μm or less.

[0440] Each gate trench 142 integrally includes an active trench portion 143 and a contact trench portion 144. The active trench portion 143 is a portion along the channel of the MISFET in the active region 111.

[0441] The contact trench portion 144 is mainly a portion for the purpose of making contact with the outer gate fingers 117 in the gate trench 142. The contact trench portion 144 is drawn out from the active trench portion 143 to the peripheral portion of the active region 111. The contact trench portion 144 is formed in the region directly below the outer gate fingers 117. The amount of drawout of the contact trench portion 144 is arbitrary.

[0442] Each gate trench 142 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each gate trench 142 includes side walls and a bottom wall. The side walls forming the long sides of each gate trench 142 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of each gate trench 142 are formed by the m-plane of the SiC single crystal.

[0443] The side walls of each gate trench 142 may extend along the normal direction Z. The side walls of each gate trench 142 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

[0444] The angle formed by the side walls of each gate trench 142 with respect to the first main surface 103 of the SiC semiconductor layer 102 within the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each gate trench 142 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

[0445] The bottom wall of each gate trench 142 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each gate trench 142 is located in the high-concentration region 108 of the SiC epitaxial layer 107.

[0446] The bottom wall of each gate trench 142 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 142 has an off-angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0447] The bottom wall of each gate trench 142 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each gate trench 142 may be formed in a convexly curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

[0448] In the normal direction Z, the depth of each gate trench 142 may be 0.5 μm or more and 3.0 μm or less. The depth of each gate trench 142 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, or 2.5 μm or more and 3.0 μm or less.

[0449] The width of each gate trench 142 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 142 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0450] Referring to FIG. 22, the opening edge portion 146 of each gate trench 142 includes an inclined portion 147 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each gate trench 142. The opening edge portion 146 of each gate trench 142 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the side wall of each gate trench 142.

[0451] In this form, the inclined portion 147 is formed in a concavely curved shape toward the inside of the SiC semiconductor layer 102. The inclined portion 147 may be formed in a convexly curved shape toward the inside of each gate trench 142. The inclined portion 147 alleviates the electric field concentration with respect to the opening edge portion 146 of each gate trench 142.

[0452] A gate insulating layer 148 and a gate electrode layer 149 are formed in each gate trench 142. In FIG. 19, the gate insulating layer 148 and the gate electrode layer 149 are indicated by hatching.

[0453] The gate insulating layer 148 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), or tantalum oxide (Ta2O3).

[0454] The gate insulating layer 148 may have a stacked structure including an SiN layer and an SiO2 layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a stacked structure including an SiO2 layer and an SiN layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a single-layer structure composed of an SiO2 layer or an SiN layer. In this form, the gate insulating layer 148 has a single-layer structure composed of an SiO2 layer.

[0455] The gate insulating layer 148 is formed in a film shape along the inner wall surface of the gate trench 142 so that a concave space is defined within the gate trench 142. The gate insulating layer 148 includes a first region 148a, a second region 148b, and a third region 148c.

[0456] The first region 148a is formed along the side wall of the gate trench 142. The second region 148b is formed along the bottom wall of the gate trench 142. The third region 148c is formed along the first main surface 103 of the SiC semiconductor layer 102. The third region 148c of the gate insulating layer 148 forms a part of the main surface insulating layer 113.

[0457] The thickness Ta of the first region 148a is smaller than the thickness Tb of the second region 148b and the thickness Tc of the third region 148c. The ratio Tb / Ta of the thickness Tb of the second region 148b to the thickness Ta of the first region 148a may be 2 or more and 5 or less. The ratio T3 / Ta of the thickness Tc of the third region 148c to the thickness Ta of the first region 148a may be 2 or more and 5 or less.

[0458] The thickness Ta of the first region 148a may be 0.01 μm or more and 0.2 μm or less. The thickness Tb of the second region 148b may be 0.05 μm or more and 0.5 μm or less. The thickness Tc of the third region 148c may be 0.05 μm or more and 0.5 μm or less.

[0459] By thinning the first region 148a of the gate insulating layer 148, an increase in carriers induced in the region near the side wall of each gate trench 142 in the body region 141 can be suppressed. Thereby, an increase in channel resistance can be suppressed. By thickening the second region 148b of the gate insulating layer 148, the electric field concentration on the bottom wall of each gate trench 142 can be alleviated.

[0460] By thickening the third region 148c of the gate insulating layer 148, the breakdown voltage of the gate insulating layer 148 in the vicinity of the opening edge portion 146 of each gate trench 142 can be improved. Further, by thickening the third region 148c, disappearance of the third region 148c due to an etching method can be suppressed.

[0461] Thereby, disappearance of the first region 148a due to an etching method can be suppressed due to disappearance of the third region 148c. As a result, the gate electrode layer 149 can be appropriately opposed to the SiC semiconductor layer 102 (body region 141) with the gate insulating layer 148 interposed therebetween.

[0462] The gate insulating layer 148 further includes a bulging portion 148d that bulges toward the inside of each gate trench 142 at the opening edge portion 146 of each gate trench 142. The bulging portion 148d is formed at a corner connecting the first region 148a and the third region 148c of the gate insulating layer 148.

[0463] The bulging portion 148d protrudes in a convexly curved shape toward the inside of each gate trench 142. The bulging portion 148d narrows the opening of each gate trench 142 at the opening edge portion 146 of each gate trench 142.

[0464] The bulged portion 148d is provided to improve the breakdown voltage of the gate insulating layer 148 at the opening edge portion 146. Of course, a gate insulating layer 148 without the bulged portion 148d may be formed. Also, a gate insulating layer 148 having a uniform thickness may be formed.

[0465] The gate electrode layer 149 is embedded in each gate trench 142 with the gate insulating layer 148 interposed therebetween. More specifically, the gate electrode layer 149 is embedded in a concave space partitioned by the gate insulating layer 148 in each gate trench 142. The gate electrode layer 149 is controlled by a gate voltage.

[0466] The gate electrode layer 149 has an upper end portion located on the opening side of each gate trench 142. The upper end portion of the gate electrode layer 149 is formed in a concave curved shape that is recessed toward the bottom wall of each gate trench 142. The upper end portion of the gate electrode layer 149 has a constricted portion constricted along the bulged portion 148d of the gate insulating layer 148.

[0467] The cross-sectional area of the gate electrode layer 149 (the cross-sectional area orthogonal to the direction in which each gate trench 142 extends) may be 0.05μm 2 or more and 0.5μm 2 or less. The cross-sectional area of the gate electrode layer 149 is defined by the product of the depth of the gate electrode layer 149 and the width of the gate electrode layer 149.

[0468] The depth of the gate electrode layer 149 is the distance from the upper end portion to the lower end portion of the gate electrode layer 149. The width of the gate electrode layer 149 is the width of the gate trench 142 at an intermediate position between the upper end portion and the lower end portion of the gate electrode layer 149. When the upper end portion is a curved surface (concave curved shape in this form), the position of the upper end portion of the gate electrode layer 149 is set to the intermediate position in the depth direction on the upper surface of the gate electrode layer 149.

[0469] The gate electrode layer 149 contains p-type polysilicon doped with p-type impurities. The p-type impurities in the gate electrode layer 149 may contain at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0470] The p-type impurity concentration of the gate electrode layer 149 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the gate electrode layer 149 is greater than the p-type impurity concentration of the body region 141.

[0471] The p-type impurity concentration of the gate electrode layer 149 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the gate electrode layer 149 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form).

[0472] Referring to FIGS. 19 and 21, a gate wiring layer 150 is formed in the active region 111. The gate wiring layer 150 is electrically connected to the gate pad 116 and the gate fingers 117, 118. In FIG. 21, the gate wiring layer 150 is indicated by hatching.

[0473] The gate wiring layer 150 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 150 is formed on the third region 148c of the gate insulating layer 148.

[0474] In this form, the gate wiring layer 150 is formed along the outer gate finger 117. More specifically, the gate wiring layer 150 is formed along the three side surfaces 105A, 105B, 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

[0475] The gate wiring layer 150 is connected to the gate electrode layer 149 exposed from the contact trench portion 144 of each gate trench 142. In this form, the gate wiring layer 150 is formed by the drawn-out portion of the gate electrode layer 149 drawn out onto the first main surface 103 of the SiC semiconductor layer 102 from each gate trench 142. The upper end portion of the gate wiring layer 150 is connected to the upper end portion of the gate electrode layer 149.

[0476] Referring to FIGS. 19, 20, and 22, a plurality of source trenches 155 are formed in the first main surface 103 of the SiC semiconductor layer 102 in the active region 111. Each source trench 155 is formed in a region between two adjacent gate trenches 142.

[0477] The plurality of source trenches 155 are each formed in a strip shape extending along the first direction X (the m-axis direction of the SiC single crystal). The plurality of source trenches 155 are formed in a stripe shape as a whole in plan view. Regarding the second direction Y, the pitch between the central portions of adjacent source trenches 155 may be 1.5 μm or more and 3 μm or less.

[0478] Each source trench 155 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each source trench 155 includes side walls and a bottom wall. The side walls forming the long sides of each source trench 155 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of each source trench 155 are formed by the m-plane of the SiC single crystal.

[0479] The side walls of each source trench 155 may extend along the normal direction Z. The side walls of each source trench 155 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

[0480] In the SiC semiconductor layer 102, the angle formed by the side wall of each source trench 155 with respect to the first main surface 103 of the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each source trench 155 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

[0481] The bottom wall of each source trench 155 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in the high-concentration region 108 of the SiC epitaxial layer 107. Even more specifically, the bottom wall of each source trench 155 is located in the region between the bottom wall of each gate trench 142 and the low-concentration region 109.

[0482] The bottom wall of each source trench 155 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 155 has an off-angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0483] The bottom wall of each source trench 155 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each source trench 155 may be formed in a convexly curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

[0484] In this form, the depth of each source trench 155 is equal to or greater than the depth of each gate trench 142. More specifically, the depth of each source trench 155 is greater than the depth of each gate trench 142.

[0485] The bottom wall of each source trench 155 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. Of course, the depth of each source trench 155 may be equal to the depth of each gate trench 142.

[0486] In the normal direction Z, the depth of each source trench 155 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of each source trench 155 to the depth of each gate trench 142 may be 1.5 or more. The ratio of the depth of each source trench 155 to the depth of each gate trench 142 is preferably 2 or more.

[0487] The width of each source trench 155 in the first direction may be substantially equal to the width of each gate trench 142 in the first direction. The width of each source trench 155 in the first direction may be equal to or greater than the width of each gate trench 142 in the first direction. The width of each source trench 155 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm).

[0488] A source insulating layer 156 and a source electrode layer 157 are formed in each source trench 155. In FIG. 19, the source insulating layer 156 and the source electrode layer 157 are indicated by hatching.

[0489] The source insulating layer 156 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), or tantalum oxide (Ta2O3).

[0490] The source insulating layer 156 may have a laminated structure including an SiN layer and an SiO2 layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a laminated structure including an SiO2 layer and an SiN layer laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a single-layer structure composed of an SiO2 layer or an SiN layer. In this form, the source insulating layer 156 has a single-layer structure composed of an SiO2 layer.

[0491] The source insulating layer 156 is formed in a film shape along the inner wall surface of each source trench 155 so that a concave space is defined within each source trench 155. The source insulating layer 156 includes a first region 156a and a second region 156b.

[0492] The first region 156a is formed along the side wall of each source trench 155. The second region 156b is formed along the bottom wall of each source trench 155. The thickness Tsa of the first region 156a is smaller than the thickness Tsb of the second region 156b.

[0493] The ratio Tsb / Tsa of the thickness Tsb of the second region 156b to the thickness Tsa of the first region 156a may be 2 or more and 5 or less. The thickness Tsa of the first region 156a may be 0.01 μm or more and 0.2 μm or less. The thickness Tsb of the second region 156b may be 0.05 μm or more and 0.5 μm or less.

[0494] The thickness Tsa of the first region 156a may be substantially equal to the thickness Ta of the first region 156a of the gate insulating layer 148. The thickness Tsb of the second region 156b may be substantially equal to the thickness Tb of the second region 156b of the gate insulating layer 148. Of course, a source insulating layer 156 having a uniform thickness may be formed.

[0495] The source electrode layer 157 is embedded in each source trench 155 with the source insulating layer 156 interposed therebetween. More specifically, the source electrode layer 157 is embedded in the concave space defined by the source insulating layer 156 in each source trench 155. The source electrode layer 157 is controlled by a source voltage.

[0496] The source electrode layer 157 has an upper end portion located on the opening side of each source trench 155. The upper end portion of the source electrode layer 157 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end portion of the source electrode layer 157 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0497] The upper end portion of the source electrode layer 157 is formed in a concave curved shape that is recessed toward the bottom wall of each source trench 155. The upper end portion of the source electrode layer 157 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0498] The upper end portion of the source electrode layer 157 may protrude above the upper end portion of the source insulating layer 156. The upper end portion of the source electrode layer 157 may be located below the upper end portion of the source insulating layer 156. The thickness of the source electrode layer 157 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0499] The source electrode layer 157 preferably contains polysilicon having properties similar to those of SiC in terms of material. Thereby, the stress generated in the SiC semiconductor layer 102 can be reduced. In this form, the source electrode layer 157 contains p-type polysilicon doped with p-type impurities. In this case, the source electrode layer 157 can be formed simultaneously with the gate electrode layer 149.

[0500] The p-type impurity concentration of the source electrode layer 157 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the source electrode layer 157 is greater than the p-type impurity concentration of the body region 141. The p-type impurities in the source electrode layer 157 may contain at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0501] The p-type impurity concentration of the source electrode layer 157 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the source electrode layer 157 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form).

[0502] The p-type impurity concentration of the source electrode layer 157 may be approximately equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the source electrode layer 157 may be approximately equal to the sheet resistance of the gate electrode layer 149.

[0503] The source electrode layer 157 may contain n-type polysilicon instead of or in addition to p-type polysilicon. The source electrode layer 157 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

[0504] Thus, the SiC semiconductor device 101 has a plurality of trench gate structures 161 and a plurality of trench source structures 162. Each trench gate structure 161 includes a gate trench 142, a gate insulating layer 148, and a gate electrode layer 149. Each trench source structure 162 includes a source trench 155, a source insulating layer 156, and a source electrode layer 157.

[0505] In the surface layer portion of the body region 141, an n + type source region 163 is formed in a region along the sidewall of each gate trench 142. The n-type impurity concentration of the source region 163 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity of the source region 163 may be phosphorus (P).

[0506] A plurality of source regions 163 are formed along the sidewalls on one side and the other side of each gate trench 142. The plurality of source regions 163 are each formed in a strip shape extending along the first direction X.

[0507] The plurality of source regions 163 are formed in a stripe shape as a whole in a plan view. Each source region 163 is exposed from the sidewalls of each gate trench 142 and each source trench 155.

[0508] Thus, in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the region along the side wall of the gate trench 142, a source region 163, a body region 141, and a drift region 135 are formed in this order from the first main surface 103 to the second main surface 104 of the SiC semiconductor layer 102.

[0509] In the body region 141, in the region along the side wall of the gate trench 142, a channel of the MISFET is formed. The channel is formed in the region along the side wall facing the a-plane of the SiC single crystal in the gate trench 142. The ON / OFF of the channel is controlled by the gate electrode layer 149.

[0510] In the active region 111, in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102, a plurality of p + -type contact regions 164 are formed. Each contact region 164 is formed in the region between two adjacent gate trenches 142 in plan view. Each contact region 164 is formed in the region on the side opposite to the gate trench 142 with respect to each source region 163.

[0511] Each contact region 164 is formed along the inner wall of each source trench 155. In this form, a plurality of contact regions 164 are formed at intervals along the inner wall of each source trench 155. Each contact region 164 is formed at an interval from each gate trench 142.

[0512] The p-type impurity concentration of each contact region 164 is higher than the p-type impurity concentration of the body region 141. The p-type impurity concentration of each contact region 164 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The p-type impurity of each contact region 164 may be aluminum (Al).

[0513] Each contact region 164 covers the sidewalls and the bottom wall of each source trench 155. The bottom of each contact region 164 may be formed parallel to the bottom wall of each source trench 155. More specifically, each contact region 164 integrally includes a first surface layer region 164a, a second surface layer region 164b, and an inner wall region 164c.

[0514] The first surface layer region 164a covers the sidewall on one side of the source trench 155 in the surface layer portion of the body region 141. The first surface layer region 164a is electrically connected to the body region 141 and the source region 163.

[0515] The first surface layer region 164a is located in the region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163. In this form, the first surface layer region 164a has a bottom portion that extends parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0516] In this form, the bottom of the first surface layer region 164a is located in the region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of the first surface layer region 164a may be located in the region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the body region 141.

[0517] In this form, the first surface layer region 164a is drawn out from the source trench 155 toward the adjacent gate trench 142. The first surface layer region 164a may extend to the intermediate region between the gate trench 142 and the source trench 155. The first surface layer region 164a is formed at a distance from the gate trench 142 toward the source trench 155 side.

[0518] The second surface layer region 164b covers the sidewall on the other side of the source trench 155 in the surface layer portion of the body region 141. The second surface layer region 164b is electrically connected to the body region 141 and the source region 163.

[0519] The second surface layer region 164b is located in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163. In this form, the second surface layer region 164b has a bottom portion that extends parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0520] In this form, the bottom of the second surface layer region 164b is located in a region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of the second surface layer region 164b may be located in a region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the body region 141.

[0521] In this form, the second surface layer region 164b is drawn from the side wall on the other side of the source trench 155 toward the adjacent gate trench 142. The second surface layer region 164b may extend to an intermediate region between the source trench 155 and the gate trench 142. The second surface layer region 164b is formed at a distance from the gate trench 142 toward the source trench 155 side.

[0522] The inner wall region 164c is located in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the first surface layer region 164a and the second surface layer region 164b (the bottom of the source region 163). The inner wall region 164c is formed in a region along the inner wall of the source trench 155 in the SiC semiconductor layer 102. The inner wall region 164c covers the side wall of the source trench 155.

[0523] The inner wall region 164c covers a corner portion connecting the side wall and the bottom wall of the source trench 155. The inner wall region 164c covers the bottom wall of the source trench 155 from the side wall of the source trench 155 via the corner portion. The bottom of the contact region 164 is formed by the inner wall region 164c.

[0524] In the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102, a plurality of deep well regions 165 are formed. Each deep well region 165 is also referred to as a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the active region 111.

[0525] Each deep well region 165 is formed in the SiC epitaxial layer 107. More specifically, each deep well region 165 is formed in the high-concentration region 108 of the SiC epitaxial layer 107.

[0526] Each deep well region 165 is formed along the inner wall of each source trench 155 so as to cover each contact region 164. Each deep well region 165 is electrically connected to each contact region 164.

[0527] Each deep well region 165 is formed in a strip shape extending along each source trench 155 in a plan view. Each deep well region 165 covers the side wall of each source trench 155.

[0528] Each deep well region 165 covers the corner connecting the side wall and the bottom wall of each source trench 155. Each deep well region 165 covers the bottom wall of each source trench 155 from the side wall of each source trench 155 via the corner. Each deep well region 165 is continuous with the body region 141 on the side wall of each source trench 155.

[0529] Each deep well region 165 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom portion of each deep well region 165 may be formed parallel to the bottom wall of each source trench 155.

[0530] The p-type impurity concentration in each deep well region 165 may be approximately equal to the p-type impurity concentration in the body region 141. The p-type impurity concentration in each deep well region 165 may exceed the p-type impurity concentration in the body region 141. The p-type impurity concentration in each deep well region 165 may be less than the p-type impurity concentration in the body region 141.

[0531] The p-type impurity concentration in each deep well region 165 may be less than or equal to the p-type impurity concentration in the contact region 164. The p-type impurity concentration in each deep well region 165 may be less than the p-type impurity concentration in the contact region 164. The p-type impurity concentration in each deep well region 165 may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0532] Each deep well region 165 forms a pn junction with the SiC semiconductor layer 102 (the high-concentration region 108 of the SiC epitaxial layer 107). From this pn junction, a depletion layer spreads toward the region between a plurality of gate trenches 142 adjacent to each other. This depletion layer spreads toward the region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142.

[0533] The depletion layer spreading from each deep well region 165 may overlap the bottom wall of each gate trench 142. The depletion layer spreading from the bottom of each deep well region 165 may overlap the bottom wall of each gate trench 142.

[0534] Referring to FIGS. 19 and 21, a p-type peripheral deep well region 166 is formed at the peripheral portion of the active region 111. The peripheral deep well region 166 is formed in the SiC epitaxial layer 107. More specifically, the peripheral deep well region 166 is formed in the high-concentration region 108 of the SiC epitaxial layer 107.

[0535] The peripheral deep well region 166 is electrically connected to each deep well region 165. The peripheral deep well region 166 has the same potential as each deep well region 165. In this form, the peripheral deep well region 166 is integrally formed with each deep well region 165.

[0536] More specifically, the peripheral deep well region 166 is formed in a region along the inner wall of the contact trench portion 144 of each gate trench 142 at the peripheral portion of the active region 111.

[0537] The peripheral deep well region 166 covers the side wall of the contact trench portion 144 of each gate trench 142. The peripheral deep well region 166 covers the corner portion connecting the side wall and the bottom wall of each contact trench portion 144.

[0538] The peripheral deep well region 166 covers the bottom wall of each contact trench portion 144 from the side wall of each contact trench portion 144 via the corner portion. Each deep well region 165 is continuous with the body region 141 on the side wall of each contact trench portion 144. The bottom of the peripheral deep well region 166 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each contact trench portion 144.

[0539] The peripheral deep well region 166 overlaps the gate wiring layer 150 in plan view. The peripheral deep well region 166 faces the gate wiring layer 150 with the gate insulating layer 148 (third region 148c) interposed therebetween.

[0540] The peripheral deep well region 166 includes a lead-out portion 166a drawn from each contact trench portion 144 to each active trench portion 143. The lead-out portion 166a is formed in the high-concentration region 108 of the SiC epitaxial layer 107. The lead-out portion 166a extends along the side wall of each active trench portion 143 and covers the bottom wall of the active trench portion 143 through the corner portion.

[0541] The lead-out portion 166a covers the side walls of the active trench portions 143 of the respective gate trenches 142. The lead-out portion 166a covers the corners connecting the side walls and the bottom wall of each active trench portion 143.

[0542] The lead-out portion 166a covers the bottom wall of each active trench portion 143 from the side wall of each active trench portion 143 via the corner. The lead-out portion 166a is continuous with the body region 141 at the side wall of each active trench portion 143. The bottom of the lead-out portion 166a is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each active trench portion 143.

[0543] The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may exceed the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the body region 141.

[0544] The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may exceed the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of each deep well region 165.

[0545] The p-type impurity concentration of the peripheral deep well region 166 may be less than or equal to the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0546] In a SiC semiconductor device having only a pn junction diode, due to the structure without trenches, there are few problems of electric field concentration in the SiC semiconductor layer 102. Each deep well region 165 (peripheral deep well region 166) makes the trench gate type MISFET approach the structure of the pn junction diode.

[0547] Thereby, in the trench gate type MISFET, the electric field in the SiC semiconductor layer 102 can be relaxed. Therefore, narrowing the pitch between a plurality of adjacent deep well regions 165 is effective in relaxing the electric field concentration.

[0548] Also, according to each deep well region 165 having a bottom on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142, the electric field concentration with respect to each gate trench 142 can be appropriately relaxed by the depletion layer.

[0549] The distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is preferably substantially constant. Thereby, it is possible to suppress variations in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0550] Therefore, it is possible to suppress the breakdown voltage (for example, breakdown withstand) of the SiC semiconductor layer 102 from being limited by the form of each deep well region 165, so that the breakdown voltage can be appropriately improved.

[0551] In this form, a high concentration region 108 of the SiC epitaxial layer 107 is interposed in the region between a plurality of adjacent deep well regions 165. Thereby, the JFET (Junction Field Effect Transistor) resistance can be reduced in the region between a plurality of adjacent deep well regions 165.

[0552] Furthermore, in this embodiment, the bottom of each deep well region 165 is located within the high-concentration region 108 of the SiC epitaxial layer 107. Thereby, a current path can be extended in the lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102 from the bottom of each deep well region 165. Thereby, the current spreading resistance can be reduced. The low-concentration region 109 of the SiC epitaxial layer 107 increases the breakdown voltage of the SiC semiconductor layer 102 in such a structure.

[0553] By forming the source trench 155, a p-type impurity can be introduced into the inner wall of the source trench 155. Thereby, since each deep well region 165 can be conformally formed with respect to the source trench 155, variations in the depth of each deep well region 165 can be appropriately suppressed. Further, by using each source trench 155, each deep well region 165 can be appropriately formed in a relatively deep region of the SiC semiconductor layer 102.

[0554] Referring to FIG. 22, a low-resistance electrode layer 167 is formed on the gate electrode layer 149. The low-resistance electrode layer 167 covers the upper end portion of the gate electrode layer 149 within each gate trench 142.

[0555] The low-resistance electrode layer 167 includes a conductive material having a sheet resistance less than that of the gate electrode layer 149. The sheet resistance of the low-resistance electrode layer 167 may be 0.01 Ω / sq or more and 10 Ω / sq or less.

[0556] The low-resistance electrode layer 167 is formed in a film shape. The low-resistance electrode layer 167 has a connection portion 167a in contact with the upper end portion of the gate electrode layer 149 and a non-connection portion 167b opposite thereto. The connection portion 167a and the non-connection portion 167b of the low-resistance electrode layer 167 may be formed in a concave curved shape following the upper end portion of the gate electrode layer 149. The connection portion 167a and the non-connection portion 167b of the low-resistance electrode layer 167 can take various forms.

[0557] The entire connecting portion 167a of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connecting portion 167a of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0558] The connecting portion 167a of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connecting portion 167a of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0559] For example, the central portion of the connecting portion 167a of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the connecting portion 167a of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0560] The entire non-connecting portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire non-connecting portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0561] The non-connecting portion 167b of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connecting portion 167b of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0562] For example, the central portion of the non-connecting portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the non-connecting portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0563] The low-resistance electrode layer 167 has an edge 167c in contact with the gate insulating layer 148. The edge 167c of the low-resistance electrode layer 167 is in contact with a corner portion that connects the first region 148a and the second region 148b in the gate insulating layer 148.

[0564] The edge 167c of the low-resistance electrode layer 167 is in contact with the third region 148c of the gate insulating layer 148. More specifically, the edge 167c of the low-resistance electrode layer 167 is in contact with the bulged portion 148d of the gate insulating layer 148.

[0565] The edge 167c of the low-resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163. The edge 167c of the low-resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 rather than in a boundary region between the body region 141 and the source region 163.

[0566] Therefore, the edge 167c of the low-resistance electrode layer 167 faces the source region 163 with the gate insulating layer 148 interposed therebetween. The edge 167c of the low-resistance electrode layer 167 does not face the body region 141 with the gate insulating layer 148 interposed therebetween.

[0567] Thereby, it is possible to suppress the formation of a current path in a region between the low-resistance electrode layer 167 and the body region 141 in the gate insulating layer 148. The current path may be formed by an undesired diffusion of the electrode material of the low-resistance electrode layer 167 with respect to the gate insulating layer 148.

[0568] In particular, the design of connecting the edge 167c of the low-resistance electrode layer 167 to the third region 148c (the corner portion of the gate insulating layer 148) of the relatively thick gate insulating layer 148 is effective in reducing the risk of forming a current path.

[0569] With respect to the normal direction Z, the thickness Tr of the low-resistance electrode layer 167 is equal to or less than the thickness TG of the gate electrode layer 149 (Tr ≦ TG). Preferably, the thickness Tr of the low-resistance electrode layer 167 is less than the thickness TG of the gate electrode layer 149 (Tr < TG). More specifically, preferably, the thickness Tr of the low-resistance electrode layer 167 is equal to or less than half of the thickness TG of the gate electrode layer 149 (Tr ≦ TG / 2).

[0570] The ratio Tr / TG of the thickness Tr of the low-resistance electrode layer 167 to the thickness TG of the gate electrode layer 149 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 149 may be 0.5 μm or more and 3 μm or less. The thickness Tr of the low-resistance electrode layer 167 may be 0.01 μm or more and 3 μm or less.

[0571] The current supplied into each gate trench 142 flows through the low-resistance electrode layer 167 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 149. As a result, the entire gate electrode layer 149 (the entire active region 111) can be quickly shifted from the off state to the on state, so that the delay of the switching response can be suppressed.

[0572] In particular, in the case of the gate trench 142 having a length on the order of millimeters (a length of 1 mm or more), it takes time for the current to be transmitted, but according to the low-resistance electrode layer 167, the delay of the switching response can be appropriately suppressed. That is, the low-resistance electrode layer 167 is formed as a current diffusion electrode layer that diffuses current in each gate trench 142.

[0573] In addition, as the miniaturization of the cell structure progresses, the width, depth, cross-sectional area, etc. of the gate electrode layer 149 become smaller, so there is concern about the delay of the switching response due to the increase in the electrical resistance in each gate trench 142.

[0574] However, according to the low-resistance electrode layer 167, the entire gate electrode layer 149 can be quickly shifted from the off state to the on state, so that the delay of the switching response due to miniaturization can be appropriately suppressed.

[0575] Referring to FIG. 21, in this form, the low-resistance electrode layer 167 also covers the upper end portion of the gate wiring layer 150. The portion of the low-resistance electrode layer 167 that covers the upper end portion of the gate wiring layer 150 is integrally formed with the portion that covers the upper end portion of the gate electrode layer 149 in the low-resistance electrode layer 167. Thereby, the low-resistance electrode layer 167 covers the entire area of the gate electrode layer 149 and the entire area of the gate wiring layer 150.

[0576] Therefore, the current supplied from the gate pad 116 and the gate fingers 117, 118 to the gate wiring layer 150 is transmitted to the entire gate electrode layer 149 and the entire gate wiring layer 150 through the low-resistance electrode layer 167 having a relatively low sheet resistance.

[0577] Thereby, since the entire gate electrode layer 149 (the entire active region 111) can be quickly shifted from the off state to the on state through the gate wiring layer 150, the delay of the switching response can be suppressed.

[0578] In particular, in the case of the gate trench 142 having a length on the order of millimeters, the delay of the switching response can be appropriately suppressed by the low-resistance electrode layer 167 that covers the upper end portion of the gate wiring layer 150.

[0579] The low-resistance electrode layer 167 includes a polyside layer. The polyside layer is formed by siliciding a portion of the surface layer of the gate electrode layer 149 with a metal material. More specifically, the polyside layer is composed of a p-type polyside layer containing p-type impurities added to the gate electrode layer 149 (p-type polysilicon). The polyside layer preferably has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0580] The sheet resistance in the gate trench 142 in which the gate electrode layer 149 and the low-resistance electrode layer 167 are embedded is equal to or less than the sheet resistance of the gate electrode layer 149 alone. The sheet resistance in the gate trench 142 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0581] The sheet resistance in the gate trench 142 is approximated to the sheet resistance of the low-resistance electrode layer 167. That is, the sheet resistance in the gate trench 142 may be 0.01 Ω / sq or more and 10 Ω / sq or less. It is preferable that the sheet resistance in the gate trench 142 is less than 10 Ω / sq.

[0582] The low-resistance electrode layer 167 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2. In particular, among these types, NiSi, CoSi2, and TiSi2 are suitable as the polysilicide layer for forming the low-resistance electrode layer 167 because the resistivity value and temperature dependence are relatively small.

[0583] On the first main surface 103 of the SiC semiconductor layer 102, source sub-trenches 168 communicating with the respective source trenches 155 are formed in a region along the upper end portion of the source electrode layer 157. The source sub-trenches 168 form a part of the side walls of the respective source trenches 155.

[0584] In this form, the source sub-trenches 168 are formed in an endless shape (a square ring shape in this form) surrounding the upper end portion of the source electrode layer 157 in plan view. The source sub-trenches 168 border the upper end portion of the source electrode layer 157.

[0585] The source sub-trenches 168 are formed by digging down a part of the source insulating layer 156. More specifically, the source sub-trenches 168 are formed by digging down from the first main surface 103 of the SiC semiconductor layer 102 to the upper end portion of the source insulating layer 156 and the upper end portion of the source electrode layer 157.

[0586] The upper end portion of the source electrode layer 157 has a shape that is constricted inward with respect to the lower end portion of the source electrode layer 157. The lower end portion of the source electrode layer 157 is a portion located on the bottom wall side of each source trench 155 in the source electrode layer 157. The width of the upper end portion of the source electrode layer 157 in the first direction may be less than the width of the lower end portion of the source electrode layer 157 in the first direction.

[0587] The source sub-trench 168 is formed in a tapered shape in which the bottom area is smaller than the opening area in a cross-sectional view. The bottom wall of the source sub-trench 168 may be formed in a convexly curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

[0588] The source region 163, the contact region 164, the source insulating layer 156, and the source electrode layer 157 are exposed from the inner wall of the source sub-trench 168. The first surface layer region 164a and the second surface layer region 164b of the contact region 164 are exposed from the inner wall of the source sub-trench 168.

[0589] At least the first region 156a of the source insulating layer 156 is exposed from the bottom wall of the source sub-trench 168. In the source insulating layer 156, the upper end portion of the first region 156a is located below the first main surface 103 of the SiC semiconductor layer 102.

[0590] The opening edge portion 169 of each source trench 155 includes an inclined portion 170 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each source trench 155. The opening edge portion 169 of each source trench 155 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the side wall of each source trench 155. The inclined portion 170 of each source trench 155 is formed by the source sub-trench 168.

[0591] In this form, the inclined portion 170 is formed in a concave curved shape that faces inward of the SiC semiconductor layer 102. The inclined portion 170 may be formed in a convex curved shape that faces inward of the source sub-trench 168. The inclined portion 170 alleviates the electric field concentration with respect to the opening edge portion 169 of each source trench 155.

[0592] Referring to FIGS. 23 and 24, the active region 111 has an active main surface 171 that forms a part of the first main surface 103 of the SiC semiconductor layer 102. The outer region 112 has an outer main surface 172 that forms a part of the first main surface 103 of the SiC semiconductor layer 102. In this form, the outer main surface 172 is connected to the side surfaces 105A to 105D of the SiC semiconductor layer 102.

[0593] The active main surface 171 and the outer main surface 172 face the c-plane of the SiC single crystal, respectively. Also, the active main surface 171 and the outer main surface 172 each have an off-angle θ that is inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0594] The outer main surface 172 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the active main surface 171. In this form, the outer region 112 is formed by digging down the first main surface 103 of the SiC semiconductor layer 102 toward the second main surface 104 side. Therefore, the outer main surface 172 is formed in a region that is recessed on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the active main surface 171.

[0595] The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The outer main surface 172 may be formed at a depth position substantially equal to the bottom wall of each source trench 155. The outer main surface 172 may be located on substantially the same plane as the bottom wall of each source trench 155.

[0596] The distance between the outer main surface 172 and the second main surface 104 of the SiC semiconductor layer 102 may be substantially equal to the distance between the bottom wall of each source trench 155 and the second main surface 104 of the SiC semiconductor layer 102.

[0597] The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155. The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155 in a range of 0 μm or more and 1 μm or less.

[0598] The SiC epitaxial layer 107 is exposed from the outer main surface 172. More specifically, the high-concentration region 108 of the SiC epitaxial layer 107 is exposed from the outer main surface 172 of the outer region 112. The outer main surface 172 faces the low-concentration region 109 of the SiC epitaxial layer 107 with the high-concentration region 108 of the SiC epitaxial layer 107 interposed therebetween.

[0599] In this form, the active region 111 is partitioned in a stepped shape by the outer region 112. The active region 111 is formed as an active mesa 173 protruding upward from the outer region 112.

[0600] The active mesa 173 includes an active sidewall 174 connecting the active main surface 171 and the outer main surface 172. The active sidewall 174 demarcates a boundary region between the active region 111 and the outer region 112. The first main surface 103 of the SiC semiconductor layer 102 is formed by the active main surface 171, the outer main surface 172, and the active sidewall 174.

[0601] In this form, the active sidewall 174 extends along the normal direction Z of the active main surface 171 (outer main surface 172). The active sidewall 174 is formed by the m-plane and a-plane of the SiC single crystal.

[0602] The active sidewall 174 may have an inclined surface that slopes downward from the active main surface 171 toward the outer main surface 172. The inclination angle of the active sidewall 174 is the angle formed between the active sidewall 174 and the active main surface 171 within the SiC semiconductor layer 102.

[0603] In this case, the inclination angle of the active sidewall 174 may be greater than 90° and less than or equal to 135°. The inclination angle of the active sidewall 174 may be greater than 90° and less than or equal to 95°, greater than or equal to 95° and less than or equal to 100°, greater than or equal to 100° and less than or equal to 110°, greater than or equal to 110° and less than or equal to 120°, or greater than or equal to 120° and less than or equal to 135°. It is preferable that the inclination angle of the active sidewall 174 is greater than 90° and less than or equal to 95°.

[0604] The SiC epitaxial layer 107 is exposed from the active sidewall 174. More specifically, the high-concentration region 108 of the SiC epitaxial layer 107 is exposed from the active sidewall 174.

[0605] At least the body region 141 is exposed from the region on the active main surface 171 side of the active sidewall 174. In FIGS. 23 and 24, a morphological example in which the body region 141 and the source region 163 are exposed from the active sidewall 174 is shown.

[0606] In the outer region 112, a p + -type diode region 181 (impurity region), a p-type outer deep well region 182, and a p-type field limit structure 183 are formed in the surface layer portion of the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102.

[0607] The diode region 181 is formed in the region between the active sidewall 174 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in the outer region 112. The diode region 181 is formed at an interval from the active sidewall 174 and the side surfaces 105A to 105D.

[0608] The diode region 181 extends in a strip shape along the active region 111 in a plan view. In this form, the diode region 181 is formed in an endless shape (a square ring shape in this form) surrounding the active region 111 in a plan view.

[0609] The diode region 181 overlaps with the source routing wiring 123 in a plan view. The diode region 181 is electrically connected to the source routing wiring 123. The diode region 181 forms part of an avalanche current absorption structure.

[0610] The diode region 181 forms a pn junction with the SiC semiconductor layer 102. More specifically, the diode region 181 is located within the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the SiC epitaxial layer 107.

[0611] More specifically, the diode region 181 is located within the high-concentration region 108 of the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the high-concentration region 108. As a result, a pn junction diode Dpn with the diode region 181 as the anode and the SiC semiconductor layer 102 as the cathode is formed.

[0612] The entirety of the diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of the diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.

[0613] The bottom of the diode region 181 may be formed at a depth position substantially equal to the bottom of the contact region 164. The bottom of the diode region 181 may be located on substantially the same plane as the bottom of the contact region 164.

[0614] The p-type impurity concentration of the diode region 181 is approximately equal to the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the diode region 181 is greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the diode region 181 is 1.0×10 18 cm -3 or more and may be 1.0×10 21 cm -3 or less.

[0615] The outer deep well region 182 is formed in a region between the active sidewall 174 and the diode region 181 in a plan view. In this form, the outer deep well region 182 is formed at an interval from the active sidewall 174 toward the diode region 181 side. The outer deep well region 182 is also referred to as a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112.

[0616] The outer deep well region 182 extends in a strip shape along the active region 111 in a plan view. In this form, the outer deep well region 182 is formed in an endless shape (a square ring shape in this form) surrounding the active region 111 in a plan view.

[0617] The outer deep well region 182 is electrically connected to the source routing wiring 123 via the diode region 181. The outer deep well region 182 may form a part of the pn junction diode Dpn. The outer deep well region 182 may form a part of an avalanche current absorption structure.

[0618] The whole of the outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of the outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.

[0619] The bottom of the outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of the diode region 181. The bottom of the outer deep well region 182 may be formed at a depth position substantially equal to the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located on substantially the same plane as the bottom of each deep well region 165.

[0620] The distance between the bottom of the outer deep well region 182 and the outer main surface 172 may be substantially equal to the distance between the bottom of each deep well region 165 and the bottom wall of each source trench 155.

[0621] The distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 may be substantially equal to the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0622] Thereby, it is possible to suppress the occurrence of variations between the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0623] Therefore, it is possible to suppress the breakdown voltage (e.g., breakdown withstand voltage) of the SiC semiconductor layer 102 from being restricted by the form of the outer deep well region 182 and the form of each deep well region 165, so that an appropriate improvement in breakdown voltage can be achieved.

[0624] The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165 in the range of 0 μm or more and 1 μm or less.

[0625] The inner peripheral edge of the outer deep well region 182 may extend up to the vicinity of the boundary region between the active region 111 and the outer region 112. The outer deep well region 182 may cross the boundary region between the active region 111 and the outer region 112.

[0626] The inner peripheral edge of the outer deep well region 182 may cover the corner connecting the active sidewall 174 and the outer main surface 172. The inner peripheral edge of the outer deep well region 182 may further extend along the active sidewall 174 and may be connected to the body region 141.

[0627] In this form, the outer peripheral edge of the outer deep well region 182 covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The outer deep well region 182 may overlap with the source routing wire 123 in plan view. The outer peripheral edge of the outer deep well region 182 may be formed at a distance from the diode region 181 toward the active sidewall 174.

[0628] The p-type impurity concentration of the outer deep well region 182 may be equal to or less than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the diode region 181.

[0629] The p-type impurity concentration of the outer deep well region 182 may be approximately equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the outer deep well region 182 may be approximately equal to the p-type impurity concentration of the body region 141.

[0630] The p-type impurity concentration of the outer deep well region 182 may exceed the p-type impurity concentration of the body region 141. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the body region 141.

[0631] The p-type impurity concentration in the outer deep well region 182 may be equal to or less than the p-type impurity concentration in the contact region 164. The p-type impurity concentration in the outer deep well region 182 may be less than the p-type impurity concentration in the contact region 164. The p-type impurity concentration in the outer deep well region 182 may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0632] The field limit structure 183 is formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. In this form, the field limit structure 183 is formed at a distance from the side surfaces 105A to 105D toward the diode region 181 side.

[0633] The field limit structure 183 includes one or more (for example, two or more and twenty or less) field limit regions 184. In this form, the field limit structure 183 includes a group of field limit regions having a plurality (five) of field limit regions 184A, 184B, 184C, 184D, 184E.

[0634] The field limit regions 184A to 184E are formed in this order at intervals along the direction away from the diode region 181. The field limit regions 184A to 184E each extend in a strip shape along the periphery of the active region 111 in a plan view.

[0635] More specifically, the field limit regions 184A to 184E are each formed in an endless shape (a square ring shape in this form) surrounding the active region 111 in a plan view. The field limit regions 184A to 184E are each also referred to as an FLR (Field Limiting Ring) region.

[0636] In this form, the bottoms of the field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of the diode region 181.

[0637] In this form, the innermost field limit region 184A among the field limit regions 184A to 184E covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The field limit region 184A may overlap with the aforementioned source routing wiring 123 in a plan view.

[0638] The field limit region 184A is electrically connected to the source routing wiring 123 via the diode region 181. The field limit region 184A may form a part of the pn junction diode Dpn. The field limit region 184A may form a part of the avalanche current absorption structure.

[0639] The entire field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of the respective gate trenches 142. The bottoms of the field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of the respective source trenches 155.

[0640] The field limit regions 184A to 184E may be formed at a depth position substantially equal to that of each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A to 184E may be located on substantially the same plane as the bottoms of the respective deep well regions 165 (outer deep well region 182).

[0641] The bottoms of the field limit regions 184A to 184E may be located on the outer main surface 172 side with respect to the bottoms of the respective deep well regions 165 (outer deep well regions 182). The bottoms of the field limit regions 184A to 184E may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottoms of the respective deep well regions 165 (outer deep well regions 182).

[0642] The widths between the mutually adjacent field limit regions 184A to 184E may be different from each other. The widths between the mutually adjacent field limit regions 184A to 184E may increase in the direction away from the active region 111. The widths between the mutually adjacent field limit regions 184A to 184E may decrease in the direction away from the active region 111.

[0643] The depths of the field limit regions 184A to 184E may be different from each other. The depths of the field limit regions 184A to 184E may decrease in the direction away from the active region 111. The depths of the field limit regions 184A to 184E may increase in the direction away from the active region 111.

[0644] The p-type impurity concentration of the field limit regions 184A to 184E may be equal to or less than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the field limit regions 184A to 184E may be smaller than the p-type impurity concentration of the diode region 181.

[0645] The p-type impurity concentration of the field limit regions 184A to 184E may be equal to or less than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A to 184E may be smaller than the p-type impurity concentration of the outer deep well region 182.

[0646] The p-type impurity concentration of the field limit regions 184A to 184E may be equal to or higher than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A to 184E may also be greater than the p-type impurity concentration of the outer deep well region 182.

[0647] The p-type impurity concentration of the field limit regions 184A to 184E is 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less. It is preferable that the p-type impurity concentration of the diode region 181 > the p-type impurity concentration of the outer deep well region 182 > the p-type impurity concentration of the field limit regions 184A to 184E.

[0648] The field limit structure 183 relaxes the electric field concentration in the outer region 112. The number, width, depth, p-type impurity concentration, etc. of the field limit regions 184 can take various values according to the electric field to be relaxed.

[0649] In this form, an example in which the field limit structure 183 includes one or more field limit regions 184 formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view has been described.

[0650] However, instead of the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102, the field limit structure 183 may include one or more field limit regions 184 formed in the region between the active sidewall 174 and the diode region 181 in a plan view.

[0651] Further, the field limit structure 183 may include one or more field limit regions 184 formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view, and one or more field limit regions 184 formed in a region between the active sidewall 174 and the diode region 181 in a plan view.

[0652] An outer insulating layer 191 is formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. The outer insulating layer 191 forms a part of the main surface insulating layer 113. The outer insulating layer 191 forms a part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113.

[0653] The outer insulating layer 191 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112. The outer insulating layer 191 is formed in a film shape along the active sidewall 174 and the outer main surface 172. The outer insulating layer 191 is continuous with the gate insulating layer 148 on the active main surface 171. More specifically, the outer insulating layer 191 is continuous with the third region 148c of the gate insulating layer 148.

[0654] The outer insulating layer 191 may contain silicon oxide. The outer insulating layer 191 may contain other insulating films such as silicon nitride. In this form, the outer insulating layer 191 is formed of the same insulating material type as the gate insulating layer 148.

[0655] The outer insulating layer 191 includes a first region 191a and a second region 191b. The first region 191a of the outer insulating layer 191 covers the active sidewall 174. The second region 191b of the outer insulating layer 191 covers the outer main surface 172.

[0656] The thickness of the second region 191b of the outer insulating layer 191 may be less than or equal to the thickness of the first region 191a of the outer insulating layer 191. The thickness of the second region 191b of the outer insulating layer 191 may be less than the thickness of the first region 191a of the outer insulating layer 191.

[0657] The thickness of the first region 191a of the outer insulating layer 191 may be substantially equal to the thickness of the first region 191a of the gate insulating layer 148. The thickness of the second region 191b of the outer insulating layer 191 may be substantially equal to the thickness of the third region 148c of the gate insulating layer 148. Of course, the outer insulating layer 191 having a uniform thickness may be formed.

[0658] Referring to FIGS. 23 and 24, the SiC semiconductor device 101 further includes a sidewall 192 that covers the active sidewall 174. The sidewall 192 protects and reinforces the active mesa 173 from the outer region 112 side.

[0659] Also, the sidewall 192 forms a step relaxation structure that relaxes the step formed between the active main surface 171 and the outer main surface 172. When an upper layer structure (coating layer) that covers the boundary region between the active region 111 and the outer region 112 is formed, the upper layer structure covers the sidewall 192. The sidewall 192 enhances the flatness of the upper layer structure.

[0660] The sidewall 192 may have an inclined portion 193 that slopes downward from the active main surface 171 toward the outer main surface 172. The inclined portion 193 can appropriately relax the step.

[0661] The inclined portion 193 of the sidewall 192 may be formed in a concave curved shape toward the SiC semiconductor layer 102 side. The inclined portion 193 of the sidewall 192 may be formed in a convex curved shape toward the side opposite to the SiC semiconductor layer 102.

[0662] The inclined portion 193 of the sidewall 192 may extend planar from the active main surface 171 side toward the outer main surface 172 side. The inclined portion 193 of the sidewall 192 may extend linearly from the active main surface 171 side toward the outer main surface 172 side.

[0663] The inclined portion 193 of the sidewall 192 may be formed in a downward stepped shape from the active main surface 171 toward the outer main surface 172. That is, the inclined portion 193 of the sidewall 192 may have one or a plurality of stepped portions recessed toward the outer main surface 172 side. The plurality of stepped portions increases the surface area of the inclined portion 193 of the sidewall 192 and enhances the adhesion to the upper layer structure.

[0664] The inclined portion 193 of the sidewall 192 may include a plurality of raised portions protruding toward the outside of the sidewall 192. The plurality of raised portions increases the surface area of the inclined portion 193 of the sidewall 192 and enhances the adhesion to the upper layer structure.

[0665] The inclined portion 193 of the sidewall 192 may include a plurality of depressions recessed toward the inside of the sidewall 192. The plurality of depressions increases the surface area of the inclined portion 193 of the sidewall 192 and enhances the adhesion to the upper layer structure.

[0666] The sidewall 192 is formed self-aligned with respect to the active main surface 171. More specifically, the sidewall 192 is formed along the active sidewall 174. In this form, the sidewall 192 is formed in an endless shape (a square ring shape in this form) surrounding the active region 111 in plan view.

[0667] The sidewall 192 preferably contains p-type polysilicon doped with p-type impurities. In this case, the sidewall 192 can be formed simultaneously with the gate electrode layer 149 and the source electrode layer 157.

[0668] The p-type impurity concentration of the sidewall 192 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the sidewall 192 is greater than the p-type impurity concentration of the body region 141. The p-type impurity of the sidewall 192 may contain at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0669] The p-type impurity concentration of the sidewall 192 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the sidewall 192 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form).

[0670] The p-type impurity concentration of the sidewall 192 may be approximately equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the sidewall 192 may be approximately equal to the sheet resistance of the gate electrode layer 149.

[0671] The sidewall 192 may contain n-type polysilicon instead of or in addition to p-type polysilicon. The sidewall 192 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

[0672] The sidewall 192 may contain an insulating material. In this case, the insulation between the active region 111 and the outer region 112 can be enhanced by the sidewall 192.

[0673] Referring to FIGS. 20 to 24, an interlayer insulating layer 201 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 201 forms a part of the main surface insulating layer 113. The interlayer insulating layer 201 forms a part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113. The main surface insulating layer 113 has a laminated structure including a gate insulating layer 148 (outer insulating layer 191) and the interlayer insulating layer 201.

[0674] The interlayer insulating layer 201 selectively covers the active region 111 and the outer region 112. More specifically, the interlayer insulating layer 201 selectively covers the third region 148c of the gate insulating layer 148 and the outer insulating layer 191.

[0675] The interlayer insulating layer 201 is formed in a film shape along the active main surface 171 and the outer main surface 172. The interlayer insulating layer 201 selectively covers the trench gate structure 161, the gate wiring layer 150, and the trench source structure 162 in the active region 111. The interlayer insulating layer 201 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112.

[0676] The interlayer insulating layer 201 is formed along the outer surface (inclined portion 193) of the sidewall 192 in the boundary region between the active region 111 and the outer region 112. The interlayer insulating layer 201 forms a part of the upper layer structure covering the sidewall 192.

[0677] The interlayer insulating layer 201 may contain silicon oxide or silicon nitride. The interlayer insulating layer 201 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

[0678] The interlayer insulating layer 201 may have a stacked structure including a PSG layer and a BPSG layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The interlayer insulating layer 201 may have a stacked structure including a BPSG layer and a PSG layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0679] A gate contact hole 202, a source contact hole 203, and a diode contact hole 204 are formed in the interlayer insulating layer 201. Further, an anchor hole 205 is formed in the interlayer insulating layer 201.

[0680] The gate contact hole 202 exposes the gate wiring layer 150 in the active region 111. The gate contact hole 202 may be formed in a strip shape along the gate wiring layer 150. The opening edge portion of the gate contact hole 202 is formed in a convex curved shape toward the inside of the gate contact hole 202.

[0681] The source contact hole 203 exposes the source region 163, the contact region 164, and the trench source structure 162 in the active region 111. The source contact hole 203 may be formed in a strip shape along the trench source structure 162 or the like. The opening edge portion of the source contact hole 203 is formed in a convex curved shape toward the inside of the source contact hole 203.

[0682] The diode contact hole 204 exposes the diode region 181 in the outer region 112. The diode contact hole 204 may be formed in a strip shape (more specifically, an endless shape) extending along the diode region 181.

[0683] The diode contact hole 204 may expose the outer deep well region 182 and / or the field limit structure 183. The opening edge portion of the diode contact hole 204 is formed in a convex curved shape toward the inside of the diode contact hole 204.

[0684] The anchor holes 205 are formed by digging down the interlayer insulating layer 201 in the outer region 112. The anchor holes 205 are formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. More specifically, the anchor holes 205 are formed in a region between the field limit structure 183 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0685] The anchor holes 205 expose the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102. The opening edge portion of the anchor holes 205 is formed in a convexly curved shape toward the inside of the anchor holes 205.

[0686] Referring to FIG. 18, the anchor holes 205 extend in a strip shape along the active region 111 in a plan view. In this form, the anchor holes 205 are formed in an endless shape (square ring shape in this form) surrounding the active region 111 in a plan view.

[0687] In this form, one anchor hole 205 is formed in a portion of the interlayer insulating layer 201 covering the outer region 112. However, a plurality of anchor holes 205 may be formed in a portion of the interlayer insulating layer 201 covering the outer region 112.

[0688] On the interlayer insulating layer 201, a main surface gate electrode layer 115 and a main surface source electrode layer 121 are formed. The main surface gate electrode layer 115 and the main surface source electrode layer 121 each have a stacked structure including a barrier electrode layer 206 and a main electrode layer 207 stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0689] The barrier electrode layer 206 may have a single-layer structure including a titanium layer or a titanium nitride layer. The barrier electrode layer 206 may have a stacked structure including a titanium layer and a titanium nitride layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0690] The thickness of the main electrode layer 207 is greater than the thickness of the barrier electrode layer 206. The main electrode layer 207 includes a conductive material having a resistance value smaller than the resistance value of the barrier electrode layer 206. The main electrode layer 207 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

[0691] The main electrode layer 207 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. In this form, the main electrode layer 207 includes an aluminum-silicon-copper alloy.

[0692] The outer gate finger 117 of the main surface gate electrode layer 115 enters the gate contact hole 202 from above the interlayer insulating layer 201. The outer gate finger 117 is electrically connected to the gate wiring layer 150 within the gate contact hole 202. Thereby, an electrical signal from the gate pad 116 is transmitted to the gate electrode layer 149 via the outer gate finger 117.

[0693] The source pad 122 of the main surface source electrode layer 121 enters the source contact hole 203 and the source sub-trench 168 from above the interlayer insulating layer 201. The source pad 122 is electrically connected to the source region 163, the contact region 164, and the source electrode layer 157 within the source contact hole 203 and the source sub-trench 168.

[0694] The source electrode layer 157 may be formed using a partial region of the source pad 122. The source electrode layer 157 may be formed by a portion that enters each source trench 155 in the source pad 122.

[0695] The source routing wiring 123 of the main surface source electrode layer 121 enters the diode contact hole 204 from above the interlayer insulating layer 201. The source routing wiring 123 is electrically connected to the diode region 181 within the diode contact hole 204.

[0696] Of the main surface source electrode layer 121, the source connection portion 124 is drawn out from the active region 111 across the sidewall 192 to the outer region 112. The source connection portion 124 forms a part of the upper layer structure covering the sidewall 192.

[0697] On the interlayer insulating layer 201, the above-described passivation layer 125 is formed. The passivation layer 125 is formed in a film shape along the interlayer insulating layer 201. The passivation layer 125 selectively covers the active region 111 and the outer region 112 via the interlayer insulating layer 201.

[0698] The passivation layer 125 is drawn out from the active region 111 across the sidewall 192 to the outer region 112. The passivation layer 125 forms a part of the upper layer structure covering the sidewall 192.

[0699] Referring to FIG. 23, in the outer region 112, the passivation layer 125 enters the anchor hole 205 from above the interlayer insulating layer 201. The passivation layer 125 is connected to the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102 within the anchor hole 205. In the region located above the anchor hole 205 on the outer surface of the passivation layer 125, a recess 211 recessed following the anchor hole 205 is formed.

[0700] On the passivation layer 125, the above-described resin layer 129 is formed. The resin layer 129 is formed in a film shape along the passivation layer 125. The resin layer 129 selectively covers the active region 111 and the outer region 112 with the passivation layer 125 and the interlayer insulating layer 201 interposed therebetween.

[0701] The resin layer 129 is drawn out from the active region 111 across the sidewall 192 to the outer region 112. The resin layer 129 forms a part of the upper layer structure covering the sidewall 192.

[0702] Referring to FIG. 23, the resin layer 129 has an anchor portion that enters the recess 211 of the passivation layer 125 in the outer region 112. In this way, an anchor structure for increasing the connection strength of the resin layer 129 is formed in the outer region 112.

[0703] The anchor structure includes an uneven structure formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. The uneven structure (anchor structure) more specifically includes unevenness formed using the interlayer insulating layer 201 that covers the outer main surface 172. Even more specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201.

[0704] The resin layer 129 meshes with the anchor holes 205. In this form, the resin layer 129 meshes with the anchor holes 205 via the passivation layer 125. Thereby, since the connection strength of the resin layer 129 with respect to the first main surface 103 of the SiC semiconductor layer 102 can be increased, peeling of the resin layer 129 can be suppressed.

[0705] As described above, the SiC semiconductor device 101 can achieve the same effects as those described for the SiC semiconductor device 1. Also, according to the SiC semiconductor device 101, a depletion layer can be expanded from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 toward the region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 142.

[0706] Thereby, the current path of the short - circuit current flowing between the main - surface source electrode layer 121 and the drain electrode layer 133 can be narrowed. Also, due to the depletion layer expanding from the boundary region between the SiC semiconductor layer 102 and the deep well region 165, the feedback capacitance Crss can be reduced inversely proportionally. Therefore, a SiC semiconductor device 101 that can improve the short - circuit withstand and reduce the feedback capacitance Crss can be provided.

[0707] The depletion layer extending from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 may overlap the bottom wall of the gate trench 142. In this case, the depletion layer extending from the bottom of the deep well region 165 may overlap the bottom wall of the gate trench 142.

[0708] Also, according to the SiC semiconductor device 101, since the region occupied by the depletion layer in the SiC semiconductor layer 102 can be increased, the feedback capacitance Crss can be reduced inversely proportionally. The feedback capacitance Crss is the capacitance between the gate electrode layer 149 and the drain electrode layer 133.

[0709] Also, according to the SiC semiconductor device 101, the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is substantially constant. Thereby, it is possible to suppress variations in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0710] Therefore, since it is possible to suppress the breakdown voltage (e.g., breakdown withstand voltage) of the SiC semiconductor layer 102 from being restricted by the form of the deep well region 165, it is possible to appropriately improve the breakdown voltage.

[0711] Also, according to the SiC semiconductor device 101, a diode region 181 is formed in the outer region 112. This diode region 181 is electrically connected to the main surface source electrode layer 121. Thereby, the avalanche current generated in the outer region 112 can be made to flow into the main surface source electrode layer 121 via the diode region 181.

[0712] That is, the avalanche current generated in the outer region 112 can be absorbed by the diode region 181 and the main surface source electrode layer 121. As a result, the stability of the operation of the MISFET can be enhanced.

[0713] Further, according to the SiC semiconductor device 101, an outer deep well region 182 is formed in the outer region 112. Thereby, in the outer region 112, the breakdown voltage of the SiC semiconductor layer 102 can be adjusted.

[0714] In particular, according to the SiC semiconductor device 101, the outer deep well region 182 is formed at a depth position substantially equal to that of the deep well region 165. More specifically, the bottom of the outer deep well region 182 is located substantially on the same plane as the bottom of the deep well region 165.

[0715] The distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 is substantially equal to the distance between the bottom of the deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0716] Thereby, it is possible to suppress variations between the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of the deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0717] Therefore, it is possible to suppress the breakdown voltage (e.g., breakdown withstand) of the SiC semiconductor layer 102 from being restricted by the form of the outer deep well region 182 and the form of the deep well region 165. As a result, an improvement in breakdown voltage can be appropriately achieved.

[0718] In particular, in the SiC semiconductor device 101, the outer region 112 is formed in the region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the active region 111. Thereby, the position of the bottom of the outer deep well region 182 can be appropriately brought close to the position of the bottom of the deep well region 165.

[0719] That is, when forming the outer deep well region 182, it is not necessary to introduce p-type impurities at a relatively deep position in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. Therefore, it is possible to appropriately suppress a large shift in the position of the bottom of the outer deep well region 182 with respect to the position of the bottom of the deep well region 165.

[0720] Moreover, in the SiC semiconductor device 101, the outer main surface 172 of the outer region 112 is located substantially on the same plane as the bottom wall of the source trench 155. Thereby, when introducing p-type impurities into the bottom wall of the source trench 155 and the outer main surface 172 of the outer region 112 with equal energy, the deep well region 165 and the outer deep well region 182 can be formed at substantially equal depth positions.

[0721] As a result, it is possible to more appropriately suppress a large shift in the position of the bottom of the outer deep well region 182 with respect to the position of the bottom of the deep well region 165.

[0722] Further, according to the SiC semiconductor device 101, a field limit structure 183 is formed in the outer region 112. Thereby, in the outer region 112, an electric field relaxation effect by the field limit structure 183 can be obtained. Therefore, the breakdown voltage of the SiC semiconductor layer 102 can be appropriately improved.

[0723] Further, according to the SiC semiconductor device 101, the active region 111 is formed as a mesa-shaped active mesa 173. The active mesa 173 includes an active sidewall 174 that connects the active main surface 171 of the active region 111 and the outer main surface 172 of the outer region 112.

[0724] In the region between the active main surface 171 and the outer main surface 172, a step relaxation structure for relaxing the step between the active main surface 171 and the outer main surface 172 is formed. The step relaxation structure includes a sidewall 192.

[0725] As a result, the step between the active main surface 171 and the outer main surface 172 can be appropriately alleviated. Therefore, the flatness of the upper layer structure formed on the sidewall 192 can be appropriately enhanced. In the SiC semiconductor device 101, as an example of the upper layer structure, an interlayer insulating layer 201, a main surface source electrode layer 121, a passivation layer 125, and a resin layer 129 are formed.

[0726] Further, according to the SiC semiconductor device 101, in the outer region 112, an anchor structure for enhancing the connection strength of the resin layer 129 is formed. The anchor structure includes an uneven structure formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112.

[0727] More specifically, the uneven structure (anchor structure) includes unevenness formed by using the interlayer insulating layer 201 formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. Even more specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201.

[0728] The resin layer 129 meshes with the anchor holes 205. In this form, the resin layer 129 meshes with the anchor holes 205 via the passivation layer 125. As a result, the connection strength of the resin layer 129 with respect to the first main surface 103 of the SiC semiconductor layer 102 can be enhanced, so that the peeling of the resin layer 129 can be appropriately suppressed.

[0729] Further, according to the SiC semiconductor device 101, a trench gate structure 161 is formed in which a gate electrode layer 149 is embedded in the gate trench 142 with a gate insulating layer 148 interposed therebetween. In this trench gate structure 161, the gate electrode layer 149 is covered by a low-resistance electrode layer 167 in a limited space of the gate trench 142. According to such a structure, the effects described with reference to FIG. 25 can be achieved.

[0730] FIG. 25 is a graph for explaining the sheet resistance in the gate trench 142. In FIG. 25, the vertical axis represents the sheet resistance [Ω / □], and the horizontal axis represents items. In FIG. 25, a first bar graph BL1, a second bar graph BL2, and a third bar graph BL3 are shown.

[0731] The first bar graph BL1 represents the sheet resistance in the gate trench 142 filled with n-type polysilicon. The second bar graph BL2 represents the sheet resistance in the gate trench 142 filled with p-type polysilicon.

[0732] The third bar graph BL3 represents the sheet resistance in the gate trench 142 filled with the gate electrode layer 149 (p-type polysilicon) and the low-resistance electrode layer 167. Here, the case where the low-resistance electrode layer 167 made of TiSi2 (p-type titanium silicide) as an example of polyside (silicide) is formed will be described.

[0733] Referring to the first bar graph BL1, the sheet resistance in the gate trench 142 filled with n-type polysilicon was 10 Ω / □. Referring to the second bar graph BL2, the sheet resistance in the gate trench 142 filled with p-type polysilicon was 200 Ω / □. Referring to the third bar graph BL3, the sheet resistance in the gate trench 142 filled with the gate electrode layer 149 (p-type polysilicon) and the low-resistance electrode layer 167 was 2 Ω / □.

[0734] P-type polysilicon has a work function different from that of n-type polysilicon. According to the structure in which p-type polysilicon is embedded in the gate trench 142, the gate threshold voltage Vth can be increased by about 1 V.

[0735] However, p-type polysilicon has a sheet resistance that is several tens of times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is adopted as the material of the gate electrode layer 149, the energy loss increases significantly as the parasitic resistance (hereinafter simply referred to as "gate resistance") in the gate trench 142 increases.

[0736] On the other hand, according to the structure having the low-resistance electrode layer 167 on the gate electrode layer 149 (p-type polysilicon), the sheet resistance can be reduced to 1 / 100 or less compared with the case where the low-resistance electrode layer 167 is not formed. That is, according to the structure having the low-resistance electrode layer 167, the sheet resistance can be reduced to 1 / 5 or less compared with the gate electrode layer 149 including n-type polysilicon.

[0737] Thus, according to the structure having the low-resistance electrode layer 167, while increasing the gate threshold voltage Vth (for example, increasing by about 1 V), the sheet resistance in the gate trench 142 can be reduced. Thereby, since the gate resistance can be reduced, the current can be efficiently diffused along the trench gate structure 161. As a result, the switching delay can be shortened.

[0738] Also, according to the structure having the low-resistance electrode layer 167, it is not necessary to increase the p-type impurity concentration in the body region 141 and the p-type impurity concentration in the contact region 164. Therefore, while suppressing an increase in the channel resistance, the gate threshold voltage Vth can be appropriately increased.

[0739] The low-resistance electrode layer 167 can contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2. In particular, among these types, NiSi, CoSi2, and TiSi2 are suitable as the polyside layer for forming the low-resistance electrode layer 167 because their resistivity values and temperature dependencies are relatively small.

[0740] As a result of further verification by the inventors of the present application, when TiSi2 is adopted as the material of the low-resistance electrode layer 167, an increase in the leakage current between the gate and the source was observed under low electric field application. On the other hand, when CoSi2 is adopted, no increase in the leakage current between the gate and the source was observed under low electric field application. Considering this point, CoSi2 is considered to be the most preferable as the polysilicide layer forming the low-resistance electrode layer 167.

[0741] Furthermore, according to the SiC semiconductor device 101, the gate wiring layer 150 is covered by the low-resistance electrode layer 167. Thereby, reduction of the gate resistance in the gate wiring layer 150 can also be achieved.

[0742] In particular, in the structure where the gate electrode layer 149 and the gate wiring layer 150 are covered by the low-resistance electrode layer 167, current can be efficiently diffused along the trench gate structure 161. Therefore, shortening of the switching delay can be appropriately achieved.

[0743] FIG. 26 is an enlarged view of the region corresponding to FIG. 19, and is an enlarged view showing the SiC semiconductor device 221 according to the fourth embodiment of the present invention. FIG. 27 is a cross-sectional view taken along line XXVII-XXVII shown in FIG. 26. Hereinafter, for the structure corresponding to the structure described for the SiC semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0744] Referring to FIGS. 26 and 27, the SiC semiconductor device 221 includes an outer gate trench 222 formed on the first main surface 103 of the SiC semiconductor layer 102 in the active region 111. The outer gate trench 222 extends in a band shape along the peripheral edge of the active region 111.

[0745] The outer gate trench 222 is formed in a region directly below the outer gate finger 117 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 222 extends along the outer gate finger 117.

[0746] The outer gate trench 222 is formed along three side surfaces 105A, 105B, 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions. The outer gate trench 222 may be formed in an endless shape (for example, a square ring shape) surrounding the inner region of the active region 111.

[0747] The outer gate trench 222 communicates with the contact trench portion 144 of each gate trench 142. Thus, the outer gate trench 222 and the gate trench 142 are formed by one trench.

[0748] The gate wiring layer 150 is embedded in the outer gate trench 222. The gate wiring layer 150 is connected to the gate electrode layer 149 at the communication portion of the gate trench 142 and the outer gate trench 222.

[0749] A low-resistance electrode layer 167 covering the gate wiring layer 150 is formed in the outer gate trench 222. In this case, the low-resistance electrode layer 167 covering the gate electrode layer 149 and the low-resistance electrode layer 167 covering the gate wiring layer 150 are located in one trench.

[0750] As described above, the SiC semiconductor device 221 can also achieve the same effects as those described for the SiC semiconductor device 101. Further, according to the SiC semiconductor device 221, it is not necessary to draw out the gate wiring layer 150 onto the first main surface 103 of the SiC semiconductor layer 102.

[0751] Thereby, at the opening edge portion 146 of the gate trench 142 (outer gate trench 222), it is possible to suppress the gate wiring layer 150 from facing the SiC semiconductor layer 102 with the gate insulating layer 148 interposed therebetween. As a result, it is possible to suppress the concentration of the electric field at the opening edge portion 146 of the gate trench 142 (outer gate trench 222).

[0752] FIG. 28 is an enlarged view of the region corresponding to FIG. 22, and is an enlarged view showing the SiC semiconductor device 231 according to the fifth embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the SiC semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0753] Referring to FIG. 28, in this embodiment, the SiC epitaxial layer 107 includes a high-concentration region 108, a low-concentration region 109, and a concentration gradient region 232 interposed between the high-concentration region 108 and the low-concentration region 109.

[0754] The concentration gradient region 232 is formed not only in the active region 111 but also in the outer region 112 in the SiC epitaxial layer 107. The concentration gradient region 232 is formed over the entire area of the SiC epitaxial layer 107.

[0755] The concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high-concentration region 108 toward the low-concentration region 109. In other words, the concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually increases from the low-concentration region 109 toward the high-concentration region 108. The concentration gradient region 232 suppresses a rapid change in the n-type impurity concentration in the region between the high-concentration region 108 and the low-concentration region 109.

[0756] When the SiC epitaxial layer 107 includes the concentration gradient region 232, the n-type impurity concentration in the high-concentration region 108 is preferably 1.5 times or more and 5 times or less the n-type impurity concentration in the low-concentration region 109. The n-type impurity concentration in the high-concentration region 108 may be 3 times or more and 5 times or less the n-type impurity concentration in the low-concentration region 109.

[0757] The thickness of the concentration gradient region 232 may be 0.5 μm or more and 2.0 μm or less. The thickness of the concentration gradient region 232 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2.0 μm or less.

[0758] Although specific descriptions are omitted, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc. are formed in the high-concentration region 108.

[0759] That is, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc. are formed in the region on the first main surface 103 side with respect to the boundary region between the high-concentration region 108 and the concentration gradient region 232 in the SiC semiconductor layer 102.

[0760] As described above, the SiC semiconductor device 231 can also achieve the same effects as those described for the SiC semiconductor device 101.

[0761] FIG. 29 is an enlarged view of the region corresponding to FIG. 19, and is an enlarged view showing the SiC semiconductor device 241 according to the sixth embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the SiC semiconductor device 101, the same reference numerals are given and the description is omitted.

[0762] Referring to FIG. 29, in this embodiment, the gate trench 142 is formed in a lattice shape in plan view. More specifically, the gate trench 142 includes a plurality of first gate trenches 242 and a plurality of second gate trenches 243. The plurality of first gate trenches 242 and the plurality of second gate trenches 243 form the active trench portion 143.

[0763] The plurality of first gate trenches 242 are formed at intervals in the second direction Y and are each formed in a strip shape extending along the first direction X. The plurality of first gate trenches 242 are formed in a stripe shape as a whole in plan view.

[0764] The side walls forming the long sides in each first gate trench 242 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides in each first gate trench 242 are formed by the m-plane of the SiC single crystal.

[0765] The plurality of second gate trenches 243 are formed at intervals in the first direction X and are each formed in a strip shape extending along the second direction Y. The plurality of second gate trenches 243 are formed in a stripe shape as a whole in plan view.

[0766] The side walls forming the long sides in each second gate trench 243 are formed by the m-plane of the SiC single crystal. The side walls forming the short sides in each second gate trench 243 are formed by the a-plane of the SiC single crystal.

[0767] The plurality of first gate trenches 242 and the plurality of second gate trenches 243 intersect with each other. Thereby, one gate trench 142 having a lattice shape is formed in plan view. A plurality of cell regions 244 are partitioned in the region surrounded by the gate trench 142.

[0768] The plurality of cell regions 244 are arranged in a matrix at intervals in the first direction X and the second direction Y in plan view. The plurality of cell regions 244 are formed in a square shape in plan view. In each cell region 244, the body region 141 is exposed from the side walls of the gate trench 142. The body region 141 is exposed from the side walls formed by the m-plane and a-plane of the SiC single crystal in the gate trench 142.

[0769] Of course, the gate trench 142 may be formed in a honeycomb shape as an aspect of the lattice shape in plan view. In this case, the plurality of cell regions 244 may be arranged in a staggered manner at intervals in the first direction X and the second direction Y. Also, in this case, the plurality of cell regions 244 may be formed in a hexagonal shape in plan view.

[0770] Each source trench 155 is formed at the center of each cell region 244 in a plan view. Each source trench 155 is formed in a pattern that appears once on a cross-sectional surface that appears when each cell region 244 is cut along the first direction X. Also, each source trench 155 is formed in a pattern that appears once on a cross-sectional surface that appears when each cell region 244 is cut along the second direction Y.

[0771] More specifically, each source trench 155 is formed in a rectangular shape in a plan view. The four side walls of each source trench 155 are formed by the m-plane and a-plane of a SiC single crystal.

[0772] The planar shape of each source trench 155 is arbitrary. Each source trench 155 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, a hexagonal shape, or a circular shape or an elliptical shape in a plan view.

[0773] The cross-sectional view along line XX-XX in FIG. 29 corresponds to the cross-sectional view shown in FIG. 20. The cross-sectional view along line XXI-XXI in FIG. 29 corresponds to the cross-sectional view shown in FIG. 21.

[0774] As described above, the SiC semiconductor device 241 can also achieve the same effects as those described for the SiC semiconductor device 101.

[0775] Although the embodiments of the present invention have been described, the embodiments of the present invention can also be implemented in other forms.

[0776] In each of the above-described embodiments, the form in which the side surfaces 5A, 105A and the side surfaces 5C, 105C of the SiC semiconductor layers 2, 102 face the a-plane of the SiC single crystal and the side surfaces 5B, 105B and the side surfaces 5D, 105D face the m-plane of the SiC single crystal has been described. However, a form in which the side surfaces 5A, 105A and the side surfaces 5C, 105C face the m-plane of the SiC single crystal and the side surfaces 5B, 105B and the side surfaces 5D, 105D face the a-plane of the SiC single crystal may be adopted.

[0777] In each of the above-described embodiments, an example in which continuous strip-shaped modified lines 22A to 22D are formed has been described. However, in each of the above-described embodiments, the broken-line strip-shaped (broken-line-shaped) modified lines 22A to 22D may be formed. That is, the modified lines 22A to 22D may be formed in a strip shape that extends intermittently. In this case, one, two, or three of the modified lines 22A to 22D may be formed in a broken-line strip shape, and the remaining ones may be formed in a strip shape.

[0778] In the above-described third to sixth embodiments, an example in which a plurality of gate trenches 142 (first gate trenches 242) extending along the m-axis direction ([1-100] direction) of the SiC single crystal are formed has been described.

[0779] However, a plurality of gate trenches 142 (first gate trenches 242) extending along the a-axis direction ([11-20] direction) of the SiC single crystal may be formed. In this case, a plurality of source trenches 155 extending along the a-axis direction ([11-20] direction) of the SiC single crystal are formed.

[0780] In the above-described third to sixth embodiments, an example in which the source electrode layer 157 is embedded in the source trench 155 with the source insulating layer 156 interposed therebetween has been described. However, the source electrode layer 157 may be directly embedded in the source trench 155 without passing through the source insulating layer 156.

[0781] In the above-described third to sixth embodiments, an example in which the source insulating layer 156 is formed along the side walls and the bottom wall of the source trench 155 has been described.

[0782] However, the source insulating layer 156 may be formed along the side wall of the source trench 155 so as to expose the bottom wall of the source trench 155. The source insulating layer 156 may be formed along the side wall and the bottom wall of the source trench 155 so as to expose a part of the bottom wall of the source trench 155.

[0783] Further, the source insulating layer 156 may be formed along the bottom wall of the source trench 155 so as to expose the side wall of the source trench 155. The source insulating layer 156 may be formed along the side wall and the bottom wall of the source trench 155 so as to expose a part of the side wall of the source trench 155.

[0784] In the foregoing third to sixth embodiments, an example in which the gate electrode layer 149 and the gate wiring layer 150 including p-type polysilicon doped with p-type impurities are formed has been described. However, when not emphasizing the increase in the gate threshold voltage Vth, the gate electrode layer 149 and the gate wiring layer 150 may contain n-type polysilicon doped with n-type impurities instead of or in addition to p-type polysilicon.

[0785] In this case, the low-resistance electrode layer 167 may be formed by siliciding a portion forming the surface layer portion in the gate electrode layer 149 (n-type polysilicon) with a metal material. That is, the low-resistance electrode layer 167 may contain n-type polyside. In the case of such a structure, reduction of the gate resistance can be achieved.

[0786] In the foregoing third to sixth embodiments, n + type SiC semiconductor substrate 106 may be replaced with a p + type SiC semiconductor substrate (106). According to this structure, instead of the MISFET, an IGBT (Insulated Gate Bipolar Transistor) can be provided. In this case, in each of the foregoing embodiments, the "source" of the MISFET is read as the "emitter" of the IGBT, and the "drain" of the MISFET is read as the "collector" of the IGBT.

[0787] In each of the foregoing embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0788] Each of the above-described embodiments can also be applied to a semiconductor device using a semiconductor material different from SiC. The semiconductor material different from SiC may be a compound semiconductor material. The compound semiconductor material may be either one or both of gallium nitride (GaN) and gallium oxide (Ga2O3).

[0789] For example, the above-described third to sixth embodiments may be a compound semiconductor device including a vertical compound semiconductor MISFET in which a compound semiconductor material is employed instead of SiC. In the compound semiconductor, magnesium may be employed as a p-type impurity (acceptor). Also, germanium (Ge), oxygen (O), or silicon (Si) may be employed as an n-type impurity (donor).

[0790] The following shows characteristic examples extracted from this specification and the drawings.

[0791] [A1] An SiC semiconductor device including an SiC single crystal, an SiC semiconductor layer having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and side surfaces connecting the first main surface and the second main surface, a rough surface region formed on the side surface of the SiC semiconductor layer, and a smooth surface region formed in a region different from the...

Claims

1. a SiC chip having a laminated structure including a SiC substrate and a SiC epitaxial layer, the SiC chip including a first main surface on the SiC epitaxial layer side, a second main surface on the SiC substrate side, and a side surface; a first rough surface region formed on a portion of the side surface that is made of the SiC substrate; a second rough surface region formed in a portion of the side surface that is made of the SiC epitaxial layer; and a smooth surface region formed on the portion of the side surface that is made of the SiC substrate.

2. The SiC semiconductor device according to claim 1 , wherein the first main surface is formed by a silicon surface of a SiC single crystal.

3. 3. The SiC semiconductor device according to claim 1, wherein the first main surface has an off-angle inclined toward an a-axis of the SiC single crystal.

4. 4. The SiC semiconductor device according to claim 1, wherein the SiC epitaxial layer has an impurity concentration different from an impurity concentration of the SiC substrate.

5. The SiC semiconductor device according to any one of claims 1 to 4, wherein the SiC epitaxial layer has a thickness less than a thickness of the SiC substrate.

6. The SiC semiconductor device according to any one of claims 1 to 5, further comprising an insulating layer covering the first main surface.

7. The SiC semiconductor device according to claim 1 , further comprising a first electrode disposed on the first main surface.

8. The SiC semiconductor device according to claim 7 , wherein the first electrode is disposed on the first main surface at a distance from the side surface.

9. The SiC semiconductor device according to any one of claims 1 to 8, further comprising a resin layer covering the first main surface.

10. The SiC semiconductor device according to claim 9 , wherein the resin layer is disposed on the first main surface with a space therebetween from the side surface.

11. The SiC semiconductor device according to any one of claims 1 to 10, further comprising a second electrode covering the second main surface.

12. The SiC semiconductor device according to any one of claims 1 to 11, further comprising a semiconductor element formed on the first main surface.

13. The SiC semiconductor device according to claim 12 , wherein the semiconductor element includes a diode.

14. The SiC semiconductor device according to claim 12 , wherein the semiconductor element includes a field effect transistor.

15. The SiC semiconductor device according to any one of claims 1 to 14, wherein the first rough surface region is formed in a band shape extending along the first main surface.

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