Semiconductor device

Abstract

To provide a semiconductor device that has been improved in short-circuit resistance and reduces delay in gate signals.SOLUTION: First and second surface electrodes are arranged so that a finger wiring 3 extending in a first direction is interposed therebetween. A gate electrode 7 extends in a second direction. A third surface electrode connects the first surface electrode and the second surface electrode between the tip of the finger wiring 3 and a gate wiring 5. A finger wiring extension portion 3A extends in a direction from the tip of the finger wiring 3 toward the gate wiring 5 while avoiding the third surface electrode. In plan view, the gate electrode 7 crossing the third surface electrode is electrically connected to the finger wiring extension portion 3A.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] In a vertical semiconductor device in which current flows between the front surface and the back surface of a semiconductor substrate, a linear electrode called a gate liner or a finger electrode for transmitting a gate signal is provided. Such a linear electrode is arranged so as to divide an emitter electrode formed on the surface of the semiconductor substrate (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A gate liner as shown in Patent Document 1 improves the delay of a gate signal. On the other hand, since the emitter electrode is divided by the gate liner, the current distribution becomes unbalanced and the short-circuit withstand decreases.

[0005] An object of the present disclosure is to provide a semiconductor device that improves the short-circuit withstand and reduces the delay of a gate signal in order to solve the above problems.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes finger wirings, surface electrodes, gate wirings, and a plurality of gate electrodes. The finger wirings extend in a first direction in the plane of the semiconductor substrate. The surface electrodes include a first surface electrode and a second surface electrode arranged so as to sandwich the finger wirings. The gate wirings have an annular shape in plan view and are provided so as to surround the surface electrodes. The plurality of gate electrodes extend in a second direction in the plane of the semiconductor substrate. The surface electrodes include a third surface electrode. The third surface electrode is provided on an extension line of the finger wirings. The third surface electrode connects the first surface electrode and the second surface electrode between the tip of the finger wirings and the gate wirings. The finger wirings include finger wiring extension portions. The finger wiring extension portions extend from the tips of the finger wirings in the direction of the gate wirings while avoiding the third surface electrodes. Among the plurality of gate electrodes, the gate electrode that crosses the third surface electrode in plan view is electrically connected to the finger wiring extension portions.

Advantages of the Invention

[0007] According to the present disclosure, there is provided a semiconductor device with improved short-circuit tolerance and reduced delay of gate signals.

[0008] The object, features, aspects, and advantages of the present disclosure will become clearer from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

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Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

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Figure 17

Figure 18

Modes for Carrying Out the Invention

[0010] <Embodiment 1> FIG. 1 is a plan view showing the configuration of the semiconductor device 101 in Embodiment 1. FIG. 2 is an enlarged plan view showing the configuration of the semiconductor device 101. FIG. 2 shows the configuration in the region P shown in FIG. 1. Note that FIGS. 1 and 2 are for explanatory purposes and do not exactly match. FIGS. 1 and 2 show the upper surface of the semiconductor device 101, and the semiconductor device 101 is a vertical semiconductor device that controls the current flowing between the upper surface and the lower surface of the semiconductor substrate 10.

[0011] The semiconductor device 101 includes an active portion (not shown), a gate pad 1, an emitter electrode 2, a finger wiring 3, a finger wiring extension 3A, a gate wiring 5, a gate wiring extension 5A, and a plurality of gate electrodes 7.

[0012] The active portion is provided on a semiconductor substrate 10 (see FIG. 7) and is disposed inside the outer peripheral portion of the semiconductor substrate 10. The active portion includes semiconductor elements (not shown). The semiconductor elements are formed of a semiconductor such as Si, for example. The semiconductor is preferably a so-called wide bandgap semiconductor such as SiC, GaN, Ga2O3, GeO2, diamond, or the like. The semiconductor elements are power semiconductor elements, control ICs (Integrated Circuits) for controlling the power semiconductor elements, or the like. The semiconductor elements are, for example, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), Schottky barrier diodes, or the like. Alternatively, the semiconductor element may be an RC-IGBT (Reverse-Conducting IGBT) in which an IGBT and a freewheeling diode are formed in one semiconductor substrate 10. The semiconductor element in Embodiment 1 is an IGBT.

[0013] The gate pad 1 is provided on the upper surface of the semiconductor substrate 10. The gate pad 1 functions as a terminal to which a gate signal is input from the outside of the semiconductor device 101.

[0014] The emitter electrode 2 is a surface electrode provided on the active portion. The emitter electrode 2 includes a first emitter electrode 2A, a second emitter electrode 2B, and a third emitter electrode 2C. The first emitter electrode 2A corresponds to the first surface electrode. The second emitter electrode 2B corresponds to the second surface electrode. The third emitter electrode 2C corresponds to the third surface electrode.

[0015] The first emitter electrode 2A and the second emitter electrode 2B are arranged so as to sandwich the finger wiring 3. In other words, the first emitter electrode 2A is arranged on one side of the finger wiring 3, and the second emitter electrode 2B is arranged on the other side. As shown by the thick line in FIG. 2, the third emitter electrode 2C is provided on the extension line of the finger wiring 3. The third emitter electrode 2C is provided between the tip of the finger wiring 3 and the gate wiring 5 and connects the first emitter electrode 2A and the second emitter electrode 2B. The first emitter electrode 2A, the second emitter electrode 2B, and the third emitter electrode 2C are one component and are continuous without being divided except for the finger wiring 3, the finger wiring extension 3A, and the gate wiring extension 5A in the active part. In the drawing, it seems to be divided into stripes by a number of horizontal lines depicting a plurality of gate electrodes 7, but actually the emitter electrode 2 (2A, 2B, 2C) is continuously formed on the upper layer of the gate electrode 7.

[0016] The emitter electrode 2 is electrically insulated from the gate pad 1, the finger wiring 3, the finger wiring extension 3A, the gate wiring 5, the gate wiring extension 5A, and the gate electrode 7. That is, the emitter electrode 2 is electrically insulated from the electrodes and wirings through which the gate signal is transmitted. As the insulating material, for example, an oxide film or the like is used. In the plan views of FIGS. 1 and 2, for the sake of illustration, the emitter electrode 2 is drawn as if it is in contact with the finger wiring 3, the finger wiring extension 3A, the gate wiring 5, and the gate wiring extension 5A, but actually it is not in contact.

[0017] The finger wiring 3 extends in the first direction in the plane of the semiconductor substrate 10 and is arranged so as to vertically cross the active part. The first direction in Embodiment 1 corresponds to the vertical direction in FIG. 1. The finger wiring 3 is electrically connected to the gate pad 1. The finger wiring 3 is formed of a metal such as aluminum.

[0018] The finger wiring extension 3A extends from the tip of the finger wiring 3 in the direction of the gate wiring 5 while avoiding the third emitter electrode 2C. The finger wiring extension 3A in Embodiment 1 extends in the second direction from the tip of the finger wiring 3 and then further extends in the first direction. The second direction is orthogonal to the first direction. The second direction in Embodiment 2 corresponds to the lateral direction in FIGS. 1 and 2.

[0019] The gate wiring 5 has an annular shape in plan view. The gate wiring 5 is provided so as to surround the emitter electrode 2 provided in the active portion. The gate wiring 5 is electrically connected to the gate pad 1. The gate wiring 5 is formed of a metal such as aluminum.

[0020] The gate wiring extension 5A branches off from the gate wiring 5. The gate wiring extension 5A extends inside the annular shape of the gate wiring 5 while avoiding the third emitter electrode 2C. The gate wiring extension 5A in Embodiment 1 branches off from the gate wiring 5 and extends in the first direction.

[0021] The plurality of gate electrodes 7 extend in the second direction in the plane of the semiconductor substrate 10 and are provided via an insulating layer below the emitter electrode 2. Both ends of the gate electrode 7 are electrically connected to the gate wiring 5, for example. The gate electrode 7 is formed of, for example, polysilicon.

[0022] Of the plurality of gate electrodes 7, in a plan view, the gate electrode 7 that crosses the third emitter electrode 2C is electrically connected to one of the finger wiring extension 3A and the gate wiring extension 5A in the annular inner region of the gate wiring 5. As shown in FIG. 2, in Embodiment 1, a part of the gate electrode 7A is in contact with the gate wiring extension 5A. A part of the gate electrodes 7B and 7C is in contact with the finger wiring extension 3A. A part of the gate electrode 7D is in contact with the finger wiring extension 3A and the finger wiring 3. A part of the gate electrode 7E is in contact with the finger wiring 3. Thus, the gate electrode 7 is in contact with any one of the finger wiring 3, the finger wiring extension 3A, and the gate wiring extension 5A. In other words, the gate electrode 7 is electrically connected to the gate pad 1 via those wirings.

[0023] In such a configuration, since the third emitter electrode 2C connects the first emitter electrode 2A and the second emitter electrode 2B to each other, the potential at the emitter electrode 2 is stabilized.

[0024] When the gate electrode 7 is formed of polysilicon and the finger wiring 3 and the gate wiring 5 are formed of metal, the gate electrode 7 has a higher resistance value per unit length than the finger wiring 3 and the gate wiring 5. Therefore, the gate signal transmitted through the gate electrode 7 is delayed more than the gate signal transmitted through the finger wiring 3 or the gate wiring 5. However, the gate electrode 7 in the semiconductor device 101 of Embodiment 1 is electrically connected to any one of the finger wiring 3, the finger wiring extension 3A, and the gate wiring extension 5A in the annular inner region of the gate wiring 5. Therefore, the delay of the gate signal is reduced.

[0025] Summarizing the above, the semiconductor device 101 in Embodiment 1 includes a finger wiring 3, an emitter electrode 2, a gate wiring 5, and a plurality of gate electrodes 7. The finger wiring 3 extends in a first direction in the plane of the semiconductor substrate 10. The emitter electrode 2 includes a first emitter electrode 2A and a second emitter electrode 2B arranged so as to sandwich the finger wiring 3. The gate wiring 5 has an annular shape in plan view and is provided so as to surround the emitter electrode 2. The plurality of gate electrodes 7 extend in a second direction in the plane of the semiconductor substrate 10. The emitter electrode 2 includes a third emitter electrode 2C. The third emitter electrode 2C is provided on an extension line of the finger wiring 3. The third emitter electrode 2C connects the first emitter electrode 2A and the second emitter electrode 2B between the tip of the finger wiring 3 and the gate wiring 5. The finger wiring 3 includes a finger wiring extension 3A. The finger wiring extension 3A extends from the tip of the finger wiring 3 in the direction of the gate wiring 5 while avoiding the third emitter electrode 2C. Among the plurality of gate electrodes 7, the gate electrode 7 that crosses the third emitter electrode 2C in plan view is electrically connected to the finger wiring extension 3A. The emitter electrode 2 is a surface electrode, and its name may change depending on the type of semiconductor element formed on the semiconductor substrate 10.

[0026] In such a semiconductor device 101, although the finger wiring 3 is provided, the third emitter electrode 2C connects the first emitter electrode 2A and the second emitter electrode 2B. Therefore, the potential at the emitter electrode 2 is stabilized and the short-circuit withstand capacity is improved. Also, the gate electrode 7 is electrically connected to the finger wiring extension 3A. Therefore, the delay of the gate signal is reduced.

[0027] (Modification Example 1 of Embodiment 1) FIG. 3 is an enlarged plan view showing the configuration of the semiconductor device 101A in Modification 1 of Embodiment 1. The semiconductor device 101A includes a finger wiring extension 3A and a gate wiring extension 5B. The finger wiring extension 3A extends from the tip of the finger wiring 3 in the second direction and then further extends in the first direction, similar to Embodiment 1. The gate wiring extension 5B branches from the gate wiring 5, extends in the first direction, then extends in the second direction, and further extends in the first direction.

[0028] The gate electrodes 7A to 7D crossing the third emitter electrode 2C are electrically connected to one of the finger wiring extension 3A and the gate wiring extension 5B in the annular inner region of the gate wiring 5. Specifically, a part of the gate electrodes 7A and 7B is in contact with the gate wiring extension 5B. A part of the gate electrodes 7C and 7D is in contact with the finger wiring extension 3A.

[0029] Also, a part of the gate electrode 7E that does not cross the third emitter electrode 2C is in contact with the finger wiring 3. In this way, the gate electrode 7 is in contact with any one of the finger wiring 3, the finger wiring extension 3A, and the gate wiring extension 5B. The same effects as in Embodiment 1 can be obtained in the semiconductor device 101A.

[0030] (Modification 2 of Embodiment 1) FIG. 4 is an enlarged plan view showing the configuration of the semiconductor device 101B in Modification 2 of Embodiment 1. The semiconductor device 101B includes a gate wiring extension 5C. The finger wiring extension 3A is not provided. The gate wiring extension 5C branches from the gate wiring 5, extends in the first direction, and then bifurcates in the second direction. The tip of the gate wiring extension 5C further extends in the first direction.

[0031] The gate electrodes 7A to 7D crossing the third emitter electrode 2C are electrically connected to the gate wiring extension 5C in the annular inner region of the gate wiring 5. Specifically, a part of the gate electrodes 7A to 7D is in contact with the gate wiring extension 5C.

[0032] Also, a part of the gate electrode 7E that does not cross the third emitter electrode 2C is in contact with the finger wiring 3. In this way, the gate electrode 7 is in contact with either the finger wiring 3 or the gate wiring extension 5C. The semiconductor device 101B also has the same effect as that of the first embodiment.

[0033] (Modification Example 3 of the First Embodiment) FIG. 5 is an enlarged plan view showing the configuration of the semiconductor device 101C in Modification Example 3 of the first embodiment. The semiconductor device 101C includes a gate wiring extension 5D. A finger wiring extension 3A is not provided. The gate wiring extension 5D includes a plurality of branch wirings 51D and 52D. The plurality of branch wirings 51D and 52D branch from a plurality of branch points in the gate wiring 5 and extend in the first direction.

[0034] The gate electrodes 7A and 7B that cross the third emitter electrode 2C are electrically connected to the gate wiring extension 5D in the annular inner region of the gate wiring 5. Specifically, a part of the gate electrodes 7A and 7B is in contact with the gate wiring extension 5D.

[0035] Also, a part of the gate electrodes 7C to 7E that do not cross the third emitter electrode 2C is in contact with the finger wiring 3. In this way, the gate electrode 7 is in contact with either the finger wiring 3 or the gate wiring extension 5D. The semiconductor device 101C also has the same effect as that of the first embodiment.

[0036] <Second Embodiment> FIG. 6 is a plan view showing the configuration of the semiconductor device 102 in the second embodiment. FIG. 6 shows the configuration around the third emitter electrode 2C.

[0037] The finger wiring extension 3A extends in the second direction from the tip of the finger wiring 3 and then further extends in the first direction. The gate wiring extension 5A branches from the gate wiring 5 and extends in the first direction.

[0038] Of the gate electrodes 7A to 7D crossing the third emitter electrode 2C, at least one of the finger wiring extension 3A and the gate wiring extension 5A is electrically connected in the annular inner region of the gate wiring 5. Specifically, a part of the gate electrode 7A is in contact with the gate wiring extension 5A. Parts of the gate electrodes 7B and 7C are in contact with both the gate wiring extension 5A and the finger wiring extension 3A. A part of the gate electrode 7D is in contact with the finger wiring extension 3A.

[0039] FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device 102. FIG. 7 shows the configuration of the cross-section along A-A' shown in FIG. 6. In the plan view of FIG. 6, the emitter electrode 2 is drawn as being in contact with the finger wiring extension 3A and the gate wiring extension 5A, but actually it is not in contact as shown in FIG. 7. Also, an oxide film 11 is formed below the wiring, and the emitter electrode 2 is insulated from the finger wiring extension 3A and the gate wiring extension 5A. The gate electrode 7C is in contact with the gate wiring extension 5A and the finger wiring extension 3A, respectively. In such a configuration, the delay of the gate signal is further reduced.

[0040] <Embodiment 3> FIG. 8 is a plan view showing the configuration of the semiconductor device 103 in Embodiment 3. FIG. 8 shows the configuration around the third emitter electrode 2C. The finger wiring extension 3A and the gate wiring extension 5A are not provided.

[0041] Among the plurality of gate electrodes 7, in a plan view, the gate electrodes 7A and 7B provided below the third emitter electrode 2C include a gate connection wiring 8A. The gate connection wiring 8A bends and extends in the first direction below the third emitter electrode 2C. The gate connection wiring 8A is electrically connected to the gate wiring 5 in the region outside the third emitter electrode 2C.

[0042] The gate electrodes 7A and 7B provided below the third emitter electrode 2C are electrically connected to the gate wiring 5 via the gate connection wiring 8A. Therefore, the delay of the gate signal is reduced. Further, since the finger wiring extension part 3A and the gate wiring extension part 5A are not provided, a decrease in the effective area that operates as an IGBT in the active part is suppressed.

[0043] (Modification of Embodiment 3) FIG. 9 is a plan view showing the configuration of the semiconductor device 103A in the modification of Embodiment 3. FIG. 10 is a cross-sectional view showing the configuration of the semiconductor device 103A. FIG. 10 shows a cross-section taken along B-B' shown in FIG. 9.

[0044] Among the plurality of gate electrodes 7, in a plan view, the gate electrodes 7A and 7B provided below the third emitter electrode 2C each include the gate connection wirings 8A and 8B. The gate connection wiring 8A bends and extends in the first direction below the third emitter electrode 2C. The gate connection wiring 8A is electrically connected to the gate wiring 5 in a region outside the third emitter electrode 2C. The gate connection wiring 8B bends and extends in the first direction below the third emitter electrode 2C, but bends in the direction opposite to the gate connection wiring 8A. The gate connection wiring 8B is electrically connected to the finger wiring 3 in a region outside the third emitter electrode 2C.

[0045] The gate electrode 7A is electrically connected to the gate wiring 5 via the gate connection wiring 8A. The gate electrode 7B is electrically connected to the finger wiring 3 via the gate connection wiring 8B. Therefore, the delay of the gate signal is reduced. Further, since the finger wiring extension part 3A and the gate wiring extension part 5A are not provided, a decrease in the effective area that operates as an IGBT in the active part is suppressed.

[0046] <Embodiment 4> FIG. 11 is a plan view showing the configuration of the semiconductor device 104 in Embodiment 4. FIG. 12 is a cross-sectional view showing the configuration of the semiconductor device 104. FIG. 12 shows a cross-section taken along C-C' shown in FIG. 11.

[0047] The semiconductor device 104 includes a plurality of trenches 12. The plurality of trenches 12 are provided in the semiconductor substrate 10 and extend in the second direction. A plurality of gate electrodes 7 are respectively formed in the plurality of trenches 12. Since the gate electrode 7 is embedded in the trench 12, the JFET (Junction Field Effect Transistor) resistance is reduced.

[0048] <Embodiment 5> FIG. 13 is a plan view showing the configuration of the semiconductor device 105 in Embodiment 5. FIG. 13 shows the configuration around the third emitter electrode 2C. FIG. 14 is a diagram showing a schematic three-dimensional shape of the electrode (AlSi) in the emitter connection region.

[0049] The second emitter electrode 2B includes a fourth emitter electrode 2D. The fourth emitter electrode 2D corresponds to the fourth surface electrode. The fourth emitter electrode 2D is provided between the tip of the finger wiring extension 3A in the first direction and the gate wiring 5.

[0050] Let the length of the third emitter electrode 2C in the first direction and the width of the fourth emitter electrode 2D in the second direction be x. Let the width of the third emitter electrode 2C in the second direction and the length of the fourth emitter electrode 2D in the first direction be y. Let the thickness of the chip be z. Let the resistivity be ρ.

[0051] When the pitch of the gate electrode 7 is 2.4 μm, it is desirable that the third emitter electrode 2C and the fourth emitter electrode 2D satisfy the following equations (1) and (2).

[0052]

Equation

[0053] When the pitch of the gate electrode 7 is 4.0 μm, it is desirable that the third emitter electrode 2C and the fourth emitter electrode 2D satisfy the following equations (3) and (4).

[0054]

Equation

[0055] Equations (1) and (3) are equations related to the inductance in the emitter electrode region. Equations (2) and (4) are equations related to the resistance. When both the inductance and the resistance are low, the short-circuit tolerance is improved.

[0056] <Embodiment 6> FIG. 15 is a plan view showing the configuration of the semiconductor device 106 in Embodiment 6. FIG. 15 shows the configuration around the third emitter electrode 2C. The semiconductor device 106 includes the island wiring 13.

[0057] The island wiring 13 is provided in a region where one of the first emitter electrode 2A and the second emitter electrode 2B is arranged. In FIG. 15, the island wiring 13 is provided in the region where the second emitter electrode 2B is arranged. The island wiring 13 is electrically insulated from the first emitter electrode 2A and the second emitter electrode 2B. On the other hand, the island wiring 13 is electrically connected to the gate electrode 7C that crosses the third emitter electrode 2C and the gate electrodes 7B and 7D other than the gate electrode 7C that crosses the third emitter electrode 2C among the plurality of gate electrodes 7.

[0058] A part of the gate electrode 7B is in contact with the gate wiring extension 5A and the island wiring 13. A part of the gate electrode 7C is in contact with the island wiring 13. A part of the gate electrode 7D is in contact with the finger wiring 3 and the island wiring 13. That is, the gate electrode 7C crossing the third emitter electrode 2C is electrically connected to the finger wiring 3 and the gate wiring extension 5A via the island wiring 13. Even with such a configuration, the same effects as those in the first embodiment can be obtained.

[0059] Even if the gate electrode 7C is electrically connected to either the finger wiring 3 or the gate wiring extension 5A via the island wiring 13, the same effects as described above can be obtained. Also, although not shown in the figure, when the finger wiring extension 3A is provided, the island wiring 13 may be electrically connected to the finger wiring extension 3A. In that case, the gate electrode 7C crossing the third emitter electrode 2C is electrically connected to the finger wiring extension 3A via the island wiring 13. That is, the gate electrode 7C only needs to be electrically connected to any one of the finger wiring 3, the finger wiring extension 3A, and the gate wiring extension 5A via the island wiring 13.

[0060] <Embodiment 7> FIG. 16 is a diagram showing the configuration of the semiconductor device 107A in Embodiment 7. As shown in FIG. 16, the semiconductor device 107A includes a wire 14 that connects the first emitter electrode 2A and the second emitter electrode 2B. The potential of the first emitter electrode 2A and the potential of the second emitter electrode 2B are stabilized, and the short-circuit tolerance is further improved.

[0061] FIG. 17 is a diagram showing the configuration of the semiconductor device 107B in Embodiment 7. As shown in FIG. 17, the semiconductor device 107B includes a metal plate 15 that connects the first emitter electrode 2A and the second emitter electrode 2B. The metal plate 15 is directly bonded to the first emitter electrode 2A and the second emitter electrode 2B by, for example, DLB (direct lead bonding). The potential of the first emitter electrode 2A and the potential of the second emitter electrode 2B are stabilized, and the short-circuit withstand capacity is further improved. The heat dissipation during the switching operation is also improved.

[0062] <Embodiment 8> FIG. 18 is a diagram showing the configuration of the semiconductor device 108 in Embodiment 8. The semiconductor device 108 includes a plurality of finger wirings 3 and a plurality of gate wiring extension parts 5A. Although not shown, the semiconductor device 108 may include a plurality of finger wiring extension parts 3A. That is, the number of the finger wirings 3, the finger wiring extension parts 3A, and the gate wiring extension parts 5A may be two or more. In FIG. 18, when the left finger wiring 3 is used as a reference, the electrode on the left side of the finger wiring 3 is the first emitter electrode 2A, and the electrode on the right side is the second emitter electrode 2B. When the right finger wiring 3 is used as a reference, the electrode on the left side of the finger wiring 3 is the first emitter electrode 2A, and the electrode on the right side is the second emitter electrode 2B. The electrode shown in the center of FIG. 18 may be defined as the first emitter electrode 2A or the second emitter electrode 2B by the reference finger wiring 3.

[0063] When the emitter electrode 2 is divided into three or more regions, two or more finger wirings 3, finger wiring extension parts 3A, and gate wiring extension parts 5A are provided respectively, so that the delay of the gate signal is reduced and the short-circuit withstand capacity is improved.

[0064] In the present disclosure, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

[0065] Hereinafter, various aspects of the present disclosure will be collectively described as appendices.

[0066] (Appendix 1) Finger wiring extending in a first direction in the plane of the semiconductor substrate, A surface electrode including a first surface electrode and a second surface electrode disposed so as to sandwich the finger wiring, A gate wiring having an annular shape in plan view and provided so as to surround the surface electrode, A plurality of gate electrodes extending in a second direction in the plane of the semiconductor substrate, and comprising, The surface electrode includes a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between a tip of the finger wiring and the gate wiring, The finger wiring includes a finger wiring extension portion that extends from the tip of the finger wiring in the direction of the gate wiring while avoiding the third surface electrode, Among the plurality of gate electrodes, in plan view, a gate electrode that crosses the third surface electrode is electrically connected to the finger wiring extension portion, a semiconductor device.

[0067] (Appendix 2) The finger wiring extension portion, After extending from the tip of the finger wiring in the second direction, it further extends in the first direction, the semiconductor device according to Appendix 1.

[0068] (Appendix 3) The gate wiring includes a gate wiring extension portion that branches from the gate wiring and extends inside the annular shape of the gate wiring while avoiding the third surface electrode, The gate electrode that crosses the third surface electrode is electrically connected to at least one of the gate wiring extension portion and the finger wiring extension portion, the semiconductor device according to Appendix 1 or Appendix 2.

[0069] (Appendix 4) The gate wiring extension portion, The semiconductor device according to Supplementary Note 3, which branches off from the gate wiring, extends in the first direction, then extends in the second direction, and further extends in the first direction.

[0070] (Supplementary Note 5) A finger wiring extending in a first direction in the plane of a semiconductor substrate, A surface electrode including a first surface electrode and a second surface electrode arranged so as to sandwich the finger wiring, A gate wiring having an annular shape in plan view and provided so as to surround the surface electrode, A plurality of gate electrodes extending in a second direction in the plane of the semiconductor substrate, and comprising: The surface electrode includes a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between a tip of the finger wiring and the gate wiring. The gate wiring includes a gate wiring extension portion that branches off from the gate wiring, avoids the third surface electrode, and extends inside the annular shape of the gate wiring. Among the plurality of gate electrodes, in plan view, a gate electrode crossing the third surface electrode is electrically connected to the gate wiring extension portion. A semiconductor device.

[0071] (Supplementary Note 6) The gate wiring extension portion branches off from the gate wiring, extends in the first direction, and then branches into two in the second direction, The tip of the gate wiring extension portion extends in the first direction. A semiconductor device according to Supplementary Note 5.

[0072] (Supplementary Note 7) The gate wiring extension portion includes a plurality of branch wirings that branch off from a plurality of branch points in the gate wiring and extend in the first direction respectively. A semiconductor device according to Supplementary Note 5 or Supplementary Note 6.

[0073] (Supplementary Note 8) The semiconductor device according to appended claim 3, wherein the gate electrode crossing the third surface electrode is electrically connected to both the gate wiring extension and the finger wiring extension.

[0074] (Appended claim 9) A finger wiring extending in a first direction in the plane of a semiconductor substrate, A surface electrode including a first surface electrode and a second surface electrode arranged so as to sandwich the finger wiring, A gate wiring having an annular shape in plan view and provided so as to surround the surface electrode, A plurality of gate electrodes extending in a second direction in the plane of the semiconductor substrate, and comprising: The surface electrode includes a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between a tip of the finger wiring and the gate wiring. Among the plurality of gate electrodes, in plan view, the gate electrode provided below the third surface electrode includes a gate connection wiring. The gate connection wiring bends and extends in the first direction below the third surface electrode, and is electrically connected to the gate wiring in a region outside the third surface electrode. A semiconductor device.

[0075] (Appended claim 10) The semiconductor device according to appended claim 9, wherein the gate connection wiring bends and extends in the first direction below the third surface electrode, and is electrically connected to the finger wiring in a region outside the third surface electrode.

[0076] (Appended claim 11) The semiconductor device according to any one of appended claims 1 to 10, wherein the plurality of gate electrodes are formed in a plurality of trenches provided in the semiconductor substrate and extending in the second direction.

[0077] (Appended claim 12) The second surface electrode includes a fourth surface electrode provided between a tip of the finger wiring extension in the first direction and the gate wiring. When the length of the third surface electrode in the first direction and the width of the fourth surface electrode in the second direction are defined as x, the width of the third surface electrode in the second direction and the length of the fourth surface electrode in the first direction are defined as y, and the thickness of the chip is defined as z, the semiconductor device according to Supplementary Note 1, wherein the third surface electrode and the fourth surface electrode satisfy the following two equations.

[0078]

Number

[0079] (Supplementary Note 13) The first surface electrode includes a fourth surface electrode provided between the tip of the finger wiring extension in the first direction and the gate wiring. When the length of the third surface electrode in the first direction and the width of the fourth surface electrode in the second direction are defined as x, the width of the third surface electrode in the second direction and the length of the fourth surface electrode in the first direction are defined as y, and the thickness of the chip is defined as z, the semiconductor device according to Supplementary Note 1, wherein the third surface electrode and the fourth surface electrode satisfy the following two equations.

[0080]

Number

[0081] (Supplementary Note 14) An island wiring provided in a region where one of the first surface electrode and the second surface electrode is disposed, and insulated from the first surface electrode and the second surface electrode is further provided. The island wiring is electrically connected to a gate electrode crossing the third surface electrode and a gate electrode other than the gate electrode crossing the third surface electrode among the plurality of gate electrodes. The gate electrode crossing the third surface electrode is electrically connected to either the finger wiring or the gate wiring extension via the island wiring. The semiconductor device according to any one of Supplementary Notes 3 to 8.

[0082] (Appendix 15) The semiconductor device according to any one of Appendices 1 to 14, further comprising a wire connecting the first surface electrode and the second surface electrode.

[0083] (Appendix 16) The semiconductor device according to any one of Appendices 1 to 15, further comprising a metal plate connecting the first surface electrode and the second surface electrode.

[0084] (Appendix 17) The semiconductor device according to Appendix 3 or Appendix 4, wherein the number of the finger wiring, the finger wiring extension, and the gate wiring extension is two or more.

Explanation of Reference Numerals

[0085] 1 Gate pad, 2 Emitter electrode, 2A First emitter electrode, 2B Second emitter electrode, 2C Third emitter electrode, 2D Fourth emitter electrode, 3 Finger wiring, 3A Finger wiring extension, 5 Gate wiring, 5A to 5D Gate wiring extensions, 7 Gate electrode, 7A to 7E Gate electrodes, 8A to 8B Gate connection wiring, 10 Semiconductor substrate, 11 Oxide film, 12 Trench, 13 Island wiring, 14 Wire, 15 Metal plate, 51D to 52D Branch wiring, 101 to 108 Semiconductor devices.

Claims

1. Finger wiring extending in a first direction in the plane of a semiconductor substrate, A surface electrode including a first surface electrode and a second surface electrode arranged so as to sandwich the finger wiring, A gate wiring having an annular shape in plan view and provided so as to surround the surface electrode, A plurality of gate electrodes extending in a second direction in the plane of the semiconductor substrate, and comprising: The surface electrode includes a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between a tip of the finger wiring and the gate wiring. The finger wiring includes a finger wiring extension portion that extends from the tip of the finger wiring in the direction of the gate wiring while avoiding the third surface electrode. Among the plurality of gate electrodes, in plan view, a gate electrode that crosses the third surface electrode is electrically connected to the finger wiring extension portion. A semiconductor device.

2. The finger wiring extension portion: After extending in the second direction from the tip of the finger wiring, it further extends in the first direction. The semiconductor device according to claim 1.

3. The gate wiring includes a gate wiring extension portion that branches from the gate wiring and extends inside the annular shape of the gate wiring while avoiding the third surface electrode. The gate electrode that crosses the third surface electrode is electrically connected to at least one of the gate wiring extension portion and the finger wiring extension portion. The semiconductor device according to claim 1.

4. The gate wiring extension portion: After branching from the gate wiring and extending in the first direction, it extends in the second direction and further extends in the first direction. The semiconductor device according to claim 3.

5. Finger wiring extending in a first direction in the plane of a semiconductor substrate, A surface electrode including a first surface electrode and a second surface electrode arranged so as to sandwich the finger wiring, A gate wiring having an annular shape in plan view and provided so as to surround the surface electrode, A plurality of gate electrodes extending in a second direction in the plane of the semiconductor substrate, and comprising: The surface electrode includes a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between a tip of the finger wiring and the gate wiring. The gate wiring includes a gate wiring extension portion that branches off from the gate wiring, avoids the third surface electrode, and extends inside the annular shape of the gate wiring. Among the plurality of gate electrodes, in a plan view, the gate electrode that crosses the third surface electrode is electrically connected to the gate wiring extension portion. A semiconductor device. **Claim 6** The gate wiring extension portion branches off from the gate wiring, extends in the first direction, and then bifurcates in the second direction. The tip of the gate wiring extension portion extends in the first direction. The semiconductor device according to claim 5. **Claim 7** The gate wiring extension portion includes a plurality of branch wirings that branch off from a plurality of branch points in the gate wiring and extend in the first direction respectively. The semiconductor device according to claim 5. **Claim 8** The gate electrode that crosses the third surface electrode is electrically connected to both the gate wiring extension portion and the finger wiring extension portion. The semiconductor device according to claim 3. **Claim 9** Finger wiring extending in a first direction in the plane of the semiconductor substrate, a surface electrode including a first surface electrode and a second surface electrode arranged so as to sandwich the finger wiring, gate wiring having an annular shape in a plan view and provided so as to surround the surface electrode, and a plurality of gate electrodes extending in a second direction in the plane of the semiconductor substrate. The surface electrode includes a third surface electrode provided on an extension line of the finger wiring and connecting the first surface electrode and the second surface electrode between the tip of the finger wiring and the gate wiring. Among the plurality of gate electrodes, in a plan view, the gate electrode provided below the third surface electrode includes a gate connection wiring. The gate connection wiring bends and extends in the first direction below the third surface electrode and is electrically connected to the gate wiring in a region outside the third surface electrode. A semiconductor device. **Claim 10** The gate connection wiring bends and extends in the first direction below the third surface electrode and is electrically connected to the finger wiring in a region outside the third surface electrode. The semiconductor device according to claim 9. **Claim 11** The plurality of gate electrodes are formed in a plurality of trenches provided in the semiconductor substrate and extending in the second direction. The semiconductor device according to any one of claims 1, 5, and 9. **Claim 12** The second surface electrode includes a fourth surface electrode provided between a tip of the finger wiring extension portion in the first direction and the gate wiring. When the length of the third surface electrode in the first direction and the width of the fourth surface electrode in the second direction are set as x, the width of the third surface electrode in the second direction and the length of the fourth surface electrode in the first direction are set as y, and the thickness of the chip is set as z, the semiconductor device according to claim 1, wherein the third surface electrode and the fourth surface electrode satisfy the following two equations. 【Number 1】

13. The first surface electrode includes a fourth surface electrode provided between a tip of the finger wiring extension portion in the first direction and the gate wiring. When the length of the third surface electrode in the first direction and the width of the fourth surface electrode in the second direction are set as x, the width of the third surface electrode in the second direction and the length of the fourth surface electrode in the first direction are set as y, and the thickness of the chip is set as z, the semiconductor device according to claim 1, wherein the third surface electrode and the fourth surface electrode satisfy the following two equations. 【Number 2】

14. An island wiring is further provided in a region where one of the first surface electrode and the second surface electrode is disposed, and the island wiring is insulated from the first surface electrode and the second surface electrode. The island wiring is electrically connected to a gate electrode crossing the third surface electrode and a gate electrode other than the gate electrode crossing the third surface electrode among the plurality of gate electrodes. The semiconductor device according to claim 3 or claim 5, wherein the gate electrode crossing the third surface electrode is electrically connected to either the finger wiring or the gate wiring extension portion via the island wiring.

15. The semiconductor device according to any one of claims 1, 5, and 9, further comprising a wire connecting the first surface electrode and the second surface electrode.

16. The semiconductor device according to any one of claims 1, 5, and 9, further comprising a metal plate connecting the first surface electrode and the second surface electrode.

17. The semiconductor device according to claim 3, wherein the number of the finger wirings, the finger wiring extension portions, and the gate wiring extension portions is two or more.

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