Evaluation device and evaluation method of complexity of circuit

Abstract

To provide a technique for evaluating complexity of model data of a circuit.SOLUTION: An evaluation device 10 includes: a model analysis part 110 for analyzing model data 100 of a circuit; a complexity evaluation part 120 for evaluating each complexity of one or more blocks 101 constituting the model data 100 obtained by analysis, and each complexity of routes of one or more signals 102; and a complexity calculation part 130 for calculating the complexity of the circuit, on the basis of each of the complexity of the one or more blocks 101, and each of the complexity of the routes of the one or more signals 102. The model data 100 includes each positional information of the one or more blocks 101 associated with the order of data processing. The model analysis part 110 analyzes the positional information, thereby determines presence / absence of the blocks 101 executed at the same time, and determines each type of the one or more signals 102.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a technique for evaluating the complexity of a circuit, and more specifically, to a technique for evaluating the complexity of circuit model data.

Background Art

[0002] In the development of circuits such as LSI (Large Scale Integration), the complexity of the circuit is used as an index to determine the design quality of the circuit. The complexity of the circuit indicates the difficulty of circuit design. When the complexity of the circuit is extremely high, it becomes difficult to design and ensure the quality of the circuit.

[0003] Designers can appropriately predict the design quality of a circuit by quantitatively measuring the complexity of the circuit. Also, when newly developing a circuit, designers can easily estimate the development man-hours by grasping in advance the complexity of the circuit planned to be designed. Furthermore, the development supervisor can ensure the efficiency and quality of circuit development by having capable designers take charge of developing circuits with high complexity.

[0004] Regarding the technique for evaluating the complexity of a circuit, for example, Japanese Patent Application Laid-Open No. 2016-081287 (Patent Document 1) discloses "a method for evaluating the complexity of a hardware circuit using a computer, wherein a processor included in the computer extracts the substitution type of a combinational circuit description sentence from a source file designed by a hardware description language stored in a memory included in the computer, and for each of the extracted substitution types, obtains a first complexity of an element related to the combinational circuit description sentence, and based on the relevance, the computer performs a process of obtaining a second complexity for each of the substitution types using the first complexity" (see [Summary]).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] According to the technology disclosed in Patent Document 1, it is not possible to evaluate the complexity of the model data of circuits designed using Model-Based Development (MBD), which has become popular in recent years. Therefore, there is a need for technology to evaluate the complexity of circuit model data.

[0007] This disclosure is made in view of the above-mentioned background, and in one aspect, its purpose is to provide a technique for evaluating the complexity of circuit model data. [Means for solving the problem]

[0008] According to one embodiment, a circuit evaluation device is provided. The evaluation device comprises a model analysis unit that analyzes model data of a circuit; a complexity evaluation unit that evaluates the complexity of each of the one or more blocks constituting the model data obtained by the analysis, and the complexity of each of the one or more signals; and a complexity calculation unit that calculates the complexity of the circuit based on the complexity of each of the one or more blocks and the complexity of each of the one or more signals. The model data includes positional information of each of the one or more blocks associated with the order of data processing. Model The analysis unit analyzes location information to determine whether there are any blocks being executed simultaneously and to determine the type of each of the one or more signals. [Effects of the Invention]

[0009] According to one embodiment, the complexity of the circuit model data can be evaluated.

[0010] The above and other purposes, features, aspects and advantages of this disclosure will become apparent from the following detailed description of this disclosure, which will be understood in conjunction with the attached drawings. [Brief explanation of the drawing]

[0011] [Figure 1] It is a diagram showing an example of the configuration of the circuit evaluation device 10. [Figure 2] It is a diagram showing an example of the configuration of the model analysis unit 110. [Figure 3] It is a diagram showing an example of the configuration of the complexity evaluation unit 120. [Figure 4] It is a diagram showing an example of the hardware configuration of the evaluation device 10. [Figure 5] It is a diagram showing an example of the model data 100 of the circuit to be evaluated. [Figure 6] It is a diagram showing an example of the expression of the configuration of the conditional branch 518. [Figure 7] It is a diagram showing another example of the expression of the configuration of the conditional branch 518. [Figure 8] It is a diagram showing an example of the block type table 800. [Figure 9] It is a diagram showing an example of the classification procedure of the block. [Figure 10] It is a diagram showing a part of the model data 100. [Figure 11] It is a diagram showing a part of the model data 100 after the sorting process. [Figure 12] It is a diagram showing an example of the analysis procedure of the position of the block. [Figure 13] It is a diagram showing an example of the signal connection table 1300. [Figure 14] It is a diagram showing an example of the analysis procedure of the connection relationship of the signal. [Figure 15] It is a diagram showing an example of the evaluation procedure of the conditional branch complexity. [Figure 16] It is a diagram showing an example of the evaluation procedure of the feedback complexity. [Figure 17] It is a diagram showing an example of the function complexity table 1700. <00000δ8>It is a diagram showing an example of the evaluation procedure of the function complexity of the block. [Figure 19] It is a diagram showing an example of the model data 1900 in another format.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the technical idea according to the present disclosure will be described while referring to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed descriptions thereof will not be repeated. Also, each embodiment, each modification example, each software configuration, each hardware configuration, each function, and each process, etc. may be selectively combined as appropriate.

[0013] <A. Configuration Example of Evaluation Device> First, an overview of an evaluation device 10 (see FIG. 1) for a circuit according to the present embodiment will be described while comparing it with an evaluation device for the complexity of a conventional circuit (hereinafter referred to as the “conventional device”).

[0014] As described above, in recent years, model-based development has become widespread. In the process of circuit design, model data is converted into source code of a hardware description language (HDL (Hardware Description Language)).

[0015] The conventional device can evaluate the complexity of the HDL source code, but cannot evaluate the complexity of the model data. Therefore, when using the conventional device, a circuit developer needs to once convert the model data into source code and input the source code into the conventional device.

[0016] However, when the model data is converted into source code, depending on the specifications of the conversion tool, source code including redundant descriptions or optimized descriptions may be generated. Therefore, the complexity output by the conventional device is affected by the conversion tool. As a result, the complexity output by the conventional device may deviate from the original complexity of the circuit.

[0017] In contrast, the evaluation device 10 directly calculates complexity from the model data by analyzing each block and signal contained in the model data. Each block contained in the model data represents each function of the circuit. Each signal contained in the model data represents the input / output of a signal or a signal line. The configuration and operation overview of the evaluation device 10 will be described below with reference to Figures 1 to 4.

[0018] (a. Functions of the evaluation device) Figure 1 shows an example of the configuration of a circuit evaluation device 10. The evaluation device 10 evaluates the complexity of the circuit model data 100. The evaluation device 10 includes a model analysis unit 110, a complexity evaluation unit 120, and a complexity calculation unit 130.

[0019] Model data 100 is designed using a model-based development tool such as Simulink®. Model data 100 consists of blocks 101 and signals 102. Block 101 indicates inputs, outputs, and other optional functions. Signal 102 indicates the direction or wiring of the signal input and output.

[0020] The model analysis unit 110 analyzes the model data 100. The complexity of the model data 100 is determined by the function of each block 101 that makes up the model data 100, the number of conditional branches, and the number of feedback loops (also called feedback signals). Therefore, the model analysis unit 110 analyzes the types of blocks 101 included in the model data 100, the number of conditional branches, and the number of feedback loops. In other words, the model analysis unit 110 analyzes the model data 100 based on the functions of the circuit represented by the model data 100. The model analysis unit 110 outputs the analysis results to the complexity evaluation unit 120.

[0021] The complexity evaluation unit 120 evaluates the analysis results individually. More specifically, the complexity evaluation unit 120 individually calculates or evaluates the functional complexity, conditional branch complexity, and feedback complexity of each block 101. The complexity evaluation unit 120 outputs the functional complexity, conditional branch complexity, and feedback complexity to the complexity calculation unit 130.

[0022] The complexity calculation unit 130 calculates the complexity of the model data 100 as a complexity calculation result value based on each complexity obtained from the complexity evaluation unit 120. In a given situation, the complexity calculation unit 130 may sum up each complexity. That is, the complexity calculation unit 130 may sum up the functional complexity, conditional branch complexity, and feedback complexity.

[0023] In other situations, the complexity calculation unit 130 may multiply each complexity by an individual coefficient. In this case, the complexity calculation unit 130 multiplies the functional complexity by a first coefficient. The complexity calculation unit 130 multiplies the conditional branch complexity by a second coefficient. The complexity calculation unit 130 multiplies the feedback complexity by a third coefficient. Then, the complexity calculation unit 130 sums up the functional complexity, conditional branch complexity, and feedback complexity after multiplying by the coefficients. The type of block 101, the number of conditional branches, and the presence or absence of feedback signals can each have a significant impact on the complexity of the model data 100. By multiplying each complexity by an individual coefficient, the complexity calculation unit 130 can more accurately calculate the overall complexity of the circuit (model data 100).

[0024] Figure 2 shows an example of the configuration of the model analysis unit 110. The functions of the model analysis unit 110 will be explained in more detail with reference to Figure 2. The model analysis unit 110 comprises a block type analysis unit 200, a block position analysis unit 210, and a signal connection analysis unit 220.

[0025] The block type analysis unit 200 analyzes the type or function of all blocks 101 included in the input model data 100. For example, each block 101 has various functions such as input, output, comparison operation, conditional branching, and filtering. In other aspects, each block 101 may have multiple functions. The block type analysis unit 200 outputs information on the type or function of all blocks 101 as an analysis result to the complexity evaluation unit 120. The block type analysis unit 200 can generate a block type table 800 (see Figure 8) as an analysis result.

[0026] The block position analysis unit 210 analyzes the positions of all blocks 101 included in the model data 100. The block position analysis unit 210 outputs the position information of each block 101 as an analysis result to the signal connection analysis unit 220.

[0027] Each block 101 is arranged chronologically according to the order in which it is executed. Each block 101 in the model data 100 can be arranged based on various formats. For example, the model data 100 is defined as information including coordinate information, as shown in Figure 5. In this case, the position of each block 101 is represented by coordinates in a two-dimensional space consisting of a first axis and a second axis. The first axis indicates the time series of data processing in the circuit (model data 100). The second axis indicates the direction in which one or more blocks are arranged in parallel. In this case, the block position analysis unit 210 analyzes the position of each block 101 based on the coordinates. The block position analysis unit 210 can also analyze the execution order of each block 101 and the presence or absence of blocks 101 that are executed simultaneously, based on the position (also called coordinates) of each block 101 in the first axis direction.

[0028] As another example, model data 100 is defined as information that does not use coordinates, but only indicates the execution order of each block 101, as shown in Figure 19. In this case, the block position analysis unit 210 analyzes the position of each block 101 based on the execution time (also called delay) of each block. The block position analysis unit 210 can also analyze the execution order of each block 101, and whether or not there are any other blocks 101 that are executed simultaneously, based on the delay of each block 101.

[0029] In certain situations, the block position analysis unit 210 may adjust the coordinates of some of the blocks 101 in the model data 100 based on the results of the analysis. More specifically, the block position analysis unit 210 may align or synchronize the positions (coordinates) of the blocks 101 in the first axis direction that are being executed simultaneously.

[0030] The signal connection analysis unit 220 analyzes the connection relationships of all signals 102 based on the position information of each block 101. The signal connection analysis unit 220 outputs information on the connection relationships of all signals 102 as an analysis result to the complexity evaluation unit 120. In some cases, the signal connection analysis unit 220 may also output information on the position information of each block 101 and information on simultaneously executed blocks 101 to the complexity evaluation unit 120. The signal connection analysis unit 220 may generate a signal connection table 1300 (see Figure 13) as an analysis result.

[0031] In one scenario, the connection relationship of each signal 102 may include information about the source block 101 and the input block 101 of each signal 102. In another scenario, the connection relationship of each signal 102 may include information about the start and end coordinates of each signal 102. Furthermore, in yet another scenario, the connection relationship of each signal 102 may include information about the source block 101, the input block 101, the start coordinates, and the end coordinates of each signal 102.

[0032] In some situations, the processing of the block type analysis unit 200 may be performed in parallel with the processing of the block position analysis unit 210 and the signal connection analysis unit 220. In other situations, the processing of the block type analysis unit 200, the processing of the block position analysis unit 210, and the processing of the signal connection analysis unit 220 may be performed sequentially.

[0033] Figure 3 shows an example of the configuration of the complexity evaluation unit 120. The functions of the complexity evaluation unit 120 will be explained in more detail with reference to Figure 3. The complexity evaluation unit 120 comprises a conditional branch evaluation unit 300, a feedback loop evaluation unit 310, and a function evaluation unit 320.

[0034] In some situations, the processing of the conditional branch evaluation unit 300, the processing of the feedback loop evaluation unit 310, and the processing of the function evaluation unit 320 may be executed in parallel. In other situations, the processing of the conditional branch evaluation unit 300, the processing of the feedback loop evaluation unit 310, and the processing of the function evaluation unit 320 may be executed in a different order.

[0035] The conditional branch evaluation unit 300 calculates the conditional branch complexity based on the analysis results obtained from the model analysis unit 110. More specifically, the conditional branch evaluation unit 300 extracts one or more conditional branch blocks 101 from the block type table 800. Next, the conditional branch evaluation unit 300 extracts the number of input signals, the number of output signals, and the number of conditions for each of the one or more conditional branch blocks 101. Then, the conditional branch evaluation unit 300 calculates the complexity of each of the one or more conditional branch blocks 101 based on the number of input signals, the number of output signals, and the number of conditions. Furthermore, the conditional branch evaluation unit 300 sums up the individual complexity values ​​of the one or more conditional branch blocks 101. The conditional branch evaluation unit 300 outputs the summed conditional branch complexity to the feedback loop evaluation unit 310.

[0036] The feedback loop evaluation unit 310 calculates the feedback complexity based on the analysis results obtained from the model analysis unit 110. More specifically, the feedback loop evaluation unit 310 obtains the start and end coordinates of each signal 102 from the signal connection table 1300. Then, the feedback loop evaluation unit 310 calculates the number of feedback loops based on the start and end coordinates of each signal 102. As an example, the feedback loop evaluation unit 310 calculates the number of feedback loops based on the start coordinate value and the end coordinate value. biggerSignal 102 can be determined to be a feedback loop. Here, the start coordinate and end coordinate refer to the coordinates in the first axis direction that indicate the time series of data processing. As another example, suppose the model analysis unit 110 defines groups of simultaneous blocks sequentially, regardless of the position of each block 101. In this case, the feedback loop evaluation unit 310 determines that a signal that goes backward in the order of the group is a feedback loop. Next, the feedback loop evaluation unit 310 calculates the feedback complexity. In some cases, the feedback complexity may be the number of feedback loops. In other cases, the feedback complexity may be the number of feedback loops multiplied by a predetermined complexity per feedback. The feedback loop evaluation unit 310 outputs the conditional branch complexity and the feedback complexity to the function evaluation unit 320.

[0037] The function evaluation unit 320 calculates the functional complexity of all blocks 101 included in the block type table 800. More specifically, the function evaluation unit 320 determines which block in the functional complexity table 1700 (see Figure 17) each block 101 corresponds to. The function evaluation unit 320 then obtains the complexity corresponding to each block 101 from the functional complexity table 1700. The functional complexity table 1700 is pre-stored in the storage 403 (see Figure 4) within the evaluation device 10. Next, the function evaluation unit 320 calculates the functional complexity by summing the complexity of each block 101. Furthermore, the function evaluation unit 320 outputs the conditional branch complexity, feedback complexity, and functional complexity to the complexity calculation unit 130.

[0038] The complexity calculation unit 130 calculates and outputs the complexity of the entire circuit (model data 100) based on the conditional branch complexity, feedback complexity, and functional complexity. In some cases, the complexity calculation unit 130 may sum the conditional branch complexity, feedback complexity, and functional complexity. The sum of these individual complexity values ​​becomes the complexity of the entire circuit (model data 100). In other cases, the complexity calculation unit 130 may multiply each of the conditional branch complexity, feedback complexity, and functional complexity by an individual coefficient. In this case, the complexity calculation unit 130 sums the individual complexity values ​​after multiplying by the coefficient. The sum of these individual complexity values ​​after multiplying by the coefficient becomes the complexity of the entire circuit (model data 100).

[0039] As explained with reference to Figures 1 to 3, the evaluation device 10 according to this embodiment includes a model analysis unit 110 that analyzes the model data 100 of the circuit, a complexity evaluation unit 120 that evaluates the complexity of each of the one or more blocks 101 that constitute the model data 100 obtained by the analysis, and the complexity of each of the one or more signals 102, and a complexity calculation unit 130 that calculates the complexity of the circuit based on the complexity of each of the one or more blocks 101 and the complexity of each of the one or more signals 102. The model data 100 includes position information of each of the one or more blocks 101 that are linked to the order of data processing. The model analysis unit 110 analyzes the position information to determine whether there are any blocks 101 that are executed simultaneously and to determine the type of each of the one or more signals 102. The type of signal 102 here includes the feedback loop signal 102 or other signals 102.

[0040] Evaluating (calculating) the complexity of one or more blocks 101 includes summing the complexity of all blocks 101 that make up the model data 100. Furthermore, evaluating (calculating) the complexity of one or more blocks 101 also includes evaluating (calculating) the conditional branch complexity. Additionally, evaluating the complexity of one or more signals 102 includes evaluating the feedback complexity based on the number of feedback loops. The circuit complexity is calculated based on functional complexity, conditional branch complexity, and feedback complexity.

[0041] (b. Hardware of the evaluation device) Figure 4 shows an example of the hardware configuration of the evaluation device 10. In some cases, each functional block shown in Figures 1 to 3 can be realized by executing a program on the hardware shown in Figure 4. In other cases, each functional block shown in Figures 1 to 3 may be realized by dedicated hardware. In this case, the evaluation device 10 will also include hardware corresponding to each function in addition to the configuration shown in Figure 4.

[0042] The evaluation device 10 includes a processor 401, RAM (Random Access Memory) 402, storage 403, external device interface (IF) 404, input unit 405, output unit 406, communication unit 407, and bus 408. The processor 401, RAM 402, storage 403, external device interface 404, input unit 405, output unit 406, and communication unit 407 are configured to communicate with each other via the bus 408.

[0043] The processor 401 can execute programs to realize various functions of the evaluation device 10. The processor 401 is composed of, for example, at least one integrated circuit. According to one embodiment, the integrated circuit may include at least one CPU (Central Processing Unit), at least one GPU (Graphics Processing Unit), at least one FPGA (Field Programmable Gate Array), at least one ASIC (Application Specific Integrated Circuit), at least one AI (Artificial Intelligence) chip, or a combination thereof.

[0044] RAM 402 functions as a workspace for processor 401. To this end, RAM 402 stores programs executed by processor 401 and data referenced by processor 401. In some cases, RAM 402 can be implemented using DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), etc.

[0045] Storage 403 is non-volatile memory that stores programs executed by processor 401 and data referenced by processor 401. Processor 401 executes programs read from storage 403 to RAM 402 and references data read from storage 403 to RAM 402. In some cases, storage 403 can be implemented by an HDD (Hard Disk Drive), SSD (Solid State Drive), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), or flash memory, etc.

[0046] The external device IF404 can be connected to any external device such as a printer, scanner, and external HDD. In some cases, the external device IF404 can be implemented using a USB (Universal Serial Bus) terminal or the like.

[0047] The input unit 405 can be connected to any input device such as a keyboard, mouse, touchpad, or gamepad. In some cases, the input unit 405 can be implemented by a USB terminal, PS / 2 terminal, and Bluetooth® module, etc. In other cases, the input unit 405 may be configured as an integrated unit with any input device.

[0048] The output unit 406 can be connected to any output device such as a cathode ray tube display, a liquid crystal display, or an organic EL (Electro-Luminescence) display. In some cases, the output unit 406 can be implemented using a USB terminal, a D-sub terminal, a DVI (Digital Visual Interface) terminal, an HDMI® (High-Definition Multimedia Interface) terminal, or a DisplayPort terminal. In other cases, the output unit 406 may be configured as an integrated unit with any output device.

[0049] The communication unit 407 is connected to other devices via a wired or wireless network. In some cases, the communication unit 407 may be implemented using a wired LAN (Local Area Network) port and a Wi-Fi (Wireless Fidelity) module, etc. In other cases, the communication unit 407 may send and receive data using communication protocols such as TCP / IP (Transmission Control Protocol / Internet Protocol) and UDP (User Datagram Protocol).

[0050] (c.Term) In this specification, the "device" may be any information processing device such as a personal computer, workstation, server device, tablet, or smartphone. The device may also be a combination of these. According to one embodiment, the device may be connected to input / output devices such as a display and a keyboard and used by a user. According to another embodiment, the device may provide various functions to a user as a service or a web application via a network. In this case, the user can use the functions of the device via a browser or client software installed on their own terminal. In one aspect, the evaluation device 10 can be realized by one device. In another aspect, the evaluation device 10 can be realized by a plurality of devices. In this case, the evaluation device 10 may be expressed as an evaluation system. Furthermore, the evaluation device 10 can be realized as a virtual machine constructed on a cloud environment.

[0051] In this specification, the "circuit" includes integrated circuits (ICs (Integrated Circuits)), LSIs, FPGAs, CPUs, GPUs, ASICs, AI chips, and any other circuits. The circuit may also include circuits manufactured from materials other than semiconductors including novel materials to be developed in the future.

[0052] In this specification, the "model data" is data of a circuit designed by a model-based development method. The model data can be expressed as data in an arbitrary format for each development tool.

[0053] In this specification, the "complexity" indicates the complexity of a circuit (model data 100) calculated from various aspects. As an example, the complexity may be an index of the complexity of the function of the circuit, the complexity of the signal flow, or a combination of these. As another example, the complexity may be an index for estimating the difficulty of circuit design, the difficulty of circuit manufacturing, or the man-hours required for circuit design or manufacturing.

[0054] <B. Configuration Example of Model Data of Circuit to Be Evaluated> Figure 5 shows an example of model data 100 for the circuit under evaluation. Model data 100 includes inputs 500, 502, 504, 506, 508, and 510 as block 101. Model data 100 also includes a comparison 512, an addition 514, a subtraction 516, and a conditional branch 518 as block 101. Furthermore, model data 100 includes an FIR (Finite Impulse Response) filter 520, an FFT (Fast Fourier Transform) 522, a peak detection 524, a hold 526, and an output 528 as block 101. Similarly, model data 100 includes signals A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O as signal 102. Among these signals 102, signal O is a feedback loop.

[0055] Each block 101 contains information about the number of input signals, the number of output signals, their type (function), and their position coordinates. Each signal 102 contains information about the block 101 to which it is connected. Each signal 102 may also contain information about its start and end coordinates. This information held by each block 101 and each signal 102 may be included in the model data 100 as metadata, etc. Each block 101 may contain a memory circuit such as a flip-flop to hold the state of the signal.

[0056] Each block 101 is arranged according to the order of data processing. In the example in Figure 5, as indicated by the arrows for each signal 102, each signal 102 passes through each block 101 from left to right. That is, each block 101 processes the data from left to right. Also, each signal is input from the left of each block 101 and output from the right of each block 101. As an example, each block 101 functions in the following order: input 500, magnitude comparison 512, conditional branching 518, FIR filter 520, FFT 522, peak detection 524, hold 526, and output 528.

[0057] When a developer defines functions that operate in series, they arrange one or more blocks 101 horizontally. Alternatively, a developer can define functions that operate in parallel by arranging multiple blocks 101 vertically. That is, the horizontal direction of the model data 100 corresponds to a first axis representing the time series of data processing in the circuit. The vertical direction of the model data 100 corresponds to a second axis representing the direction in which one or more blocks are arranged in parallel. In some cases, the vertical direction of the model data 100 may correspond to the first axis representing the time series of data processing in the circuit. Alternatively, the horizontal direction of the model data 100 may correspond to a second axis representing the direction in which one or more blocks are arranged in parallel.

[0058] Developers can define blocks 101 that are executed simultaneously by aligning the coordinates in the left-right direction (first axis direction) and arranging multiple blocks vertically (second axis direction). Hereafter, blocks 101 that are executed simultaneously will be referred to as simultaneous blocks. For example, if block A and block B are executed simultaneously, blocks A and B are simultaneous blocks. When defining simultaneous blocks, a certain degree of misalignment in the left-right direction (first axis direction) of blocks 101 arranged in parallel is acceptable. As an example, the block position analysis unit 210 can determine whether the misalignment in the left-right direction (first axis direction) of blocks 101 arranged in parallel is below a predetermined threshold. Based on the fact that the misalignment is below a predetermined threshold, the block position analysis unit 210 can determine that the blocks 101 arranged in parallel are simultaneous blocks. In a given situation, the concurrently executed blocks 101 may be configured to be definable as a group in any way, regardless of coordinates.

[0059] Figure 6 shows an example of how the configuration of conditional branch 518 can be represented. Conditional branch 518 is a function (block) that is one of the major factors that complicates circuits. Refer to Figure 6 to explain the information contained in conditional branch 518.

[0060] Description 600 represents the conditional branch 518 of the model data 100 as source code. According to Description 600, the conditional branch 518 has three branches. Also, as can be seen from FIG. 5, the conditional branch 518 has three inputs and one output. The number of input signals, the number of output signals, and the number of conditions are factors contributing to the complexity of the conditional branch 518. mosquito As can be seen, the conditional branch 518 has three inputs and one output. The number of input signals, the number of output signals, and the number of conditions are factors contributing to the complexity of the conditional branch 518.

[0061] In a certain aspect, the conditional branch evaluation unit 300 may convert the conditional branch 518 into Description 600. In this case, the conditional branch evaluation unit 300 extracts the number of input signals, the number of output signals, and the number of conditions of the conditional branch 518 from Description 600. In other aspects, the conditional branch evaluation unit 300 may directly analyze the conditional branch 518 without going through Description 600 to extract the number of input signals, the number of output signals, and the number of conditions of the conditional branch 518.

[0062] FIG. 7 is a diagram showing another example of the expression of the configuration of the conditional branch 518. The conditional branch 518 can also be expressed as a combination of multiple blocks. The block data 700 represents the conditional branch 518 of the model data 100 using a combination of blocks. to The conditional branch 518 can also be expressed as a combination of multiple blocks. The block data 700 represents the conditional branch 518 of the model data 100 using a combination of blocks.

[0063] In a certain aspect, the conditional branch evaluation unit 300 may convert the conditional branch 518 into the block data 700. In this case, the conditional branch evaluation unit 300 extracts the number of input signals, the number of output signals, and the number of conditions of the conditional branch 518 from the block data 700. In other aspects, the conditional branch evaluation unit 300 may directly analyze the conditional branch 518 without going through the block data 700 to extract the number of input signals, the number of output signals, and the number of conditions of the conditional branch 518.

[0064] <C. Analysis Procedure of Model Data> Next, referring to FIGS. 8 to 14, the analysis procedure of the model data 100 will be described in detail. The analysis procedure of the model data 100 includes three aspects: analysis of the function of blocks, analysis of the position of blocks, and analysis of the connection relationship of signals.

[0065] (a. Analysis of block functionality) Figure 8 shows an example of a block type table 800. The block type analysis unit 200 generates the block type table 800 by analyzing the model data 100. The block type analysis unit 200 stores the generated block type table 800 in the storage 403. In some cases, the block type table 800 may be represented as a table in a relational database, or it may be represented in any other arbitrary data format such as JSON (JavaScript® Object Notation).

[0066] The block type table 800 includes the following items: No (Number) item 801, Block item 802, Input signal count item 803, Output signal count item 804, Function item 805, and Condition count item 806.

[0067] The "No." field 801 contains an identifier to uniquely identify each record. The "Block" field 802 contains the name or identifier of each block 101. The "Number of Input Signals" field 803 contains the number of input signals for each block 101. The "Number of Output Signals" field 804 contains the number of output signals for each block 101. The "Function" field 805 contains the function or type of each block 101. The "Number of Conditions" field 806 contains the number of conditions for each block 101. Blocks 101 other than conditional branches do not contain any conditions. Therefore, the "Number of Conditions" field 806 for blocks 101 other than conditional branches may contain 0, blank, NULL, etc.

[0068] For example, record No. 7 is the record for the magnitude comparison 512 in Figure 5. According to Figure 5, signals A and O are input to the magnitude comparison 512. Signal G is output from the magnitude comparison 512. The magnitude comparison 512 is a function that compares numerical values. Therefore, referring to record No. 7, the input signal count item 803 is "2" and the output signal count item 804 is "1". Also, the function item 805 of record No. 7 is "numerical comparison".

[0069] Figure 9 shows an example of a block classification procedure. The block type analysis unit 200 generates a block type table 800 by executing the process shown in Figure 9. In one scenario, the processor 401 may read a program for performing the process in Figure 9 from the storage 403 into the RAM 402 and execute the program. In other scenarios, part or all of the process can be implemented as a combination of circuit elements configured to perform the process.

[0070] Similarly, the processor 401 may load a program for performing each of the processes shown in Figure 10 and later into the RAM 402 from the storage 403 and execute the program. In addition, some or all of the processes shown in Figure 10 and later can also be implemented as a combination of circuit elements configured to perform the process.

[0071] In step S910, the block type analysis unit 200 extracts each block 101 from the model data 100. In step S920, the block type analysis unit 200 extracts the number of input signals and output signals for each block 101.

[0072] In step S930, the block type analysis unit 200 determines the type of each extracted block 101. In some cases, the evaluation device 10 may have a list of block types 101 pre-stored in the storage 403. In this case, the evaluation device 10 can determine the type of each block 101 by comparing each block 101 with the type list. In other cases, the model data 100 may include type information for each block 101 as metadata, etc. In this case, the evaluation device 10 can determine the type of each block 101 by acquiring the metadata, etc.

[0073] In step S940, the block type analysis unit 200 determines whether the extracted block 101 is a conditional branch or not. If the block type analysis unit 200 determines that the extracted block 101 is a conditional branch (YES in step S940), it transfers control to step S950. Otherwise (NO in step S940), the block type analysis unit 200 transfers control to step S960. As an example, in Figure 5, a conditional branch 518 is extracted from the model data 100, so the block type analysis unit 200 transfers control to step S950.

[0074] In step S950, the block type analysis unit 200 extracts the number of conditions in the conditional branch. As shown in Figure 5 as an example, the block type analysis unit 200 extracts the number of conditions "3" from conditional branch 518.

[0075] In step S960, the block type analysis unit 200 creates a block type table 800. More specifically, the block type analysis unit 200 generates each record in the block type table 800 based on the information obtained from the processing in steps S910 to S950.

[0076] (b. Analysis of block locations) Figure 10 shows a portion of the model data 100. Referring to Figure 10, the procedure by which the block position analysis unit 210 determines the presence or absence of simultaneous blocks will be explained. The model data 100 is defined in a coordinate space consisting of the x-axis 1010 and the y-axis 1020. The x-axis 1010 corresponds to the first axis, which shows the time series of data processing in the circuit. The y-axis 1020 corresponds to the second axis, which shows the direction in which one or more blocks 101 are arranged in parallel.

[0077] The block position analysis unit 210 obtains the coordinates of the lower left corner of all blocks 101 (hereinafter referred to as the "start coordinates"). For example, the start coordinates of the size comparison 512 are (10,20). The start coordinates of the addition 514 are (10,5,15). The start coordinates of the subtraction 516 are (9,10).

[0078] Furthermore, the block position analysis unit 210 obtains the width of all blocks 101 in the x-axis direction 1010. For example, the widths of the size comparison 512, addition 514, and subtraction 516 are all "2". Alternatively, the block position analysis unit 210 may obtain the coordinates of the bottom right corner of all blocks 101 (hereinafter referred to as the "end coordinates"). The end coordinates of the size comparison 512 are (12,20), which is 2 from the start coordinates. Similarly, the end coordinates of the addition 514 are (12,5,15). The end coordinates of the subtraction 516 are (11,10).

[0079] Next, the block position analysis unit 210 determines the presence or absence of block 101 in the positive direction from x=0 to the x-axis 1010. The block position analysis unit 210 sets the first detected block 101 as the reference block. In the example in Figure 10, the block position analysis unit 210 selects subtraction 516 as the reference block.

[0080] Next, the block position analysis unit 210 determines whether there is a block whose interval from the start coordinate to the end coordinate (hereinafter simply referred to as "interval") overlaps with the interval of a reference block. If at least a portion of the interval of a certain block 101 overlaps with the interval of a reference block, the block position analysis unit 210 determines that the certain block 101 is executed simultaneously with the reference block.

[0081] For example, the interval of the reference block (subtraction 516) is (9 to 11) in the x-axis 1010 direction. The interval of the addition 514 is (10.5 to 12.5) in the x-axis 1010 direction. The interval of addition 514 overlaps with the interval of the reference block (subtraction 516) in the x-axis 1010 direction (10.5 to 11). Therefore, the block position analysis unit 210 determines that addition 514 and subtraction 516 are simultaneous blocks.

[0082] Similarly, the interval for the comparison 512 is (10 to 12) in the x-axis direction 1010. The interval for the comparison 512 overlaps with the interval for the reference block (subtraction 516) in the x-axis direction 1010 (10 to 11). Therefore, the block position analysis unit 210 determines that the comparison 512 and the subtraction 516 are simultaneous blocks.

[0083] In a given situation, the block position analysis unit 210 may determine the presence or absence of simultaneous blocks using a different method. For example, the block position analysis unit 210 calculates the difference in coordinates in the x-axis direction 1010 between a reference block and other blocks. Based on the fact that this difference is within a predetermined threshold, the block position analysis unit 210 may then determine that the reference block and other blocks are simultaneous blocks. The coordinates of each block 101 to be compared may be the coordinates of any part of each block 101. For example, the coordinates of each block 101 to be compared may be the coordinates of the rightmost, center, or leftmost part of each block 101.

[0084] As described above, in the example in Figure 10, the block position analysis unit 210 determines that the comparison 512, addition 514, and subtraction 516 are simultaneous blocks. The block position analysis unit 210 may also manage simultaneous blocks as a group.

[0085] After the above processing, the block position analysis unit 210 searches for a block 101 that has not been determined to be a simultaneous block and for which the simultaneous block determination process has not been performed, starting from x=0 in the positive direction of the x-axis 1010. The block position analysis unit 210 selects a block 101 that meets these conditions as the next reference block. Then, it repeatedly executes the above process for determining the presence or absence of simultaneous blocks.

[0086] In the example in Figure 10, the comparison 512 and addition 514 are determined to be simultaneous blocks and therefore cannot be reference blocks. For this reason, the block position analysis unit 210 selects conditional branch 518 as the next reference block. However, there are no blocks whose interval from the start coordinate to the end coordinate overlaps with conditional branch 518. For this reason, the block position analysis unit 210 determines that conditional branch 518 is not a simultaneous block. Similarly, the block position analysis unit 210 selects the block following conditional branch 518 as the reference block.

[0087] In a given situation, the block position analysis unit 210 may determine the presence or absence of simultaneous blocks using a different method. For example, suppose that subtraction 516, addition 514, and comparison 512 are arranged slightly offset from each other like steps. In this case, the block position analysis unit 210 may determine that subtraction 516, addition 514, and comparison 512 are simultaneous blocks. The block position analysis unit 210 calculates the coordinate difference in the x-axis 1010 direction between the reference block and the other blocks. Then, based on the fact that the difference is within a predetermined threshold, the block position analysis unit 210 determines that the reference block and the other blocks are simultaneous blocks. Next, the block position analysis unit 210 searches for a block 101 that has not been determined to be a simultaneous block in the positive x-axis 1010 direction from x=0. The block position analysis unit 210 selects the block 101 that meets the condition as the next reference block. Then, the block position analysis unit 210 repeatedly executes the above process for determining the presence or absence of simultaneous blocks. Finally, the block position analysis unit 210 groups of blocks that have been determined to be consecutive simultaneous blocks and determines them to be a single simultaneous block.

[0088] As a special case, suppose that any of the multiple blocks arranged in series are in a position where they can be determined to be simultaneous blocks with respect to the reference block. In this case, the block position analysis unit 210 selects the block that is executed earliest among the multiple blocks as the simultaneous block with respect to the reference block. To illustrate with an example using Figure 10, suppose that the model data 100 includes adders 514A and 514B arranged in series instead of adder 514. And suppose that both adders 514A and 514B are in a position where they can be determined to be simultaneous blocks with respect to subtraction 516. In this case, the block position analysis unit 210 determines that the leftmost adder 514A is the simultaneous block with respect to subtraction 516.

[0089] Figure 11 shows a portion of the model data 100 after alignment processing. The block position analysis unit 210 may align multiple blocks 101 that it has determined to be simultaneous blocks. For example, the block position analysis unit 210 aligns the other blocks 101 to match a reference block. In the example in Figure 11, the starting coordinates of the comparison 512 and addition 514 are aligned to the starting coordinates of the reference block, subtraction 516. In this way, the block position analysis unit 210 can improve the readability of the model data 100 by modifying it.

[0090] Figure 12 shows an example of the block position analysis procedure. The block position analysis unit 210 is included in the model analysis unit 110. Therefore, the block position analysis unit 210, which is the main unit that executes each of the following steps, may be read as the model analysis unit 110. In step S1205, the block position analysis unit 210 extracts the coordinates of each block from the model data 100. In step S1210, the block position analysis unit 210 uses coordinate x=0 as its starting point. In step S1215, the block position analysis unit 210 determines whether or not block 101 is present in the positive direction of the x-axis 1010.

[0091] In step S1220, the block position analysis unit 210 determines that block 101 is located in the positive direction of the x-axis 1010 (YES in step S1220), and transfers control to step S1225. Otherwise (NO in step S1220), the block position analysis unit 210 transfers control to step S1260. In step S1225, the block position analysis unit 210 sets the detected block 101 as the reference block.

[0092] In step S1230, the block position analysis unit 210 determines whether there are other blocks between the start coordinates of the reference block and the width of the reference block. That is, the block position analysis unit 210 determines whether there are any blocks whose interval from the start coordinates to the end coordinates overlaps with the reference block. If the block position analysis unit 210 determines that there are other blocks between the start coordinates of the reference block and the width of the reference block (YES in step S1230), it transfers control to step S1235. Otherwise (NO in step S1230), the block position analysis unit 210 transfers control to step S1245.

[0093] In step S1235, the block position analysis unit 210 determines that the reference block and other blocks are simultaneous blocks. There may be two or more other blocks. In step S1240, the block position analysis unit 210 sets the next block as the reference block. The next block is block 101, which has not been determined to be a simultaneous block and for which the simultaneous block determination process has not been performed.

[0094] In step S1245, the block position analysis unit 210 obtains the y coordinates of all blocks 101 that have been determined to be simultaneous blocks with respect to the reference block. In step S1250, the block position analysis unit 210 determines that only the one with the smallest x coordinate among simultaneous blocks with the same y coordinate is a simultaneous block. The block position analysis unit 210 also excludes the other blocks 101 from being simultaneous blocks. The processes in steps S1245 and S1250 correspond to the processes described using addition 514A and addition 514B as examples, referring to Figure 10.

[0095] In step S1255, the block position analysis unit 210 aligns the x-coordinates of all blocks 101 determined to be simultaneous blocks with the x-coordinates of the reference block. The process in this step corresponds to the process described with reference to Figure 11.

[0096] In step S1260, the block position analysis unit 210 determines whether or not it has performed the simultaneous block determination process for the block 101 having the largest x-coordinate. If the block position analysis unit 210 determines that it has performed the simultaneous block determination process for the block 101 having the largest x-coordinate (YES in step S1260), it terminates the simultaneous block determination process. Otherwise (NO in step S1260), the block position analysis unit 210 transfers control to step S1215.

[0097] As explained with reference to Figures 10 to 12, the model analysis unit 110 can determine whether there are any blocks that are being executed simultaneously by analyzing the positional information of each block 101. The positional information is the placement coordinates of one or more blocks. In one situation, the positional information may be the interval from the start coordinate to the end coordinate of one or more blocks. In other situations, the positional information may be the start coordinate and width of one or more blocks.

[0098] Furthermore, the placement coordinates are coordinates in a two-dimensional space consisting of a first axis (x-axis 1010) and a second axis (y-axis 1020). The first axis indicates the time series of data processing in the circuit. The second axis indicates the direction in which one or more blocks 101 are arranged in parallel. Determining whether or not there are blocks 101 that are executed simultaneously includes determining whether or not there are blocks 101 that are executed simultaneously based on whether or not the difference in coordinates of one or more blocks 101 in the direction of the first axis is less than or equal to a predetermined threshold. In a given situation, determining whether or not there are blocks 101 that are executed simultaneously may include determining whether or not there are blocks 101 whose interval from the start coordinate to the end coordinate overlaps with that of a reference block in at least part of the interval.

[0099] Furthermore, one or more blocks 101 that constitute the model data 100 include a first block, a second block, and a third block. Also, the second and third blocks are assumed to have the same coordinates in the direction of the second axis (y-axis 1020). Moreover, the first block, the second block, and the third block have different coordinates in the direction of the second axis (y-axis 1020), and the difference in coordinates between the first block, the second block, and the third block in the direction of the first axis (x-axis 1010) is less than or equal to a predetermined threshold. In this case, the model analysis unit 110 can determine that the block that is executed earlier among the second and third blocks is the block 101 that is executed simultaneously with the first block.

[0100] Furthermore, based on its determination that there are blocks 101 that are executed simultaneously, the model analysis unit 110 can align the coordinates of the simultaneously executed blocks 101 in the direction of the first axis (x-axis 1010). More specifically, the model analysis unit 110 can align the x-coordinate values ​​at the starting coordinates of each of the simultaneously executed blocks 101.

[0101] (c. Analysis of signal connection relationships) Figure 13 shows an example of a signal connection table 1300. The signal connection analysis unit 220 generates the signal connection table 1300 by analyzing the model data 100. In a certain scenario, the signal connection analysis unit 220 may generate the signal connection table 1300 by analyzing the model data 100 after the processing shown in Figure 11 has been performed. Signal connection analysis unit 220 The generated signal connection table 1300 is stored in the storage 403. In some cases, the signal connection table 1300 may be represented as a table in a relational database, or it may be represented in any other arbitrary data format such as JSON.

[0102] The signal connection table 1300 includes the following items: No. item 1301, Signal item 1302, Start Coordinate item 1303, and End Coordinate item 1304. The No. item 1301 contains an identifier to uniquely identify each record. The Signal item 1302 contains the name or identifier of each signal 102. The Start Coordinate item 1303 contains the Start Coordinate value for each signal 102. The Start Coordinate value is the x-coordinate value of the starting position of each signal 102. The End Coordinate item 1304 contains the End Coordinate value for each signal 102. The End Coordinate value is the x-coordinate value of the ending position of each signal 102.

[0103] Figure 14 shows an example of the procedure for analyzing signal connection relationships. The signal connection analysis unit 220 generates a signal connection table 1300 by executing the process shown in Figure 14.

[0104] In step S1410, the signal connection analysis unit 220 extracts signal 102 from the model data 100. In the example in Figure 5, the signal connection analysis unit 220 extracts signals A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O.

[0105] In step S1420, the signal connection analysis unit 220 extracts the coordinates of the output source block for each signal 102 as the starting coordinates. For example, the starting coordinates of signal A are the coordinates of the input 500, which is the output source block. Identified as. More specifically, the start coordinate of signal A is the x coordinate of the end coordinate of input 500 That is .

[0106] In step S1430, the signal connection analysis unit 220 extracts the coordinates of the destination block of each signal 102 as the end coordinates. As an example, the end coordinate of signal A is the coordinate of the magnitude comparison 512 which is the destination block Identified as . More specifically, the end coordinate of signal A is the x coordinate of the start coordinate of magnitude comparison 512 That is .

[0107] In step S1440, the signal connection analysis unit 220 creates a signal connection table 1300 based on the information obtained in the processes from steps S1410 to S1430.

[0108] <D. Evaluation Procedure for Complexity of Model Data> Next, referring to FIGS. 15 to 18, the evaluation procedure for the complexity of the model data 100 will be described in detail. The evaluation procedure for the complexity of the model data 100 includes evaluation of the conditional branch complexity, evaluation of the feedback complexity, and evaluation of the complexity for each function of the block 101.

[0109] (a. Evaluation of Conditional Branch Complexity) FIG. 15 is a diagram showing an example of the evaluation procedure for the conditional branch complexity. The conditional branch evaluation unit 300 is included in the complexity evaluation unit 120. Therefore, the conditional branch evaluation unit 300 which is the execution subject of each step below may be read as the complexity evaluation unit 120.

[0110] In step S1510, the conditional branch evaluation unit 300 extracts the block 101 from the block type table 800. In step S1520, the conditional branch evaluation unit 300 determines whether the type of the extracted block 101 is a conditional branch. If the conditional branch evaluation unit 300 determines that the type of the extracted block 101 is a conditional branch (YES in step S1520), the control is transferred to step S1530. Otherwise (NO in step S1520), the conditional branch evaluation unit 300 transfers the control to step S1550.

[0111] In step S1530, the conditional branch evaluation unit 300 calculates the complexity of the extracted block 101 from the number of input signals, the number of output signals, and the number of conditions. In step S1540, the conditional branch evaluation unit 300 adds the calculated conditional branch complexity to the value calculated in step S1530. Multiple Add the miscellaneous value.

[0112] In step S1550, the conditional branch evaluation unit 300 determines whether the judgment process for all blocks 101 has been completed. If the conditional branch evaluation unit 300 determines that the judgment process for all blocks 101 has been completed (YES in step S1550), it transfers control to step S1560. Otherwise (NO in step S1550), the conditional branch evaluation unit 300 transfers control to step S1510.

[0113] In step S1560, the conditional branch evaluation unit 300 completes the calculation of the conditional branch complexity. Here, the conditional branch complexity is the sum of the complexity of one or more extracted conditional branch blocks.

[0114] As described above, the complexity evaluation unit 120 (conditional branch evaluation unit 300) calculates the complexity of a conditional branch block based on the number of input signals, the number of output signals, and the number of conditions of the conditional branch block if one or more blocks 101 are conditional branch blocks.

[0115] (b. Evaluation of feedback complexity) Figure 16 shows an example of the feedback complexity evaluation procedure. The feedback loop evaluation unit 310 is included in the complexity evaluation unit 120. Therefore, the feedback loop evaluation unit 310, which is the main entity executing each of the following steps, may be read as the complexity evaluation unit 120.

[0116] In step S1610, the feedback loop evaluation unit 310 extracts signal 102 from the signal connection table 1300. In step S1620, the feedback loop evaluation unit 310 calculates the end coordinate-start coordinate value of the extracted signal 102.

[0117] In step S1630, the feedback loop evaluation unit 310 determines that the value calculated in step S1620 is 0. less than Determine whether or not this is the case. The start and end coordinates of signal 102 are coordinates indicating the position in the direction of the first axis (x-axis 1010) which represents the time series of data processing. less than This means that the end coordinates of signal 102 exist chronologically earlier than the start coordinates. In other words, the value is 0 less than This means that the signal 102 is a feedback loop. The feedback loop evaluation unit 310 evaluates the value to 0. less than If it is determined that this is the case (YES in step S1630), control is transferred to step S1640. Otherwise (NO in step S1630), the feedback loop evaluation unit 310 transfers control to step S1660.

[0118] In step S1640, the feedback loop evaluation unit 310 calculates the feedback complexity of the detected feedback loop. In some cases, the feedback complexity may be a fixed value. For example, the feedback complexity may be the number of feedback loops. In other cases, the feedback complexity may change based on the end coordinate-start coordinate values ​​of signal 102, etc. In step S1650, the feedback loop evaluation unit 310 adds the feedback complexity calculated in step S1640 to the feedback complexity already calculated.

[0119] In step S1660, the feedback loop evaluation unit 310 determines whether or not the judgment processing for all signals 102 has been completed. If the feedback loop evaluation unit 310 determines that the judgment processing for all signals 102 has been completed (YES in step S1660), it transfers control to step S1670. Otherwise (NO in step S1660), the feedback loop evaluation unit 310 transfers control to step S1610. In step S1670, the feedback loop evaluation unit 310 completes the calculation of the feedback complexity. The feedback complexity here is: detection One or more The calculations for each part of the feedback loop This is the sum of the feedback complexity values.

[0120] As described above, the complexity evaluation unit 120 (feedback loop evaluation unit 310) calculates the complexity of each of the one or more signals 102 based on whether each of the one or more signals 102 indicates a feedback loop. In some situations, the complexity of each of the one or more signals 102 may be a fixed value. In other situations, the complexity of each of the one or more signals 102 is calculated based on the start coordinate and end coordinate. Even if the values ​​are different Good. The complexity evaluation unit 120 (feedback loop evaluation unit 310) also calculates the sum of the complexity of each of the one or more signals 102.

[0121] (c. Evaluation of the complexity of each function in a block) Figure 17 shows an example of a functional complexity table 1700. The functional complexity table 1700 is a table that defines the complexity of each function that makes up the circuit. The functional complexity table 1700 is used to determine the complexity of each block 101. The functional complexity table 1700 is pre-stored in storage 403. In some cases, the functional complexity table 1700 may be represented as a table in a relational database, or it may be represented in any other arbitrary data format such as JSON.

[0122] The functional complexity table 1700 includes three items: a No. item 1701, a Function item 1702, and a Complexity item 1703. The No. item 1701 contains an identifier to uniquely identify each record. The Function item 1702 contains the name or identifier of each function that constitutes the circuit. The functions of the circuit correspond to each block 101 in the model data 100. In some cases, each block 101 may have two or more functions. The Complexity item 1703 contains the complexity of each function. Each function complexity can be calculated in advance by analyzing the man-hours spent on developing past products, for example.

[0123] Figure 18 shows an example of a procedure for evaluating the functional complexity of a block. The functional evaluation unit 320 is included in the complexity evaluation unit 120. Therefore, the functional evaluation unit 320, which is the main entity executing each of the following steps, may be read as the complexity evaluation unit 120.

[0124] In step S1810, the function evaluation unit 320 extracts block 101 from the block type table 800. In step S1820, the function evaluation unit 320 obtains the function complexity corresponding to the extracted block 101 from the function complexity table 1700. Assume that the extracted block 101 has multiple functions. In this case, the complexity of the extracted block 101 will be the sum of the individual function complexities. Therefore, the function evaluation unit 320 obtains multiple function complexities corresponding to the extracted block 101 from the function complexity table 1700. In step S1830, the function evaluation unit 320 adds the complexity obtained in step S1820 to the calculated function complexity.

[0125] In step S1840, the function evaluation unit 320 determines whether or not the judgment processing for all blocks 101 has been completed. If the function evaluation unit 320 determines that the judgment processing for all blocks 101 has been completed (YES in step S1840), it transfers control to step S1850. Otherwise (NO in step S1840), the function evaluation unit 320 transfers control to step S1810. In step S1850, the function evaluation unit 320 completes the calculation of the function complexity. machine The complexity is the total value of the complexities of all the blocks 101 included in the model data 100.

[0126] As described above, the complexity evaluation unit 120 (function evaluation unit 320) calculates the complexity of each of the one or more blocks 101 based on the function of each of the one or more blocks. When a block 101 has a plurality of functions, the complexity of the block 101 is the total value of the plurality of function complexities. Further, the complexity evaluation unit 120 (function evaluation unit 320) sums up the complexities of each of the one or more blocks.

[0127] The complexity evaluation unit 120 outputs the conditional branch complexity, the feedback complexity, and the function complexity to the complexity calculation unit 130. The complexity calculation unit 130 calculates the complexity of the entire circuit (model data 100) based on the conditional branch complexity, the feedback complexity, and the function complexity.

[0128] In a certain aspect, the complexity calculation unit 130 may sum up the conditional branch complexity, the feedback complexity, and the function complexity. In another aspect, the complexity calculation unit 130 may multiply each complexity by an individual coefficient. In this case, the complexity calculation unit 130 multiplies the function complexity by a first coefficient. The complexity calculation unit 130 multiplies the conditional branch complexity by a second coefficient. The complexity calculation unit 130 multiplies the feedback complexity by a third coefficient. Then, the complexity calculation unit 130 sums up the function complexity, the conditional branch complexity, and the feedback complexity after multiplying by the coefficients.

[0129] <E. Application Example> FIG. 19 is a diagram showing an example of model data 1900 in another format. Referring to FIG. 19, a procedure for the evaluation device 10 to evaluate the complexity of the model data 1900 will be described.

[0130] Each block in the model data 1900 does not have a value of the x coordinate indicating the time series, unlike the block 101 of the model data and Multiple circuits for processes 1 to 3 are arranged in parallel. Each circuit for processes 1 to 3 is composed of multiple blocks.

[0131] Process 1 includes, as a block, input 1901, FIR filter 1902, FFT 1904, peak detection 1906, hold 1908, and output 1910. Process 1 also includes signals P, Q, R, S, T, U. Process 2 includes, as a block, input 1912, input 1914, conditional branch 1916, x2 1918, threshold determination 1920, delay 1922, and output 1924. Process 2 also includes signals W, X, Y, Z, AA. Process 3 includes, as a block, input 1926, +7 1928, delay 1930, and output 1932. Process 3 also includes signals BB, CC.

[0132] The model analysis unit 110 consists of one or more blocks that constitute each process. , or a combination of one or more blocks The models are compared. Then, the model analysis unit 110 analyzes the compared blocks. or combination of blocks If the sum of the delays of these blocks is equal, or combination of blocks The system determines that these are simultaneous blocks. For example, the delay of the FIR filter 1902 in process 1 is "20". Also, the combined delay of the conditional branch 1916 and x21918 in process 2 is "20". Therefore, the model analysis unit 110 sets the FIR filter 1902 in process 1 and the conditional branch 1916 and x21918 in process 2 as simultaneous blocks.

[0133] Furthermore, suppose the developer wants to execute the output 1910 of process 1, the output 1924 of process 2, and the output 1932 of process 3 simultaneously. In this case, the developer may add a setting to the model data 1900 so that outputs 1910, 1924, and 1932 are executed simultaneously. When the model analysis unit 110 detects such a setting, Among multiple processes, the process that requires an additional delay to synchronize their execution timing. Add a delay block. See Figure 19 for an example. SoA delay of 1922 is added to process 2. A delay of 1930 is also added to process 3. As a result, outputs 1910, 1924, and 1932 are executed simultaneously at a delay of "68" from the start of the process. Thus, the model analysis unit 110 has a function to insert delay blocks into each process in order to execute multiple blocks simultaneously at a specific timing. The model analysis unit 110 uses the delay block insertion function to make multiple blocks simultaneous blocks. You could also say .

[0134] Next, the procedure for calculating the complexity of the model data 1900 will be described. The conditional branching evaluation unit 300 can calculate the conditional branching complexity of the model data 1900 using the procedure shown in Figure 15. The function evaluation unit 320 can calculate the function complexity of the model data 1900 using the procedure shown in Figure 18. The feedback loop evaluation unit 310 can calculate the feedback complexity of the model data 1900 using the procedure shown in Figure 16. However, when the feedback loop evaluation unit 310 determines whether or not there is a feedback loop in the model data 1900, it uses the block delay rather than the signal coordinates.

[0135] The feedback loop determination process will be explained using signals Q and U from process 1 as examples. The total execution time (delay) of the blocks at the start position of signal Q is "20". The total execution time (delay) of the blocks at the end position of signal Q is "20". From this, it can be seen that signal Q is not input to a block executed before signal Q occurs. Therefore, the feedback loop evaluation unit 310 determines that signal Q is not a feedback loop. The total execution time (delay) of the blocks at the start position of signal U is "68". The total execution time (delay) of the blocks at the end position of signal U is "52". From this, it can be seen that signal U is input to a block executed before signal U occurs. Therefore, the feedback loop evaluation unit 310 determines that signal U is a feedback loop. In this way, the feedback loop evaluation unit 310 can determine the presence or absence of a feedback loop based on the delay of each block. Alternatively, the feedback loop evaluation unit 310 can determine the presence or absence of a feedback loop based on the delay at the start position and the delay at the end position of each signal. The method for calculating the feedback complexity of model data 1900 is the same as the method shown in Figure 16.

[0136] The complexity calculation unit 130 calculates and outputs the complexity of the entire circuit based on the conditional branch complexity, feedback complexity, and functional complexity calculated from the model data 1900. In some cases, the complexity calculation unit 130 may sum the conditional branch complexity, feedback complexity, and functional complexity. The sum of these complexities becomes the complexity of the model data 1900 representing the entire circuit. In other cases, the complexity calculation unit 130 may multiply each of the conditional branch complexity, feedback complexity, and functional complexity by an individual coefficient. In this case, the complexity calculation unit 130 sums the complexities after multiplying by the coefficient. The sum of these complexities after multiplying by the coefficient becomes the complexity of the model data 1900 representing the entire circuit.

[0137] As described above, when the model analysis unit 110 analyzes the model data 1900, each block ofLocation information is stored from the start of data processing. Each This is the delay until the block's processing is executed. Furthermore, the start and end positions of each signal are determined based on the delay of the block to which each signal is connected.

[0138] Furthermore, as explained with reference to Figure 19, depending on the model data format, determining whether or not blocks are executed concurrently may involve determining whether or not the delays of each of the blocks, or the combination of each of the blocks, are the same.

[0139] Furthermore, when the model data 1900 includes multiple circuits that are executed in parallel, and a point is specified for aligning the execution timing of the multiple circuits, the model analysis unit 110 aligns the delays in the execution timing of the multiple circuits. Of the multiple circuits, the one that requires additional delay. , late Add delayed blocks (delays of 1922, 1930, etc.).

[0140] <F.まとめ> As described above, the evaluation device 10 according to this embodiment can evaluate the complexity of a circuit by directly analyzing model data. By using the evaluation device 10, developers do not need to convert the model data into HDL source code. As a result, the circuit complexity output by the evaluation device 10 is not affected by the tools used to convert the model data into source code. In other words, the evaluation device 10 can more accurately evaluate (calculate) the complexity of the circuit under design.

[0141] The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than the foregoing description, and all modifications are intended to be equivalent to the claims. Furthermore, the disclosures described in the embodiments and each variation are intended to be implemented, as far as possible, individually or in combination. [Explanation of Symbols]

[0142] 10 Evaluation device, 100, 1900 Model data, 101 Block, 102 Signal, 110 Model analysis unit, 120 Complexity evaluation unit, 130 Complexity calculation unit, 200 Block type analysis unit, 210 Block position analysis unit, 220 Signal connection analysis unit, 300 Conditional branch evaluation unit, 310 Feedback loop evaluation unit, 320 Function evaluation unit, 401 Processor, 402 RAM, 403 Storage, 404 External device IF, 405 Input unit, 406 Output unit, 407 Communication unit, 408 Bus, 500, 502, 504, 506, 508, 510, 1901, 1912, 1914, 1926 Input, 512 Larger / smaller comparison, 514, 514A, 514B Addition, 516 Subtraction, 518, 1916 Conditional branching, 520, 1902; FIR filter, 522, 1904; FFT, 524, 1906; Peak detection, 526, 1908; Hold, 528, 1910, 1924, 1932; Output, 600; Description, 700; Block data, 800; Block type table, 801, 1301, 1701; No. item, 802; Block item, 803; Number of input signals item, 804; Number of output signals item, 805; Function item, 806; Number of conditions item, 1302; Signal item, 1303; Start coordinate item, 1304; End coordinate item, 1702; Function item, 1703; Complexity item, 1010; x-axis, 1020; y-axis, 1300; Signal connection table, 1700; Function complexity table, 1918; x2, 1920 threshold Value judgment: 1922, 1930. Delay: 1928 +7.

Claims

1. The model analysis unit analyzes the circuit model data, A complexity evaluation unit that evaluates the complexity of each of the one or more blocks constituting the model data obtained by the analysis, and the complexity of each of the one or more signals, The system includes a complexity calculation unit that calculates the complexity of the circuit based on the complexity of each of the one or more blocks and the complexity of each of the one or more signals, The aforementioned model data includes the position information of each of the one or more blocks associated with the order of data processing. The model analysis unit is an evaluation device that analyzes the position information to determine whether there are any blocks that are executed simultaneously and to determine the type of each of the one or more signals.

2. The evaluation device according to claim 1, wherein the position information is the arrangement coordinates of each of the one or more blocks.

3. The aforementioned arrangement coordinates are coordinates in a two-dimensional space consisting of a first axis and a second axis, The first axis represents the time series of the data processing in the circuit. The second axis indicates the direction in which the one or more blocks are arranged in parallel. The evaluation apparatus according to claim 2, wherein determining whether or not there are blocks to be executed simultaneously includes determining whether or not there are blocks to be executed simultaneously based on whether or not the difference in coordinates of each of the one or more blocks in the direction of the first axis is less than or equal to a predetermined threshold.

4. The aforementioned one or more blocks include a first block, a second block, and a third block, The second block and the third block have the same coordinates in the direction of the second axis, The first block, the second block, and the third block have different coordinates in the direction of the second axis, and The first block, the second block, and the third block are defined as follows when the difference in coordinates in the direction of the first axis is less than or equal to the predetermined threshold: The evaluation device according to claim 3, wherein the model analysis unit determines that the block with the earlier execution order among the second block and the third block is a block that is executed simultaneously with the first block.

5. The evaluation device according to claim 3, wherein the model analysis unit aligns the coordinates of the simultaneously executed blocks in the direction of the first axis based on the determination that there are blocks that are executed simultaneously.

6. The evaluation device according to claim 1, wherein the position information of each of the one or more blocks is a delay from the start of the data processing to the time when the processing of each of the one or more blocks is executed.

7. The evaluation apparatus according to claim 6, wherein determining whether or not there are concurrently executed blocks includes determining whether or not there are concurrently executed blocks based on whether or not the delays of each of the one or more blocks, or the combination of the one or more blocks, are the same.

8. The evaluation apparatus according to claim 6, wherein the model analysis unit, when the model data comprises a plurality of circuits that are executed in parallel, specifies a point for aligning the execution timing of the plurality of circuits, adds a delay block to the circuits among the plurality of circuits that require additional delay in order to align the delays in the execution timing of the plurality of circuits.

9. The complexity evaluation unit calculates the complexity of each of the one or more blocks based on the function of each of the one or more blocks, according to any one of claims 1 to 8.

10. The evaluation device according to any one of claims 1 to 8, wherein the complexity evaluation unit calculates the complexity of the conditional branch block based on the number of input signals, the number of output signals, and the number of conditions of the conditional branch block when one or more of the blocks are conditional branch blocks.

11. The evaluation device according to any one of claims 1 to 8, wherein the complexity evaluation unit calculates the complexity of each of the one or more signals based on whether or not each of the one or more signals exhibits a feedback loop.

12. Analyzing circuit model data, The complexity of each of the one or more blocks constituting the model data obtained by the analysis, and the complexity of each of the one or more signals, This includes calculating the complexity of the circuit based on the complexity of each of the one or more blocks and the complexity of each of the one or more signals, The aforementioned model data includes the position information of each of the one or more blocks associated with the order of data processing. A circuit evaluation method further comprising analyzing the position information to determine whether there are any blocks that are executed simultaneously, and determining the type of each of the one or more signals.

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