Piezoelectric device

Abstract

To improve a piezoelectric element.SOLUTION: A piezoelectric device includes a piezoelectric element layer including a piezoelectric element, a thin film transistor layer between the piezoelectric element layer and a supporter, and a pedestal disposed between the supporter and the thin film transistor layer or on the side of the supporter opposite to the thin film transistor layer. The piezoelectric element includes an upper electrode, a lower electrode, and a piezoelectric film between the upper electrode and the lower electrode. Inside the pedestal, there is a gap region overlapping with the piezoelectric element in the stacking direction.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to piezoelectric devices.

Background Art

[0002] Ultrasonic sensors are used in various fields, such as non-destructive inspection of objects, object detection, and fingerprint reading. For example, as fingerprint sensors, integrated MEMS ultrasonic fingerprint sensors using MEMS (Micro Electro Mechanical Systems) and TFT (Thin Film Transistor) ultrasonic fingerprint sensors have been developed. These include a pixel array composed of two-dimensionally arranged pixels, and each pixel includes an ultrasonic transducer.

[0003] The ultrasonic transducer is, for example, a piezoelectric element. The ultrasonic transducer in a pixel may be composed of a single element that transmits and receives ultrasonic waves, or may be composed of a transmitter that transmits ultrasonic waves and a receiver that receives ultrasonic waves. Specifically, the ultrasonic transducer emits ultrasonic waves in response to an electrical signal, receives the ultrasonic waves reflected by an object, and converts them into an electrical signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] A TFT-driven fingerprint sensor using a piezoelectric element has a structure in which a piezoelectric thin film is sandwiched between upper and lower electrodes and utilizes thickness vibration. In this case, there is a problem that the voltage-pressure conversion efficiency is low and the power consumption increases when multi-pixel and large-area are realized. In order to increase the piezoelectric vibration amplitude, a thin-film piezoelectric element using a diaphragm structure has been proposed. However, in a fingerprint sensor having a diaphragm structure, the process damage during void generation easily reaches the piezoelectric element.

Means for Solving the Problems

[0007] One aspect of the present disclosure is a piezoelectric device having a stacked structure on a support, including a piezoelectric element layer including a piezoelectric element, a thin-film transistor layer between the piezoelectric element layer and the support, and a pedestal disposed between the support and the thin-film transistor layer. The piezoelectric element includes an upper electrode, a lower electrode, and a piezoelectric film between the upper electrode and the lower electrode. Inside the pedestal, there is a void region that overlaps the piezoelectric element in the stacking direction.

Effects of the Invention

[0008] According to one aspect of the present disclosure, the piezoelectric element can be improved.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 6

Figure 7A

Figure 7B

Figure 7C

Figure 7D

Figure 8

Figure 9A

Figure 9B

Figure 10

Figure 11A

Figure 11B

Figure 11C

Figure 11D

Figure 12A

Figure 12B

Figure 12C

Figure 12D

Figure 13A

Figure 13B

Figure 13C

Embodiments for Carrying Out the Invention

[0010] Hereinafter, the ultrasonic sensor device of the present disclosure will be described in detail with reference to the drawings. The size and scale of each component in each drawing are appropriately changed and described in order to ensure the visibility of the drawing. Also, the hatching in each drawing is for distinguishing each component and does not necessarily mean a cut surface. Further, although the non-linear element used as a switching element or an amplifying element is referred to as a transistor, the transistor includes a Thin Film Transistor (TFT).

[0011] The ultrasonic sensor device of the present disclosure can be used, for example, in medical or industrial inspection fields, or for fingerprint and object detection. The ultrasonic sensor device according to an embodiment of the present specification includes a pixel array composed of a plurality of arranged pixels. The pixel array is composed of pixels in a one-dimensional array or a two-dimensional array, for example.

[0012] Each pixel includes a piezoelectric element as an ultrasonic transducer. The piezoelectric element transmits and receives ultrasonic waves. The piezoelectric element may be composed of a single element that transmits and receives ultrasonic waves, or may be composed of a transmitter that transmits ultrasonic waves and a receiver that receives ultrasonic waves. The ultrasonic wave has a frequency outside the audible range of 20 kHz or more. The frequency of the ultrasonic wave is appropriately selected according to the application field and usage situation.

[0013] The piezoelectric element generates ultrasonic waves according to an electrical signal from the control circuit and converts the received ultrasonic waves into an electrical signal. The pixel holds the electrical signal converted by the piezoelectric element. The received signal converted by the piezoelectric element is transmitted from the pixel to the control circuit as a response signal.

[0014] The TFT-driven fingerprint sensor using a piezoelectric element has a structure in which a piezoelectric thin film is sandwiched between upper and lower electrodes and utilizes thickness vibration. In this case, there is a problem that the voltage-pressure conversion efficiency is low and the power consumption increases when multi-pixels and large areas are formed. In order to increase the piezoelectric vibration amplitude, a thin film piezoelectric element using a diaphragm structure has been proposed. However, in a fingerprint sensor having a diaphragm structure, the process damage during void generation easily reaches the piezoelectric element.

[0015] One embodiment of the present disclosure realizes a diaphragm structure by forming a void below the vibrating region of the thin film transistor layer. Thereby, the process damage to the piezoelectric element during void generation can be reduced. [Device Configuration]

[0016] FIG. 1 is a block diagram showing a configuration example of an ultrasonic sensor device according to an embodiment of the present disclosure. The ultrasonic sensor device 10 includes a pixel array substrate 11 and a control circuit. The ultrasonic sensor device 10 and the pixel array substrate 11 are piezoelectric device. The control circuit includes a multiplexer circuit 15, a drive circuit 14, a signal detection circuit 16, and a main control circuit 18. Note that a part of the control circuit may be omitted or other circuits may be added, and a part of the functions of one circuit may be included in other circuits.

[0017] The pixel array substrate 11 includes an insulating substrate (for example, a glass substrate) and a pixel region 12 in which pixels 13 are arranged in a vertical and horizontal matrix on the insulating substrate. The pixel array in this example is composed of two-dimensionally arranged pixels, but may be composed of one-dimensionally arranged pixels.

[0018] The multiplexer circuit 15 is formed on the insulating substrate of the pixel array substrate 11, is connected to each signal line Dm of the pixel columns arranged in the vertical direction in FIG. 1, and reduces the number of signal lines by converting them in time series in the multiplexer circuit, and then the signal detection circuit 16 performs detection.

[0019] The drive circuit 14 controls the driving of the pixels 13 for transmitting and receiving ultrasonic waves by the pixels 13. The multiplexer circuit 15 receives the ultrasonic detection signals from the pixels 13 transmitted by the signal lines Dm and outputs them to the signal detection circuit 16. The signal detection circuit 16 detects the signals from each of the signal lines converted in time series by the multiplexer circuit.

[0020] The main control circuit 18 controls the drive circuit 14, the multiplexer circuit 15, and the signal detection circuit 16. The main control circuit 18 acquires the response signals output from each pixel and performs necessary processing. The drive circuit 14, the signal detection circuit 16, and the main control circuit 18 may be mounted on the pixel array substrate 11 or as separate components from the pixel array substrate 11.

[0021] FIG. 2 schematically shows a configuration example of a terminal including a pixel array substrate 11 according to an embodiment of the present disclosure. The terminal includes a stacked pixel array substrate 11, a display panel 31, and a touch panel 32. The touch panel 32 can adopt any type of touch detection method such as a capacitance type or a resistive film type. The display panel 31 may be an OLED (Organic light emitting diode) display panel or other types of display panels. The display panel 31 and the touch panel 32 can be controlled by a main control circuit 18 together with the pixel array substrate 11.

[0022] The positional relationship among the pixel array substrate 11, the display panel 31, and the touch panel 32 is not limited to the example in FIG. 2 and is arbitrary. For example, the pixel array substrate 11 and the display panel 31 may not be stacked and may be arranged apart from each other in the plane (as viewed in the stacking direction) on one side or different sides of the touch panel 32. The laminate of the display panel and the touch panel and the laminate of the pixel array of the ultrasonic sensor device and other touch panels may be separately mounted. The pixel array substrate 11 may not be stacked with other functional panels such as a display panel or a touch panel. [Pixel Circuit Configuration]

[0023] FIG. 3 shows the circuit configuration of one pixel 13. The pixel 13 includes a piezoelectric element PE which is an ultrasonic transducer. This piezoelectric element PE has both functions of ultrasonic oscillation and reception. One electrode of the piezoelectric element PE is indicated by the symbol TX. The electrode TX may be referred to as a transmission electrode and the other electrode as a reception electrode. In the element configuration example described later, the electrode TX is an upper electrode and the other electrode is a lower electrode. The side farther from the insulating substrate is the upper side and the closer side is the lower side.

[0024] In the piezoelectric element PE, a voltage VRX corresponding to the received ultrasonic vibration is induced. One pixel circuit of the ultrasonic sensor device 10 of the present disclosure includes three thin film transistors TR1, TR2, TR3, and a diode D1. The semiconductor material of the thin film transistor is, for example, low temperature polysilicon, an oxide semiconductor, or amorphous silicon.

[0025] The cathode terminal of diode D1 is connected to node N1 between the gate terminal of transistor TR1 and the source / drain terminal of transistor TR3. The anode terminal is connected to diode bias line PA. One of the source / drain terminals of transistor TR1 is connected to power line PP, and the other source / drain terminal is connected to one of the source / drain terminals of transistor TR2.

[0026] The gate terminal of transistor TR2 is connected to control line Rn. The other of the source / drain terminals of transistor TR2 is connected to signal line Dm. The gate terminal of transistor TR3 is connected to control line Rn+1. The signal transmitted by control line Rn+1 is the same as the signal transmitted by control line Rn of the next pixel row. The source / drain terminals of transistor TR3 are connected to the anode terminal and the cathode terminal of diode D1, respectively.

[0027] Transistor TR1 (amplification transistor) realizes the function of amplifying the potential at one end of piezoelectric element PE. Transistor TR2 is a switch element and realizes the function of controlling the output from the pixel circuit. Transistor TR3 is a switch element and realizes the function of resetting the potential at one end of piezoelectric element PE and the gate electrode (node N1) potential of transistor TR1.

[0028] In ultrasonic sensor device 10 shown in FIG. 1, there is one signal line Dm for one pixel column in which a plurality of pixels 13 are arranged in the vertical direction. All the pixels 13 in the same pixel column are connected to signal line Dm. This signal line Dm is connected to one multiplexer circuit 15 at the end of pixel array substrate 11. [Structure of Pixel]

[0029] FIG. 4 schematically shows a cross-sectional structure of a part of one pixel. In the following description, up and down refer to up and down in the drawing. Also, the side closer to the substrate is called the lower side, and the side farther from the substrate is called the upper side. The pixel array substrate 11 includes a support (substrate) 151 and a medium 210 facing the support 151. The medium 210 is, for example, a flexible or non-flexible insulating substrate of resin or glass. As shown in FIG. 2, a laminate of a display panel or a touch panel that does not affect ultrasonic waves may be disposed on or instead of the medium 210. A plurality of pixels are arranged in the plane between the support 151 and the medium 210.

[0030] The ultrasonic waves transmitted from the piezoelectric element are reflected from the surface of the medium 210 and return to the piezoelectric element. When, for example, human skin or the like exists on the surface of the medium 210, the reflectivity of the ultrasonic waves changes. The presence or absence (concavity and convexity) of the skin can be sensed by the intensity of the reflected ultrasonic waves.

[0031] The pixel includes a piezoelectric element layer 200 and a TFT layer 190 between the support 151 and the medium 210. The TFT layer 190 exists between the piezoelectric element layer 200 and the support 151. The TFT layer 190 includes a pixel circuit that drives and controls each piezoelectric element.

[0032] The piezoelectric element layer 200 includes a plurality of piezoelectric elements. The piezoelectric element, which is an ultrasonic transducer, includes a lower electrode 162, an upper electrode 166, and a piezoelectric film 165 (piezoelectric material layer). The piezoelectric film 165 is disposed between the upper electrode 166 and the lower electrode 162. The upper electrode 166 and the lower electrode 162 can be formed of a conductor, for example, ITO, molybdenum, or the like. The piezoelectric material may be an organic or inorganic material, and for example, polyvinylidene fluoride (PVDF) or lead zirconate titanate (PZT) can be used.

[0033] In the configuration example shown in FIG. 4, the upper electrodes 166 of the plurality of pixels are different portions of a single common electrode. In one embodiment of the present disclosure, the upper electrodes 166 of all the pixels in the pixel array are different portions of a single common electrode having a shape that completely covers the entire surface of the pixel region. The same applies to the piezoelectric film 165. The lower electrodes 162 are separated between the pixels. The plurality of lower electrodes 162 are disposed on the surface of the planarization film 161 in the piezoelectric element layer 200. The planarization film 161 is formed of, for example, an organic material.

[0034] The upper electrode 166 is a transmission electrode, and the lower electrode 162 is a reception electrode. By applying an excitation signal to the upper electrode 166, ultrasonic waves are simultaneously oscillated from the piezoelectric elements of all the pixels, and a reception signal unique to each pixel is obtained by the lower electrode 162. The upper electrode and the piezoelectric film may be separated for each pixel.

[0035] The TFT layer 190 includes a pixel circuit that drives and controls each piezoelectric element. The pixel circuit includes a plurality of switches. The pixel circuit (TFT layer 190) is formed between the support 151 and the layer of the lower electrode 162. The pixel circuit controls the potential of the lower electrode 162 and holds the reception signal of the lower electrode 162. In the configuration example shown in FIG. 4, the upper electrode 166 is disposed on the side (upper side in the drawing) that emits ultrasonic waves and receives reflected waves.

[0036] FIG. 4 shows the transistor TR3 and the transistor TR1 in the pixel circuit. The support 151 is formed of, for example, glass or resin and is a flexible or flexible substrate. A semiconductor active layer 155 is laminated on the insulating substrate 152. The insulating substrate 152 may be formed of an organic material such as polyimide, or may be a laminate of an inorganic film such as SiOx or SiNx and an organic material such as polyimide. The semiconductor active layer 155 includes a low-resistance source / drain region and a high-resistance channel region therebetween. The semiconductor material of the semiconductor active layer 155 may be, for example, low-temperature polysilicon, an oxide semiconductor, or amorphous silicon.

[0037] The semiconductor active layer 155 is covered with a gate insulating layer 156. The gate insulating layer 156 may be formed of an inorganic material such as silicon oxide, silicon nitride, or a laminate thereof. The gate insulating layer 156 is formed of, for example, silicon oxide. A gate electrode is formed on the semiconductor active layer 155 via the gate insulating layer 156. Ta, Mo, Al, or an alloy thereof can be used for the gate electrode.

[0038] The transistor TR3 includes a gate electrode 157A, and the transistor TR1 includes a gate electrode 157B. An interlayer insulating film 158 is formed on the layers of the gate electrodes 157A and 157B. The interlayer insulating film 158 may be formed of an inorganic material such as silicon nitride, silicon oxide, or a laminate thereof. The interlayer insulating film 158 is formed of, for example, silicon nitride.

[0039] Within the pixel region 12, a source / drain electrode layer of a transistor is formed on the interlayer insulating film 158. The source / drain electrode layer includes source / drain electrodes 159 and 160 of the transistor TR3 and a wiring portion 171. The source / drain electrode layer is formed of, for example, an Al-based alloy.

[0040] A passivation layer 175 is formed so as to cover the source / drain electrode layer. The passivation layer 175 may be formed of an inorganic material such as silicon oxide, silicon nitride, or a laminate thereof. The passivation layer 175 is formed of, for example, silicon oxide.

[0041] The source / drain electrodes 159 and 160 are connected to the semiconductor active layer 155 by contact portions formed in contact holes of the interlayer insulating film 158 and the gate insulating layer 156. The wiring portion 171 extends from the source / drain electrode 160 of the transistor TR3 and is connected to the gate electrode 157B of the transistor TR1 by a contact portion formed in a contact hole of the interlayer insulating film 158 and the gate insulating layer 156. The wiring portion 171 and the source / drain electrode 160 are formed of the same metal layer and are continuous.

[0042] An insulating planarization film 161 is formed over the source / drain electrodes 159 and 160 and the wiring portion 171. The planarization film 161 may be formed of, for example, an organic material. A lower electrode 162 is formed over the planarization film 161. The lower electrode 162 is connected to the source / drain electrode 160 or the wiring portion 171 by a contact portion 201 formed in a contact hole of the planarization film 161 and the passivation layer 175. The TFT layer 190 is formed below the lower electrode 162.

[0043] A piezoelectric film 165 is formed over the lower electrode 162. The piezoelectric film 165 is in contact with the upper surface of the lower electrode 162 and the upper surface of the planarization film 161. An upper electrode 166 is formed in contact with the piezoelectric film 165. The lower electrode 162, the piezoelectric film 165, and the upper electrode 166 constitute a piezoelectric element.

[0044] A pedestal layer exists between the insulating substrate 152 and the support 151. The pedestal layer includes a plurality of pedestals 250, and each pedestal 250 is a pedestal of the TFT layer 190 in each pixel. The pedestal layer further includes a void region 220 for each pixel 13, and at least a part of the void region 220 overlaps at least a part of the piezoelectric element in the stacking direction. The pedestals 250 exist outside the void region 220.

[0045] The gap region 220 realizes the diaphragm structure of the pixel 13, can increase the amplitude (sound pressure) of the piezoelectric element, and further can reduce the power consumption. The gap region 220 is formed on the opposite side of the piezoelectric element layer 200 with the TFT layer 190 interposed therebetween. Therefore, the process damage to the piezoelectric element can be reduced. In the related art, for the active element layer (corresponding to the TFT layer of the present disclosure), the gap region and the piezoelectric element layer are formed on the same surface side. Alternatively, the gap region and the piezoelectric element layer are formed in contact with each other. In such a case, the process damage when creating the gap region easily reaches the piezoelectric element layer. One embodiment of the present disclosure can solve this problem. Also, the gap region 220 can reduce the coupling capacitance between the contact portion 201 and the wiring in the TFT layer 190, and improve the SN of the signal from the pixel 13.

[0046] In one embodiment of the present specification, the entire area of the lower electrode 162 may be accommodated in the gap region 220 when viewed in the stacking direction (the vertical direction in FIG. 4). Thereby, the amplitude of the piezoelectric element can be increased more effectively.

[0047] There is no material constituting the pixel 13 in the gap region 220, including the material of the pedestal 250. The pedestal 250 is formed of the same or different material as the support 151. The pedestal 250 is formed of an organic material such as polyimide or photoresist, for example. By using an organic material, a pedestal 250 with a large thickness, that is, a deep gap region 220 can be easily formed. The depth of the gap region 220 means the dimension in the vertical direction, and may be, for example, between 20 μm and 500 μm. The pedestal 250 may be formed of an inorganic material.

[0048] FIG. 5A is a plan view showing a partial configuration of the pixel 13. As described above, the pixel 13 has a stacked structure composed of a plurality of layers. FIG. 5A shows some components of some layers of the pixel 13. In FIG. 5A, the lower electrode 162 of the piezoelectric element is shown by a dashed line. The contact portion 201 interconnects the lower electrode 162 and the wiring portion 171. In FIG. 5A, the piezoelectric film 165 and the upper electrode 166 are omitted.

[0049] In FIG. 5A, components in the same layer are illustrated with the same filling pattern. In the TFT layer 190, a pedestal layer 510 including a pedestal 250, a semiconductor layer 520 including a semiconductor active layer 155 of the TFT, a gate electrode layer 530 including gate electrodes 157A and 157B, and an S / D electrode layer 540 including source / drain electrodes 159 and 160 and a wiring portion 171 are illustrated in FIG. 5A. They are laminated in the order of the pedestal layer 510, the semiconductor layer 520, the gate electrode layer 530, and the S / D electrode layer 540 from the support 151.

[0050] FIG. 5B is a plan view schematically showing the pedestal 250 of pixel 13 included in the pedestal layer 510 shown in FIG. 5A. In the example shown in FIG. 5B, the pedestal 250 is ring-shaped and surrounds the entire void region 220. More specifically, the pedestal 250 is rectangular-ring-shaped and is composed of four side portions 252A, 252B, 252C, and 252D. The angle between adjacent side portions is a right angle.

[0051] Note that the pedestal 250 may have a ring shape different from a rectangle, may be composed of three sides or five or more sides, and may include curves. Also, the pedestal 250 may have a shape different from a ring shape. As shown in FIG. 5B, the entire lower electrode 162 of one pixel 13 is accommodated in the void region 220 when viewed in the stacking direction (the direction perpendicular to the paper surface in FIG. 5B). A part of the lower electrode 162 may exist outside the void region 220.

[0052] FIG. 5C schematically shows a layout example of the pedestal layer 510 and the semiconductor layer 520, which is a layer above it, in pixel 13. Also, FIG. 5D shows the pedestal layer 510, the semiconductor layer 520, and the gate electrode layer 530 above them.

[0053] FIG. 6 shows simulation results of a pixel having the void region 220 described with reference to FIGS. 4 to 5D and a pixel having no void region. The horizontal axis represents the vibration frequency of the piezoelectric element, and the vertical axis represents the amplitude. Line 601 shows the simulation result of the pixel having the void region 220, and line 602 shows the simulation result of the pixel having no void region 220. As shown in FIG. 6, the pixel having the void region 220 shows a larger amplitude and can lower the resonance frequency. The decrease in the resonance frequency realizes low power consumption, facilitation of the configuration of a high-frequency circuit, and reduction of the influence of parasitic capacitance.

[0054] Next, another configuration example of pixel 13 will be described. Unless otherwise specified, the description of the above other configuration examples can be applied. FIG. 7A is a plan view schematically showing the structure of pixel 13 according to an embodiment of the present specification. Compared with the structure example shown in FIG. 5A, the semiconductor and conductor included in the TFT layer 190 are arranged biased toward the ends of the void region 220. In the example shown in the figure, the components of the semiconductor layer 520, the gate electrode layer 530, and the S / D electrode layer 540 of the TFT layer 190 are brought closer to the ends within the region of pixel 13. The void region 220 surrounded by the pedestal 250 is indicated by a broken line.

[0055] Within the void region 220, there is a one-stroke writing region 222. The one-stroke writing region 222 is the region with the largest area among the continuous regions where there are no semiconductor layers and electrode layers that surround the edges of the components of the semiconductor layer 520, the gate electrode layer 530, and the S / D electrode layer 540 in one stroke. Since the components of the semiconductor layer 520, the gate electrode layer 530, and the S / D electrode layer 540 are brought closer to the ends within the region of pixel 13, the one-stroke writing region 222 is more than 1 / 3 of the area of the void region 220. Also, the central region 221 including the center of gravity of the void region 220 is indicated by a broken line. The stacking relationship of the different layers is the same as the structure shown in FIG. 4.

[0056] FIG. 7B is a plan view showing the positional relationship among the pedestal 250 in the pedestal layer 510, the void region 220 surrounded by the pedestal 250, the central region 221 of the void region 220, and the lower electrode 162 in the structure shown in FIG. 7A. In the example shown in FIG. 7B, when viewed in the stacking direction, the entire area of the lower electrode 162 overlaps with the void region 220, and the entire area of the central region 221 overlaps with the lower electrode 162.

[0057] In the configuration example shown in FIG. 7B, the void region 220 surrounded by the ring-shaped pedestal 250 is composed of a central region 221 including the center of gravity G of the void region 220 and an outer region outside thereof. The outer shape of the central region 221 is similar to the outer shape of the void region 220, and their centers of gravity G are common. The outer periphery of the central region 221 is composed of the midpoints between the center of gravity G and the outer periphery of the outer region (void region 220). In the example of FIG. 7B, the void region 220 is a rectangle with a vertical side length of 2LV and a horizontal side length of 2LH. The central region 221 is a rectangle with a vertical side length of LV and a horizontal side length of LH.

[0058] FIG. 7C schematically shows a layout example of the pedestal layer 510, the semiconductor layer 520, and the central region 211 in the pixel 13. FIG. 7D schematically shows a layout example of the pedestal layer 510, the semiconductor layer 520, the gate electrode layer 530, and the central region 211.

[0059] Referring to FIG. 7A, the density of the conductor and semiconductor regions in the central region 221 is smaller than that in the outer region. That is, the density of the conductor regions of the gate electrode layer 530 and the S / D electrode layer 540 in the central region 221 is smaller than their density in the outer region. Also, the density of the semiconductor region of the semiconductor layer 520 in the central region 221 is smaller than its density in the outer region.

[0060] In this way, by shifting the rigid conductor and semiconductor regions from the center to the ends, a larger amplitude can be obtained. In the examples shown in FIGS. 7A to 7D, although a part of the conductor and semiconductor regions exists within the central region 221, the conductor and semiconductor regions may be removed from the central region 221 without existing within the central region 221.

[0061] Next, another configuration example of pixel 13 will be described. FIG. 8 schematically shows a partial cross-sectional structure of one pixel 13. In the following, unless otherwise specified, the description of the above other configuration example may be applicable. As described above, a void region 220 is formed in pedestal layer 510 on support 151. Pedestal layer 510 is formed of, for example, a photoresist having a thickness of 10 μm to 100 μm.

[0062] Insulating substrate 152 is composed of an organic material and exists on pedestal layer 510. Insulating substrate 152 is formed of, for example, polyimide. Insulating substrate 152 has a thickness of, for example, 1 μm to 10 μm.

[0063] TFT layer 190 includes a plurality of inorganic insulating layers. Specifically, from the bottom, it includes gate insulating layer 156, interlayer insulating film 158, and passivation layer 175. Gate insulating layer 156 exists between the upper gate electrode layer 530 and the lower semiconductor layer 520. Interlayer insulating film 158 covers gate electrode layer 530 and exists between the upper S / D electrode layer 540 and the lower gate electrode layer 530. Passivation layer 175 is formed on S / D electrode layer 540 and interlayer insulating film 158.

[0064] These can be formed of silicon insulators. For example, gate insulating layer 156 is formed of silicon oxide, interlayer insulating film 158 is formed of silicon nitride, and passivation layer 175 is formed of silicon oxide. Each inorganic insulating layer may have a thickness of, for example, 0.1 μm to 1.0 μm.

[0065] In at least a partial region overlapping with the gap region 220 in the stacking direction, the inorganic substances are removed and do not exist. Specifically, in this region, the conductor layers 530, 504, the semiconductor layer 520, and the inorganic insulating layers 156, 158, and 175 are removed and do not exist. In the cross-section shown in FIG. 8, in the inorganic substance removal region 620 overlapping with the gap region 220, the conductor, semiconductor, and inorganic insulating materials of the TFT layer 190 are removed and do not exist. That is, the inorganic substance removal region 620 is a one-stroke writing region, and further, the inorganic insulating material is removed from the one-stroke writing region 222 shown in FIG. 7A.

[0066] In the TFT layer 190, the region from which the conductor, semiconductor, and inorganic insulating materials are removed is filled by a part of the planarization film 161. The planarization film 161 is formed of an organic insulator, for example, a photoresist or polyimide. The planarization film 161 may have a thickness of, for example, 0.5 μm to 2 μm. The planarization film 161 is an upper layer of the passivation layer 175 and covers the entire TFT layer 190.

[0067] In this way, by removing the rigid inorganic materials of the TFT 190 from at least a partial region overlapping with the gap region 220, the amplitude of the piezoelectric element can be improved. Note that in the removal region 620, inorganic substances of the inorganic insulator, that is, conductors or semiconductors, may exist.

[0068] A piezoelectric element is formed on the planarization film 161. The piezoelectric film 165 sandwiched between the upper electrode 166 and the lower electrode 162 may have a thickness of, for example, 1 μm to 10 μm. In the structural example shown in FIG. 8, a part of the lower electrode 162 overlaps with the gap region 220 when viewed in the stacking direction, and the other part exists outside the gap region 220.

[0069] FIG. 9A is a plan view schematically showing a structural example of a pixel including the inorganic substance removal region 620. FIG. 9B is a diagram for explaining the relationship between the pedestal layer 510 and other layers or regions in the structural example shown in FIG. 9A. FIG. 9B is a view of the structural example shown in FIG. 9A as seen from the lower side, that is, from the pedestal layer 510 side.

[0070] The entire inorganic substance removal region 620 indicated by the broken line overlaps with the void region 220 in the pedestal layer 510. When viewed in the stacking direction, the inorganic substance removal region 620 is a part of the void region 220. Also, a part of the central region 221 overlaps with the inorganic substance removal region 620, and the other part exists outside the inorganic substance removal region 620. The entire central region 221 may overlap with the inorganic substance removal region 620 when viewed in the stacking direction.

[0071] In the structural examples shown in FIGS. 9A and 9B, in each of the semiconductor layer 520, the gate electrode layer 530, and the S / D electrode layer 540, the region overlapping with the pedestal layer 510 is larger than the region outside the pedestal layer 510. More specifically, the entire semiconductor layer 520 overlaps with the pedestal layer 510. By arranging these layers constituting the TFT, i.e., the semiconductor layer 520, the gate electrode layer 530, and the S / D electrode layer 540, on the pedestal, the vibration of the TFT can be suppressed, and the electrical noise caused thereby can be reduced. Also, most of the gate electrode layer 530 and the S / D electrode layer 540 overlap with the pedestal layer 510. The entire gate electrode layer 530 and the S / D electrode layer 540 may overlap with the pedestal layer 510, and a part of the semiconductor layer 520 may exist outside the pedestal layer 510.

[0072] FIG. 10 shows the simulation results of a pixel having the void region 220 described with reference to FIGS. 7A to 7D and not having the inorganic substance removal region 620, and a pixel having the void region 220 and the inorganic substance removal region 620 described with reference to FIGS. 8 to 9B. The horizontal axis indicates the vibration frequency of the piezoelectric element, and the vertical axis indicates the amplitude.

[0073] Line 601 shows the simulation result of a pixel having the void region 220 and not having the inorganic substance removal region 620, and line 604 shows the simulation result of a pixel not having the void region 220. As shown in FIG. 10, the pixel having the inorganic substance removal region 620 shows a larger resonance amplitude and can also lower the resonance frequency. The decrease in the resonance frequency realizes low power consumption, facilitates the configuration of high-frequency circuits, and reduces the influence of parasitic capacitance. [Manufacturing Method]

[0074] Hereinafter, a method for manufacturing the pixel 13 on the pixel array substrate 11 will be described. FIGS. 11A to 11D show an example of the method for manufacturing the pixel 13. As shown in FIG. 11A, the manufacturing method forms patterns of the TFT layer 190, the piezoelectric element layer 200, and other necessary layers respectively on an insulating substrate formed of glass or polyimide, here a glass substrate 580, by patterning using photolithography.

[0075] For example, the metal layer can be formed by sputtering, for example, and the semiconductor layer and the inorganic insulator layer can be formed by CVD. The organic film can be formed, for example, by spin coating or solution coating method. Pattern formation of each layer is performed by etching and removing the photoresist pattern after forming the photoresist pattern. Formation of a low-resistance region in the semiconductor layer can utilize, for example, impurity ion implantation using a gate electrode as a mask or plasma treatment of an oxide semiconductor.

[0076] Next, as shown in FIG. 11B, a temporary support substrate 590 made of, for example, glass is bonded to the opposite side of the glass substrate 580, and the glass substrate 580 is peeled off from the TFT layer 190. Peeling of the glass substrate 580 can use, for example, laser lift-off.

[0077] Next, as shown in FIG. 11C, a pedestal layer 510 is formed with a photoresist pattern on the support 151, and the upper surface of the pedestal layer 510 and the lower surface of the TFT layer 190 are bonded together, for example, in a heated state. Another method may be to form the pedestal layer 510 on the lower surface of the TFT layer 190 by patterning the photoresist and attach the support 151 to the lower surface of the pedestal layer 510.

[0078] Next, as shown in FIG. 11D, the temporary support substrate 590 is peeled off from the piezoelectric element layer 200. For the peeling of the temporary support substrate 590, for example, laser lift-off can be used. Alternatively, when the temporary support substrate 590 is bonded in FIG. 11B, if an adhesive whose adhesive force decreases by heating is used, the temporary support substrate 590 can be peeled off simultaneously when the pedestal layer is bonded by heating in FIG. 11C.

[0079] As described above, in one embodiment of the present disclosure, after forming the TFT layer and the piezoelectric element layer on the substrate, the substrate is peeled off, a pedestal is formed on the insulating substrate or the TFT layer, and further, the pedestal is bonded to the TFT layer or the insulating substrate.

[0080] FIGS. 12A to 12D show another example of the manufacturing method of the pixel 13. As shown in FIG. 12A, a polyimide film 595 is formed on an insulating substrate, here a glass substrate 580, by, for example, a solution coating method or vapor deposition. Then, the TFT layer 195 and the piezoelectric element layer 200 are formed. In this example, the insulating substrate 152 under the semiconductor layer in the TFT layer 190 is omitted.

[0081] Next, as shown in FIG. 12B, after the temporary support substrate 590 is bonded to the upper surface of the piezoelectric element layer 200, the glass substrate 580 is peeled off by, for example, laser lift-off. Next, as shown in FIG. 12C, the polyimide film 595 is partially removed by patterning to form the pedestal layer 515 and the insulating substrate 525. In this way, the pedestal layer 515 (the pedestal) and the insulating substrate 525 are each a part of the polyimide film 595 and are integrally formed of the same material. A void region 527 is formed in the removed portion. In this example, the pedestal layer 515 exists on the lower surface of the insulating substrate 525, that is, on the opposite side of the TFT layer 195 with the insulating substrate 525 interposed therebetween.

[0082] As shown in FIG. 12D, the temporary support substrate 590 is peeled off from the piezoelectric element layer 200 and placed on the support 151. For example, laser lift-off can be used to peel off the temporary support substrate 590. As described above, in one embodiment of the present disclosure, an insulating film (e.g., a polyimide film) is formed on a substrate, and a TFT layer and a piezoelectric element layer are formed thereon. Then, the substrate is peeled off, and a part of the insulating film is removed to form a pedestal, a void region, and an insulating substrate. This enables efficient manufacturing.

[0083] FIGS. 13A to 13C show another example of a method for manufacturing the pixel 13. In this example, voids and pedestals are formed in the glass substrate by etching using HF (hydrofluoric acid). This enables efficient manufacturing.

[0084] As shown in FIG. 13A, a semiconductor film 711, an insulating film 713 serving as a gate insulating layer, and a photoresist film 715 are sequentially formed on a glass substrate 701. Then, holes are formed in the photoresist film 715 by photolithography, and further, holes 731 penetrating the photoresist film 715, the insulating film 713, and the semiconductor film 711 are formed by etching. Note that the insulating film 713 may be omitted, and an inorganic or organic insulating film may be formed between the semiconductor film 711 and the glass substrate 701.

[0085] Next, as shown in FIG. 13B, the glass substrate 701 is etched with an HF solution as an etching solution through the holes 731 to form a void region 721. One or a plurality of holes 731 may be formed to form one void region 721. In the glass substrate 701, the region surrounding the void region 721 is a pedestal 751 (pedestal region), and the other part is a region of the support. In this example, the lower side of the pedestal 751 and the void region 721 corresponds to the insulating substrate. That is, the pedestal 751 is integrally formed of the same material as the support. After the void region 721 is formed, the photoresist film 715 is removed.

[0086] Next, as shown in FIG. 13C, the TFT layer 195 and the piezoelectric element layer 200 are formed. For example, the gate electrode layer is formed by sputtering and patterned by photolithography (including etching). Next, using the gate electrode as a mask, a low-resistance region is formed by impurity ion implantation or plasma. Thereafter, the interlayer insulating film is formed by CVD, and holes are formed in the interlayer insulating film and the gate insulating layer by photolithography. Next, the S / D electrode layer is formed by sputtering and patterned by photolithography.

[0087] Next, the passivation layer is formed by, for example, CVD, a planarization film is formed thereon by, for example, the coating method, and further, holes are formed by patterning. Next, the lower electrode of the piezoelectric element is formed by sputtering and patterned by photolithography. Further, the piezoelectric film is formed by, for example, the coating method or vapor deposition, and further, the upper electrode is formed by, for example, sputtering. Thus, the TFT layer 195 and the piezoelectric element layer 200 are formed. Note that the holes shown in the TFT layer 195 in FIG. 13C can be filled with the material of the planarization film.

[0088] As described above, in one embodiment of the present disclosure, after forming the semiconductor film 711 on the glass substrate 701, a void region is formed in the glass substrate by an etching solution through the holes formed in the semiconductor film 711. Thereafter, the TFT layer 195 including the semiconductor film 711 and the upper piezoelectric element layer 200 are formed by photolithography. Thereby, the void region and the pedestal can be efficiently formed.

[0089] As described above, the embodiments of the present disclosure have been described, but the present disclosure is not limited to the above-described embodiments. Those skilled in the art can easily change, add, and convert each element of the above-described embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

Description of Reference Numerals

[0090] 10 Ultrasonic sensor device, 11 Pixel array substrate, 12 Pixel region, 13 Pixel, 14 Driving circuit, 15 Multiplexer circuit, 16 Signal detection circuit, 18 Main control circuit, TR1, TR2, TR3 Transistors, D1 Diode, Rn, Rn+1 Control lines, Dm Signal line, PE Piezoelectric element, TX Transmission electrode, PA Diode bias wiring, PP Power supply line, 190, 195 TFT layers, 200 Piezoelectric element layer, 250 Pedestal, 510 Pedestal layer

Claims

1. A piezoelectric device having a laminated structure on a support, comprising: a piezoelectric element layer including a piezoelectric element; a thin film transistor layer between the piezoelectric element layer and the support; a pedestal disposed between the support and the thin film transistor layer; wherein the piezoelectric element includes an upper electrode, a lower electrode, and a piezoelectric film between the upper electrode and the lower electrode; inside the pedestal, there is a void region overlapping the piezoelectric element in the lamination direction; a piezoelectric device.

2. The piezoelectric device according to claim 1, wherein the entire area of the lower electrode is accommodated in the void region when viewed in the lamination direction; a piezoelectric device.

3. The piezoelectric device according to claim 1, wherein the pedestal is formed of a material different from that of the support; the pedestal is ring-shaped and surrounds the entire area of the void region; a piezoelectric device.

4. The piezoelectric device according to claim 1, wherein there is a substrate integrally formed of the same material as the pedestal between the pedestal and the thin film transistor layer; a piezoelectric device.

5. The piezoelectric device according to claim 1, wherein the semiconductor and conductor included in the thin film transistor layer are disposed biased towards the edge of the void region; a piezoelectric device.

6. The piezoelectric device according to claim 1, wherein the region of the thin film transistor layer overlapping the void region is composed of a central region including the center of gravity of the void region and an outer region outside the central region; the outer periphery of the central region is composed of the midpoint between the center of gravity and the outer periphery of the outer region; the density of the conductor region and the semiconductor region in the central region is smaller than the density of the conductor region and the semiconductor region in the outer region; a piezoelectric device.

7. The piezoelectric device according to claim 1, wherein the thin film transistor layer includes a semiconductor layer, a gate electrode layer, and a source / drain electrode layer; the maximum area of a continuous region where the semiconductor layer, the gate electrode layer, and the source / drain electrode layer do not exist, which surrounds the edges of the components of the semiconductor layer, the gate electrode layer, and the source / drain electrode layer in one stroke, is 1 / 3 or more of the area of the void region; a piezoelectric device.

8. The piezoelectric device according to claim 1, wherein the thin film transistor layer includes one or more inorganic layers; in the thin film transistor layer, at least a part of the region overlapping the void region in the lamination direction has the inorganic matter removed and is filled with an organic matter; a piezoelectric device.

9. A piezoelectric device according to claim 1, wherein the support and the pedestal are integrally formed of the same material, piezoelectric device.

10. A piezoelectric device according to claim 1, wherein the piezoelectric element layer includes a plurality of piezoelectric elements laid out in a plane, a void region overlapping each of the plurality of piezoelectric elements in a stacking direction exists between the thin film transistor layer and the support, the piezoelectric device includes a pedestal surrounding each of the void regions between the thin film transistor layer and the support, piezoelectric device.

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