Imaging device

Abstract

To provide an imaging device of low power consumption.SOLUTION: In a pixel, a first circuit and a second circuit are provided. The first circuit can generate imaging data, and can keep differential data from data acquired in an initial frame. In the second circuit, a circuit that compares the differential data with the voltage range that is optionally set is provided. The second circuit supplies a readout signal according to the comparison result to the first circuit. With this structure, readout is not performed from the pixel when it is determined that the differential data is within the set voltage range and readout is performed from the pixel only when it is determined that the differential data is not within the voltage range.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, as the technical field of one aspect of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, their operating methods, or their manufacturing methods can be cited as an example.

[0003] Note that in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of a semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device may have a semiconductor device.

Background Art

[0004] Techniques for forming transistors using an oxide semiconductor thin film formed on a substrate have attracted attention. For example, Patent Document 1 discloses an imaging device configured to use a transistor having an extremely low off-current with an oxide semiconductor in a pixel circuit.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the imaging of moving images using a CMOS image sensor or the like, an operation is performed to read out data acquired for all pixels for each frame. In this operation, data that can be regarded as the same may be acquired for the same pixel in a plurality of consecutive frames.

[0007] For example, a subject stationary outdoors is subject to changes in natural light brightness over time, but there are almost no changes that can be detected by humans in a short interval of 1 / 10 second or less corresponding to the frame rate of the moving image. That is, it can be said that data that can be regarded as the same is acquired over a plurality of frames.

[0008] This data is read out for each frame and consumes power. If the data can be regarded as the same, the power consumption can be reduced by omitting the read operation.

[0009] Therefore, one of the objects of one aspect of the present invention is to provide an imaging device with low power consumption. Or, one of the objects is to provide an imaging device capable of detecting changes in a subject. Or, one of the objects is to provide an imaging device with high reliability. Or, one of the objects is to provide a novel imaging device or the like. Or, one of the objects is to provide an operation method of the above imaging device. Or, one of the objects is to provide a novel semiconductor device or the like.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be naturally clarified from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention relates to an imaging device having a circuit that compares data between adjacent frames and determines pixels to be read out.

[0012] One aspect of the present invention is an imaging device having a first circuit and a second circuit in a pixel. The first circuit has a first node, a second node, and a first switch. The first node has a function of holding first image data generated in a first frame period, and the first node has a function of holding second image data generated in an n-th frame (n is a natural number of 2 or more) period. The second node has a function of holding difference data that is the difference between the first image data and the second image data. The first switch has a function of controlling the output of the first image data and the second image data. The second circuit has a comparison circuit and an output circuit. The comparison circuit has a function of determining whether the difference data is within an arbitrarily set voltage range. The output circuit outputs a voltage that turns off the first switch when the difference data is within the voltage range, and outputs a voltage that turns on the first switch when the difference data is not within the voltage range.

[0013] The first circuit has a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor. One electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the first transistor. The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor. One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. The other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fifth transistor. The other electrode of the second capacitor can be electrically connected to one of the source or drain of the sixth transistor. The fifth transistor can operate as the first switch.

[0014] The first circuit further includes a seventh transistor. One of the source or drain of the seventh transistor is electrically connected to the other of the source or drain of the first transistor and one of the source or drain of the second transistor. The other of the source or drain of the seventh transistor may be electrically connected to the gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor.

[0015] Preferably, the first to seventh transistors have a metal oxide in the channel formation region. The metal oxide can include In, Zn, and M (where M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0016] The comparison circuit includes a first sense amplifier and a second sense amplifier. The first sense amplifier has a third node, and the second sense amplifier has a fourth node. The output circuit has a fifth node. The first sense amplifier has a first input portion for inputting a voltage at the lower end of the voltage range, and the second sense amplifier has a second input portion for inputting a voltage at the upper end of the voltage range. The first sense amplifier and the second sense amplifier each have a third input portion to which the second node is electrically connected. The third node and the fourth node are electrically connected to the output circuit, and the fifth node can be electrically connected to the first switch.

[0017] The second node of one pixel may be electrically connected to the third input portion, and the first switches of a plurality of pixels may be electrically connected to the fifth node.

[0018] The second circuit further includes an inverter circuit. The transistors included in the inverter circuit, the first sense amplifier, the second sense amplifier, and the output circuit can have silicon in the channel formation region.

[0019] Alternatively, the first sense amplifier and the second sense amplifier each have a first power switch and a second power switch. The first power switch has a p-channel transistor, and the second power switch has an n-channel transistor. The n-channel transistor may have a metal oxide in a channel formation region. The metal oxide preferably has In, Zn, and M (where M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0020] The first circuit and the second circuit can have an overlapping region with each other. Alternatively, a plurality of first circuits and one second circuit may have an overlapping region with each other.

[0021] In another aspect of the present invention, in a pixel, a first voltage and a second voltage (first voltage < second voltage) are set, first image data is acquired in a first frame period, second image data is acquired in an nth frame (n is a natural number of 2 or more) period, a third voltage that is the difference between the first image data and the second image data is calculated, the first voltage, the second voltage, and the third voltage are compared, and when the third voltage is greater than the first voltage and less than the second voltage, the second data is not read out from the pixel, and when the third voltage is less than the first voltage or the third voltage is greater than the second voltage, the second data is read out from the pixel. This is an operation method of an imaging device.

Advantages of the Invention

[0022] By using one aspect of the present invention, an imaging device with low power consumption can be provided. Alternatively, an imaging device capable of detecting a change in a subject can be provided. Alternatively, a highly reliable imaging device can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, an operation method of the above imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

Brief Description of the Drawings

[0023]

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Embodiments for Carrying Out the Invention

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof may be omitted. Note that the hatching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings.

[0025] Also, even if an element is illustrated as a single element on a circuit diagram, the element may be composed of a plurality of elements as long as there is no functional inconvenience. For example, transistors operating as switches may be connected in series or in parallel. Also, the capacitor may be divided and arranged at a plurality of positions.

[0026] In addition, one conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in this specification, a plurality of names may be used for the same element. Also, even if elements are illustrated as being directly connected on a circuit diagram, in actuality, the elements may be connected via one or a plurality of conductors, and such a configuration is also included in the category of direct connection in this specification.

[0027] (Embodiment 1) In this embodiment, an imaging device which is one aspect of the present invention will be described with reference to the drawings.

[0028] One aspect of the present invention has a function of comparing data between frames and determining whether to perform reading according to the result. Whether to perform reading can be controlled on a pixel-by-pixel basis.

[0029] The pixel is provided with a first circuit and a second circuit. The first circuit can generate imaging data and can hold difference data that is the difference from the data of the initial frame. The second circuit is provided with a circuit that compares the difference data with an arbitrarily set voltage range. The second circuit supplies a read signal according to the comparison result to the first circuit.

[0030] By using this configuration, for example, when it is determined that the difference data is within the set voltage range, reading from the pixel is not performed, and when it is determined that the difference data is not within the voltage range, reading from the pixel can be performed.

[0031] Therefore, when data that can be regarded as the same as the data of the initial frame is acquired, the read operation can be omitted, and power consumption can be reduced. When performing this operation, based on the data of the initial frame, only the data of the pixel for which reading has been performed needs to be rewritten to generate frame data.

[0032] <Pixel circuit> FIG. 1 is a circuit diagram of a pixel included in an imaging device according to an aspect of the present invention. The pixel has a circuit 10 and a circuit 11. The circuit 10 has a function of generating and holding imaging data. Also, it can hold difference data that is the difference between the data acquired during the period of the first frame (initial frame) and the data acquired during the period of the nth (n is a natural number of 2 or more) frame (target frame). The circuit 11 is a determination circuit, and can determine the magnitude of the difference data and determine whether to perform reading from the circuit 10.

[0033] <Circuit 10> The circuit 10 includes a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a transistor 106, a transistor 107, a capacitor 108, and a capacitor 109. Note that the capacitor 108 can also be omitted.

[0034] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103, the gate of the transistor 104, one electrode of the capacitor 108, and one electrode of the capacitor 109. One of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 105. The other of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 106. The other electrode of the capacitor 109 is electrically connected to one of the source or drain of the transistor 107.

[0035] Also, the gate of the transistor 106 is electrically connected to the circuit 11 via the wiring 242. The other electrode of the capacitor 109 is electrically connected to the circuit 11 via the wiring 241.

[0036] Here, the point (wiring) where the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, the gate of the transistor 104, one electrode of the capacitor 108, and one electrode of the capacitor 109 are connected is defined as the node FD1. Also, the point (wiring) where the other electrode of the capacitor 109, one of the source or drain of the transistor 107, and the wiring 241 are connected is defined as the node FD2. The node FD1 can hold the data acquired in each frame period. The node FD2 can hold the data of the initial frame or the difference data, which is the difference between the data of the initial frame and the data of the target frame.

[0037] The other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 121. The other of the source or drain of the transistor 103 is electrically connected to the wiring 122. The other of the source or drain of the transistor 105 is electrically connected to the wiring 125. The other of the source or drain of the transistor 106 is electrically connected to the wiring 123. The other of the source or drain of the transistor 107 is electrically connected to the wiring 124.

[0038] The gate of the transistor 102 is electrically connected to the wiring 231. The gate of the transistor 103 is electrically connected to the wiring 232. The gate of the transistor 105 is electrically connected to the wiring 234. The gate of the transistor 107 is electrically connected to the wiring 233. Note that the wiring 234 is also electrically connected to the circuit 11.

[0039] The wirings 121 to 124 can have the function as a power supply line. For example, the wiring 121 can be a low potential power supply line, and the wirings 122, 123, and 124 can be high potential power supply lines. In the configuration shown in FIG. 1, since the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102, the power supply lines are as described above. On the other hand, as shown in FIG. 2A, the anode side of the photoelectric conversion device 101 may be electrically connected to the transistor 102. In this case, the wiring 122 may be a low potential power supply line, and the wirings 121, 123, and 124 may be high potential power supply lines.

[0040] The wirings 231 to 234 can have the function as signal lines for controlling the conduction of each transistor. The wiring 125 can have the function as an output line and is electrically connected to a readout circuit having, for example, an interlayer double sampling circuit (CDS circuit), an A / D conversion circuit, or the like.

[0041] Transistor 102 has a function of controlling the potential of node FD1. Transistor 103 has a function of resetting the potential of node FD1. Transistor 104 functions as an element of a source follower circuit. Transistors 105 and 106 have a function of selecting the output of a pixel. Transistor 107 has a function of resetting the potential of node FD2.

[0042] It is preferable to use, as the transistors included in circuit 10, transistors having a metal oxide in the channel formation region (hereinafter referred to as OS transistors). OS transistors have the characteristic of extremely low off-current. In particular, it is preferable to use transistors with low off-current for transistors 102, 103, and 107. By using these transistors as OS transistors, the period during which charges can be held at nodes FD1 and FD2 can be made extremely long, and image data with little deterioration can be read out.

[0043] In addition, transistors having silicon in the channel formation region (hereinafter referred to as Si transistors) can also be used for transistors 102 to 107. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single-crystalline silicon). Si transistors have high mobility and are suitable for high-speed operation.

[0044] When transistors 102 and 103 are Si transistors, it is preferable to adopt a configuration in which transistor 111 is further provided as shown in FIG. 2B. Here, transistor 111 is an OS transistor.

[0045] One of the source or drain of transistor 111 is electrically connected to the other of the source or drain of transistor 102 and one of the source or drain of transistor 103. The other of the source or drain of transistor 111 is electrically connected to the gate of transistor 104, one electrode of capacitor 108, and one electrode of capacitor 109.

[0046] The gate of transistor 111 is electrically connected to wiring 235. Wiring 235 can function as a signal line for controlling the conduction of transistor 111.

[0047] In the configuration of FIG. 2B, the point (wiring) to which the other of the source or drain of transistor 111, the gate of transistor 104, one electrode of capacitor 108, and one electrode of capacitor 109 are connected becomes node FD1.

[0048] Since transistor 111 is an OS transistor with low off-current, the charge holding function of nodes FD1 and FD2 can be enhanced. Also, since the photoelectric conversion device 101 can be an embedded photodiode formed on a silicon substrate, a pixel circuit with less noise can be formed.

[0049] <Circuit 11> FIG. 3 shows a circuit diagram of circuit 11. Circuit 11 has sense amplifiers 11A and 11B as comparison circuits. It also has an output circuit 11C. Inverters 171 and 172 are connected to a part of the signal lines connected to sense amplifiers 11A, 11B, and output circuit 11C. Note that the connection relationships of the elements constituting circuit 11 are referred to FIG. 3, and detailed descriptions are omitted.

[0050] Sense amplifier 11A has a configuration in which an inverter latch circuit (transistors 141, 142, 143, 144) is electrically connected to power switches (transistors 131, 133) connected to a high-potential power supply line (wiring 127), and the inverter latch circuit is electrically connected to power switches (transistors 135, 137) connected to a low-potential power supply line (wiring 128) via transistors 145 and 146.

[0051] The gate of transistor 145 is electrically connected to node FD2 of circuit 10 via wiring 241. The gate of transistor 146 is electrically connected to wiring 238. Wiring 238 is a wiring to which a fixed potential determined by the purpose is supplied.

[0052] Also, transistor 147 is electrically connected to node LATNB of the inverter latch circuit, and transistor 148 is electrically connected to node LATN. Transistor 147 has a function of precharging node LATNB to the potential of wiring 129. Transistor 148 has a function of precharging node LATN to the potential of wiring 129. The potential of wiring 129 can be, for example, a potential intermediate between the potential of wiring 127 and the potential of wiring 128.

[0053] Sense amplifier 11B has a configuration in which an inverter latch circuit (transistors 151, 152, 153, 154) is electrically connected to power switches (transistors 132, 134) connected to the high potential power supply line (wiring 127), and the inverter latch circuit is electrically connected to power switches (transistors 136, 138) connected to the low potential power supply line (wiring 128) via transistors 155 and 156.

[0054] The gate of transistor 155 is electrically connected to node FD2 of circuit 10 via wiring 241. The gate of transistor 156 is electrically connected to wiring 239. Wiring 239 is a wiring to which a fixed potential determined by the purpose is supplied.

[0055] Also, transistor 157 is electrically connected to node LATPB of the inverter latch circuit, and transistor 158 is electrically connected to node LATP. Transistor 157 has a function of precharging node LATPB to the potential of wiring 129. Transistor 158 has a function of precharging node LATP to the potential of wiring 129.

[0056] The output circuit 11C includes power switches (transistors 161, 162) connected to the high-potential power supply line (wiring 127), power switches (transistors 167, 168) connected to the low-potential power supply line (wiring 128), and transistors 163, 164, 165, 166, 169. Each transistor is electrically connected to the output node PCTR.

[0057] Also, the gates of transistors 164, 165 are electrically connected to the node LATN. The gates of transistors 163, 166 are electrically connected to the node LATPB. The gate of transistor 169 is electrically connected to the wiring 236 via the inverter 172. The output node PCTR is electrically connected to the gate of the transistor 106 included in the circuit 10 via the wiring 242.

[0058] Wiring 236, 234, 237 are electrically connected to the circuit 11. Wiring 236, 234, 237 are signal lines for controlling the conduction of the transistors.

[0059] When a high potential (“H”) is supplied to the wiring 236, the potential of the node PCTR is forced to be high potential (“H”), and the transistor 106 in the circuit 10 conducts. That is, the transistor 106, which is one of the two select transistors included in the circuit 10, can be forced to conduct.

[0060] The wiring 236 can be electrically connected to the gates of the transistors 131, 131, 161. Also, the wiring 236 can be electrically connected to the gates of the transistors 135, 136, 167, 169 via the inverter 172.

[0061] The wiring 234 can be electrically connected to the gates of the transistors 133, 134, 162 via the inverter 171. Also, the wiring 234 can be electrically connected to the gates of the transistors 137, 138, 168. When a low potential (“L”) is supplied to the wiring 236 and a high potential (“H”) is supplied to the wiring 234, each power switch can be turned on.

[0062] The wiring 237 can be electrically connected to the gates of the transistors 147, 148, 157, and 158. When a high potential (“H”) is supplied to the wiring 237, the transistors 147, 148, 157, and 158 are turned on, and the pre-charge of the nodes LATNB, LATN, LATPB, and LATP can be performed.

[0063] The circuit 11 includes p-channel transistors (transistors 131, 132, 133, 134, 141, 143, 151, 153, 161, 162, 164, 169). It also includes n-channel transistors (transistors 135, 136, 137, 138, 142, 144, 145, 146, 147, 148, 152, 154, 155, 156, 157, 158, 165, 166, 167, 168).

[0064] As these transistors, it is preferable to use Si transistors. Alternatively, OS transistors may be used for the n-channel transistors. In particular, by using OS transistors for the transistors 135, 136, 137, and 138 that constitute the power switch, unnecessary leakage current between the power lines generated during non-operation can be suppressed, and power consumption can be suppressed.

[0065] <Operations of Circuit 10 and Circuit 11> Next, the operations of circuit 10 and circuit 11 will be described. The operations include an imaging operation and a readout operation of an initial frame, a normal imaging operation, a differential calculation operation, a determination operation, etc., which will be described in order. In the following description, a high potential signal for turning on an n-channel transistor and a high potential signal for turning off a p-channel transistor are represented by “H”, and a low potential signal for turning off an n-channel transistor and a low potential signal for turning on a p-channel transistor are represented by “L”.

[0066] Also, in circuit 11, assume that potential VN is supplied to wiring 238 and potential VP is supplied to wiring 239. Potential VN is the voltage at the lower end of the voltage range used for determination, and potential VP is the voltage at the upper end. This voltage range corresponds to the range in which the data of the initial frame and the data of the target frame are regarded as the same.

[0067] <Imaging operation of the initial frame> Figure 4 is a timing chart for explaining the imaging operation (period T1) and the readout operation (period T2) of the initial frame. In the figure, [0] to [n] (n is a natural number) represent row numbers. Also, in the following description, only the explanation regarding row number [0] will be given.

[0068] During period T1, when the potential of wiring 231 is set to "H", the potential of wiring 232 is set to "H", the potential of wiring 233 is set to "H", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "L", and the potential of wiring 234[0:n] is set to "L", in circuit 10, transistors 102, 103, and 107 conduct, and the potentials of the cathode of the photoelectric conversion device 101 and node FD1 are reset to the potential "VRES1" of wiring 122. Also, the potential of node FD2 is reset to the potential "VRES2" of wiring 124.

[0069] Next, when the potential of wiring 231 is set to "L", charges accumulate at the cathode according to the operation of the photoelectric conversion device 101. Also, the potential of wiring 232 is set to "L", transistor 103 is made non-conductive, and the potential of node FD1 is held at "VRES1".

[0070] Next, when the potential of wiring 231 is set to "H" after a predetermined exposure time has elapsed, the charges accumulated at the cathode of the photoelectric conversion device 101 are transferred to node FD1. At this time, the potential of node FD1 decreases by a potential ("Vref") corresponding to the amount of transferred charges and becomes "VRES1 - Vref". At this time, assume that "VRES2" is supplied to node FD2.

[0071] Next, set the potential of wiring 231 to "L", the potential of wiring 233 to "L", turn off transistors 102 and 107, and hold the potential of node FD1 at "VRES1 - Vref". Also, hold the potential of node FD2 at "VRES2". Here, it can be said that "VRES2" is the value obtained by replacing the data of the initial frame. The above is the description of the imaging operation of the initial frame.

[0072] <Reading operation of the initial frame>

[0073] During period T2, when the potential of wiring 231 is "L", the potential of wiring 232 is "L", the potential of wiring 233 is "L", the potential of wiring 236 is "H", the potential of wiring 237 is "L", and the potential of wiring 234[0:n] is "L", as shown in FIG. 5, in circuit 11, all power switches are turned off and transistor 169 conducts. Therefore, the potential of output node PCTR becomes "H", and in circuit 10, transistor 106 conducts, and the potential of wiring 123 (power supply potential) is supplied to the other of the source or drain of transistor 104. Note that in the figure, 〇 indicates conduction of the transistor and × indicates non - conduction of the transistor.

[0074] Next, when the potential of wiring 234[0] is set to "H", transistor 105 conducts, and data corresponding to the potential of node FD1 is output to wiring 125. The above is the description of the reading operation of the initial frame. The data read here can be held in, for example, a frame memory.

[0075] <Normal imaging operation and differential calculation operation> FIG. 6 is a timing chart for explaining the normal imaging operation and differential calculation operation (period T3), differential determination operation and reading operation (period T4) following the reading operation of the initial frame (period T2 in FIG. 4).

[0076] During period T3, when the potential of wiring 231 is “H”, the potential of wiring 232 is “H”, the potential of wiring 233 is “L”, the potential of wiring 236 is “L”, the potential of wiring 237 is “L”, and the potential of wiring 234[0:n] is “L”, transistors 102 and 103 are turned on, and the cathode of the photoelectric conversion device 101 and the potential of node FD1 are reset to the potential “VRES1” of wiring 122.

[0077] At this time, since node FD2 is in a floating state, due to the capacitive coupling of capacitor 109, the change in the potential of node FD1 is added to the potential of node FD2. Since the change in the potential of node FD1 is “+Vref”, the potential of node FD2 becomes “VRES2 + Vref”.

[0078] Next, when the potential of wiring 231 is set to “L”, charges are accumulated at the cathode according to the operation of the photoelectric conversion device 101. Also, the potential of wiring 232 is set to “L”, and transistor 103 is turned off to hold the potential of node FD1 at “VRES1”.

[0079] Next, when the potential of wiring 231 is set to “H” after a predetermined exposure time has elapsed, the charges accumulated at the cathode of the photoelectric conversion device 101 are transferred to node FD1. At this time, the potential of node FD1 decreases by a potential (“Vtar1”) corresponding to the amount of transferred charges and becomes “VRES1 - Vtar1”. Also, due to the capacitive coupling of capacitor 109, the change in the potential of node FD1 is added to the potential of node FD2. Since the change in the potential of node FD1 is “-Vtar1”, the potential of node FD2 becomes “VRES2 + Vref - Vtar1”.

[0080] Next, the potential of wiring 231 is set to “L”, and transistor 102 is turned off to hold the potential of node FD1 at “VRES1 - Vtar1”. Also, the potential of node FD2 is held at “VRES2 + Vref - Vtar1”.

[0081] The above are the normal imaging operation and the difference calculation operation. As a result of the normal imaging operation, "VRES1 - Vtar1" is held at node FD1. Also, as a result of the difference calculation operation, "VRES2 + Vref - Vtar1" is held at node FD2. "VRES2" is the reset potential, but it can be regarded as 0. Therefore, "+Vref - Vtar1" is the difference itself between the data of the initial frame and the data acquired in the normal imaging operation.

[0082] <Difference determination operation, readout operation (no difference exceeding)>

[0083] During period T4, when the potential of wiring 231 is "L", the potential of wiring 232 is "L", the potential of wiring 233 is "L", the potential of wiring 236 is "L", the potential of wiring 237 is "H", and the potential of wiring 234[0:n] is "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 are turned on, and nodes LATNB, LATN, LATPB, and LATP are precharged to the potential of wiring 129.

[0084] Next, when the potential of wiring 237 is "L" and the potential of wiring 234[0] is "H", as shown in FIG. 8, all power switches are turned on, and current starts to flow through the sense amplifier. Here, the potential "VRES2 + Vref - Vtar1" of node FD2 is supplied to the gates of transistor 145 and transistor 155, the potential "VN" is supplied to wiring 238, and the potential "VP" is supplied to wiring 239.

[0085] At this time, as shown in FIG. 6, if "VN" < "VRES2 + Vref - Vtar1" < "VP", since the channel resistance of transistor 145 is lower than that of transistor 146, the precharge potential of node LATNB drops preferentially compared to the precharge potential of node LATN. Therefore, transistors 142 and 143 are turned on, and the power supply voltage is supplied from wirings 127 and 128, and the potentials of nodes LATNB and LATN are determined.

[0086] Also, since the channel resistance of transistor 156 is lower than that of transistor 155, the precharge potential of node LATP decreases preferentially over that of node LATPB. Therefore, transistors 151 and 154 conduct, and the power supply voltage is supplied from wirings 127 and 128, and the potentials of node LATP and node LATPB are determined.

[0087] At this time, since the potential of node LATN is "H" and the potential of node LATPB is "H", transistors 165 and 166 conduct, transistors 163 and 164 become non-conductive, and the potential of output node PCTR becomes "L". Therefore, in circuit 10, transistor 106 does not conduct, power is not supplied to transistor 104, and thus even if transistor 105 conducts, the data of node FD1 is not output to wiring 125. That is, if "VN" < "VRES2 + Vref - Vtar1" < "VP", no data is output from circuit 10.

[0088] Here, since a bias transistor (not shown) of a source follower is connected to wiring 125, if transistor 104 does not output data, the potential of wiring 125 becomes 0V. When reading data, a steady current flows through the bias transistor. Therefore, power consumption corresponding to the steady current can be suppressed if the read operation is not performed.

[0089] <Differential determination operation, read operation (with positive differential exceeding)> Using the timing chart of FIG. 9, the case where the differential exceeds the set voltage range on the higher side is explained. Note that since period T5 is the same normal imaging operation and differential calculation operation as period T3, the explanation is omitted. However, the potential of node FD1 by the normal imaging operation is "VRES1 - Vtar2" (Vtar1 > Vtar2), the potential of node FD2 is "VRES1 + Vref - Vtar2", and assume "VP" < "VRES1 + Vref - Vtar2".

[0090] During period T6, when the potential of wiring 231 is "L", the potential of wiring 232 is "L", the potential of wiring 233 is "L", the potential of wiring 236 is "L", the potential of wiring 237 is "H", and the potential of wiring 234[0:n] is "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 conduct, and nodes LATNB, LATN, LATPB, and LATP are pre-charged to the potential of wiring 129.

[0091] Next, when the potential of wiring 237 is "L" and the potential of wiring 234[0] is "H", as shown in FIG. 10, all power switches are turned on, and current starts to flow through the sense amplifier. Here, the potential "VRES2 + Vref - Vtar2" of node FD2 is supplied to the gates of transistor 145 and transistor 155, the potential "VN" is supplied to wiring 238, and the potential "VP" is supplied to wiring 239.

[0092] At this time, as shown in FIG. 9, if "VN" < "VP" < "VRES2 + Vref - Vtar2", since the channel resistance of transistor 145 is lower than that of transistor 146, the pre-charge potential of node LATNB decreases preferentially compared to the pre-charge potential of node LATN. Therefore, transistors 142 and 143 conduct, and the power supply voltage is supplied from wirings 127 and 128, and the potentials of nodes LATNB and LATN are determined.

[0093] Also, since the channel resistance of transistor 155 is lower than that of transistor 156, the pre-charge potential of node LATPB decreases preferentially compared to LATP. Therefore, transistors 152 and 153 conduct, and the power supply voltage is supplied from wirings 127 and 128, and the potentials of nodes LATPB and LATP are determined.

[0094] At this time, since the potential of node LATN is "H" and the potential of node LATPB is "L", transistors 163 and 165 are turned on, transistors 164 and 166 are turned off, and the potential of output node PCTR becomes "H". Therefore, in circuit 10, transistor 106 is turned on and power is supplied to transistor 104, so the data of node FD1 is output to wiring 125 by the conduction of transistor 105. That is, if "VN" < "VP" < "VRES2+Vref-Vtar2", data will be output from circuit 10.

[0095] The data output from circuit 10 is stored in the frame memory where the image data of the initial frame is stored at the address corresponding to that circuit 10. That is, data rewriting is performed only for the read address of circuit 10. By such an operation, the writing power can be reduced compared to the case of rewriting the data of all circuits 10.

[0096] Note that even when the read operation is not performed, digital data corresponding to 0V analog data is generated by the A / D conversion circuit. When such digital data is generated, control may be performed so as not to perform the writing operation to the frame memory.

[0097] <Differential determination operation, read operation (with minus differential exceeding)> Using the timing chart of FIG. 11, the case where the differential exceeds the set voltage range on the lower side will be described. Since period T7 is the same normal imaging operation and differential calculation operation as period T3, the description will be omitted. However, the potential of node FD1 by the normal imaging operation is "VRES1-Vtar3" ("Vtar3" > "Vtar1"), the potential of node FD2 is "VRES1+Vref-Vtar3", and "VRES1+Vref-Vtar3" < "VN" < "VP".

[0098] During period T8, when the potential of wiring 231 is "L", the potential of wiring 232 is "L", the potential of wiring 233 is "L", the potential of wiring 236 is "L", the potential of wiring 237 is "H", and the potential of wiring 234[0:n] is "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 conduct, and nodes LATNB, LATN, LATPB, and LATP are pre-charged to the potential of wiring 129.

[0099] Next, when the potential of wiring 237 is "L" and the potential of wiring 234[0] is "H", as shown in FIG. 12, all power switches are turned on, and current starts to flow through the sense amplifier. Here, the potential "VRES2 + Vref - Vtar3" of node FD2 is supplied to the gates of transistor 145 and transistor 155, the potential "VN" is supplied to wiring 238, and the potential "VP" is supplied to wiring 239.

[0100] At this time, as shown in FIG. 11, if "VRES2 + Vref - Vtar3" < "VN" < "VP", since the channel resistance of transistor 146 is lower than that of transistor 145, the pre-charge potential of node LATN decreases preferentially compared to the pre-charge potential of node LATNB. Therefore, transistors 141 and 144 conduct, and the power supply voltage is supplied from wirings 127 and 128, and the potentials of nodes LATN and LATNB are determined.

[0101] Also, since the channel resistance of transistor 154 is lower than that of transistor 155, the pre-charge potential of node LATP decreases preferentially compared to node LATPB. Therefore, transistors 151 and 154 conduct, and the power supply voltage is supplied from wirings 127 and 128, and the potentials of nodes LATP and LATPB are determined.

[0102] At this time, since the potential of node LATN is "L" and the potential of node LATPB is "H", transistor 164 conducts, transistors 163 and 165 do not conduct, and the potential of output node PCTR becomes "H". Therefore, in circuit 10, transistor 106 conducts and power is supplied to transistor 104, so the data of node FD1 is output to wiring 125 by the conduction of transistor 105. That is, if "VRES2 + Vref - Vtar3" < "VN" < "VP", data will be output from circuit 10.

[0103] As described above, the output of circuit 10 can be controlled by the operation of circuit 11. Note that as time passes, the data of the initial frame and the data of the target frame deviate greatly, so it is preferable to update the data of the initial frame at regular intervals or for every certain number of frames. Note that the data of the initial frame may be updated every other frame.

[0104] Also, in the timing charts of FIGS. 4, 6, 9, and 11, the operation of circuit 10 shown in FIG. 1 is shown. In the case of the configuration of FIG. 2B, the potential supply operation of wiring 235 may be added as shown in FIG. 13. Note that FIG. 13 shows the imaging operation (period T1) of the initial frame, and the same applies to the normal imaging operation (period T3, etc.).

[0105] <Configuration of Imaging Device> FIG. 14 is a block diagram for explaining an imaging device according to an aspect of the present invention. The imaging device includes a pixel array 21 having pixels (circuits 10 and 11) arranged in a matrix, a circuit 22 (load driver) having a function of selecting rows of the pixel array 21, a circuit 23 having a function of reading data from circuit 10, and a circuit 28 for supplying a power potential. Note that in FIG. 14, the number of wirings connecting each element is simplified. Also, circuits 22, 23, and 28 may be plural.

[0106] The circuit 23 can include a circuit 24 (CDS circuit) for performing correlated double sampling processing on the output data of the circuit 10, a circuit 25 (such as an A / D conversion circuit) having a function of converting the analog data output from the circuit 24 into digital data, a circuit 26 (column driver) having a function of selecting a column for outputting data, and the like. The circuit 10 and the circuit 23 are electrically connected via a wiring 125.

[0107] Here, in FIG. 14, it is illustrated such that the circuits 10 and 11 have an overlapping region. Although details will be described later, by forming the circuits 10 and 11 in a stack structure, it becomes easier to reduce the pixel area and the resolution can be increased. Further, by forming the circuit 11 with Si transistors and forming the circuit 10 thereon with OS transistors, a stack structure can be formed without performing processes such as bonding.

[0108] Note that it is not limited to a configuration in which one circuit 10 and one circuit 11 overlap. For example, as shown in FIG. 15A, a configuration in which two circuits 10 arranged in the horizontal direction (the direction in which the gate lines extend) overlap one circuit 11 may be used. Alternatively, as shown in FIG. 15B, a configuration in which two circuits 10 arranged in the vertical direction (the direction in which the source lines extend) overlap one circuit 11 may be used. Alternatively, as shown in FIG. 15C, a configuration in which 2×2 circuits 10 arranged in the horizontal and vertical directions overlap one circuit 11 may be used. Alternatively, as shown in FIG. 15D, a configuration in which 3×3 circuits 10 arranged in the horizontal and vertical directions overlap one circuit 11 may be used. Alternatively, the number of circuits 10 overlapping one circuit 11 may be more than 3×3.

[0109] Thus, in a configuration in which a plurality of circuits 10 are connected to one circuit 11, differential data of any one of the circuits 10 may be acquired, and other circuits 10 may perform the same operation according to the determination. An example thereof will be described below.

[0110] FIG. 16 is a diagram for explaining the connection form of 3×3 circuits 10 (circuits 10[0,0] to [2,2]) and one circuit 11. Since the three signal lines (wiring 231, 232, 233) in each row are electrically connected to each other, in the 3×3 circuits 10, operations other than the read operation are performed simultaneously. The selection signal lines (wiring 234[0:2]) of each row are electrically connected to the circuit 11 via the OR circuit 112. Therefore, the circuit 11 can be operated according to the selection operation of each row.

[0111] Here, one of the nodes FD2 of the circuit 10 is electrically connected to the circuit 11. FIG. 16 shows an example in which the node FD2 of the circuit 10[0,1] is connected to the circuit 11, but it may be connected to the node FD2 of other circuits 10. Further, the output node PCTR of the circuit 11 is electrically connected to all the circuits 10. Therefore, it is determined whether to read all the circuits 10 according to the value of the node FD2 of one circuit 10. In such a configuration, the number of circuits 11 can be reduced, so that the power required for precharging the sense amplifiers of the circuits 11 can be reduced.

[0112] FIG. 17 is a configuration in which a transistor 113 is added to the configuration of FIG. 16 and the OR circuit 112 is omitted. The transistor 113 is provided between the output node PCTR of the circuit 11 and the wiring 242. In the configuration of FIG. 17, first, the node FD2 of the circuit 10 in the row to be read first is connected to the circuit 11. The gate of the transistor 113 is connected to the wiring 234 connected to the circuit 10 of the row.

[0113] In the read operation of the first row, the potential of the output node PCTR is determined in the circuit 11, and the transistor 113 is turned on and output to each circuit 10. When reading the next row, the transistor 113 is turned off, so the potential of the wiring 242 is held. Therefore, the same operation (read or not read) can be performed in all the circuits 10.

[0114] In such a configuration, the potential generated at the output node PCTR of the circuit 11 can be held during the selection operation of the first row. Therefore, since it is not necessary to generate the potential of the output node PCTR during the selection operations of the other rows, the number of operations of the circuit 11 can be reduced, and the power consumption can be decreased.

[0115] In one aspect of the present invention, as illustrated in FIG. 18A, a configuration in which a back gate is provided for a transistor may be adopted. FIG. 18A shows a configuration in which the back gate is electrically connected to the front gate, which has the effect of increasing the on-current. Alternatively, as shown in FIG. 18B, a configuration in which a fixed potential can be supplied to the back gate may be adopted. In this configuration, the threshold voltage of the transistor can be controlled. Also, FIGS. 18A and 18B may be mixed within one circuit. Further, a transistor without a back gate may be provided.

[0116] Also, in the circuit 10, the arrangement order of the transistors 104, 105, and 106 connected in series to the wirings 123 and 125 may be the configurations shown in FIGS. 19A to 19E in addition to the configuration shown in FIG. 1.

[0117] Also, in the configuration of the circuit 10 shown in FIG. 2B, as shown in FIG. 20A, one of the source or drain of the transistor 103 may be electrically connected to the other of the source or drain of the transistor 111, one electrode of the capacitor 108, and the gate of the transistor 104. Further, as shown in FIG. 20B, the gate of the transistor 102 and the gate of the transistor 111 may be electrically connected by the wiring 231, and the wiring 235 may be omitted.

[0118] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0119] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one aspect of the present invention will be described.

[0120] <Structural example> FIG. 21A is a diagram showing an example of the structure of a pixel of an imaging device, and can have a stacked structure of layer 561 and layer 563.

[0121] Layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can have a layer 565a and a layer 565b as shown in FIG. 22A. In some cases, a layer may be equivalently referred to as a region.

[0122] The photoelectric conversion device 101 shown in FIG. 22A is a pn junction type photodiode. For example, a p-type semiconductor can be used for layer 565a and an n-type semiconductor can be used for layer 565b. Alternatively, an n-type semiconductor can be used for layer 565a and a p-type semiconductor can be used for layer 565b.

[0123] The above pn junction type photodiode can typically be formed using single crystal silicon.

[0124] In addition, the photoelectric conversion device 101 included in layer 561 may be a stack of a layer 566a, a layer 566b, a layer 566c, and a layer 566d as shown in FIG. 22B. The photoelectric conversion device 101 shown in FIG. 22B is an example of an avalanche photodiode. Layer 566a and layer 566d correspond to electrodes, and layer 566b and 566c correspond to a photoelectric conversion section.

[0125] Layer 566a is preferably a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a stack thereof can be used.

[0126] For layer 566d, it is preferable to use a conductive layer having high transmittance for visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene can be used. Note that a configuration in which layer 566d is omitted is also possible.

[0127] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode using, for example, a selenium-based material as the photoelectric conversion layer. It is preferable to use a selenium-based material which is a p-type semiconductor for the layer 566b, and a gallium oxide or the like which is an n-type semiconductor for the layer 566c.

[0128] A photoelectric conversion device using a selenium-based material has a characteristic of high external quantum efficiency with respect to visible light. In this photoelectric conversion device, by utilizing avalanche multiplication, the amplification of electrons with respect to the amount of incident light can be increased. Further, since the selenium-based material has a high optical absorption coefficient, it has production advantages such as that the photoelectric conversion layer can be formed as a thin film. The thin film of the selenium-based material can be formed using a vacuum evaporation method, a sputtering method, or the like.

[0129] As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS) can be used.

[0130] The n-type semiconductor is preferably formed of a material having a wide bandgap and having translucency with respect to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used. Further, these materials also have a function as a hole injection blocking layer and can also reduce the dark current.

[0131] Further, as shown in FIG. 22C, the photoelectric conversion device 101 included in the layer 561 may be a laminate of a layer 567a, a layer 567b, a layer 567c, a layer 567d, and a layer 567e. The photoelectric conversion device 101 shown in FIG. 22C is an example of an organic photoconductive film, the layer 567a is a lower electrode, the layer 567e is a translucent upper electrode, and the layers 567b, 567c, and 567d correspond to the photoelectric conversion unit.

[0132] Either one of the layers 567b and 567d of the photoelectric conversion unit can be a hole transport layer, and the other can be an electron transport layer. Also, the layer 567c can be a photoelectric conversion layer.

[0133] As the hole transport layer, for example, molybdenum oxide or the like can be used. As the electron transport layer, for example, C 60 、C 70 fullerenes such as, or derivatives thereof, can be used.

[0134] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0135] As the layer 563 shown in FIG. 21A, for example, a silicon substrate can be used. The silicon substrate has Si transistors or the like. Using the Si transistors, a pixel circuit can be formed. Also, a circuit for driving a pixel circuit or the like, a readout circuit for the pixel circuit, an image processing circuit, a neural network, a communication circuit, etc. can be formed.

[0136] Also, a memory circuit such as a DRAM (Dynamic Random Access Memory), a CPU (Central Processing Unit), an MCU (Micro Controller Unit), etc. may be formed. In the present embodiment, the circuits 10 and 11 described in Embodiment 1 are called pixel circuits, and the other above-mentioned circuits are called functional circuits.

[0137] For example, in the transistors included in the circuits 10, 11, and functional circuits (circuits 22, 23, 28, etc.), some or all of them can be provided in the layer 563.

[0138] Further, as shown in FIG. 21B, the layer 563 may be a stack of a plurality of layers. In FIG. 21B, three layers of layer 563a, layer 563b, and layer 563c are illustrated, but it may also be two layers. Or the layer 563 may be a stack of four or more layers. These layers can be laminated using, for example, a bonding process or the like. With such a configuration, the pixel circuit and the functional circuit can be dispersed in a plurality of layers and the pixel circuit and the functional circuit can be provided in an overlapping manner, so that a small and highly functional imaging device can be manufactured.

[0139] Further, as shown in FIG. 21C, the pixel may have a stacked structure of layer 561, layer 562, and layer 563.

[0140] The layer 562 can have an OS transistor. For example, the circuit 10 can be formed in the layer 562 and the circuit 11 can be formed in the layer 563. Also, one or more of the above-described functional circuits may be formed by an OS transistor. Or, one or more of the functional circuits may be formed using the Si transistor included in the layer 563 and the OS transistor included in the layer 562. Or, the layer 563 may be used as a support substrate such as a glass substrate, and the pixel circuit and the functional circuit may be formed by the OS transistor included in the layer 562.

[0141] For example, a normally-off CPU (also referred to as a "Noff-CPU") can be realized using an OS transistor and an Si transistor. Note that the Noff-CPU is an integrated circuit including a normally-off type transistor that is in a non-conductive state (also referred to as an off state) even when the gate voltage is 0V.

[0142] The Noff-CPU can stop the power supply to the unnecessary circuits within the Noff-CPU and put the circuits into a standby state. In the circuits where the power supply is stopped and in the standby state, no power is consumed. Therefore, the Noff-CPU can minimize the power consumption. Also, the Noff-CPU can retain information necessary for operations such as set conditions for a long time even when the power supply is stopped. To resume from the standby state, it is only necessary to resume the power supply to the circuits, and no rewriting such as set conditions is required. That is, a high-speed resume from the standby state is possible. In this way, the Noff-CPU can reduce the power consumption without significantly reducing the operating speed.

[0143] Also, as shown in FIG. 21D, the layer 562 may be a stack of a plurality of layers. In FIG. 21D, two layers, i.e., the layer 562a and the layer 562b, are illustrated, but a stack of three or more layers may also be possible. These layers can be formed, for example, by stacking them on the layer 563. Or, it may be formed by bonding the layer formed on the layer 563 and the layer formed on the layer 561.

[0144] As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, it is an oxide semiconductor containing indium, etc., and for example, CAAC-OS or CAC-OS described later can be used. In CAAC-OS, the atoms constituting the crystal are stable, and it is suitable for transistors that emphasize reliability. Also, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors that perform high-speed driving.

[0145] Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits an extremely low off-current characteristic of several yA / μm (current value per 1-μm channel width). In addition, the OS transistor has characteristics different from those of Si transistors, such as no occurrence of impact ionization, avalanche breakdown, and short-channel effects, and can form a high-voltage and highly reliable circuit. Also, variations in electrical characteristics due to non-uniform crystallinity, which are problematic in Si transistors, are less likely to occur in OS transistors.

[0146] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn-based oxide containing indium, zinc, and one or more selected from metals such as M (aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can be formed using, for example, a sputtering method, an ALD (Atomic layer deposition) method, or an MOCVD (Metal organic chemical vapor deposition) method.

[0147] When forming the In-M-Zn-based oxide by the sputtering method, it is preferable that the atomic ratio of the metal elements in the sputtering target satisfies In≧M and Zn≧M. As such atomic ratios of the metal elements in the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 10:1:3, etc. are preferable. Note that the atomic ratio of the formed semiconductor layer includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0148] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the semiconductor layer has a carrier density of 1×10 17 / cm3 Hereinafter, preferably 1×10 15 / cm 3 Hereinafter, more preferably 1×10 13 / cm 3 Hereinafter, even more preferably 1×10 11 / cm 3 Hereinafter, even more preferably 1×10 10 / cm 3 less than, and oxides having 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0149] Note that the present invention is not limited to these, and an oxide semiconductor having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate.

[0150] In the oxide semiconductor constituting the semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and the semiconductor becomes n-type. For this reason, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0151] In addition, when an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. For this reason, the concentration of the alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16atoms / cm 3 Make it as follows.

[0152] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. For this reason, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 5 × 10 18 atoms / cm 3 It is preferably made below.

[0153] In addition, when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen that binds to metal atoms to become water, so oxygen vacancies may be formed in the oxide semiconductor. When oxygen vacancies are contained in the channel formation region in the oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen enters oxygen vacancies may function as donors, and electrons as carriers may be generated. Also, part of the hydrogen may combine with oxygen that binds to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

[0154] Defects in which hydrogen enters oxygen vacancies can function as donors in the oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in the oxide semiconductor, it may be evaluated by the carrier concentration instead of the donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, the carrier concentration assuming a state where no electric field is applied may be used instead of the donor concentration. That is, the "carrier concentration" described in this specification and the like may be paraphrased as the "donor concentration" in some cases.

[0155] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) is 1 × 1020 atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 less than. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0156] Also, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, polycrystalline structure, microcrystalline structure, or amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0157] The oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide film with an amorphous structure is, for example, a completely amorphous structure and has no crystal part.

[0158] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.

[0159] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0160] CAC-OS is, for example, a composition of a material in which elements constituting an oxide semiconductor are unevenly distributed in a size range of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following, in an oxide semiconductor, a state in which one or more metal elements are unevenly distributed and regions containing the metal element are mixed in a size range of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0161] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may also be included.

[0162] For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO.) refers to indium oxide (hereinafter, InO X1 (where X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (where X2, Y2, and Z2 are real numbers greater than 0).), and gallium oxide (hereinafter, GaO X3 (where X3 is a real number greater than 0).), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are real numbers greater than 0).), etc., and the material separates to form a mosaic state, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 is a configuration uniformly distributed in the film (hereinafter, also referred to as a cloud state).

[0163] That is, CAC-OS is a composite oxide semiconductor having a structure in which a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 or a region mainly composed of InO X1 are mixed. In this specification, for example, when the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, it is said that the first region has a higher In concentration compared to the second region.

[0164] Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a representative example, InGaO3(ZnO) m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number). Examples of the crystalline compound include those represented by

[0165] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.

[0166] On the other hand, CAC-OS relates to the material composition of an oxide semiconductor. CAC-OS refers to a structure in which, in a material composition containing In, Ga, Zn, and O, a region observed as nanoparticle-like with Ga as the main component and a region observed as nanoparticle-like with In as the main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0167] Note that CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga is not included.

[0168] Note that GaO X3The region with In as the main component and In X2 Zn Y2 O Z2 or InO X1 as the main component may not have a clear boundary observable.

[0169] In addition, when one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are included instead of gallium, CAC-OS refers to a structure in which the region observed as nanoparticles mainly composed of the metal element and the region observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0170] CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by the sputtering method, any one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used as the film-forming gas. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, it is preferable to set the flow rate ratio of oxygen gas to be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0171] When CAC-OS is measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods, it has the characteristic that no distinct peak is observed. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0172] In addition, in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness (ring region) in a ring shape and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0173] In addition, for example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), GaO X3 is the main component region, and In X2 Zn Y2 O Z2 or InO X1 is the main component region, and it can be confirmed that they are unevenly distributed and have a mixed structure.

[0174] CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed and has properties different from those of the IGZO compound. That is, CAC-OS has a structure in which regions mainly composed of GaO X3 etc. and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 are phase-separated from each other, and the regions mainly composed of each element have a mosaic structure.

[0175] Here, the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 is a region with higher conductivity compared to the region mainly composed of GaO X3 etc. That is, when carriers flow through the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 as the main component, the conductivity as an oxide semiconductor is exhibited. Therefore, InX2 Zn Y2 O Z2 、 or InO X1 Regions where such is the main component are distributed in a cloud-like manner in the oxide semiconductor, thereby enabling a high field-effect mobility (μ).

[0176] On the other hand, regions where GaO X3 etc. are the main component are regions with high insulation compared to regions where In X2 Zn Y2 O Z2 、 or InO X1 is the main component. That is, when regions where GaO X3 etc. are the main component are distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.

[0177] Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by GaO X3 etc. and the conductivity caused by In X2 Zn Y2 O Z2 、 or InO X1 act complementarily to achieve a high on-current (I on ) and a high field-effect mobility (μ).

[0178] In addition, a semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0179] <Stacked Structure 1> Next, the stacked structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Or, some of the elements shown below may be omitted. Also, the stacked structure shown below can be formed using a bonding process, a polishing process, etc. as needed.

[0180] FIG. 23 is an example of a cross-sectional view of a laminate having layers 560, 561, and layer 563, and having a bonding surface between layer 563a and layer 563b that constitute layer 563.

[0181] <layer 563b> Layer 563b has elements of circuit 11 provided on silicon substrate 610. Here, transistor 203 and transistor 204 of inverter 172, and transistor 169 are shown as part of the elements of circuit 11.

[0182] In layer 563b, silicon substrate 610, insulating layers 611, 612, 613, 614, 615, 616, 617, 618 are provided. Also, conductive layer 619 is provided. Insulating layer 611 has a function as a protective film. Insulating layers 612, 613, 614, 615, 616, 617 have functions as interlayer insulating films and planarization films. Insulating layer 618 and conductive layer 619 have functions as bonding layers. Conductive layer 619 is electrically connected to transistor 169.

[0183] As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the interlayer insulating film and the planarization film, for example, an inorganic insulating film such as a silicon oxide film, an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. The bonding layer will be described later.

[0184] In addition, as the wiring, electrodes, and conductors that can be used for electrical connection between devices, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the above-described metal elements as components, or alloys combining the above-described metal elements, etc. may be appropriately selected and used. The conductor is not limited to a single layer, and may be a plurality of layers composed of different materials.

[0185] <Layer 563a> Layer 563a has elements of circuit 10. Here, transistor 102 and transistor 106 are shown as part of the elements of circuit 10. In the cross-sectional view shown in FIG. 23, their electrical connection is not shown.

[0186] A silicon substrate 632 and insulating layers 631, 633, 634, 635, 637, 638 are provided in layer 563a. In addition, conductive layers 636, 639 are provided.

[0187] Insulating layer 631 and conductive layer 639 have the function as a bonding layer. Insulating layers 634, 635, 637 have the function as an interlayer insulating film and a planarization film. Insulating layer 633 has the function as a protective film. Insulating layer 638 has the function of insulating silicon substrate 632 and conductive layer 639. Insulating layer 638 can be formed of the same material as other insulating layers. Also, insulating layer 638 may be formed of the same material as insulating layer 631.

[0188] Conductive layer 639 is electrically connected to the gate of transistor 106 and conductive layer 619. Also, conductive layer 636 is electrically connected to wiring 121 (see FIG. 1).

[0189] The Si transistor shown in FIG. 23 is of a fin type having a channel formation region on a silicon substrate (silicon substrates 610, 632). A cross-section in the channel width direction (the cross-section of A1 - A2 shown in layer 563a of FIG. 23) is shown in FIG. 24A. Note that the Si transistor may be of a planar type as shown in FIG. 24B.

[0190] Alternatively, as shown in FIG. 24C, it may be a transistor having a semiconductor layer 545 of a silicon thin film. The semiconductor layer 545 can be, for example, single-crystalline silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on the silicon substrate 632.

[0191] <layer 561> Layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on layer 563a. In FIG. 23, as the photoelectric conversion device 101, a configuration using the organic photoconductive film shown in FIG. 22C as the photoelectric conversion layer is shown. Here, layer 567a is used as the cathode and layer 567e is used as the anode.

[0192] Insulating layers 651, 652, 653, 654, and conductive layer 655 are provided in layer 561.

[0193] Insulating layers 651, 653, 654 have functions as an interlayer insulating film and a planarizing film. Further, insulating layer 654 is provided to cover the end portion of the photoelectric conversion device 101 and also has a function of preventing a short circuit between layer 567e and layer 567a. Insulating layer 652 has a function as an element isolation layer. As the element isolation layer, it is preferable to use an organic insulating film or the like.

[0194] Layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102 that layer 563a has. Layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 that layer 563a has via the conductive layer 655.

[0195] <layer 560> Layer 560 is formed on layer 561. Layer 560 has a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0196] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. As the light-shielding layer 671, a metal layer such as aluminum or tungsten can be used. Further, a dielectric film having a function as an antireflection film may be laminated on the metal layer.

[0197] A color filter can be used for the optical conversion layer 672. By assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel of the color filter, a color image can be obtained. For example, as shown in the perspective view (including a cross section) of FIG. 31A, the color filter 672R (red), the color filter 672G (green), and the color filter 672B (blue) can be assigned to different pixels, respectively.

[0198] Further, if a wavelength cut filter is used for the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be achieved.

[0199] For example, if an infrared filter that blocks light with a wavelength equal to or less than that of visible light is used for the optical conversion layer 672, an infrared imaging device can be achieved. Further, if a filter that blocks light with a wavelength equal to or less than that of near-infrared light is used for the optical conversion layer 672, a far-infrared imaging device can be achieved. Further, if an ultraviolet filter that blocks light with a wavelength equal to or greater than that of visible light is used for the optical conversion layer 672, an ultraviolet imaging device can be achieved.

[0200] Note that a plurality of different optical conversion layers may be arranged in one imaging device. For example, as shown in FIG. 31B, the color filter 672R (red), the color filter 672G (green), the color filter 672B (blue), and the infrared filter 672IR can be assigned to different pixels, respectively. With this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0201] Alternatively, as shown in FIG. 31C, the color filter 672R (red), the color filter 672G (green), the color filter 672B (blue), and the ultraviolet filter 672UV can be assigned to different pixels. In this configuration, a visible light image and an ultraviolet light image can be acquired simultaneously.

[0202] Further, if a scintillator is used for the optical conversion layer 672, an imaging device that obtains an image visualizing the intensity of radiation used in an X-ray imaging device or the like can be provided. When radiation such as X-rays transmitted through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is acquired by detecting the light with the photoelectric conversion device 101. Further, the imaging device having such a configuration may be used for a radiation detector or the like.

[0203] The scintillator includes a substance that emits visible light or ultraviolet light by absorbing the energy when irradiated with radiation such as X-rays or gamma rays. For example, those in which Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. are dispersed in resin or ceramics can be used.

[0204] A microlens array 673 is provided on the optical conversion layer 672. The light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, the condensed light can be incident on the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of resin, glass, or the like having high translucency with respect to light having the wavelength of the imaging target.

[0205] <Lamination> Next, the lamination of the layer 563b and the layer 563a will be described.

[0206] An insulating layer 618 and a conductive layer 619 are provided in layer 563b. The conductive layer 619 has a region embedded in the insulating layer 618. Also, the surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that their heights match respectively.

[0207] An insulating layer 631 and a conductive layer 639 are provided in layer 563a. The conductive layer 639 has a region embedded in the insulating layer 631. Also, the surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that their heights match respectively.

[0208] Here, it is preferable that the main components of the conductive layer 619 and the conductive layer 639 are the same metal element. Also, it is preferable that the insulating layer 618 and the insulating layer 631 are composed of the same components.

[0209] For example, for the conductive layers 619, 639, Cu, Al, Sn, Zn, W, Ag, Pt, Au, etc. can be used. From the ease of bonding, preferably Cu, Al, W, or Au is used. Also, for the insulating layers 618, 631, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used.

[0210] That is, it is preferable to use the same metal material shown above for each of the conductive layer 619 and the conductive layer 639. Also, it is preferable to use the same insulating material shown above for each of the insulating layer 618 and the insulating layer 631. With such a configuration, bonding can be performed with the boundary between layer 563b and layer 563a as the bonding position.

[0211] Note that the conductive layer 619 and the conductive layer 639 may have a multilayer structure of multiple layers. In that case, it is only necessary that the surface layer (bonding surface) is the same metal material. Also, the insulating layer 618 and the insulating layer 631 may also have a multilayer structure of multiple layers. In that case, it is only necessary that the surface layer (bonding surface) is the same insulating material.

[0212] Through this bonding, an electrical connection between the conductive layer 619 and the conductive layer 639 can be obtained. Also, a connection having the mechanical strength of the insulating layer 618 and the insulating layer 631 can be obtained.

[0213] For the bonding between metal layers, a surface activation bonding method can be used in which the oxide film on the surface and the adsorbed layer of impurities are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method or the like in which the surfaces are bonded by using both temperature and pressure can be used. Since bonding occurs at the atomic level in both cases, excellent bonding can be obtained not only electrically but also mechanically.

[0214] Also, for the bonding between insulating layers, after obtaining high flatness by polishing or the like, a hydrophilic bonding method or the like can be used in which the surfaces that have been subjected to hydrophilic treatment with oxygen plasma or the like are brought into contact and temporarily bonded, and then permanent bonding is performed by dehydration through heat treatment. Since the hydrophilic bonding method also causes bonding at the atomic level, excellent mechanical bonding can be obtained.

[0215] When laminating the layer 563b and the layer 563a, since the insulating layer and the metal layer are mixed on each bonding surface, for example, a combination of the surface activation bonding method and the hydrophilic bonding method may be used.

[0216] For example, a method can be used in which the surface is cleaned after polishing, an antioxidant treatment is performed on the surface of the metal layer, and then a hydrophilic treatment is performed for bonding. Also, the surface of the metal layer can be made of a metal with low oxidation resistance such as Au, and a hydrophilic treatment may be performed. In addition, a bonding method other than the methods described above may be used.

[0217] Through the above lamination, the elements of the layer 563b and the elements of the layer 563a can be electrically connected.

[0218] <Modification example of the laminated structure 1> FIG. 25 is a modification of the laminated structure shown in FIG. 23, in which the configuration of the photoelectric conversion device 101 included in layer 561 and a partial configuration of layer 563a are different, and there is also a bonding surface between layer 561 and layer 563a.

[0219] Layer 561 has a photoelectric conversion device 101, insulating layers 661, 662, 664, 665, and conductive layers 685, 686.

[0220] The photoelectric conversion device 101 is a pn junction type photodiode formed on a silicon substrate, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. The photoelectric conversion device 101 is an embedded type photodiode, and the dark current can be suppressed and the noise can be reduced by a thin p-type region (a part of layer 565b) provided on the surface side (current extraction side) of layer 565a.

[0221] The insulating layers 661 and the conductive layers 685, 686 have functions as bonding layers. The insulating layer 662 has functions as an interlayer insulating film and a planarizing film. The insulating layer 664 has a function as an element isolation layer. The insulating layer 665 has a function of suppressing the outflow of carriers.

[0222] A groove for separating pixels is provided in the silicon substrate, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the groove. By providing the insulating layer 665, the carriers generated in the photoelectric conversion device 101 can be suppressed from flowing out to adjacent pixels. In addition, the insulating layer 665 also has a function of suppressing the intrusion of stray light. Therefore, color mixing can be suppressed by the insulating layer 665. Note that an antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0223] The element isolation layer can be formed using the LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed using the STI (Shallow Trench Isolation) method or the like. As the insulating layer 665, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used. Note that the insulating layer 665 may have a multilayer structure. Note that a configuration without an element isolation layer can also be adopted.

[0224] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions embedded in the insulating layer 661. Also, the surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that their heights are the same.

[0225] In the layer 563a, an insulating layer 638 is formed on the insulating layer 637. Also, a conductive layer 683 electrically connected to one of the source or drain of the transistor 102 and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0226] The insulating layer 638 and the conductive layers 683 and 684 have the function of a bonding layer. The conductive layers 683 and 684 have regions embedded in the insulating layer 638. Also, the surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that their heights are the same.

[0227] Here, the conductive layers 683, 684, 685, and 686 are bonding layers similar to the aforementioned conductive layers 619 and 639. Also, the insulating layers 638 and 661 are bonding layers similar to the aforementioned insulating layers 618 and 631.

[0228] Therefore, by bonding the conductive layer 683 and the conductive layer 685, one of the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device and the source or drain of the transistor 102 can be electrically connected. Also, by bonding the conductive layer 684 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring 121 (see FIG. 1) can be electrically connected. Further, by bonding the insulating layer 638 and the insulating layer 661, an electrical and mechanical junction between the layer 561 and the layer 563a can be achieved.

[0229] <Stacked Structure 2> FIG. 26 is an example of a cross-sectional view of a laminate having layers 560, 561, 562, 563 and no bonding surface. An Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Since the configurations of the layer 563, the layer 561 and the layer 560 are the same as those shown in FIG. 23, the description thereof is omitted here.

[0230] <Layer 562> The layer 562 is formed on the layer 563. The layer 562 has an OS transistor. Here, the transistor 102 and the transistor 106 are shown as part of the elements of the circuit 10. In the cross-sectional view shown in FIG. 26, their electrical connection is not shown.

[0231] The layer 562 is provided with insulating layers 621, 622, 623, 624, 625, 626, 628. Also, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 121 (see FIG. 1).

[0232] The insulating layer 621 has a function as a blocking layer. The insulating layers 622, 623, 625, 626, 628 have functions as interlayer insulating films and planarization films. The insulating layer 624 has a function as a protective film.

[0233] As the blocking layer, it is preferable to use a film having a function of preventing the diffusion of hydrogen. In an Si device, hydrogen is required to terminate dangling bonds, but hydrogen near the OS transistor becomes one of the factors generating carriers in the oxide semiconductor layer, reducing reliability. Therefore, it is preferable to provide a hydrogen blocking film between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0234] As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0235] The gate of transistor 106 is electrically connected to transistor 169 via a plug.

[0236] One of the source or drain of transistor 102 is electrically connected to layer 567a of the photoelectric conversion device 101 included in layer 561. The conductive layer 627 is electrically connected to layer 567e of the photoelectric conversion device 101 included in layer 561.

[0237] Fig. 27A shows the details of the OS transistor. The OS transistor shown in Fig. 27A has a self-aligned structure in which an insulating layer is provided on a stack of an oxide semiconductor layer and a conductive layer, and source electrode 705 and drain electrode 706 are formed by providing an opening reaching the oxide semiconductor layer.

[0238] The OS transistor can have a configuration including a channel formation region formed in the oxide semiconductor layer, a source region 703, and a drain region 704, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. The oxide semiconductor layer 707 may be further provided in the opening.

[0239] As shown in FIG. 27B, the OS transistor may have a self-aligned structure in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.

[0240] Alternatively, as shown in FIG. 27C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0241] The OS transistor shows a structure having the back gate 535, but it may also have a structure without a back gate. The back gate 535 may be electrically connected to the front gate of the transistor provided opposite to each other, as in the cross-sectional view in the channel width direction of the transistor shown in FIG. 27D. Note that FIG. 27D shows an example of the cross-section of B1 - B2 of the transistor in FIG. 27A, and the same applies to transistors with other structures. Also, it may be configured to supply a fixed potential different from the front gate to the back gate 535.

[0242] <Modification Example 1 of the Stacked Structure 2> FIG. 28 is a modification example of the stacked structure shown in FIG. 26, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and a part of the configuration of the layer 562 are different, and it has a bonding surface between the layer 561 and the layer 562.

[0243] The photoelectric conversion device 101 included in the layer 561 is a pn junction photodiode formed on a silicon substrate, and is the same as the configuration shown in FIG. 25.

[0244] In the layer 562, an insulating layer 648 is formed on the insulating layer 626. Also, a conductive layer 688 electrically connected to one of the source or drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0245] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have regions embedded in the insulating layer 648. Also, the surfaces of the insulating layer 648 and the conductive layers 688 and 689 are planarized so that their heights match respectively.

[0246] Here, the conductive layers 688 and 689 are bonding layers similar to the aforementioned conductive layers 619 and 639. Also, the insulating layer 648 is a bonding layer similar to the aforementioned insulating layers 618 and 631.

[0247] Therefore, by bonding the conductive layer 688 and the conductive layer 685, one of the source or drain of the transistor 102 and the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device can be electrically connected. Also, by bonding the conductive layer 689 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring 121 (see FIG. 1) can be electrically connected. Also, by bonding the insulating layer 648 and the insulating layer 661, the electrical and mechanical bonding between the layer 561 and the layer 562a can be achieved.

[0248] When stacking multiple Si devices, multiple polishing processes and bonding processes are required. Therefore, there are problems such as a large number of processes, the need for dedicated equipment, low yield, etc., and the manufacturing cost is also high. Since the OS transistor can be formed by stacking on a silicon substrate on which the device is formed, the bonding process can be reduced.

[0249] <Modification Example 2 of the Stacked Structure 2> FIG. 29 is a modification example of the stacked structure shown in FIG. 28, in which the configuration of the layer 561 and a part of the configuration of the layer 562 are different, and it has a bonding surface between the layer 561 and the layer 562.

[0250] In this modification example, the transistor 102 included in the circuit 10 is provided in the layer 561. In the layer 561, the transistor 102 is formed of an Si transistor. One of the source or drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source or drain acts as the node FD1.

[0251] In this case, in the layer 562, transistors are provided, excluding at least the transistor 102 among the transistors constituting the circuit 10. FIG. 29 illustrates an example in which the transistors 104 and 106 are provided.

[0252] <Stacked structure 3> Also, in FIGS. 25 to 29, the stacked structure of the configuration of the circuit 10 shown in FIG. 1 is illustrated. However, in the case of the circuit 10 shown in FIG. 2B, the structure shown in FIG. 30 can be adopted. In FIG. 30, Si transistors 102, 103, 104, 105, 106 (the transistor 105 is not shown) are provided in the layer 561, and the transistor 111 which is an OS transistor is provided in the layer 561. Note that, in FIG. 30, a configuration in which the layer 562 and the layer 563 are bonded together is illustrated. However, similar to FIG. 29, a configuration in which the layer 561 and the layer 562 are bonded together may also be adopted.

[0253] <Package, module> FIG. 32A1 is an external perspective view of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 410 for fixing the image sensor chip 450 (see FIG. 32A3), a cover glass 420, an adhesive 430 for bonding the two, and the like.

[0254] FIG. 32A2 is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball grid array) with solder balls as bumps 440. Note that, not limited to BGA, it may have an LGA (Land grid array) or a PGA (Pin Grid Array), etc.

[0255] FIG. 32A3 is a perspective view of a package shown with a part of the cover glass 420 and the adhesive 430 omitted. An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 and the bump 440 are electrically connected via a through hole. The electrode pad 460 is electrically connected to the image sensor chip 450 by a wire 470.

[0256] Also, FIG. 32B1 is an external perspective view of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip 451 (see FIG. 32B3), a lens cover 421, a lens 435, and the like. Also, an IC chip 490 (see FIG. 32B3) having functions such as a drive circuit and a signal conversion circuit of the imaging device is provided between the package substrate 411 and the image sensor chip 451, and has a configuration as a SiP (System in package).

[0257] FIG. 32B2 is an external perspective view of the lower surface side of the camera module. The lower surface and side surfaces of the package substrate 411 have a QFN (Quad flat no-lead package) configuration in which mounting lands 441 are provided. Note that this configuration is an example, and a QFP (Quad flat package) or the above-described BGA may be provided.

[0258] FIG. 32B3 is a perspective view of the module shown with a part of the lens cover 421 and the lens 435 omitted. The land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by a wire 471.

[0259] By housing the image sensor chip in a package in the form described above, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0260] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0261] (Embodiment 3) As electronic devices that can use the imaging device according to one aspect of the present invention, display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like can be mentioned. Specific examples of these electronic devices are shown in FIGS. 33A to 33F.

[0262] FIG. 33A shows an example of a mobile phone, which has a housing 981, a display unit 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone is provided with a touch sensor on the display unit 982. Any operation such as making a call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus. The imaging device and its operation method according to one aspect of the present invention can be applied to the mobile phone, and power consumption can be suppressed.

[0263] FIG. 33B shows a portable data terminal, which has a housing 911, a display unit 912, a speaker 913, a camera 919, and the like. Information can be input and output by the touch panel function of the display unit 912. Also, characters and the like can be recognized from the image acquired by the camera 919, and the characters can be output as audio by the speaker 913. The imaging device and its operation method according to one aspect of the present invention can be applied to the portable data terminal, and power consumption can be suppressed.

[0264] Fig. 33C is a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, etc. A rotation mechanism or the like is provided in the camera unit 952, and by installing it on the ceiling, imaging of the entire surrounding area becomes possible. An imaging device and its operation method according to an aspect of the present invention can be applied to the elements for image acquisition in the camera unit, and power consumption can be suppressed. Note that the surveillance camera is a common name and does not limit the use. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0265] Fig. 33D is a video camera, which includes a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, etc. The operation keys 974 and the lens 975 are provided on the first housing 971, and the display unit 973 is provided on the second housing 972. An imaging device and its operation method according to an aspect of the present invention can be applied to the video camera, and power consumption can be suppressed.

[0266] Fig. 33E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, etc. An imaging device and its operation method according to an aspect of the present invention can be applied to the digital camera, and power consumption can be suppressed.

[0267] Fig. 33F is a wristwatch-type information terminal, which includes a display unit 932, a housing-cum-wristband 933, a camera 939, etc. The display unit 932 is provided with a touch panel for operating the information terminal. The display unit 932 and the housing-cum-wristband 933 have flexibility and excellent wearability on the body. An imaging device and its operation method according to an aspect of the present invention can be applied to the information terminal, and power consumption can be suppressed.

[0268] This embodiment can be appropriately combined with the descriptions of other embodiments.

Description of Reference Numerals

[0269] 10: Circuit, 11: Circuit, 11A: Sense Amplifier, 11B: Sense Amplifier, 11C: Output Circuit, 21: Pixel Array, 22: Circuit, 23: Circuit, 24: Circuit, 25: Circuit, 26: Circuit, 28: Circuit, 101: Photoelectric Conversion Device, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Transistor, 107: Transistor, 108: Capacitor, 109: Capacitor, 111: Transistor, 112: OR Circuit, 113: Transistor, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 131: Transistor, 132: Transistor, 133: Transistor, 134: Transistor, 135: Transistor, 136: Transistor, 137: Transistor, 138: Transistor, 141: Transistor, 142: Transistor, 143: Transistor, 144: Transistor, 145: Transistor, 146: Transistor, 147: Transistor, 148: Transistor, 151: Transistor, 152: Transistor, 153: Transistor, 154: Transistor, 155: Transistor, 156: Transistor, 157: Transistor, 158: Transistor, 161: Transistor, 162: Transistor, 163: Transistor, 164: Transistor, 165: Transistor, 166: Transistor, 167: Transistor, 168: Transistor, 169: Transistor, 171: Inverter, 172: Inverter, 203: Transistor, 204: Transistor, 231: Wiring, 232: Wiring, 233: Wiring, 234: Wiring, 235: Wiring, 236: Wiring, 237: Wiring, 238: Wiring, 239: Wiring, 241: Wiring, 242: Wiring, 410: Package Substrate, 411: Package Substrate, 420: Cover Glass, 421: Lens Cover, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image Sensor Chip, 451: Image Sensor Chip, 460: Electrode Pad, 461: Electrode Pad, 470: Wire, 471: Wire, 490: IC Chip, 535: Back Gate, 545: Semiconductor Layer, 546: Insulating Layer, 560: Layer, 561: Layer, 562: Layer, 562a: Layer, 562b: Layer, 563: Layer, 563a: Layer, 563b: Layer, 563c: Layer,565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 610: silicon substrate, 611: insulating layer, 612: insulating layer, 613: insulating layer, 614: insulating layer, 615: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 626: insulating layer, 627: conductive layer, 628: insulating layer, 631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light-shielding layer, 672: optical conversion layer, 673: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing-cum-wristband, 939: camera, 951: support base, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light-emitting part, 971: housing, 972: housing, 973: display unit, 974: operation key, 975: lens, 976: connection part, 977: speaker, 978: microphone, 981: housing, 982: display unit, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera,

Claims

【Claim 1】 An imaging device having a first circuit and a second circuit in a pixel, wherein the first circuit includes a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor; one electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the first transistor; the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor; the other of the source or drain of the second transistor is electrically connected to a first power line; one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor; the other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fifth transistor; the other of the source or drain of the fifth transistor is electrically connected to a second power line; the other electrode of the second capacitor is electrically connected to one of the source or drain of the sixth transistor; the other of the source or drain of the sixth transistor is electrically connected to a third power line; each of the first power line, the second power line, and the third power line is supplied with a potential higher than the other electrode of the photoelectric conversion device; the first circuit has a function of holding first image data generated in a first frame period at the gate of the third transistor of the first circuit; the first circuit has a function of holding second image data generated in an n-th frame period (n is a natural number of 2 or more) at the gate of the third transistor; the first circuit has a function of holding difference data, which is the difference between the first image data and the second image data, at one of the source or drain of the sixth transistor of the first circuit; the fifth transistor has a function of controlling the output of the first image data and the second image data; the second circuit includes a comparison circuit and an output circuit; The comparison circuit has a function of determining whether the differential data is within an arbitrarily set voltage range. The output circuit has a function of outputting a voltage for turning off the fifth transistor when the differential data is within the voltage range, and outputting a voltage for turning on the fifth transistor when the differential data is not within the voltage range. An imaging device. **Claim 2** In claim 1, each of the first transistor to the sixth transistor has a metal oxide in a channel formation region. An imaging device. **Claim 3** In claim 2, the metal oxide contains at least In. An imaging device.

Images