Semiconductor stack layer, semiconductor element, and method for manufacturing the same

Abstract

To provide a semiconductor stack layer, a semiconductor element, and a method for manufacturing the semiconductor element.SOLUTION: A semiconductor element includes a first semiconductor layer and a light emitting structure. The first semiconductor layer includes a first III-V group semiconductor material, a first impurity, and a second impurity. The light emitting structure is located in the first semiconductor layer and includes an active structure. The first semiconductor layer includes the second impurity in a higher concentration than the first impurity. The first impurity is carbon and the second impurity is hydrogen.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a light-emitting device including a semiconductor stack layer.

Background Art

[0002] With the rapid progress of science and technology, semiconductor devices play a very important role in fields such as information transmission and energy conversion, and research and development of related materials are continuously carried out. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic devices, such as light emitting diodes (LEDs), laser diodes (LDs), solar cells, etc., and can also be applied to fields such as lighting, medical, display, communication, detection, and power systems. Light-emitting diode devices are suitable for solid-state lighting sources, and have advantages such as low power consumption and long service life, so they are widely applied to traffic signal lights, backlight modules, various lighting, medical devices, etc. instead of conventional light sources.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a semiconductor stack layer, a semiconductor device, and a method for manufacturing the same.

Means for Solving the Problems

[0004] According to one aspect of the present invention, a semiconductor device is provided, which includes a first semiconductor layer and a light-emitting structure. The first semiconductor layer includes a first III-V semiconductor material, a first impurity, and a second impurity. The light-emitting structure is located on the first semiconductor layer and includes an active structure. In the first semiconductor layer, the concentration of the second impurity is higher than the concentration of the first impurity, the first impurity is carbon, and the second impurity is hydrogen.

[0005] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, which includes forming a first semiconductor layer, the first semiconductor layer including a first III-V semiconductor material, a first impurity, and a second impurity; and forming a light-emitting structure, the light-emitting structure being located on the first semiconductor layer and including an active structure. In the first semiconductor layer, the concentration of the second impurity is higher than the concentration of the first impurity, the first impurity is carbon, and the second impurity is hydrogen.

[0006] According to another aspect of the present invention, a semiconductor stack layer is provided, which includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a first III-V semiconductor material, a first impurity, and a second impurity. The second semiconductor layer is located on the first semiconductor layer and includes a second III-V semiconductor material. In the first semiconductor layer, the concentration of the second impurity is higher than the concentration of the first impurity, the first impurity is carbon, the second impurity is hydrogen, and the XRD FWHM of the first semiconductor layer is 300 arcsec or less.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 6

Mode for Carrying Out the Invention

[0008] Hereinafter, several embodiments will be described to enable those skilled in the art to more easily understand the present invention. Note that these embodiments are merely illustrative and do not limit the present invention. Also, those skilled in the art may adjust the embodiments described below according to needs. For example, the order of the processes may be changed, and / or some steps may be increased or decreased.

[0009] The general formula InGaAsP represents In x1 Ga 1-x1 As 1-y1 P y1 where 0 < x1 < 1 and 0 < y1 < 1; AlGaInAs represents (Al y2 Ga (1-y2) ) 1-x2 In x2 As, where 0 < x2 < 1 and 0 < y2 < 1; the general formula AlGaInP represents (Al y3 Ga (1-y3) ) 1-x3 In x3 P, where 0 < x3 < 1 and 0 < y3 < 1; the general formula InGaAs represents In x4 Ga 1-x4Represents As, where 0 < x4 < 1; the composition, additives, and impurities (dopants) of each layer included in the semiconductor device of the present invention can be analyzed by any suitable method, for example, SIMS (secondary ion mass spectrometer), and the thickness of each layer can also be analyzed by any suitable method, for example, TEM (transmission electron microscopy) or SEM (scanning electron microscope). Also, each impurity mentioned in the present invention is either deliberately added or inadvertently added. Deliberately adding means, for example, performing in-situ doping during the epitaxial growth period and / or executing an implanting process using a P-type or N-type dopant after epitaxial growth. Inadvertently adding means, for example, being generated by the design of the process.

[0010] What those skilled in the art should understand is that based on each embodiment described below, other components may be added. For example, unless otherwise specified, descriptions such as "forming a second layer on the first layer" may include embodiments where the first layer is in direct contact with the second layer, and may also include embodiments where there are other layers between the first layer and the second layer and the two do not directly contact each other. Also, the vertical relationship of each layer may change depending on the operation or use of the structure or device in different orientations. Furthermore, in the present invention, expressions such as "a layer consisting essentially of only X material" indicate that the main composition of the layer is X material, but do not exclude the inclusion of dopants and unavoidable impurities.

[0011] FIG. 1 is a structural diagram of a semiconductor stack layer 10 in an embodiment of the present invention. The semiconductor stack layer 10 includes a first semiconductor layer 100 and a second semiconductor layer 102. The second semiconductor layer 102 is adjacent to the first semiconductor layer 100. In this embodiment, the surface 100a of the first semiconductor layer 100 is in direct contact with the surface 102a of the second semiconductor layer 102. There is no other structure (such as a buffer layer, etc.) between the first semiconductor layer 100 and the second semiconductor layer 102.

[0012] In this embodiment, the first semiconductor layer 100 includes a first III-V semiconductor material. The first III-V semiconductor material is, for example, a binary III-V semiconductor material. The first III-V semiconductor material is a material composed of Group III and Group V elements in the periodic table of chemical elements. The Group III element may be Ga or In. The Group V element may be As or P, and preferably does not contain N. In one embodiment, the first semiconductor layer 100 consists essentially of only the first III-V semiconductor material, for example, consists essentially of only a binary III-V semiconductor material. In one embodiment, the first semiconductor layer 100 includes InP and preferably consists essentially of only InP. The first semiconductor layer 100 may contain impurities. In one embodiment, the first semiconductor layer 100 contains a first impurity and a second impurity. In this embodiment, the concentration of the second impurity in the first semiconductor layer 100 is greater than the concentration of the first impurity. The first impurity is, for example, carbon (C), and the second impurity is, for example, hydrogen (H). Thereby, the first semiconductor layer 100 has a surface with stable properties and relatively few crystal defects, and such a surface can be, for example, a surface for epitaxial layer growth. In one embodiment, the first semiconductor layer 100 may contain a third impurity. The third impurity is, for example, Si. In one embodiment, the impurities in the first semiconductor layer 100 each independently have an impurity concentration of about 1×10 16 cm -3 ~ about 1×10 19 cm -3 and may have an impurity concentration of, for example, about 5×10 16 cm -3 ~ about 5×10 17 cm -3 or an impurity concentration of about 6×10 17 cm -3 ~ about 5×10 18 cm -3 etc. In one embodiment, the concentration of the third impurity in the first semiconductor layer 100 is less than 1×10 19 cm -3 and, for example, is about 6×10 16 cm -3 ~ about 1×1017 cm -3 is within the range. When the impurities in the first semiconductor layer 100 have an appropriate impurity concentration, the first semiconductor layer 100 has relatively good conductivity. In one embodiment, the conductivity type of the first semiconductor layer 100 is N-type.

[0013] In this embodiment, the second semiconductor layer 102 includes a second III-V semiconductor material. The second III-V semiconductor material is, for example, a binary III-V semiconductor material. The second III-V semiconductor material is a material composed of elements of Group III and Group V in the periodic table of chemical elements. The Group III element may be Ga or In. The Group V element may be As or P, but preferably does not contain N. The second III-V semiconductor material is different from the first III-V semiconductor material. In one embodiment, each constituent element of the second III-V semiconductor material is different from each constituent element of the first III-V semiconductor material. In one embodiment, the second semiconductor layer 102 consists essentially of only the second III-V semiconductor material, for example, consists essentially of only a binary III-V semiconductor material. In one embodiment, the second semiconductor layer 102 includes GaAs and preferably consists essentially of only GaAs. The second semiconductor layer 102 may contain a plurality of impurities. The plurality of impurities in the second semiconductor layer 102 are each independently about 5×10 15 cm -3 ~ about 1×10 20 cm -3 and may have an impurity concentration of, for example, about 1×10 17 cm -3 ~ about 1×10 18 cm -3 an impurity concentration of, about 1×10 18 cm -3 ~ about 1×10 19 cm -3 an impurity concentration of, or about 1×10 19 cm -3 ~ about 1×10 20 cm -3has an impurity concentration. When the impurities in the second semiconductor layer 102 have an appropriate impurity concentration, the second semiconductor layer 102 has relatively good conductivity. The impurities in the second semiconductor layer 102 may include Si, Zn, C, or H, etc. In one embodiment, the conductivity type of the second semiconductor layer 102 is N-type. In some embodiments, the first semiconductor layer 100 has the same conductivity type as the second semiconductor layer 102, for example, both are P-type or N-type. In one embodiment, the resistivity of the second semiconductor layer 102 is 7 10 9 Ω·cm or more and 10 8 Ω·cm or less, for example, 10

[0014] Ω·cm or more. In some embodiments, both the first semiconductor layer 100 and the second semiconductor layer 102 contain a first impurity, a second impurity, and a third impurity. In some embodiments, the concentration of the third impurity in the second semiconductor layer 102 is higher than the concentration of the third impurity in the first semiconductor layer 100. In some embodiments, the concentration of the second impurity in the second semiconductor layer 102 is higher than the concentration of the second impurity in the first semiconductor layer 100. In some embodiments, the concentration of the first impurity in the second semiconductor layer 102 is lower than the concentration of the first impurity in the first semiconductor layer 100. The above-mentioned first impurity is, for example, carbon (C), the second impurity is, for example, hydrogen (H), and the third impurity is, for example, silicon (Si). By containing such specific impurities, the first semiconductor layer 100 and the second semiconductor layer 102 can obtain appropriate conductivity and epitaxial growth quality.

[0015] Further, the first semiconductor layer 100 has a first lattice constant L1, and the second semiconductor layer 102 has a second lattice constant L2. In this embodiment, the first lattice constant L1 is larger than the second lattice constant L2, and the difference ΔL% between the first lattice constant L1 and the second lattice constant L2 is 2% or more, preferably 2.5% or more or 3% or more, and 10% or less, preferably 5% or less. Specifically, the difference between the first lattice constant L1 and the second lattice constant L2 can be calculated from the formula ΔL% = (L1 - L2) / L2 * 100%. The above-mentioned lattice constant is obtained from the X-ray diffraction spectrum of the semiconductor material measured at a temperature of 300 K. Here, as shown in Table 1 below, the lattice constants of only several types of semiconductor compounds are taken as examples.

[0016]

Table 1

[0017] FIG. 2A is a structural diagram of a part of the semiconductor element 20 in an embodiment of the present invention. In this embodiment, the semiconductor element 20 includes a first semiconductor layer 100, a third semiconductor layer 204, and a light-emitting structure 206. Regarding the composition of the first semiconductor layer 100 and the like, since the description of the first semiconductor layer 100 described above can be referred to, the detailed description thereof is omitted here. Further, the third semiconductor layer 204 and the light-emitting structure 206 can be sequentially formed on the first semiconductor layer 100 by LPE (Liquid Phase Epitaxy), MBE (Molecular Beam Epitaxy), CBE (Chemical Beam Epitaxy), MOCVD (Metal Organic Chemical Vapor Deposition), or HVPE (hydride vapor phase epitaxial). In some embodiments, the first semiconductor layer 100, the third semiconductor layer 204, and the light-emitting structure 206 are sequentially formed on the second semiconductor layer 102 described in the previous embodiment, and then the second semiconductor layer 102 is removed to form the structure shown in FIG. 2A.

[0018] As shown in FIG. 2A, the third semiconductor layer 204 is located in and adjacent to the first semiconductor layer 100. In this embodiment, there is no other structure (such as a buffer layer, etc.) between the first semiconductor layer 100 and the third semiconductor layer 204. The third semiconductor layer 204 may include a third III-V semiconductor material. The third III-V semiconductor material is, for example, a binary III-V semiconductor material. The third III-V semiconductor material is a material composed of elements of Group III and Group V in the periodic table of chemical elements. The Group III element may be Ga or In. The Group V element may be As or P, and preferably does not contain N. In some embodiments, the third III-V semiconductor material is the same as the aforementioned first III-V semiconductor material. Specifically, in some embodiments, the third semiconductor layer 204 consists essentially of only the third III-V semiconductor material, for example, consists essentially of only a binary III-V semiconductor material. In one embodiment, the third semiconductor layer 204 includes InP and preferably consists essentially of only InP. Also, the third semiconductor layer 204 may include a plurality of impurities. In some embodiments, the plurality of impurities in the third semiconductor layer 204 may each independently have an impurity concentration of about 5×10 16 cm -3 ~ about 5×10 18 cm -3 , for example, about 5×10 17 cm -3 ~ about 2×10 18 cm -3 or an impurity concentration of about 5×10 16 cm -3 ~ about 5×10 17 cm -3has an impurity concentration. In some embodiments, both the first semiconductor layer 100 and the third semiconductor layer 204 contain a first impurity, a second impurity, and a third impurity. The first impurity is, for example, carbon (C), the second impurity is, for example, hydrogen (H), and the third impurity is, for example, silicon (Si). In some embodiments, forming the third semiconductor layer 204 on the first semiconductor layer 100 can help further stabilize the epitaxial growth quality. In some embodiments, the third semiconductor layer 204 can improve the light emission efficiency of the semiconductor device 20 as a window layer, and the third semiconductor layer 204 is transparent to the light emitted by the light emitting structure 206. Also, in one embodiment, the conductivity type of the third semiconductor layer 204 is N-type.

[0019] The light-emitting structure 206 includes an active structure 210, a fourth semiconductor layer 208, and a fifth semiconductor layer 212. The active structure 210 may include a SH (single heterostructure), DH (double heterostructure), DDH (double-side double heterostructure), or MQW (multiple quantum wells) structure. When the semiconductor device 20 is operating, the active structure 210 can emit radiation light. This radiation light is preferably infrared light, for example, near-infrared light (Near Infrared, NIR). Specifically, when the radiation light is near-infrared light, it has a peak wavelength between 800 nm and 1700 nm, such as 810 nm, 840 nm, 910 nm, 940 nm, 1050 nm, 1070 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1450 nm, 1550 nm, 1600 nm, 1650 nm, 1700 nm, etc. The active structure 110 may include a fourth III-V semiconductor material, preferably consisting essentially of only the fourth III-V semiconductor material. The fourth III-V semiconductor material is a material composed of Group III and Group V elements in the periodic table of chemical elements. The Group III element may be Ga or In. The Group V element may be As or P, preferably not containing N. The fourth III-V semiconductor material may consist of a quaternary III-V semiconductor material. In some embodiments, the active structure 110 consists essentially of only the fourth III-V semiconductor material. For example, the active structure 110 includes a quaternary III-V semiconductor material (e.g., InGaAsP or AlGaInAs), preferably consisting essentially of only the quaternary III-V semiconductor material (e.g., InGaAsP or AlGaInAs).

[0020] The fourth semiconductor layer 208 and the fifth semiconductor layer 212 are respectively located on both sides of the active structure 210, and the fourth semiconductor layer 208 and the fifth semiconductor layer 212 have opposite conductivity types. For example, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 are an n-type semiconductor and a p-type semiconductor respectively, and may provide electrons and holes respectively. Alternatively, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 are a p-type semiconductor and an n-type semiconductor respectively, and may provide holes and electrons respectively. The fourth semiconductor layer 208 may have the same conductivity type as the third semiconductor layer 204. For example, both are n-type semiconductor layers. Also, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 respectively include a fifth III-V semiconductor material and a sixth III-V semiconductor material. The fifth III-V semiconductor material and the sixth III-V semiconductor material may each consist of a binary, ternary, or quaternary III-V semiconductor material. The III-V semiconductor material is a material composed of elements of Group III and Group V in the periodic table of chemical elements. The Group III element may be Ga or In. The Group V element may be As or P, and preferably does not contain N. In one embodiment, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 each include a quaternary III-V semiconductor material (e.g., InGaAsP, AlGaInP, or AlGaInAs), and preferably consist essentially of only a quaternary semiconductor material (e.g., InGaAsP, AlGaInP, or AlGaInAs).

[0021] The fourth semiconductor layer 208 and the fifth semiconductor layer 212 have different conductivity types by adding different impurities. Specifically, the impurities include, but are not limited to, Mg, Zn, Si, Te, etc. In some embodiments, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be doped by performing in-situ doping during the epitaxial growth period and / or by performing an implanting process using a P-type or N-type dopant after epitaxial growth. In one embodiment, the impurities in the fourth semiconductor layer 208 and the fifth semiconductor layer 212 are each independently about 2×10 17 cm-3 ~ about 1×10 20 cm -3 may have an impurity concentration of, for example, about 5×10 17 cm -3 ~ about 5×10 19 cm -3 and have an impurity concentration of.

[0022] In some embodiments, an etch stop layer may be further provided between the first semiconductor layer 100 and the light-emitting structure 206. As shown in FIG. 2A, for example, the etch stop layer (not shown) may be located between the first semiconductor layer 100 and the third semiconductor layer 204. Next, by removing the first semiconductor layer 100 according to the needs of the device structure, a semiconductor device 20' as shown in FIG. 2B can be formed. By providing the etch stop layer, it is possible to avoid destroying the third semiconductor layer 204 and the light-emitting structure 206 when removing the first semiconductor layer 100. Subsequently, the semiconductor device 20' may include a connection layer (not shown), and is connected to the support substrate by the connection layer, and subsequent processes can be performed. In one embodiment, the semiconductor device 20' includes only the structure as shown in FIG. 2B, that is, it does not have a support substrate. In some embodiments, the etch stop layer includes a seventh III-V semiconductor material. The seventh III-V semiconductor material may be a ternary or quaternary III-V semiconductor material. The III-V semiconductor material is a material composed of elements of Group III and Group V in the periodic table of chemical elements. The Group III element may be Al, Ga, or In. The Group V element may be As or P, and preferably does not contain N. The etch stop layer preferably includes a Group V element different from the Group V element in the composition of the first semiconductor layer 100. In one embodiment, the etch stop layer includes a ternary III-V semiconductor material (for example, InGaAs). In one embodiment, the etch stop layer consists essentially of only a ternary semiconductor material (for example, InGaAs).

[0023] As described above, since the first semiconductor layer 100 has a surface with a relatively low density of defects, it is even more suitable for use as a base layer for growing a semiconductor epitaxial layer. Specifically, when the third semiconductor layer 204 and other semiconductor layers are further formed on the first semiconductor layer 100, each semiconductor layer still has good epitaxial growth quality.

[0024] FIG. 3 is a structural diagram of a semiconductor device according to an embodiment of the present invention. In this embodiment, the semiconductor device 30 includes a first semiconductor layer 300, a third semiconductor layer 304, a light-emitting structure 306, a window layer 314, a first electrode 318, and a second electrode 320. Regarding the compositions of the first semiconductor layer 300, the third semiconductor layer 304, and the light-emitting structure 306, reference can be made to the descriptions of the first semiconductor layer 100, the third semiconductor layer 204, and the light-emitting structure 206 described above, and detailed descriptions thereof are omitted here. Specifically, regarding the compositions of the fourth semiconductor layer 308, the active structure 310, and the fifth semiconductor layer 312 in the light-emitting structure 306, reference can be made to the descriptions of the fourth semiconductor layer 208, the active structure 210, and the fifth semiconductor layer 212 described above.

[0025] In this embodiment, the window layer 314 is located in the light-emitting structure 306 and is adjacent to the fifth semiconductor layer 312 in the light-emitting structure 306. Also, the conductivity type of the window layer 314 is opposite to that of the third semiconductor layer 304. For example, when the window layer 314 is a P-type semiconductor layer, the third semiconductor layer 304 is an N-type semiconductor layer. The window layer 314 may be used as a light extraction layer, whereby the light-emitting efficiency of the semiconductor device 30 can be further improved. Also, the window layer 314 is transparent to the light emitted by the light-emitting structure 306.

[0026] The first electrode 318 and the second electrode 320 are used for electrical connection to an external power source, and the first electrode 318 and the second electrode 320 are electrically connected to the light-emitting structure 306. In this embodiment, the first electrode 320 is adjacent to the window layer 314, and the second electrode 318 is adjacent to the first semiconductor layer 300. However, in practice, it is not limited thereto. Also, the materials of the first electrode 318 and the second electrode 320 may be the same or different, and may include, for example, a transparent conductive material, a metal, or an alloy. The transparent conductive material may include a metal oxide, such as ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, or IZO. Examples of the metal include Au, Pt, Ti, Al, Cu, or Ni. Examples of the alloy include GeAuNi, BeAu, GeAu, ZnAu, etc.

[0027] FIG. 4 is a structural diagram of a semiconductor device according to an embodiment of the present invention. In this embodiment, the semiconductor device 40 includes a first semiconductor layer 400, a second semiconductor layer 402, a third semiconductor layer 404, a light-emitting structure 406, a window layer 414, a contact layer 416, a first electrode 420, and a second electrode 418. The main difference between the semiconductor device 40 and the aforementioned semiconductor device 30 is that it further includes a second semiconductor layer 402 and a contact layer 416. Regarding the composition of the first semiconductor layer 400, the second semiconductor layer 402, the third semiconductor layer 404, the light-emitting structure 406, the window layer 414, the first electrode 420, and the second electrode 418, reference may be made to the description of the aforementioned embodiment, and the detailed description thereof is omitted here. Specifically, regarding the composition of the fourth semiconductor layer 408, the active structure 410, and the fifth semiconductor layer 412 in the light-emitting structure 406, reference may be made to the descriptions of the aforementioned fourth semiconductor layer 208, active structure 210, and fifth semiconductor layer 212, respectively.

[0028] The contact layer 416 is located between the first electrode 420 and the window layer 414 and is used to conduct current. The contact layer 416 may have the same conductivity type as the window layer 314. For example, it is a P-type semiconductor layer. In this embodiment, the contact layer 416 is adjacent to the first electrode 420. Specifically, the contact layer 416 is, for example, a doped or undoped semiconductor material layer and may include a group VIII III-V semiconductor material. The group VIII III-V semiconductor material may be a binary or ternary III-V semiconductor material, such as GaAs or InGaAs. When the first electrode 420 includes a metal or an alloy, an ohmic contact is formed between the first electrode 420 and the contact layer 416, so that a good electrical contact can be formed between the first electrode 420 and the light-emitting structure 406.

[0029] FIGS. 5A to 5B are cross-sectional views showing a method for manufacturing a semiconductor stack layer according to an embodiment of the present invention. FIG. 5C is a flowchart for manufacturing a semiconductor stack layer according to an embodiment. Such a semiconductor stack layer can be, for example, part of the structure of a semiconductor device. As shown in FIGS. 5A and 5B, first, a second semiconductor layer 502 is provided, and a first semiconductor layer 500 is formed on the second semiconductor layer 502. For the descriptions of the first semiconductor layer 500 and the second semiconductor layer 502, reference can be made to the descriptions of the first semiconductor layer 100 and the second semiconductor layer 102 in the foregoing embodiments, and the detailed descriptions are omitted here.

[0030] Referring to FIGS. 5A to 5C, step S510 is performed to grow a part of the first semiconductor layer 500 at a first temperature. The growth of the first semiconductor layer 500 can be achieved, for example, by LPE (Liquid Phase Epitaxy), MBE (Molecular Beam Epitaxy), CBE (Chemical Beam Epitaxy), MOCVD (Metal Organic Chemical Vapor Deposition), or HVPE (hydride vapor phase epitaxial). The first temperature is, for example, 650°C or less and 400°C or more, preferably 520°C or less, and more preferably in the range of 450°C to 510°C or 420°C to 500°C. By growing the first semiconductor layer 500 within such a temperature range, better epitaxial growth quality can be obtained.

[0031] Subsequently, step S520 is performed to provide a second temperature higher than the first temperature. The second temperature is, for example, 700°C or more and 850°C or less, preferably greater than 750°C, and more preferably in the range of 760°C to 810°C or 780°C to 800°C. In step S520, for example, the epitaxial growth environment temperature is adjusted from the first temperature to the second temperature. In some embodiments, the difference between the first temperature and the second temperature is 300°C or more, thereby achieving a better epitaxial growth effect. Also, the growth of the first semiconductor layer 500 may not be performed at the second temperature. In this step, the environmental temperature is adjusted to a relatively high second temperature to perform high-temperature tempering. By not growing the first semiconductor layer 500 at the second temperature, the stress in a part of the first semiconductor layer 500 grown at the previous first temperature can be adjusted, so that crystal defects can be reduced.

[0032] Thereafter, proceed to step S530 to check whether the thickness of the first semiconductor layer 500 has reached a predetermined thickness. When the first semiconductor layer 500 has reached the predetermined thickness, it means that the manufacturing of the first semiconductor layer 500 and the second semiconductor layer 502 is completed. In some embodiments, the predetermined thickness is 20 μm or less, preferably 10 μm or less, more preferably 5 μm or less, and may also be 1 μm or more. When the first semiconductor layer 500 has not reached the predetermined thickness, proceed to step S540 and repeat steps S510 and S520. For example, repeat steps S510 and S520 at least two or more times. In some embodiments, steps S510 and S520 may be repeated 10 times or more, whereby a semiconductor stack layer with an appropriate thickness and relatively stable epitaxial growth quality can be obtained. Also, the number of times of repeatedly executing steps S510 and S520 may be 30 times or less.

[0033] As described above, in the method of heating and cooling in the manufacturing process of the foregoing first semiconductor layer 500, it is not necessary to solve the problem of stress caused by lattice mismatch between the first semiconductor layer 500 and the second semiconductor layer 502 by other buffer structures or processes, and a structure with good epitaxial growth quality can be obtained.

[0034] In some embodiments, the stack layer of the first semiconductor layer 500 and the second semiconductor layer 502 may be used as a base layer, and subsequent epitaxial growth may be performed according to needs. For example, a light-emitting structure or the like can be directly formed on the stack layer of the first semiconductor layer 500 and the second semiconductor layer 502.

[0035] As shown in FIG. 5D, a third semiconductor layer 504 can be further formed on the first semiconductor layer 500 and the second semiconductor layer 502. For the description of the third semiconductor layer 504, reference can be made to the description of the third semiconductor layer 204 in the foregoing embodiments, and the detailed description thereof is omitted here. As described above, the light-emitting structure can be formed on the third semiconductor layer 504. One side of the first semiconductor layer 500 is adjacent to the second semiconductor layer 502, and the other side is adjacent to the third semiconductor layer 504. The surface 500a of the first semiconductor layer 500 is in direct contact with the surface 502a of the second semiconductor layer 502, and the other surface 500b is in direct contact with the surface 504a of the third semiconductor layer 504.

[0036] FIG. 5E is a diagram showing the relationship between the concentration of elements and the depth in a partial range of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 5E is the result of performing SIMS analysis on a partial region of a semiconductor device including the structure shown in FIG. 5D. As shown in FIG. 5E, according to the thickness and order of each layer in the semiconductor device, it can be roughly divided into a first region Z1, a second region Z2, and a third region Z3. Specifically, the first region Z1 corresponds to the second semiconductor layer 502, the second region Z2 corresponds to the first semiconductor layer 500, and the third region Z3 corresponds to the third semiconductor layer 504. Also, in this embodiment, both the first semiconductor layer 500 and the third semiconductor layer 504 contain a plurality of impurities, and the first semiconductor layer 500 and the third semiconductor layer 504 are substantially composed of only InP. The second semiconductor layer 502 contains a plurality of impurities, and the second semiconductor layer 502 is substantially composed of only GaAs. These impurities include at least a first impurity, a second impurity, and a third impurity. The first impurity is carbon (C) and is represented by C1, the second impurity is hydrogen (H) and is represented by C2, and the third impurity is silicon (Si) and is represented by C3. The concentrations of C1, C2, and C3 of the first, second, and third impurities are shown on the left vertical axis of FIG. 5E. In this embodiment, the first impurity and the second impurity are unintentionally added, and the third impurity is intentionally added.

[0037] By growing the first semiconductor layer 500 with a single-layer structure in the above-described manner, the first impurity and the second impurity that are unintentionally added have an impurity concentration greater than 10 16 cm -3 in the first semiconductor layer 500, and the concentration curve of carbon (C) can have a pattern like a periodic change. As shown in FIG. 5E, in the second region Z2, the concentration of the second impurity is higher than the concentration of the first impurity, that is, the hydrogen (H) concentration in the first semiconductor layer 500 is higher than the carbon (C) concentration. Also, the concentration of the third impurity in the second region Z2 is lower than the concentration of the third impurity in the first region Z1 and lower than the concentration of the third impurity in the third region Z3. That is, the silicon (Si) concentration in the first semiconductor layer 500 is lower than the silicon (Si) concentration in the second semiconductor layer 502 or the third semiconductor layer 504. Also, in the second region Z2, the concentration of the second impurity is higher than the concentration of the third impurity, that is, the hydrogen (H) concentration in the first semiconductor layer 500 is higher than the silicon (Si) concentration.

[0038] FIG. 5F is a partial enlarged view of the concentration curve of the first impurity (carbon (C)) within the dotted-line frame region in the second region Z2 of FIG. 5E. As shown in FIG. 5F, in this embodiment, the distribution of the concentration of the first impurity (carbon (C)) includes at least i local maximum values (concentrations C shown in the figure L1 , C L2 , …, C Li ) and i local minimum values (concentrations C shown in the figure M1 , C M2 , …, C Mi ), where i is a positive integer of 5 or more, and in the local region as shown in FIG. 5F, i = 8. The local maximum values and the local minimum values appear alternately, and any one of the local maximum values is larger than any one of the local minimum values. As shown in FIG. 5E, at several depth positions in the second region Z2, the concentration of the third impurity is smaller than the local maximum value, and at several depth positions in the second region Z2, the concentration of the third impurity is larger than the local minimum value. That is, in the second region Z2, the concentration of the third impurity is smaller than several local maximum values and larger than several local minimum values.

[0039] As shown in FIG. 5E, in this embodiment, the impurity concentration of silicon (Si) in the first semiconductor layer 500 is 1×10 17 cm -3 or less, and is in the range of about 5×10 16 cm -3 to about 9×10 16 cm -3 ; the carbon (C) concentration is in the range of about 4×10 16 cm -3 to about 9×10 16 cm -3 ; the hydrogen (H) concentration is in the range of about 1×10 17 cm -3 to about 5×10 17 cm -3 . Also, in some embodiments, the first region Z1, the second region Z2, and the third region Z3 further contain inevitable impurities such as oxygen (O), etc., but are not shown here for the sake of convenience. In one embodiment, the distribution of the oxygen (O) concentration in the first region Z1, the second region Z2, and the third region Z3 is 3×10 15 cm -3 to 2×10 16 cm -3 , which is close to the detection limit by SIMS analysis.

[0040] FIG. 6 is a package structure diagram of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 6, the package structure 600 includes a semiconductor device 60, a package substrate 61, a mounting body 63, connection lines (or bonding wires) 65, a contact structure 66, and a package material 68. The package substrate 61 may include a ceramic or glass material. The package substrate 61 has a plurality of through holes 62. By filling the through holes 62 with a conductive material, such as a metal, etc., conduction and / or heat dissipation can be assisted. The mounting body 63 is located on one surface of the package substrate 61 and includes a conductive material, such as a metal. The contact structure 66 is located on the other surface of the package substrate 61. In this embodiment, the contact structure 66 includes a contact pad 66a and a contact pad 66b, and the contact pad 66a and the contact pad 66b can be electrically connected to the mounting body 63 through the through holes 62. In one embodiment, the contact structure 66 may further include a heat dissipation pad (not shown), and the heat dissipation pad is located, for example, between the contact pad 66a and the contact pad 66b. The semiconductor device 60 is located on the mounting body 63 and may be a semiconductor device described in any one of the embodiments of the present invention. In this embodiment, the mounting body 63 includes a first portion 63a and a second portion 63b, and the semiconductor device 60 can be electrically connected to the second portion 63b of the mounting body 63 through the connection line 65. The material of the connection line 65 may include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least any one of these elements. The package material 68 covers the semiconductor device 60 and has the effect of protecting the semiconductor device 60. Specifically, the package material 68 may include a resin material, such as an epoxy resin, a silicone resin, etc. The package material 68 may further include a plurality of wavelength conversion particles (not shown) for converting the first light emitted by the semiconductor device 60 into second light. The wavelength of the second light is greater than the wavelength of the first light.

[0041] The semiconductor device according to the present invention can be applied to products in the fields of lighting, medical, display, communication, detection, power supply systems, etc., such as lighting fixtures, monitors, mobile phones, tablet computers, in-vehicle instrument panels, televisions, detectors, computers, wearable devices (e.g., wristwatches, bracelets, necklaces, etc.), traffic signal lights, outdoor displays, medical devices, etc.

[0042] From the above, according to some embodiments of the present invention, a semiconductor structure can be provided, which has good epitaxial growth quality on the surface, can be used, for example, as a substrate of a semiconductor device, and is advantageous for further reducing the production cost of the semiconductor device. Also, according to some embodiments of the present invention, a semiconductor device and a manufacturing method thereof can be provided, which can achieve excellent technical effects in terms of adjusting stress due to lattice mismatch during heteroepitaxial growth, so that the occurrence of defects at the interface of the epitaxial layer can be avoided.

[0043] As described above, the preferred embodiments of the present invention have been described. However, the present invention is not limited to this embodiment, and any changes to the present invention belong to the technical scope of the present invention as long as they do not depart from the spirit of the present invention.

Description of Reference Numerals

[0044] 10: Semiconductor stack layer 20, 20’, 30, 40, 60: Semiconductor device 61: Package substrate 62: Through hole 63: Mounting body 63a: First part 63b: Second part 65: Connection line 66: Contact structure 66a, 66b: Contact pad 68: Package material 100, 300, 400, 500: First semiconductor layer 102, 402, 502: Second semiconductor layer 204, 304, 404, 504: Third semiconductor layer 206, 306, 406: Light-emitting structure 208, 308, 408: Fourth semiconductor layer 210, 310, 410: Active structure 212, 312, 412: Fifth semiconductor layer 414: Window layer 416: Contact layer 600: Package structure 318, 418: First electrode 320, 420: Second electrode S510, S520, S530, S540: Steps C1: First concentration C2: Second concentration C3: Second concentration C L1 , C L2 , C Li , C M1 , C M2 , C Mi : Concentration

Claims

1. A semiconductor device comprising: a first semiconductor layer including a first III-V semiconductor material; a light-emitting structure located on the first semiconductor layer and including an active structure; a second semiconductor layer located under the first semiconductor layer and including a second III-V semiconductor material; and a third semiconductor layer located between the first semiconductor layer and the light-emitting structure and including a third III-V semiconductor material, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer contain a first impurity, the first semiconductor layer does not contain nitrogen, in the first semiconductor layer, the concentration distribution of the first impurity includes at least a plurality of local maxima and a plurality of local minima, the plurality of local maxima and the plurality of local minima appear alternately, and any one of the plurality of local maxima is larger than any one of the plurality of local minima, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the conductivity type of the first semiconductor layer is n-type, a semiconductor device.

3. The semiconductor device according to claim 1, wherein each constituent element of the second III-V semiconductor material is different from each constituent element of the first III-V semiconductor material, a semiconductor device.

4. The semiconductor device according to claim 1, wherein the concentration of the first impurity in the first semiconductor layer is higher than the concentration of the first impurity in the third semiconductor layer, a semiconductor device.

5. The semiconductor device according to claim 1, wherein the thickness of the first semiconductor layer is 1 μm or more and 5 μm or less, a semiconductor device.

6. The semiconductor device according to claim 1, wherein the active structure includes a fourth III-V semiconductor material, and the fourth III-V semiconductor material is a quaternary III-V semiconductor material, a semiconductor device.

7. The semiconductor device according to claim 1, wherein the third III-V semiconductor material is the same as the first III-V semiconductor material, a semiconductor device.

8. The semiconductor device according to claim 1, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer further contain a second impurity, a semiconductor device.

9. The semiconductor device according to claim 8, The first impurity and the second impurity have an impurity concentration greater than 10 16 cm -3 in the first semiconductor layer, semiconductor device.

10. A package structure of a semiconductor device, comprising: a carrier; a semiconductor device located on the carrier; and a package material covering the semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 9, a package structure.

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