Semiconductor device

Abstract

To provide a semiconductor device with less variation in transistor characteristic.SOLUTION: A semiconductor device includes a first insulator, a first oxide on the first insulator, a first conductor and a second conductor on the first oxide, a first layer and a second layer in contact with a side surface of the first oxide, a second insulator on the first insulator, on the first layer, on the second layer, on the first conductor, and on the second conductor, a third insulator on the second insulator, a second oxide disposed between the first conductor and the second conductor and disposed on the first oxide, a fourth insulator on the second oxide, and a third conductor on the fourth insulator. Each of the first layer and the second layer contains metal contained in the first conductor and the second conductor. The first insulator in a region in contact with the second insulator includes a region whose metal concentration is lower than that of the first layer or the second layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device. Another aspect of the present invention relates to a semiconductor wafer and a module.

[0002] Note that in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices may be said to have semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

Background Art

[0004] Techniques for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface have attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0005] In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystals nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 2).

[0006] In Non-Patent Document 1 and Non-Patent Document 2, techniques for fabricating transistors using oxide semiconductors having a CAAC structure are disclosed.

Prior Art Documents

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a semiconductor device with little variation in transistor characteristics as one of the problems. Another aspect of the present invention is to provide a semiconductor device with good reliability as one of the problems. Another aspect of the present invention is to provide a semiconductor device having good electrical characteristics as one of the problems. Another aspect of the present invention is to provide a semiconductor device with a large on-current as one of the problems. Another aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration as one of the problems. Another aspect of the present invention is to provide a low-power consumption semiconductor device as one of the problems.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention includes a first insulator, a first oxide on the first insulator, a first conductor and a second conductor on the first oxide, a first layer and a second layer in contact with the side surface of the first oxide, a second insulator on the first insulator, on the first layer, on the second layer, on the first conductor, and on the second conductor, a third insulator on the second insulator, a second oxide disposed between the first conductor and the second conductor and on the first oxide, a fourth insulator on the second oxide, and a third conductor on the fourth insulator. Each of the first layer and the second layer contains a metal included in the first conductor and the second conductor. The first insulator in the region in contact with the second insulator has a region with a lower metal concentration than the first layer or the second layer. It is a semiconductor device.

[0011] In the semiconductor device, it is preferable that each of the thicknesses of the first layer and the second layer has a region of 0.5 nm or more and 1.5 nm or less.

[0012] Also, in the semiconductor device, it is preferable that the metal is tantalum.

[0013] Also, in the semiconductor device, it is preferable that the first oxide has indium, an element M (M is gallium, aluminum, yttrium, or tin), and zinc.

[0014] Another aspect of the present invention is to form a first insulator, form a first oxide film on the first insulator, form a first conductive film on the first oxide film, form a resist mask on the first conductive film, cure the resist mask, and process the first oxide film and the first conductive film using the resist mask to form island-shaped first oxide and conductive layers. The layer formed on the first insulator by the processing is removed by performing a dry etching process. A second insulator is formed on the first insulator, on the first oxide, and on the conductive layer. A third insulator is formed on the second insulator. An opening is formed in the third insulator, the second insulator, and the conductive layer so that the first oxide is exposed to form a first conductor and a second conductor. A second oxide film is formed on the first insulator, on the first oxide, and on the third insulator. An insulating film is formed on the second oxide film. A second conductive film is formed on the insulating film. A part of the second oxide film, a part of the insulating film, and a part of the second conductive film are removed until the third insulator is exposed. This is a method for manufacturing a semiconductor device.

[0015] In the method for manufacturing the semiconductor device described above, the step of curing the resist mask, the step of forming island-shaped first oxide and conductive layers by processing the first oxide film and the first conductive film using the resist mask, and the step of removing the layer formed on the first insulator by the processing by performing a dry etching process are preferably performed continuously using a single dry etching apparatus.

[0016] Another aspect of the present invention has a first layer having a first memory device, a second layer having a second memory device, and a first insulator. The second layer is provided above the first layer. The first memory device has a first transistor and a first capacitor device. The second memory device has a second transistor and a second capacitor device. The first transistor has a second insulator, a first oxide on the second insulator, a first conductor and a second conductor on the first oxide, a third insulator on the first insulator, on the first conductor, and on the second conductor, a fourth insulator on the third insulator, a second oxide disposed between the first conductor and the second conductor and on the first oxide, a fifth insulator on the second oxide, and a third conductor on the fifth insulator. The second transistor has a sixth insulator, a third oxide on the sixth insulator, a fourth conductor and a fifth conductor on the third oxide, a seventh insulator on the sixth insulator, on the fourth conductor, and on the fifth conductor, an eighth insulator on the seventh insulator, a fourth oxide disposed between the fourth conductor and the fifth conductor and on the third oxide, a ninth insulator on the fourth oxide, and a sixth conductor on the ninth insulator. The first insulator has a region in contact with each of the side surfaces of the second insulator, the third insulator, the fourth insulator, the sixth insulator, the seventh insulator, and the eighth insulator. Each of the first oxide and the third oxide has a region where the hydrogen concentration is less than 1×10 20 atoms / cm 3 . It is a semiconductor device having such a region.

Advantages of the Invention

[0017] According to one aspect of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Further, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Further, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Further, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Further, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Further, according to one aspect of the present invention, a low-power consumption semiconductor device can be provided.

[0018] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0019]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different modes, and the forms and details can be variously changed without departing from the spirit and scope thereof. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0021] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Thus, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may unintentionally become thinner due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. Also, in the drawings, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and repeated explanations may be omitted. Also, when referring to similar functions, the hatching patterns may be the same and may not be particularly labeled with reference numerals.

[0022] Also, particularly in top views (also referred to as "plan views") and perspective views, etc., for ease of understanding the invention, the description of some components may be omitted. Also, the description of some hidden lines, etc. may be omitted.

[0023] Also, in this specification, etc., ordinal numbers such as first, second, etc. are used for convenience and do not indicate the process order or stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third", etc. and described. Also, the ordinal numbers described in this specification, etc. may not match the ordinal numbers used to specify an aspect of the present invention.

[0024] Also, in this specification, etc., terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0025] For example, in this specification and the like, when it is explicitly described that X and Y are connected, it shall be considered that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected, as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in a figure or text, and those other than the connection relationship shown in the figure or text shall also be considered as disclosed in the figure or text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0026] Also, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And it has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0027] Also, the functions of the source and the drain may be interchanged when transistors with different polarities are adopted or when the direction of current changes in a circuit operation. Therefore, in this specification and the like, the terms source and drain may be used interchangeably in some cases.

[0028] Note that the channel length refers to, for example, in the top view of a transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be a single value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0029] Note that the channel width refers to, for example, in the top view of a transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the length of the channel formation region in the vertical direction with respect to the channel length direction in the channel formation region. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0030] Note that in this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may be different from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may become non-negligible. For example, in a fine transistor in which the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

[0031] In such cases, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0032] In this specification, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

[0033] Note that the impurities in the semiconductor refer to, for example, components other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components of the oxide semiconductor, etc., such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Note that water may also function as an impurity. Also, for example, due to the mixing of impurities, oxygen vacancies (denoted as V O may be formed in the oxide semiconductor.)

[0034] Note that in this specification and the like, silicon oxynitride refers to a substance having a higher oxygen content than nitrogen in its composition. Also, silicon nitride oxide refers to a substance having a higher nitrogen content than oxygen in its composition.

[0035] In addition, in this specification and the like, the term "insulator" can be rephrased as an insulating film or an insulating layer. Also, the term "conductor" can be rephrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be rephrased as a semiconductor film or a semiconductor layer.

[0036] In this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0038] In this specification and the like, normally-off means that when no potential is applied to the gate or the gate is given a ground potential, the drain current per 1 μm of channel width flowing through the transistor is -20 1×10 -18 A or less at room temperature, 1×10 -16 A or less at 85 °C, or 1×10

[0039] (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1 to 22.

[0040] <Configuration Example of Semiconductor Device> The configuration of a semiconductor device having a transistor 200 will be described with reference to FIGS. 1A to 1D. FIGS. 1A to 1D are a top view and cross-sectional views of a semiconductor device having a transistor 200. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 1A and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 1C is a cross-sectional view of the portion indicated by the dashed line A3 - A4 in FIG. 1A and is also a cross-sectional view in the channel width direction of the transistor 200. FIG. 1D is a cross-sectional view of the portion indicated by the dashed line A5 - A6 in FIG. 1A. In the top view of FIG. 1A, some elements are omitted for clarity of the drawing.

[0041] A semiconductor device according to one aspect of the present invention includes an insulator 211 on a substrate (not shown), an insulator 212 on the insulator 211, an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, and an insulator 284 on the insulator 283. The insulator 211, the insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 function as interlayer films. Further, it has conductors 240a and 240b that are electrically connected to the transistor 200 and function as plugs. An insulator 241a is provided in contact with the side surface of the conductor 240a that functions as a plug, and an insulator 241b is provided in contact with the side surface of the conductor 240b that functions as a plug. Further, on the insulator 284, on the conductor 240a, and on the conductor 240b, a conductor 246a that is electrically connected to the conductor 240a and functions as a wiring is provided, and a conductor 246b that is electrically connected to the conductor 240b and functions as a wiring is provided. Further, an insulator 286 is provided on the conductor 246a, on the conductor 246b, and on the insulator 284.

[0042] An insulator 241a is provided in contact with the inner wall of the opening such as an insulator 280, an insulator 282, an insulator 283, and an insulator 284. A first conductor of a conductor 240a is provided in contact with the side surface of the insulator 241a, and a second conductor of the conductor 240a is further provided inside. Also, an insulator 241b is provided in contact with the inner wall of the opening such as an insulator 280, an insulator 282, an insulator 283, and an insulator 284. A first conductor of a conductor 240b is provided in contact with the side surface of the insulator 241b, and a second conductor of the conductor 240b is further provided inside. Here, the height of the upper surface of the conductor 240a can be made approximately the same as the height of the upper surface of the insulator 284 in the region overlapping with the conductor 246a. Also, the height of the upper surface of the conductor 240b can be made approximately the same as the height of the upper surface of the insulator 284 in the region overlapping with the conductor 246b. Note that in the transistor 200, a configuration in which the first conductor and the second conductor of the conductor 240a are stacked and the first conductor and the second conductor of the conductor 240b are stacked is shown, but the present invention is not limited to this. For example, each of the conductor 240a and the conductor 240b may be provided with a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be assigned in the formation order for distinction.

[0043] [Transistor 200] As shown in FIGS. 1A to 1D, the transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and on the conductors 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, oxides 243a, 243b, and 230c on the oxide 230b, a conductor 242a on the oxide 243a, a conductor 242b on the oxide 243b, an oxide 230d on the oxide 230c, an insulator 250 on the oxide 230d, conductors 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping a part of the oxide 230c, a layer 244a in contact with the side surfaces of the oxide 230a, the oxide 230b, the oxide 243a, and the conductor 242a, a layer 244b in contact with the side surfaces of the oxide 230a, the oxide 230b, the oxide 243b, and the conductor 242b, and an insulator 254 in contact with the upper surface of the insulator 224, the side surfaces of the layer 244a, the side surfaces of the layer 244b, the upper surface of the conductor 242a, and the upper surface of the conductor 242b. Further, the oxide 230c is in contact with the side surfaces of the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b. Also, an insulator 282 is in contact with the upper surfaces of the conductors 260, the insulator 250, the oxide 230d, the oxide 230c, and the insulator 280, respectively.

[0044] The insulator 280 is provided with an opening reaching the oxide 230b. Inside the opening, an oxide 230c, an oxide 230d, an insulator 250, and a conductor 260 are arranged. Also, in the channel length direction of the transistor 200, a conductor 260, an insulator 250, an oxide 230d, and an oxide 230c are provided between the conductor 242a and the oxide 243a, and between the conductor 242b and the oxide 243b. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. Further, the oxide 230c has a region in contact with the oxide 230b, a region overlapping with the side surface of the conductor 260 via the oxide 230d and the insulator 250, and a region overlapping with the bottom surface of the conductor 260 via the oxide 230d and the insulator 250.

[0045] The oxide 230 preferably has an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, an oxide 230c disposed on the oxide 230b and at least partially in contact with the oxide 230b, and an oxide 230d disposed on the oxide 230c.

[0046] Note that in the transistor 200, the oxide 230 is shown having a structure in which four layers of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d are stacked, but the present invention is not limited thereto. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230d, or a stacked structure of five or more layers may be provided, or each of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may have a stacked structure.

[0047] Conductor 260 functions as a first gate (also referred to as a top gate) electrode, and conductor 205 functions as a second gate (also referred to as a back gate) electrode. Also, insulator 250 functions as a first gate insulator, and insulators 224 and 222 function as second gate insulators. Further, conductor 242a functions as one of a source or a drain, and conductor 242b functions as the other of the source or the drain. Also, oxide 230 functions as a channel formation region.

[0048] Here, an enlarged view of the vicinity of the channel formation region in FIG. 1B is shown in FIG. 2. As shown in FIG. 2, oxide 230 has a region 234 that functions as a channel formation region of transistor 200, and regions 236a and 236b that are provided so as to sandwich region 234 and function as a source region or a drain region. Region 234 at least partially overlaps conductor 260. Conductors 242a and 242b are provided on oxide 230b, and lower resistance regions are formed in the vicinity of conductor 242a in region 236a and in the vicinity of conductor 242b in region 236b.

[0049] Regions 236a and 236b that function as a source region or a drain region are regions where the carrier concentration is increased and the resistance is reduced due to, for example, a low oxygen concentration, inclusion of impurities such as hydrogen, nitrogen, and metal elements. That is, regions 236a and 236b are regions with a higher carrier concentration and lower resistance compared to region 234. Also, region 234 that functions as a channel formation region is a region with a lower carrier concentration and higher resistance due to, for example, a higher oxygen concentration and a lower impurity concentration than regions 236a and 236b. Also, a region may be formed between region 234 and region 236a (region 236b) where the oxygen concentration is equal to or higher than the oxygen concentration of region 236a (region 236b) and equal to or lower than the oxygen concentration of region 234.

[0050] Also, in FIG. 2, the width of region 234 in the channel length direction matches the width of conductor 260, but one aspect of the present invention is not limited to this. The width of region 234 may be shorter than the width of conductor 260, or may be longer than the width of conductor 260.

[0051] In addition, in oxide 230, it may be difficult to clearly detect the boundary of each region. The concentration of impurities such as hydrogen, nitrogen, and metal elements detected within each region is not limited to a stepwise change from region to region, and may also change continuously within each region. That is, the concentration of impurities such as hydrogen, nitrogen, and metal elements may decrease in regions closer to the channel formation region.

[0052] For transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for oxide 230 (oxide 230a, oxide 230b, oxide 230c, and oxide 230d) including the channel formation region.

[0053] In addition, as the metal oxide that functions as a semiconductor, it is preferable to use one having a bandgap of 2 eV or more, and more preferably one having a bandgap of 2.5 eV or more. By using a metal oxide with a large bandgap in this way, the off-current of the transistor can be reduced.

[0054] As oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.) may be used. Further, as oxide 230, an In-Ga oxide, an In-Zn oxide, or indium oxide may be used.

[0055] The oxide 230 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. Further, the oxide 230 preferably has a laminated structure of a plurality of oxide layers having a common element (as a main component) other than oxygen.

[0056] Specifically, in the metal oxide used for the oxide 230a or the oxide 230d, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b or the oxide 230c. The larger the atomic ratio of the element M to In, the easier it is to suppress the diffusion of impurities or oxygen. Therefore, by having the oxide 230a under the oxide 230b, the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. Further, by having the oxide 230d on the oxide 230c, the diffusion of impurities from the structure formed above the oxide 230d to the oxide 230c can be suppressed.

[0057] In other words, in the metal oxide used for the oxide 230b or the oxide 230c, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a or the oxide 230d. At this time, the main path of the carriers is at or near the oxide 230b, the oxide 230c, for example, at the interface between the oxide 230b and the oxide 230c. Further, since the oxide 230b and the oxide 230c have a common element (as a main component) other than oxygen, the density of defect levels at the interface between the oxide 230b and the oxide 230c can be lowered, so the influence of interface scattering on carrier conduction is small and a high on-current can be obtained.

[0058] In order to make the oxide 230c the main carrier path, in the oxide 230c, the atomic ratio of indium to the metal element that is the main component is preferably greater than the atomic ratio of indium to the metal element that is the main component in the oxide 230b. By using a metal oxide with a high indium content in the channel formation region, the on-current of the transistor can be increased. Therefore, by adopting such a configuration, the oxide 230c can be made the main carrier path.

[0059] Also, in order to make the oxide 230c the main carrier path, the lower end of the conduction band of the oxide 230c is preferably farther from the vacuum level than the lower ends of the conduction bands of the oxide 230a, the oxide 230b, and the oxide 230d. In other words, the electron affinity of the oxide 230c is preferably greater than the electron affinities of the oxide 230a, the oxide 230b, and the oxide 230d.

[0060] The oxide 230b and the oxide 230c preferably each have crystallinity. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) described later as the oxide 230b and the oxide 230c. Also, the oxide 230d may be configured to have crystallinity.

[0061] By using CAAC-OS for the oxide 230b and the oxide 230c, it is possible to reduce impurities and oxygen deficiencies in the region where the channel is formed in the oxide semiconductor. As a result, fluctuations in electrical characteristics are suppressed, stable electrical characteristics are realized, and a transistor with improved reliability can be provided.

[0062] Also, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0063] In addition, CAAC-OS has the property of facilitating the movement of oxygen in a direction perpendicular to the c-axis of the crystal of the CAAC structure. Therefore, the oxygen in the oxide 230c can be efficiently supplied to the oxide 230b.

[0064] CAAC-OS is a metal oxide with a highly crystalline and dense structure and has few impurities and defects (such as oxygen deficiencies). In particular, after the formation of the metal oxide, by performing heat treatment at a temperature at which the metal oxide does not polycrystallize (for example, 400 °C or higher and 600 °C or lower), CAAC-OS can be made into a structure with higher crystallinity and density. In this way, by increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0065] In a transistor using an oxide semiconductor, if impurities and oxygen deficiencies are present in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to vary and the reliability may deteriorate. In addition, hydrogen near the oxygen deficiency may form a defect in which hydrogen enters the oxygen deficiency (hereinafter sometimes referred to as V O H).) and may generate electrons serving as carriers. For this reason, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics (characteristics in which a channel exists even when no voltage is applied to the gate electrode and current flows through the transistor). Therefore, in the channel formation region in the oxide semiconductor, it is preferable that impurities and oxygen deficiencies are reduced as much as possible. In other words, in the channel formation region in the oxide semiconductor, it is preferable that the carrier concentration is reduced and it is i-type (intrinsic) or substantially i-type.

[0066] On the other hand, an insulator containing oxygen that desorbs by heating (hereinafter sometimes referred to as excess oxygen) is provided near the oxide semiconductor, and by performing heat treatment, a configuration may be adopted in which oxygen can be supplied from the insulator to the oxide semiconductor. Thereby, the oxygen deficiency contained in the channel formation region in the oxide semiconductor can be repaired by the supplied oxygen. Further, by reacting a part of the supplied oxygen with the hydrogen remaining in the oxide semiconductor, the hydrogen can be removed (dehydrated) as H2O. Thereby, the formation of V O H in the oxide semiconductor can be suppressed.

[0067] However, if an excessive amount of oxygen is supplied to the source region or the drain region, the carrier concentration in the source region or the drain region may decrease, causing a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility. Further, if the oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0068] Therefore, in the oxide semiconductor, the region 234 that functions as the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, but the regions 236a and 236b that function as the source region or the drain region preferably have a high carrier concentration and are n-type. That is, it is preferable to supply oxygen to the region 234 of the oxide semiconductor and not to supply an excessive amount of oxygen to the regions 236a and 236b.

[0069] For example, by forming the insulator 254 by sputtering, oxygen can be implanted into the insulator 224. Then, the oxygen implanted into the insulator 224 is supplied to the oxide 230b through the oxide 230c. Thereby, oxygen can be selectively supplied to the oxide 230c that occupies most of the region 234 and the region of the oxide 230b that is in contact with the oxide 230c.

[0070] Further, by using CAAC-OS having the dense structure as described above as the oxide 230b, it is possible to reduce impurities and oxygen diffusion in the oxide 230b. Therefore, it is possible to reduce the diffusion of oxygen supplied to the region 234 of the oxide 230b to the regions 236a and 236b of the oxide 230b.

[0071] Also, part of the excess oxygen diffused into the oxide 230c diffuses into the oxide 230d. Since oxygen hardly diffuses in the oxide 230d compared to the oxide 230c, the diffusion of oxygen into the insulator 250 is relatively suppressed. Thereby, it is possible to suppress the oxidation of the conductor 260 through the insulator 250.

[0072] Although details will be described later, when etching the oxide 230a and the oxide 230b, a layer 244A may be formed on the insulator 224 or the like (see FIGS. 6B to 6D). When the layer 244A is formed on the insulator 224, the amount of oxygen injected into the insulator 224 by forming the insulator 254 using the sputtering method is reduced. Further, when the layer 244A has a function of suppressing oxygen diffusion, the diffusion of excess oxygen contained in the insulator 280 or the like into the insulator 224 is suppressed. Thereby, there is a concern that the amount of oxygen supplied to the channel formation region of the oxide 230 may decrease.

[0073] Note that the film thickness of the layer 244A on the insulator 224 tends to be thicker as it is closer to the conductive layer 242B and thinner as it is farther from the conductive layer 242B. For example, when the integration degree of the transistors is different, the distribution of the film thickness of the layer 244A may be different. Therefore, the amount of oxygen supplied to the channel formation region of the oxide 230 varies.

[0074] Therefore, in the transistor 200 according to one aspect of the present invention, it is preferable to remove the layer 244A on the insulator 224. Further, in the transistor 200 according to one aspect of the present invention, it is preferable to suppress the formation of the layer 244A and remove the layer 244A on the insulator 224.

[0075] For the removal of layer 244A, a dry etching method or a wet etching method may be used. In particular, it is preferable to use a dry etching method. Details will be described later.

[0076] Note that when removing layer 244A on insulator 224, a part of layer 244A may remain, and layer 244B may be formed so as to cover the side surfaces of oxide 230a, oxide 230b, etc. (see FIGS. 7A to 7D). When layer 244B has a function of suppressing oxygen diffusion, layer 244B formed on the side surfaces of oxide 230a and oxide 230b can suppress oxygen from mixing into regions 236a and 236b. Therefore, regions 236a and 236b can maintain a low-resistance region.

[0077] In a subsequent process, layer 244a is disposed in contact with the side surfaces of oxide 230a, the side surfaces of oxide 230b, oxide 243a, and the side surfaces of conductor 242a (see FIGS. 1A, 1B, and 1D). That is, oxide 230a and oxide 230b are separated from insulator 280 by insulator 254 and layer 244a which is difficult to diffuse oxygen. Thereby, it is possible to suppress the excessive oxygen contained in insulator 280 from directly diffusing into oxide 230a and oxide 230b. Although only the side of conductor 242a (region 236a side) has been mentioned above, the diffusion of excessive oxygen can be suppressed in the same manner on the side of conductor 242b (region 236b side).

[0078] As described above, oxygen is selectively supplied to region 234 of the oxide semiconductor to make region 234 i-type or substantially i-type, and to suppress the oxygen diffusing into regions 236a and 236b that function as source regions or drain regions, so that the n-type of regions 236a and 236b can be maintained. Thereby, the variation in the electrical characteristics of transistor 200 can be suppressed, and the variation in the electrical characteristics of transistor 200 within the substrate surface can be suppressed.

[0079] By configuring as described above, a semiconductor device with less variation in transistor characteristics can be provided. Also, a semiconductor device with good reliability can be provided. Further, a semiconductor device having good electrical characteristics can be provided.

[0080] Incidentally, as a parameter for evaluating the reliability of a transistor, for example, there is a shift voltage (Vsh) measured in a +GBT (Gate Bias Temperature) stress test of the transistor. Vsh is defined as the Vg at which the tangent line at the point where the slope on the drain current (Id)-gate voltage (Vg) curve of the transistor is maximum intersects the straight line of Id = 1 pA. Also, the change amount of Vsh is represented as ΔVsh.

[0081] In the +GBT stress test of the transistor, ΔVsh may shift in the negative direction with the passage of time. Also, ΔVsh may show a behavior of fluctuating not only in the - direction (for example, the negative direction) but also in both the negative and positive directions. Incidentally, in this specification and the like, the above behavior may be referred to as the zigzag behavior of ΔVsh in the +GBT stress test.

[0082] By using a metal oxide that does not contain element M as a main component or a metal oxide with a small ratio of element M for the oxide 230c, for example, ΔVsh can be reduced, the zigzag behavior of ΔVsh can be suppressed, and the reliability of the transistor can be improved.

[0083] Also, the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used for the oxide 230c, and more preferably contains all of the metal elements. For example, as the oxide 230c, an In-M-Zn oxide, an In-Zn oxide, or indium oxide may be used, and as the oxide 230d, an In-M-Zn oxide, an M-Zn oxide, or an oxide of element M may be used. Thereby, the density of defect energy levels at the interface between the oxide 230c and the oxide 230d can be lowered.

[0084] Further, the oxide 230d is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c. By providing the oxide 230d between the insulator 250 and the oxide 230c, it is possible to suppress the oxygen contained in the insulator 280 from diffusing into the insulator 250. Therefore, the oxygen can be efficiently supplied to the oxide 230b through the oxide 230c.

[0085] Also, in the metal oxide used for the oxide 230d, by making the atomic ratio of In to the metal element that is the main component smaller than the atomic ratio of In to the metal element that is the main component in the metal oxide used for the oxide 230c, it is possible to suppress the diffusion of In to the insulator 250 side. Since the insulator 250 functions as a gate insulator, if In is mixed into the insulator 250 or the like, the characteristics of the transistor deteriorate. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it becomes possible to provide a highly reliable semiconductor device.

[0086] Here, at the junctions of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d, the lower end of the conduction band changes smoothly. In other words, it can also be said that the lower end of the conduction band at the junctions of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d changes continuously or is continuously joined. To achieve this, it is preferable to lower the density of defect levels in the mixed layers formed at the interfaces between the oxide 230a and the oxide 230b, between the oxide 230b and the oxide 230c, and between the oxide 230c and the oxide 230d.

[0087] Specifically, by having the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c, and the oxide 230c and the oxide 230d have a common element other than oxygen as the main component, it is possible to form a mixed layer with a low density of defect levels. For example, when the oxide 230b is an In-M-Zn oxide, an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, indium oxide, etc. may be used as the oxide 230a, the oxide 230c, and the oxide 230d.

[0088] Specifically, as the oxide 230a, a metal oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof may be used. Further, as the oxide 230b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof may be used. Further, as the oxide 230c, a metal oxide having a composition of In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, In:M:Zn = 5:1:3 [atomic ratio] or in the vicinity thereof, or In:M:Zn = 10:1:3 [atomic ratio] or in the vicinity thereof, or indium oxide may be used. Further, as the oxide 230d, a metal oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, M:Zn = 2:1 [atomic ratio] or in the vicinity thereof, or M:Zn = 2:5 [atomic ratio] or in the vicinity thereof, or an oxide of element M may be used. Here, the vicinity of the composition includes a range of ±30% of the desired atomic ratio. Further, as the element M, it is preferable to use gallium.

[0089] By configuring the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d as described above, the density of defect levels at the interfaces between the oxide 230a and the oxide 230b, between the oxide 230b and the oxide 230c, and between the oxide 230c and the oxide 230d can be lowered. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.

[0090] Further, in a cross-sectional view in the channel length direction of the transistor, it is preferable to provide a groove portion in the oxide 230b and embed the oxide 230c having CAAC-OS in the groove portion. At this time, the oxide 230c is arranged so as to cover the inner wall (side wall and bottom surface) of the groove portion.

[0091] Further, the depth of the groove portion of the oxide 230b preferably substantially matches the film thickness of the oxide 230c. In other words, the upper surface of the oxide 230c in the region overlapping with the oxide 230b is preferably arranged substantially in line with the interface between the oxide 230b and the oxide 243a or the oxide 243b. For example, when taking the bottom surface of the insulator 222 as a reference, the difference in height between the interface between the oxide 230b and the oxide 243a or the oxide 243b and the interface between the oxide 230c and the oxide 230d is preferably equal to or less than the film thickness of the oxide 230c, and more preferably equal to or less than half of the film thickness of the oxide 230c.

[0092] With the above configuration, in the transistor, defects such as V O the influence of H and impurities can be reduced, and a channel can be formed in the oxide 230c. Thereby, good electrical characteristics can be imparted to the transistor. Furthermore, a semiconductor device with less variation in transistor characteristics and good reliability can be provided.

[0093] Also, it is preferable that impurities at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof are reduced or removed. In particular, impurities such as aluminum and silicon preferably are reduced or removed because they inhibit the improvement of the crystallinity or c-axis orientation of the oxide 230c and the oxide 230b. For example, the concentration of aluminum atoms at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof is preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, and even more preferably 1.0 atomic% or less.

[0094] Note that a region of a metal oxide in which the improvement of crystallinity or c-axis orientation is inhibited by impurities such as aluminum and silicon and which becomes a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor) may be referred to as a non-CAAC region. In the non-CAAC region, V OH is likely to be formed in a large amount. Therefore, when a non-CAAC region is formed in the channel formation region, the transistor may be easily normally turned on. From the above, in the channel formation region, it is preferable that the non-CAAC region is reduced or removed.

[0095] On the other hand, in the oxides 230b and 230c having a CAAC structure, since a dense crystal structure is formed, V O H is less likely to exist stably. Further, in the post-oxidation treatment described later, by supplying excess oxygen to the oxides 230b and 230c, V O H → V O + H, V O + O → null reaction can proceed. Thereby, V O H in the oxides 230b and 230c is reduced, and further V O can also be reduced. Thus, since the oxides 230b and 230c have a CAAC structure, normal turn-on of the transistor can be suppressed.

[0096] In FIG. 2, a configuration is shown in which the side surface of the opening for embedding the conductor 260 etc. is substantially perpendicular to the formation surface of the oxide 230b including the groove portion of the oxide 230b, but one aspect of the present invention is not limited thereto. The bottom of the opening may have a U-shaped shape having a gentle curved surface.

[0097] Here, in the oxide 230c, the c-axis of the crystal having the CAAC structure preferably faces a direction substantially perpendicular to the formation surface or the upper surface of the oxide 230c. Therefore, it has a region where the crystal layer extends so as to be substantially parallel to the bottom surface and the side surface of the opening. It is more preferable that the oxide 230d also has the same crystal structure as the oxide 230c.

[0098] In addition, the angle formed between the a-b plane of the crystal of the CAAC structure of the oxide 230c in the groove portion and the a-b plane of the crystal of the CAAC structure of the oxide 230b is preferably 60 degrees or less, more preferably 45 degrees or less, and even more preferably 30 degrees or less. Thus, by reducing the angle formed between the a-b plane of the crystal of the CAAC structure of the oxide 230c in the groove portion and the a-b plane of the crystal of the CAAC structure of the oxide 230b, the crystallinity of the oxide 230c can be increased in the groove portion.

[0099] Note that the oxide composed of the non-CAAC region is not limited to being formed so as to be surrounded by the oxide 230b, the oxide 243a, the oxide 230c, and the oxide 230d, and may also be formed so as to be sandwiched between the oxide 230b and the oxide 230c.

[0100] Further, as shown in FIG. 1C, in a cross-sectional view in the channel width direction of the transistor 200, a curved surface may be provided between the side surface and the upper surface of the oxide 230b. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter, also referred to as a round shape).

[0101] The radius of curvature of the curved surface is greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242a or the conductor 242b, or less than half of the length of the region of the upper surface of the oxide 230b that does not have the curved surface, which is preferable. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and even more preferably 2 nm or more and 10 nm or less. By adopting such a shape, the covering property of the insulator 250 and the conductor 260 formed in a later process to the groove portion can be improved. In addition, it is possible to prevent a decrease in the length of the region of the upper surface of the oxide 230b that does not have the curved surface, and suppress a decrease in the on-current and mobility of the transistor 200. Therefore, a semiconductor device having good electrical characteristics can be provided.

[0102] Note that the oxide 230c may be provided for each transistor 200. That is, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 may not be in contact with each other. Also, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, the oxide 230c may not be disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0103] In a semiconductor device in which a plurality of transistors 200 are arranged in the channel width direction, by adopting the above configuration, the oxide 230c is provided independently for each transistor 200. Therefore, it is possible to suppress the generation of parasitic transistors between the transistor 200 and the transistor 200 adjacent to the transistor 200, and to suppress the generation of a leakage path along the conductor 260. Therefore, it is possible to provide a semiconductor device having good electrical characteristics and capable of miniaturization or high integration.

[0104] For example, in the channel width direction of the transistor 200, when the distance between the side end portions of the oxide 230c of the transistor 200 facing each other and the side end portions of the oxide 230c of the transistor 200 adjacent to the transistor 200 is represented as L1, L1 is made larger than 0 nm. Also, in the channel width direction of the transistor 200, when the distance between the side end portions of the oxide 230a of the transistor 200 facing each other and the side end portions of the oxide 230a of the transistor 200 adjacent to the transistor 200 is represented as L2, the value of the ratio (L1 / L2) of L1 to L2 is preferably larger than 0 and less than 1, more preferably 0.1 or more and 0.9 or less, and still more preferably 0.2 or more and 0.8 or less. Note that L2 may be the distance between the side end portions of the oxide 230b of the transistor 200 facing each other and the side end portions of the oxide 230b of the transistor 200 adjacent to the transistor 200.

[0105] By reducing the ratio of L1 to L2 (L1 / L2) described above, even if the oxide 230c is displaced in the region not disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 can be separated from each other.

[0106] Further, by increasing the ratio of L1 to L2 (L1 / L2) described above, even if the distance between the transistor 200 and the transistor 200 adjacent to the transistor 200 is narrowed, the width of the minimum processing dimension can be ensured, and further miniaturization or high integration of the semiconductor device can be achieved.

[0107] Note that each of the conductor 260 and the insulator 250 may be commonly used between adjacent transistors 200. That is, the conductor 260 of the transistor 200 has a region continuously provided with the conductor 260 of the transistor 200 adjacent to the transistor 200. Also, the insulator 250 of the transistor 200 has a region continuously provided with the insulator 250 of the transistor 200 adjacent to the transistor 200.

[0108] Also, with the above configuration, the oxide 230d has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200. Note that the oxide 230d of the transistor 200 may be configured to be separated from the oxide 230d of the transistor 200 adjacent to the transistor 200. At this time, the insulator 250 has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0109] Insulators 211, 212, 214, 254, 282, 283, 284, and 286 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable to use an insulating material for insulators 211, 212, 214, 254, 282, 283, 284, and 286 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms (i.e., the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the above oxygen is difficult to permeate).

[0110] Note that in this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability). Alternatively, it refers to a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0111] For example, it is preferable to use silicon nitride or the like for insulators 211, 212, 283, and 284, and aluminum oxide or the like for insulators 214, 254, and 282. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through insulators 211, 212, and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in insulator 224 or the like to the substrate side through insulators 211, 212, and 214. In this way, it is preferable to form a structure in which the transistor 200 is surrounded by insulators 211, 212, 214, 254, 282, 283, 284, and 286 that have a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0112] Also, in some cases, it is preferable to lower the resistivity of the insulator 211, the insulator 284, and the insulator 286. For example, by setting the resistivity of the insulator 211, the insulator 284, and the insulator 286 to approximately 1×10 13 Ωcm, in a process using plasma or the like in the semiconductor device manufacturing process, the insulator 211, the insulator 284, and the insulator 286 may be able to mitigate the charge-up of the conductor 205, the conductor 242a, the conductor 242b, the conductor 260, the conductor 246a, or the conductor 246b. The resistivity of the insulator 211, the insulator 284, and the insulator 286 is preferably 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.

[0113] Note that the insulator 211 or the insulator 212 does not necessarily have to be provided, and the insulator 283 or the insulator 284 does not necessarily have to be provided. For example, this is the case when the insulator 212 and the insulator 284 are formed by CVD using a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content.

[0114] Also, the insulator 216 and the insulator 280 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 216 and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, etc. may be appropriately used.

[0115] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no negative potential is applied.

[0116] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Also, the conductor 205 is preferably provided by being embedded in the insulator 214 or the insulator 216.

[0117] Note that, as shown in FIG. 1A, the conductor 205 is preferably provided to be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 preferably extends also in the region outside the end portions intersecting the channel width direction of the oxides 230a and 230b. That is, outside the side surfaces in the channel width direction of the oxide 230, it is preferable that the conductor 205 and the conductor 260 overlap via an insulator. By having such a configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, the structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0118] In the present specification and the like, the transistor with an S-channel structure refers to a structure of a transistor that electrically surrounds a channel formation region by an electric field of one and the other of a pair of gate electrodes. Further, the S-channel structure disclosed in the present specification and the like is different from a Fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to enhance the resistance to the short-channel effect, in other words, to obtain a transistor in which the short-channel effect hardly occurs.

[0119] Further, as shown in FIG. 1C, the conductor 205 is extended to also function as a wiring. However, the present invention is not limited to this, and a configuration may be adopted in which a conductor functioning as a wiring is provided under the conductor 205. Further, the conductor 205 does not necessarily have to be provided one by one for each transistor. For example, a configuration may be adopted in which the conductor 205 is shared by a plurality of transistors.

[0120] Note that in the transistor 200, the conductor 205 is shown as a configuration in which the conductor 205a and the conductor 205b are laminated, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned in the formation order for distinction.

[0121] Here, for the conductor 205a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0122] By using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As the conductive material having a function of suppressing oxygen diffusion, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, as the conductor 205a, the above conductive material may be a single layer or a laminate. For example, the conductor 205a may be a laminate of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.

[0123] In addition, for the conductor 205b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205b is shown as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the conductive material.

[0124] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). In addition, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0125] The insulator 222 may be made of an insulator containing one or both oxides of aluminum and hafnium, which are insulating materials. As such an insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 or the oxide 230.

[0126] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to the above insulator. Alternatively, these insulators may be nitrided. Further, the insulator 222 may be used by laminating silicon oxide, silicon oxynitride or silicon nitride on these insulators.

[0127] Further, the insulator 222 may be used in a single layer or in a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0128] The insulator 224 in contact with the oxide 230 preferably desorbs oxygen upon heating. For example, the insulator 224 may be appropriately silicon oxide, silicon oxynitride, or the like. By providing an oxygen-containing insulator in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0129] Specifically, as the insulator 224, it is preferable to use an oxide material in which some oxygen desorbs upon heating, in other words, an insulator material having an excess oxygen region. The oxide film that desorbs oxygen upon heating is one in which the desorption amount of oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, more preferably 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more as determined by TDS (Thermal Desorption Spectroscopy) analysis. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0130] Further, the insulator having the excess oxygen region and the oxide 230 may be subjected to any one or more of heat treatment, microwave treatment, or RF treatment in contact with each other. By performing this treatment, water or hydrogen in the oxide 230 can be removed. For example, in the oxide 230, a reaction occurs in which the bond of a defect (V O H) in which hydrogen enters the oxygen vacancy is broken, in other words, a reaction of "V O H → V O + H" occurs, and dehydrogenation can be achieved. A part of the hydrogen generated at this time may combine with oxygen to form H2O and be removed from the oxide 230 or the insulator near the oxide 230. Also, a part of the hydrogen may diffuse or be captured (also referred to as gettering) by the conductor 242a or the conductor 242b.

[0131] The above microwave treatment is preferably carried out using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or the insulator near the oxide 230. Further, the above microwave treatment may be carried out at a pressure of 133 Pa or more, preferably 200 Pa or more, more preferably 400 Pa or more. Further, as the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0132] Further, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment in a state where the surface of the oxide 230 is exposed. The heat treatment may be carried out, for example, at 100°C or more and 450°C or less, more preferably 350°C or more and 400°C or less. The heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably carried out in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 230 to reduce oxygen deficiency. The heat treatment may also be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously carried out in an atmosphere of nitrogen gas or an inert gas.

[0133] Note that by performing an oxygen addition treatment on the oxide 230, the oxygen deficiency in the oxide 230 is repaired by the supplied oxygen, in other words, "V" OThe reaction of "+O→null" can be promoted. Further, by reacting the oxygen supplied to the hydrogen remaining in the oxide 230, the hydrogen can be removed (dehydrated) as H2O. As a result, the hydrogen remaining in the oxide 230 recombines with oxygen vacancies to form V O The formation of H can be suppressed.

[0134] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0135] The oxide 243a and the oxide 243b may be provided on the oxide 230b.

[0136] The oxide 243a and the oxide 243b preferably have a function of suppressing oxygen permeation. By disposing the oxide 243a (oxide 243b) having a function of suppressing oxygen permeation between the conductor 242a (conductor 242b) functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242a (conductor 242b) and the oxide 230b is reduced, which is preferable. By adopting such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved. Note that when the electrical resistance between the conductor 242a (conductor 242b) and the oxide 230b can be sufficiently reduced, the oxide 243a (oxide 243b) may not be provided.

[0137] As the oxide 243a and the oxide 243b, a metal oxide having an element M may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. It is preferable that the concentration of the element M in the oxide 243a and the oxide 243b is higher than that in the oxide 230b. Further, gallium oxide may be used as the oxide 243a and the oxide 243b. Further, a metal oxide such as an In-M-Zn oxide may be used as the oxide 243a and the oxide 243b. Specifically, in the metal oxide used for the oxide 243a and the oxide 243b, it is preferable that the atomic ratio of the element M to In is larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, the film thickness of the oxide 243a and the oxide 243b is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and still more preferably 1 nm or more and 2 nm or less. Further, it is preferable that the oxide 243a and the oxide 243b have crystallinity. When the oxide 243a and the oxide 243b have crystallinity, the release of oxygen in the oxide 230 can be preferably suppressed. For example, as the oxide 243a and the oxide 243b, if they have a crystal structure such as a hexagonal crystal, the release of oxygen in the oxide 230 may be suppressed.

[0138] The conductor 242a is provided on the oxide 243a, and the conductor 242b is provided on the oxide 243b. The conductor 242a and the conductor 242b each function as a source electrode or a drain electrode of the transistor 200.

[0139] As the conductor 242a and the conductor 242b, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one aspect of the present invention, nitrides containing tantalum are particularly preferred. Further, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. These materials are preferred because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when absorbing oxygen.

[0140] There may be a curved surface between the side surface and the upper surface of the conductor 242a, and between the side surface and the upper surface of the conductor 242b. That is, the end of the side surface and the end of the upper surface may be curved. The curved surface has a curvature radius of, for example, 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the ends of the conductor 242a and the conductor 242b. By not having a corner at the end, the film covering property in the subsequent film forming process is improved.

[0141] When the oxide 243a (oxide 243b) is not provided, the conductor 242a (conductor 242b) contacts the oxide 230b or the oxide 230c, so that oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a (conductor 242b), and the conductor 242a (conductor 242b) may be oxidized. When the conductor 242a and the conductor 242b are oxidized, the probability of the conductivity of the conductor 242a and the conductor 242b decreasing is high. Note that the diffusion of oxygen in the oxide 230b or the oxide 230c into the conductor 242a and the conductor 242b can be rephrased as the conductor 242a and the conductor 242b absorbing oxygen in the oxide 230b or the oxide 230c.

[0142] In addition, when oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a and the conductor 242b, a layer may be formed between the conductor 242a and the oxide 230b, between the conductor 242b and the oxide 230b, between the conductor 242a and the oxide 230c, or between the conductor 242b and the oxide 230c. Since the layer contains more oxygen than the conductor 242a or the conductor 242b, the layer is presumed to be insulating. At this time, the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and can be regarded as a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly composed of the MIS structure.

[0143] In addition, hydrogen contained in the oxide 230b, the oxide 230c, etc. may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b, the oxide 230c, etc. is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may combine with nitrogen possessed by the conductor 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b, the oxide 230c, etc. may be absorbed by the conductor 242a or the conductor 242b.

[0144] The layer 244a (layer 244b) is in contact with the side surfaces of the oxide 230a, the side surfaces of the oxide 230b, the side surfaces of the oxide 243a (oxide 243b), and the side surfaces of the conductor 242a (conductor 242b).

[0145] Layers 244a and 244b may have a function of suppressing oxygen diffusion. With the above configuration, it is possible to suppress oxygen contained in the insulator 280 from mixing in from the sides of the oxides 230b and 230a in the region overlapping with the conductor 242a or the conductor 242b. Thereby, it is possible to maintain the n-type on the side surfaces and in the vicinity thereof of the oxide 230b and the side surfaces and in the vicinity thereof of the oxide 230a in the region overlapping with the conductor 242a or the conductor 242b.

[0146] In this way, by making the side surfaces of the oxide 230a and the side surfaces of the oxide 230b that overlap with the conductor 242a or the conductor 242b functioning as the source electrode and the drain electrode n-type, the on-current of the transistor 200 can be increased.

[0147] Layers 244a and 244b contain one or more kinds of elements that are the main components of a film (such as the conductive layer 242B) that is partially removed during the etching of the oxides 230a and 230b, and oxygen. For example, when a nitride containing tantalum is used as the conductive layer 242B, layers 244a and 244b may contain tantalum and oxygen. Also, for example, when a nitride containing titanium is used as the conductive layer 242B, layers 244a and 244b may contain titanium and oxygen. Oxides containing metal elements such as tantalum-containing oxides and titanium-containing oxides are preferable because they have a function of suppressing oxygen diffusion.

[0148] Also, the film thicknesses of layers 244a and 244b are 0.1 nm or more and 3.0 nm or less, preferably 0.2 nm or more and 2.0 nm or less, and more preferably 0.5 nm or more and 1.5 nm or less.

[0149] The insulator 254 is provided to cover the side surfaces of the oxide 230a, the side surfaces of the oxide 230b, the side surfaces of the oxide 243a (oxide 243b), the side surfaces of the conductor 242a (conductor 242b), and the upper surfaces of the conductor 242a (conductor 242b) via the layer 244a (layer 244b).

[0150] The insulator 254 preferably has a function of suppressing oxygen diffusion. For example, the insulator 254 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 254, for example, an insulator containing one or both oxides of aluminum and hafnium may be formed into a film.

[0151] In addition, the insulator 254 is preferably formed into a film of aluminum oxide or hafnium oxide in an atmosphere containing oxygen by a bias sputtering method. The bias sputtering method is a method of sputtering while applying RF power to a substrate. By applying RF power to the substrate, the potential of the substrate becomes a negative potential (referred to as a bias potential) with respect to the plasma potential, and the + ions in the plasma are accelerated by this bias potential and injected into the substrate. The bias potential can be controlled by the magnitude of the RF power applied to the substrate. Therefore, by forming a film of aluminum oxide or hafnium oxide in an atmosphere containing oxygen by the bias sputtering method, oxygen can be injected into the insulator 224.

[0152] In the bias sputtering method, the amount of oxygen injected into the insulator 224 serving as the base of the insulator 254 can be controlled by the magnitude of the RF power applied to the substrate. For example, as the RF power, 0.31 W / cm 2 or more, preferably 0.62 W / cm 2 or more, more preferably 1.86 W / cm 2 or more of a bias may be applied to the substrate. That is, by the RF power when forming the insulator 254, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected. Also, the amount of oxygen suitable for improving the reliability of the transistor can be injected. Also, the frequency of the RF is preferably 10 MHz or more. Typically, it is 13.56 MHz. The higher the frequency of the RF, the smaller the damage to the substrate can be. Therefore, by adjusting the RF power applied to the substrate, the amount of oxygen injected into the insulator 224 can be controlled, so that the amount of oxygen injected into the insulator 224 can be optimized.

[0153] As described above, the insulator 254 has a function of injecting oxygen into the underlying film, while the insulator 254 itself has a function of suppressing oxygen permeation. Therefore, when the insulator 280 is formed on the insulator 254 in a subsequent process and oxygen is diffused from the insulator 280, it is possible to prevent oxygen from directly diffusing from the insulator 280 into the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B.

[0154] By providing the insulator 254 and the layer 244a (layer 244b) as described above, the oxide 230a, the oxide 230b, the oxide 243a (oxide 243b), and the conductor 242a (conductor 242b) can be separated from the insulator 280. Thus, it is possible to suppress oxygen from directly diffusing from the insulator 280 into the oxide 230a, the oxide 230b, the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b. Thereby, it is possible to prevent excessive oxygen from being supplied to the source region and the drain region of the oxide 230 and reduce the carrier concentration in the source region and the drain region. In addition, it is possible to suppress the excessive oxidation of the conductor 242a and the conductor 242b, an increase in the resistivity, and a reduction in the on-current.

[0155] The insulator 250 is preferably disposed in contact with at least a part of the oxide 230d. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0156] The insulator 250 is preferably formed using an insulator that releases oxygen upon heating, similar to the insulator 224. By providing an insulator that releases oxygen upon heating as the insulator 250 in contact with at least a part of the oxide 230d, oxygen can be effectively supplied to the channel formation region of the oxide 230, and oxygen deficiency in the channel formation region of the oxide 230 can be reduced. Therefore, fluctuations in electrical characteristics can be suppressed, stable electrical characteristics can be realized, and a transistor with improved reliability can be provided. Also, similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0157] In FIGS. 1B and 1C, the insulator 250 is shown as a single layer, but it may have a laminated structure of two or more layers. When the insulator 250 has a two-layer laminated structure, the lower layer of the insulator 250 is preferably formed using an insulator that releases oxygen upon heating, and the upper layer of the insulator 250 is preferably formed using an insulator having a function of suppressing oxygen diffusion. With such a configuration, diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260 can be suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Also, oxidation of the conductor 260 by oxygen contained in the lower layer of the insulator 250 can be suppressed. For example, the lower layer of the insulator 250 can be provided using a material that can be used for the above-described insulator 250, and the upper layer of the insulator 250 can be provided using a material similar to the insulator 222.

[0158] When silicon oxide, silicon oxynitride, etc. are used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be an insulating material that is a high-k material with a high relative dielectric constant. By forming the gate insulator as a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Also, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0159] As the upper layer of the insulator 250, specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230 can be used. In particular, it is preferable to use an insulator containing one or both oxides of aluminum and hafnium.

[0160] By forming the insulator 250 into a two-layer laminated structure, the physical thickness of the insulator 250 can maintain the distance between the conductor 260 and the oxide 230, thereby suppressing the leakage current between the conductor 260 and the oxide 230. In addition, the physical distance between the conductor 260 and the oxide 230, and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted appropriately.

[0161] Also, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0162] Note that the metal oxide preferably has a function as a part of the first gate electrode. For example, a metal oxide that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming the conductor 260a by sputtering, the electrical resistance value of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0163] By having the above metal oxide, it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260.

[0164] The conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to wrap the bottom surface and the side surface of the conductor 260b. Further, as shown in FIGS. 1B and 1C, the upper surface of the conductor 260 is disposed substantially flush with the upper surface of the insulator 250, the upper surface of the oxide 230d, and the upper surface of the oxide 230c. In FIGS. 1B and 1C, the conductor 260 is shown as a two-layer structure of a conductor 260a and a conductor 260b, but it may be a single-layer structure or a laminated structure of three or more layers.

[0165] For the conductor 260a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0166] In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized by oxygen contained in the insulator 250 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0167] In addition, since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, for the conductor 260b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0168] In the transistor 200, the conductor 260 is self-aligned to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, it can be surely arranged in the region between the conductor 242a and the conductor 242b without aligning the conductor 260.

[0169] Also, as shown in FIG. 1C, in the channel width direction of the transistor 200, it is preferable that the bottom surface of the region of the conductor 260 where the conductor 260 and the oxide 230b do not overlap is lower than the bottom surface of the oxide 230b. By configuring the conductor 260 that functions as a gate electrode to cover the side surface and the upper surface of the channel formation region of the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 can easily act on the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. When the bottom surface of the insulator 222 is used as a reference, the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230a, the oxide 230b, and the conductor 260 do not overlap is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0170] The insulator 280 is provided on the insulator 254. Also, the upper surface of the insulator 280 may be planarized.

[0171] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably provided using a material similar to the insulator 216, for example. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen that desorbs by heating.

[0172] Also, it is preferable that the impurity concentrations such as water and hydrogen in the insulator 280 are reduced. Further, the insulator 280 preferably has a low hydrogen concentration and has an excess oxygen region or excess oxygen, and for example, it may be provided using the same material as the insulator 216. Also, the insulator 280 may have a structure in which the above materials are laminated. For example, a laminated structure of silicon oxide formed by sputtering and silicon oxynitride formed by chemical vapor deposition (CVD) laminated thereon may be used. Further, silicon nitride may be laminated thereon.

[0173] The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280. Also, the insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282 and the insulator 283, for example, insulators such as aluminum oxide, silicon nitride, and silicon oxynitride may be used. For example, aluminum oxide with high blocking property against oxygen may be used as the insulator 282, and silicon nitride with high blocking property against hydrogen may be used as the insulator 283.

[0174] For the conductor 240a and the conductor 240b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum.

[0175] Further, each of the conductors 240a and 240b may have a laminated structure. When each of the conductors 240a and 240b has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulator 284, the insulator 283, the insulator 282, the insulator 280, and the insulator 254. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Further, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. In addition, it is possible to suppress impurities such as water and hydrogen contained in the upper layer than the insulator 284 from mixing into the oxide 230 through the conductors 240a and 240b.

[0176] As the insulators 241a and 241b, for example, insulators such as silicon nitride, aluminum oxide, and silicon oxynitride may be used. Since the insulators 241a and 241b are provided in contact with the insulator 254, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 from mixing into the oxide 230 through the conductors 240a and 240b. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0177] Further, a conductor 246a that functions as a wiring in contact with the upper surface of the conductor 240a and a conductor 246b that functions as a wiring in contact with the upper surface of the conductor 240b may be arranged. It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductors 246a and 246b. Further, the conductor may have a laminated structure, and for example, it may be a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.

[0178] The insulator 286 is provided on the conductor 246a, on the conductor 246b, and on the insulator 284. As a result, the upper surface of the conductor 246a, the side surface of the conductor 246a, the upper surface of the conductor 246b, and the side surface of the conductor 246b are in contact with the insulator 286, and the lower surface of the conductor 246a and the lower surface of the conductor 246b are in contact with the insulator 284. That is, the conductors 246a and 246b can be configured to be wrapped by the insulator 284 and the insulator 286. By adopting such a configuration, the permeation of oxygen from the outside can be suppressed, and the oxidation of the conductors 246a and 246b can be prevented. In addition, it is preferable because it can prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 246a and 246b.

[0179] <Constituent materials of semiconductor device> Hereinafter, the constituent materials that can be used in the semiconductor device will be described.

[0180] <<Substrate>> As the substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, and the like. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Or, those with elements provided on these substrates may also be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0181] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties.

[0182] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the operating voltage of the transistor while maintaining the physical film thickness. On the other hand, by using a material with a low relative permittivity for the insulator that functions as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0183] In addition, examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0184] In addition, examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores, or resin.

[0185] Furthermore, a transistor using a metal oxide can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0186] In addition, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated.

[0187] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Also, a semiconductor having a high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0188] Also, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining a material containing the above-described metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining a material containing the above-described metal element and a conductive material containing nitrogen may be used. Also, a laminated structure combining a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0189] In the case of using an oxide in the channel formation region of a transistor, it is preferable to use a stacked structure in which a conductor functioning as a gate electrode combines a material containing the above-described metal element and a conductive material containing oxygen. In this case, it is advisable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is likely to be supplied to the channel formation region.

[0190] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing the metal element and oxygen included in the metal oxide in which the channel is formed. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen included in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0191] <<Metal Oxide>> As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. Hereinafter, the metal oxides applicable to the oxide 230 according to the present invention will be described.

[0192] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0193] In addition, in this specification etc., a metal oxide having nitrogen may sometimes be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0194] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 3A. FIG. 3A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0195] As shown in FIG. 3A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, "CAAC (c-axis-aligned crystalline)", "nc (nanocrystalline)", and "CAC (cloud-aligned composite)" are included in "Crystalline" (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, single crystal and poly crystal are included in "Crystal".

[0196] Note that the structure within the thick frame shown in Fig. 3A is an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, this structure can be rephrased as a structure that is energetically unstable "Amorphous" and completely different from "Crystal".

[0197] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in Fig. 3B. Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 3B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 3B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 3B is 500 nm.

[0198] As shown in Fig. 3B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected at around 2θ = 31°. Note that, as shown in Fig. 3B, the peak at around 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0199] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Fig. 3C. Fig. 3C is the diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in Fig. 3C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0200] As shown in Fig. 3C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0201] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from Fig. 3A. For example, the oxide semiconductor can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystalline oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0202] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0203] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions are such that the c-axis is oriented in a specific direction. Here, the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain refers to a portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0204] Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be about several tens of nm.

[0205] Also, in an In-M-Zn oxide (where the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Here, indium and the element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0206] When performing structural analysis on the CAAC-OS film using, for example, an XRD apparatus, in the out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0207] Also, for example, in the electron diffraction pattern of the CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0208] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0209] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to carrier capture. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, indium-zinc oxide and indium-gallium-zinc oxide are preferable because they can suppress the generation of grain boundaries more than indium oxide.

[0210] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation, defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0211] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Note that since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam with a probe diameter larger than the nanocrystals (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern like a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0212] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0213] [[Constitution of Oxide Semiconductor]] Next, the details of the above-mentioned CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0214] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a state in which regions having the metal element are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0215] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0216] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0217] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0218] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0219] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0220] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on )、high field-effect mobility (μ), and good switching operation can be achieved.

[0221] Oxide semiconductors have various structures, each with different characteristics. The oxide semiconductor of one aspect of the present invention may have two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0222] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0223] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0224] It is preferable to use an oxide semiconductor with a low carrier concentration in the transistor. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, still more preferably 1×10 11 cm -3 or less, even more preferably 1×10 10 cm -3 less than, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Further, an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. In this specification and the like, when the carrier concentration of the metal oxide in the channel formation region is 1×10 16 cm -3 The following cases are defined as substantially high-purity intrinsic.

[0225] In addition, since the oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0226] In addition, the charge trapped in the trap levels of the oxide semiconductor may take a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high density of trap levels may have unstable electrical characteristics.

[0227] In addition, in a transistor using an oxide semiconductor, when impurities and oxygen deficiencies are present in the channel formation region in the oxide semiconductor, the oxide semiconductor may have a lower resistance. Also, the electrical characteristics may easily fluctuate and the reliability may deteriorate.

[0228] In a transistor using an oxide semiconductor in the channel formation region, when a low-resistance region is formed in the channel formation region, a leakage current (parasitic channel) between the source electrode and the drain electrode of the transistor is likely to occur in the low-resistance region. Also, due to the parasitic channel, transistor characteristic defects such as normal ionization of the transistor, an increase in leakage current, and a variation (shift) in threshold voltage due to stress application are likely to occur. Further, when the processing accuracy of the transistor is low, the parasitic channel varies from transistor to transistor, resulting in variations in transistor characteristics.

[0229] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film.

[0230] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0231] When impurities are incorporated into the oxide semiconductor, defect levels or oxygen deficiencies may be formed. Therefore, when impurities are incorporated into the channel formation region of the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are likely to fluctuate, and the reliability may deteriorate. Further, if the channel formation region contains oxygen deficiencies, the transistor tends to have normally-on characteristics (characteristics in which a channel exists even without applying a voltage to the gate electrode and current flows through the transistor).

[0232] In a transistor using a metal oxide, its electrical characteristics fluctuate due to impurities and oxygen deficiencies in the metal oxide, and it tends to have normally-on characteristics. Further, when the transistor is driven in a state where the metal oxide has excessive oxygen exceeding an appropriate value, the valence of the excessive oxygen atoms changes, and the electrical characteristics of the transistor fluctuate, which may result in poor reliability.

[0233] Further, when impurities are present in the channel formation region of the oxide semiconductor, the crystallinity of the channel formation region may decrease, and the crystallinity of the oxide provided in contact with the channel formation region may also decrease. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to deteriorate. Further, when the crystallinity of the oxide provided in contact with the channel formation region is low, interface levels are formed, and the stability or reliability of the transistor may deteriorate.

[0234] Examples of the impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0235] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0236] Further, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0237] Also, when nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen in the semiconductor layer tends to have normally-on characteristics. Or, when nitrogen is contained in the oxide semiconductor, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 or less, more preferably less than 1×10 18 atoms / cm 3 or less, even more preferably less than 5×10 17atoms / cm 3 Make it as follows.

[0238] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, and thus may form oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is made less than 1 × 10 20 atoms / cm 3 less than, preferably less than 1 × 10 19 atoms / cm 3 less than, more preferably less than 5 × 10 18 atoms / cm 3 less than, still more preferably less than 1 × 10 18 atoms / cm 3 Make it less than.

[0239] Defects (V O H) in which hydrogen has entered the oxygen vacancies can function as donors in the metal oxide. However, it is difficult to quantitatively evaluate such defects. Therefore, in the metal oxide, it may be evaluated by the carrier concentration instead of the donor concentration. Thus, in this specification and the like, as a parameter of the metal oxide, the carrier concentration assuming a state where no electric field is applied may be used instead of the donor concentration. That is, the "carrier concentration" described in this specification and the like may be paraphrased as the "donor concentration". Also, the "carrier concentration" described in this specification and the like can be paraphrased as the "carrier density".

[0240] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0241] <<Other semiconductor materials>> The semiconductor materials that can be used for the oxide 230 are not limited to the above-described metal oxides. As the oxide 230, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) as the semiconductor material. In particular, it is suitable to use a layer material that functions as a semiconductor as the semiconductor material.

[0242] Here, in this specification and the like, the layer material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer material has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0243] Examples of the layer material include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing a chalcogen. Further, chalcogens are a general term for elements belonging to Group 16 and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0244] As the oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide applicable as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0245] <Modification Example of Semiconductor Device> Hereinafter, with reference to FIGS. 4A to 4D, an example of a semiconductor device according to one aspect of the present invention will be described.

[0246] FIG. 4A shows a top view of the semiconductor device. FIG. 4B is a cross-sectional view corresponding to the portion indicated by the dashed line A1 - A2 in FIG. 4A. FIG. 4C is a cross-sectional view corresponding to the portion indicated by the dashed line A3 - A4 in FIG. 4A. FIG. 4D is a cross-sectional view corresponding to the portion indicated by the dashed line A5 - A6 in FIG. 4A. In the top view of FIG. 4A, some elements are omitted for clarity of the drawing.

[0247] In the semiconductor device shown in FIGS. 4A to 4D, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Also in this section, the materials described in detail in <Configuration Example of Semiconductor Device> can be used for the constituent materials of the semiconductor device.

[0248] <<Modification Example 1 of Semiconductor Device>> The semiconductor device shown in FIGS. 4A to 4D is a modification of the semiconductor device shown in FIGS. 1A to 1D. The semiconductor device shown in FIGS. 4A to 4D is different from the semiconductor device shown in FIGS. 1A to 1D in the shapes of the insulator 283 and the insulator 284. Also, it is different in having the insulator 274 and the insulator 287.

[0249] In the semiconductor device shown in FIGS. 4A to 4D, insulators 212, 214, 216, 222, 224, 254, 280, and 282 are patterned, and an insulator 287 is provided in contact with the side surfaces of the insulators 212, 214, 216, 222, 224, 254, 280, and 282. Also, insulators 283 and 284 are structured to cover the insulators 212, 214, 216, 222, 224, 254, 280, 282, and 287. That is, the insulator 283 contacts the upper surface of the insulator 282, the upper surface and side surfaces of the insulator 287, and the upper surface of the insulator 211, and the insulator 284 contacts the upper surface and side surfaces of the insulator 283. As a result, the insulators 214, 216, 222, 224, 254, 280, 282, and 287, including the oxide 230, etc., are isolated from the outside by the insulators 283 and 284 and the insulator 211. In other words, the transistor 200 is disposed within a region sealed by the insulators 283 and 284 and the insulator 211.

[0250] For example, it is preferable to form the insulators 212, 214, 287, and 282 using a material having a function of capturing hydrogen and fixing hydrogen, and to form the insulators 211, 283, and 284 using a material having a function of suppressing diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used as the insulators 212, 214, 287, and 282. Also, typically, silicon nitride can be used as the insulators 211, 283, and 284.

[0251] With the above configuration, it is possible to suppress hydrogen contained outside the sealed region from mixing into the sealed region.

[0252] In addition, in the transistor 200 shown in FIGS. 4A to 4D, the insulator 211, the insulator 283, and the insulator 284 are shown as being provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 211, the insulator 283, and the insulator 284 may be provided with a laminated structure of two or more layers.

[0253] The insulator 274 functions as an interlayer film. The insulator 274 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. The insulator 274 can be provided using, for example, the same material as the insulator 280.

[0254] <Method of manufacturing a semiconductor device> Next, a method of manufacturing a semiconductor device according to an aspect of the present invention, shown in FIGS. 4A to 4D, will be described with reference to FIGS. 5 to 21.

[0255] Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A show top views. Also, Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, and 21B are cross-sectional views corresponding to the portions indicated by the dashed lines A1 - A2 in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A respectively, and are also cross-sectional views in the channel length direction of the transistor 200. Further, Figures 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, and 21C are cross-sectional views corresponding to the portions indicated by the dashed lines A3 - A4 in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A respectively, and are also cross-sectional views in the channel width direction of the transistor 200. Also, Figures 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, 13D, 14D, 15D, 16D, 17D, 18D, 19D, 20D, and 21D are cross-sectional views of the portions indicated by the dashed lines A5 - A6 in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A respectively. Note that in the top views of Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A, some elements are omitted for clarity of the figure.

[0256] First, prepare a substrate (not shown), and form an insulator 211 on the substrate. The formation of the insulator 211 can be performed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0257] Note that the CVD method can be classified into a plasma enhanced CVD (PECVD) method that uses plasma, a thermal CVD (TCVD) method that uses heat, a photo CVD method that uses light, and the like. Furthermore, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on the raw material gas used.

[0258] In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Also, since the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0259] Also, as the ALD method, a thermal ALD method that performs the reaction of the precursor and the reactant only with thermal energy, a plasma enhanced ALD (PEALD) method that uses a plasma-excited reactant, or the like can be used.

[0260] In addition, the ALD method utilizes the self-limiting property of atoms and can deposit atoms one by one, enabling extremely thin film formation, film formation on structures with a high aspect ratio, film formation with few defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. In the PEALD (Plasma Enhanced ALD) method, film formation at a lower temperature may be possible by using plasma. Note that some of the precursors used in the ALD method contain impurities such as carbon. Therefore, the film formed by the ALD method may contain more impurities such as carbon compared to the film formed by other film formation methods. The quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0261] Unlike film formation methods in which particles emitted from a target or the like are deposited, the CVD method and the ALD method are film formation methods in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is less affected by the shape of the object to be processed and is a film formation method having good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method with a high film formation rate.

[0262] The composition of the obtained film can be controlled by the flow rate ratio of the source gases in the CVD method and the ALD method. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases. Also, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened because it does not require the time for conveyance and pressure adjustment compared to the case of forming a film using a plurality of film formation chambers. Therefore, the productivity of semiconductor devices may be increased.

[0263] In this embodiment, the insulator 211 is formed by depositing silicon nitride by the CVD method.

[0264] Next, an insulator 212 is formed on the insulator 211. The formation of the insulator 212 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 212 is formed by depositing silicon nitride by the sputtering method.

[0265] In this way, by using an insulator such as silicon nitride, which is difficult for copper to penetrate, as the insulator 211 and the insulator 212, even if a metal that easily diffuses, such as copper, is used for the conductor in the lower layer (not shown) than the insulator 211, it is possible to suppress the upward diffusion of the metal through the insulator 211 and the insulator 212. Further, by using an insulator such as silicon nitride, which is difficult for impurities such as water and hydrogen to penetrate, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the lower layer than the insulator 211.

[0266] Next, an insulator 214 is formed on the insulator 212. The formation of the insulator 214 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0267] The hydrogen concentration of the insulator 212 is preferably lower than the hydrogen concentration of the insulator 211, and the hydrogen concentration of the insulator 214 is preferably lower than the hydrogen concentration of the insulator 212. By forming silicon nitride by the sputtering method as the insulator 212, it is possible to form silicon nitride having a lower hydrogen concentration than the insulator 211 formed by depositing silicon nitride by the CVD method. Further, by using aluminum oxide as the insulator 214, the hydrogen concentration can be made lower than that of the insulator 212.

[0268] In a subsequent process, a transistor 200 is formed on the insulator 214. However, it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and the film with a relatively high hydrogen concentration is preferably disposed remotely from the transistor 200.

[0269] Next, an insulator 216 is formed on the insulator 214. The insulator 216 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. Further, the insulator 216 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulator 216 can be reduced.

[0270] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, a groove or a slit. In some cases, the region where the opening is formed may be referred to as an opening portion. The opening may be formed using wet etching, but dry etching is more preferable for microfabrication. Further, it is preferable to select the insulator 214 as an etching stopper film when forming a groove by etching the insulator 216. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 for forming the groove, the insulator 214 may be formed of silicon nitride, aluminum oxide, or hafnium oxide.

[0271] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0272] After the formation of the opening, a conductive film that becomes the conductor 205a is formed. It is desirable that the conductive film contains a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of a conductor having a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, etc. The formation of the conductive film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.

[0273] In the present embodiment, the conductive film that becomes the conductor 205a has a multilayer structure. First, tantalum nitride is formed by a sputtering method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, even if a metal such as copper that is easy to diffuse is used as the conductive film that becomes the conductor 205b described later, the diffusion of the metal outside the conductor 205a can be prevented.

[0274] Next, a conductive film that will become the conductor 205b is formed. The formation of the conductive film can be performed using methods such as plating, sputtering, CVD, MBE, PLD, ALD, etc. In the present embodiment, a low-resistance conductive material such as copper is formed as the conductive film.

[0275] Next, by performing CMP processing, a part of the conductive film that will become the conductor 205a and the conductive film that will become the conductor 205b are removed, and the insulator 216 is exposed. As a result, only in the opening, the conductor 205a and the conductor 205b remain. Thereby, the conductor 205 with a flat upper surface can be formed (see FIGS. 5A to 5D). Note that a part of the insulator 216 may be removed by the CMP processing.

[0276] In the above, the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but one aspect of the present invention is not limited to this. For example, the conductor 205 may be formed on the insulator 214, the insulator 216 may be formed on the conductor 205, and by performing CMP processing on the insulator 216, a part of the insulator 216 may be removed to expose the surface of the conductor 205.

[0277] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, an insulator containing one or both of oxides of aluminum and hafnium may be formed. The insulator containing one or both of oxides of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing inside the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0278] The formation of the insulator 222 can be performed using methods such as sputtering, CVD, MBE, PLD, ALD, etc.

[0279] Subsequently, heat treatment is preferably performed. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be adjusted to about 20%. The heat treatment may also be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas.

[0280] Also, the gas used in the above heat treatment is preferably highly purified. For example, the water content in the gas used in the above heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less. By performing heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the insulator 222 as much as possible.

[0281] In this embodiment, as the heat treatment, after the formation of the insulator 222, the flow rate of nitrogen gas is set to 4 slm, the flow rate of oxygen gas is set to 1 slm, and the treatment is carried out at a temperature of 400°C for 1 hour. By this heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Also, when an oxide containing hafnium is used as the insulator 222, the crystallinity of the insulator 222 can be improved by this heat treatment. The heat treatment can also be carried out at the timing such as after the formation of the insulator 224.

[0282] Next, an insulator 224 is formed on the insulator 222. The formation of the insulator 224 can be carried out using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide or silicon oxynitride is formed as the insulator 224 by a CVD method. The insulator 224 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulator 224 can be reduced. Since the insulator 224 will be in contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration is thus reduced.

[0283] Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed in a reduced pressure state. For the plasma treatment containing oxygen, it is preferable to use, for example, a device having a power source for generating high-density plasma using microwaves. Alternatively, it may have a power source for applying RF (Radio Frequency) to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224. Alternatively, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, heat treatment may not be performed.

[0284] Here, for example, after forming an aluminum oxide film on the insulator 224 by sputtering, CMP processing may be performed until the insulator 224 is reached. By performing the CMP processing, the surface of the insulator 224 can be planarized and smoothed. By disposing the aluminum oxide on the insulator 224 and performing CMP processing, it becomes easy to detect the end point of the CMP processing. Also, although a part of the insulator 224 may be polished by the CMP processing and the film thickness of the insulator 224 may become thinner, the film thickness may be adjusted during the film formation of the insulator 224. By performing planarization and smoothing of the surface of the insulator 224, it may be possible to prevent deterioration of the coverage rate of the oxide film to be formed later and prevent a decrease in the yield of the semiconductor device. Further, it is preferable to form an aluminum oxide film on the insulator 224 by sputtering because oxygen can be added to the insulator 224.

[0285] Next, an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224 (see FIGS. 5A to 5D). Note that it is preferable to form the oxide film 230A and the oxide film 230B continuously without exposing them to the atmospheric environment. By forming the film without opening to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and it is possible to keep the vicinity of the interface between the oxide film 230A and the oxide film 230B clean.

[0286] The oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0287] For example, when forming the oxide film 230A and the oxide film 230B by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. Also, when forming the above oxide film by sputtering, the above In-M-Zn oxide target or the like can be used.

[0288] In particular, when forming the oxide film 230A, a part of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0289] Also, when forming the oxide film 230B by sputtering, if the proportion of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, an oxygen-excess type oxide semiconductor is formed. A transistor using an oxygen-excess type oxide semiconductor in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this. When forming the oxide film 230B by sputtering, if the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type oxide semiconductor is formed. A transistor using an oxygen-deficient type oxide semiconductor in the channel formation region can obtain relatively high field-effect mobility. Also, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.

[0290] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. Also, the oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1. Note that each oxide film may be formed according to the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and the atomic ratio.

[0291] Next, a oxide film 243A is formed on the oxide film 230B (see FIGS. 5A to 5D). The formation of the oxide film 243A can be carried out using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable that the atomic ratio of Ga to In in the oxide film 243A is larger than the atomic ratio of Ga to In in the oxide film 230B. In the present embodiment, the oxide film 243A is formed by a sputtering method using an oxide target of In:Ga:Zn = 1:3:4 [atomic ratio].

[0292] Note that it is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A without exposing them to the atmosphere. For example, a multi-chamber type film forming apparatus may be used.

[0293] Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not crystallize polycrystallinely, and may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 400 ° C. or higher and 600 ° C. or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be adjusted to about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after performing the heat treatment in an atmosphere of nitrogen gas or an inert gas.

[0294] Also, the gas used in the above heat treatment is preferably highly purified. For example, the moisture content contained in the gas used in the above heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the oxide film 230A, the oxide film 230B, the oxide film 243A, and the like as much as possible.

[0295] In this embodiment, as the heat treatment, after performing a treatment at a temperature of 550°C for 1 hour in a nitrogen atmosphere, a treatment is continuously performed at a temperature of 550°C for 1 hour in an oxygen atmosphere. By this heat treatment, impurities such as water and hydrogen in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be removed. Further, by this heat treatment, the crystallinity of the oxide film 230B can be improved, and a denser and more compact structure can be obtained. Thereby, the diffusion of oxygen or impurities in the oxide film 230B can be suppressed.

[0296] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 5A to 5D). The conductive film 242A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that a heat treatment may be performed before forming the conductive film 242A. The heat treatment is performed under reduced pressure, and the conductive film 242A may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A and the like can be removed, and further, the moisture concentration and the hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 200°C.

[0297] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into an island shape using a lithography method.

[0298] First, a resist is formed on the conductive film 242A, and the resist is exposed through a mask. Next, the exposed region is removed or left using a developer to form a resist mask 277 (see FIGS. 5A to 5D).

[0299] For example, the resist mask 277 may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, a mask is not required.

[0300] Here, the heat resistance and dry etching resistance of the resist mask 277 may be improved. In this specification, improving the heat resistance and dry etching resistance of the resist mask may sometimes be referred to as curing the resist mask.

[0301] For example, by irradiating the resist mask with ultraviolet light, the resist molecules crosslink, and the heat resistance and dry etching resistance of the resist mask can be improved. As the ultraviolet light, it is preferable to use near ultraviolet light (ultraviolet light having a wavelength of 200 nm or more and 380 nm or less) or far ultraviolet light (ultraviolet light having a wavelength of 10 nm or more and 200 nm or less, also referred to as vacuum ultraviolet light), and it is more preferable to use ultraviolet light having a wavelength of 250 nm or more and 300 nm or less. Further, after irradiating the ultraviolet light, high-temperature heat treatment may be performed.

[0302] Also, for example, by exposing the resist mask to plasma and modifying the film quality on the resist surface side, the heat resistance and dry etching resistance of the resist mask can be improved. For the plasma, it is advisable to use H2 gas, a mixed gas of H2 and Ar, a mixed gas of CF4 and O2, a mixed gas of C2HCl3 and O2, or the like.

[0303] Next, by performing an etching process through the resist mask 277, the oxide films 230A, 230B, 243A, and the conductive film 242A are processed into island shapes to form the oxides 230a, 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 6A to 6D). Note that a dry etching method or a wet etching method can be used for this processing. Processing by a dry etching method is suitable for fine processing. Also, the oxide films 230A, 230B, 243A, and the conductive film 242A may be processed under different conditions. Note that in this step, the film thickness of the region that does not overlap with the oxide 230a of the insulator 224 may become thin.

[0304] Here, the oxides 230a, 230b, the oxide layer 243B, and the conductive layer 242B are formed so as to at least partially overlap with the conductor 205. Also, the side surfaces of the oxides 230a, 230b, the oxide layer 243B, and the conductive layer 242B are preferably substantially perpendicular to the upper surface of the insulator 222. When a plurality of transistors 200 are provided, the side surfaces of the oxides 230a, 230b, the oxide layer 243B, and the conductive layer 242B being substantially perpendicular to the upper surface of the insulator 222 enables reduction in area and increase in density. Alternatively, the configuration may be such that the angle formed by the side surfaces of the oxides 230a, 230b, the oxide layer 243B, and the conductive layer 242B and the upper surface of the insulator 222 is a small angle. With such a shape, in subsequent steps, the covering property of a film such as the insulator 254 is improved, and defects such as looseness can be reduced.

[0305] Also, the side surface of the conductive layer 242B has a curved surface between the side surface and the upper surface of the conductive layer 242B. That is, it is preferable that the end of the side surface and the end of the upper surface are curved. For example, at the end of the conductive layer 242B, the curved surface has a curvature radius of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less. By not having a corner at the end, the covering property of the film in the subsequent film formation step is improved.

[0306] In the above processing, layer 244A is formed on the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B (see FIGS. 6B to 6D). Layer 244A is a layer formed by a part of the conductive layer 242B being etched and rising up in the chamber and then redepositing. Therefore, layer 244A becomes an oxide containing the main component of the conductive layer 242B. For example, when tantalum nitride is used for the conductive layer 242B, layer 244A becomes an oxide containing tantalum.

[0307] Next, by anisotropically etching layer 244A, layer 244A on the insulator 224 and the conductive layer 242B is removed. At this time, a part of layer 244A may remain and layer 244B may be formed (see FIGS. 7A to 7D).

[0308] By the above anisotropic etching, layer 244A on the insulator 224 is removed. Therefore, in the interface between the insulator 224 and the insulator 254 to be formed later and in the vicinity thereof, the concentration of the metal contained in layer 244B becomes below the detection limit. Depending on the method of the above anisotropic etching and the like, the metal contained in layer 244B may be detected in the interface and the vicinity thereof. In any case, the concentration of the metal contained in layer 244B in the interface and the vicinity thereof is lower than the concentration of the metal in layer 244B. Or, the insulator 224 in the region in contact with the insulator 254 has a region with a lower concentration of the metal than layer 244a or layer 244b formed from layer 244B.

[0309] Note that after the above anisotropic etching, the resist mask 277 may remain. The remaining resist mask 277 can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process.

[0310] Note that the curing of the resist mask 277, the island processing of the oxide films 230A, 230B, 243A, and the conductive film 242A, and the anisotropic etching of the layer 244A are all preferably performed continuously using a single dry etching apparatus. Further, when the resist mask 277 remains after the anisotropic etching, the curing of the resist mask 277, the island processing of the oxide films 230A, 230B, 243A, and the conductive film 242A, the anisotropic etching of the layer 244A, and the removal of the resist mask 277 (also referred to as resist stripping) are all preferably performed continuously using a single dry etching apparatus. By continuously processing these steps, the steps can be simplified. Note that a step of removing deposits on the inner wall of the processing chamber of the dry etching apparatus (so-called chamber cleaning step) may be performed between the anisotropic etching and the resist stripping.

[0311] Next, an insulator 254 is formed on the insulator 224, the layer 244B, and the conductive layer 242B (see FIGS. 8B to 8D). The formation of the insulator 254 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, the insulator 254 is formed of aluminum oxide by a sputtering method.

[0312] Next, an insulating film that becomes the insulator 280 is formed on the insulator 254. The formation of the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulating film, a silicon oxide film may be formed using a sputtering method, and then a silicon oxide film may be formed thereon using a PEALD method or a thermal ALD method. Further, the insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulator 280 can be reduced. Note that a heat treatment may be performed before the formation of the insulating film. The heat treatment is performed under reduced pressure, and the insulating film may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 254 and the like can be removed, and further, the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be reduced. Also, the heat treatment conditions described above can be used for the heat treatment.

[0313] Next, a CMP treatment is performed on the insulating film to form an insulator 280 having a flat upper surface (see FIGS. 8B to 8D). Similar to the insulator 224, aluminum oxide may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.

[0314] Here, a microwave treatment may be performed. The microwave treatment is preferably performed in an atmosphere containing oxygen and under reduced pressure. By performing the microwave treatment, an electric field by the microwave is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., and V O H in the oxide 230b and the oxide 230a can be divided into oxygen vacancies and hydrogen. A part of the hydrogen divided at this time may combine with the oxygen of the insulator 280 and be removed as water molecules. Also, a part of the hydrogen may be gettered by the conductor 242a or the conductor 242b via the insulator 254.

[0315] Also, heat treatment may be performed while maintaining a reduced pressure state after the microwave treatment. By performing such treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0316] Also, by performing microwave treatment, the film quality of the insulator 280 can be modified to suppress the diffusion of hydrogen, water, impurities, and the like. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 through the insulator 280 in subsequent processes after the formation of the insulator 280 or by heat treatment or the like.

[0317] Next, a part of the insulator 280, a part of the insulator 254, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the layer 244B are processed to form an opening reaching the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 242a, the conductor 242b, the oxide 243a, the oxide 243b, the layer 244a, and the layer 244b are formed (see FIGS. 9A to 9D).

[0318] When forming the above opening, the upper part of the oxide 230b is removed. By removing a part of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the opening formation step or in a step different from the opening formation step.

[0319] In addition, for the processing of a part of the insulator 280, a part of the insulator 254, a part of the conductive layer 242B, a part of the oxide layer 243B, a part of the layer 244B, and a part of the oxide 230b, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for microfabrication. Also, the processing may be performed under different conditions respectively. For example, a part of the insulator 280 may be processed by the dry etching method, a part of the insulator 254 may be processed by the wet etching method, and a part of the oxide layer 243B, a part of the conductive layer 242B, and a part of the oxide 230b may be processed by the dry etching method. Also, the processing of a part of the oxide layer 243B and a part of the conductive layer 242B and the processing of a part of the oxide 230b may be performed under different conditions. Also, a part of the layer 244B may be processed when a part of the insulator 254 is processed, or may be processed when a part of the oxide layer 243B and a part of the conductive layer 242B are processed.

[0320] Here, when removing a part of the oxide 230b using the dry etching method to form a groove, it is preferable to increase the bias power for processing. For example, it is preferable that the power density of the bias power is 0.03 W / cm 2 or more, and more preferably 0.06 W / cm 2 or more. Also, the dry etching treatment time may be appropriately set according to the depth of the groove.

[0321] When forming the above opening, the surface of the oxide 230b corresponding to the bottom of the opening may be damaged. In the damaged region of the oxide 230b, crystal defects such as oxygen vacancies are formed, and impurities (metal elements such as hydrogen, nitrogen, silicon, and aluminum) may be present. In the damaged region, since oxygen vacancies and impurities such as hydrogen are likely to exist, the reaction of V O +H → V O H is likely to occur. In this way, in the damaged region, V OA large amount of H will be formed. Therefore, even if the oxide 230c is formed on the oxide 230b while leaving the damaged region of the oxide 230b, the transistor is likely to have normal-on characteristics. Further, due to the variation of the damaged region within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0322] Here, it is preferable to remove impurities attached to the surface or diffused inside the oxide 230a, the oxide 230b, etc. Further, it is preferable to remove the damaged region formed on the surface of the oxide 230b by the dry etching. Examples of the impurities include components contained in the insulator 280, the insulator 254, the layer 244B, and the conductive layer 242B, components contained in members used in the apparatus for forming the opening, and components contained in the gas or liquid used for etching. Examples of the impurities include aluminum, silicon, tantalum, fluorine, chlorine, etc.

[0323] In order to remove the damaged region, the above impurities, etc., a cleaning process is performed. Examples of the cleaning method include wet cleaning using a cleaning liquid, etc., plasma treatment using plasma, cleaning by heat treatment, etc., and the above cleaning may be appropriately combined. Note that the groove portion may become deeper by the cleaning process.

[0324] As the wet cleaning, a cleaning process may be performed using an aqueous solution obtained by diluting aqueous ammonia, oxalic acid, phosphoric acid, hydrofluoric acid, etc. with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning using these aqueous solutions, pure water, or carbonated water may be performed. Alternatively, these cleanings may be appropriately combined.

[0325] In addition, in this specification and the like, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available aqueous ammonia with pure water may be referred to as diluted aqueous ammonia. Further, the concentration, temperature, etc. of the aqueous solution may be appropriately adjusted according to the impurities to be removed, the configuration of the semiconductor device to be cleaned, etc. The ammonia concentration of the diluted aqueous ammonia may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. Also, the hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0326] Note that for ultrasonic cleaning, a frequency of 200 kHz or more, preferably 900 kHz or more, is used. By using this frequency, damage to the oxide 230b and the like can be reduced.

[0327] Also, the above cleaning process may be performed multiple times, and the cleaning liquid may be changed for each cleaning process. For example, as the first cleaning process, a process using diluted hydrofluoric acid or diluted aqueous ammonia may be performed, and as the second cleaning process, a process using pure water or carbonated water may be performed.

[0328] In this embodiment, as the above cleaning process, wet cleaning is performed using diluted hydrofluoric acid, and then wet cleaning is performed using pure water or carbonated water. By performing this cleaning process, impurities adhering to the surface or diffusing inside the oxides 230a, 230b, etc. can be removed. Further, the crystallinity of the oxide 230c formed on the oxide 230b can be enhanced.

[0329] Heretofore, due to processing such as dry etching or the above cleaning process, the film thickness of the insulator 224 in a region that overlaps the above opening and does not overlap the oxide 230b may become thinner than the film thickness of the insulator 224 in a region that overlaps the oxide 230b.

[0330] Heat treatment may be performed after the etching or after the cleaning. The heat treatment may be performed at 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 230a and the oxide 230b to reduce oxygen deficiency. Further, by performing such heat treatment, the crystallinity of the oxide 230b can be improved, and the crystallinity of the oxide 230c formed in the groove portion of the oxide 230b can also be improved. Also, the heat treatment may be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, heat treatment may be continuously performed in a nitrogen atmosphere without exposure to the atmosphere.

[0331] By removing the damage region, an oxide 230c having CAAC-OS can be formed in the groove portion of the oxide 230b from which the damage region has been removed. Further, the damage region may be removed by providing a groove portion above the oxide 230b in a cross-sectional view in the channel length direction of the transistor.

[0332] Next, a oxide film 230C is formed (see FIGS. 10A to 10D). Heat treatment may be performed before the formation of the oxide film 230C. The heat treatment is preferably performed under reduced pressure and the oxide film 230C is continuously formed without exposure to the atmosphere. Also, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and further, the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is 200°C.

[0333] Here, the oxide film 230C is preferably provided so as to be in contact with at least the inner wall of the groove formed in the oxide 230b, a part of the side surface of the oxide 243a, a part of the side surface of the oxide 243b, a part of the side surface of the conductor 242a, a part of the side surface of the conductor 242b, a part of the side surface of the insulator 254, and a part of the side surface of the insulator 280. The conductor 242a (conductor 242b) is surrounded by the oxide 243a (oxide 243b), the insulator 254, the layer 244a (layer 244b), and the oxide film 230C, so that a decrease in conductivity due to oxidation of the conductor 242a (conductor 242b) in subsequent processes can be suppressed.

[0334] The formation of the oxide film 230C can be carried out using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed using the same film formation method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C. In the present embodiment, the oxide film 230C is formed by a sputtering method using an oxide target of In:Ga:Zn = 4:2:3 [atomic ratio], an oxide target of In:Ga:Zn = 5:1:3 [atomic ratio], an oxide target of In:Ga:Zn = 10:1:3 [atomic ratio], or an indium oxide target.

[0335] When forming the oxide film 230C, a part of the oxygen contained in the sputtering gas may be supplied to the oxides 230a and 230b. Alternatively, when forming the oxide film 230C, a part of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%. Further, by forming the oxide film 230C in an atmosphere containing a large amount of oxygen in this way, the oxide film 230C is likely to become CAAC-OS.

[0336] The formation of the oxide film 230C is preferably carried out while heating the substrate. At this time, by setting the substrate temperature to 200 °C or higher, oxygen deficiencies in the oxide film 230C and the oxide 230b can be reduced. By forming the film while heating the substrate, the crystallinity of the oxide film 230C and the oxide 230b can be improved.

[0337] Next, a mask is formed on the oxide film 230C by a lithography method. Note that, as the mask, a hard mask or a resist mask may be used.

[0338] Next, a part of the oxide film 230C is selectively removed using the above mask. Note that a part of the oxide film 230C may be removed using a wet etching method or the like. By this step, a part of the oxide film 230C located between the transistors 200 adjacent in the channel width direction can be removed.

[0339] Note that, by the above step, in the region where a part of the oxide film 230C is removed, the surfaces of the insulator 224 and the insulator 280 are exposed. At this time, the film thicknesses of the insulator 224 and the insulator 280 in the region may become thinner. Also, the insulator 224 in the region may be removed and the surface of the insulator 222 may be exposed. Further, the step of forming the mask may also serve as the step of removing a part of the oxide film 230C.

[0340] Next, the above mask is removed (see FIGS. 11A, 11C, and 11D). Note that the mask may be removed using an etching method or the like.

[0341] Next, a oxide film 230D is formed (see FIGS. 12A to 12D). The formation of the oxide film 230D can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230D may be formed using the same film formation method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230D. In the present embodiment, as the oxide film 230D, a film is formed by a sputtering method using an oxide target of In:Ga:Zn = 1:3:4 [atomic ratio].

[0342] When the oxide film 230D is formed, a part of the oxygen contained in the sputtering gas may be supplied to the oxide film 230C. Alternatively, when the oxide film 230D is formed, a part of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, more preferably 100%.

[0343] Next, an insulating film 250A is formed (see FIGS. 12A to 12D). Heat treatment may be performed before the formation of the insulating film 250A. The heat treatment is performed under reduced pressure, and the insulating film 250A may be continuously formed without being exposed to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230D and the like can be removed, and further, the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0344] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes the insulator 250 in contact with the oxide 230d in a later process, it is preferable that the hydrogen concentration is reduced in this way.

[0345] In addition, when the insulator 250 has a two-layer laminated structure, it is preferable that the insulating film forming the lower layer of the insulator 250 and the insulating film forming the upper layer of the insulator 250 are continuously formed without being exposed to the atmospheric environment. By forming the film without exposing it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulating film forming the lower layer of the insulator 250 and the insulating film forming the upper layer of the insulator 250, and it is possible to keep the vicinity of the interface between the insulating film forming the lower layer of the insulator 250 and the insulating film forming the upper layer of the insulator 250 clean.

[0346] Here, after forming the insulating film 250A, microwave treatment may be performed in an atmosphere containing oxygen and under reduced pressure. By performing the microwave treatment, an electric field by the microwave is applied to the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, the oxide 230a, etc., and V in the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a O H can be divided into V O and hydrogen. At this time, a part of the hydrogen thus divided may be combined with oxygen to form H2O and removed from the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a. Also, a part of the hydrogen may be gettered by the conductor 242a and the conductor 242b. Thus, by performing the microwave treatment, the hydrogen concentration in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. Also, after dividing V O H in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D into V O and hydrogen, oxygen is supplied to the V O that may exist, so that V O can be repaired or supplemented.

[0347] Also, heat treatment may be performed while maintaining a reduced pressure state after microwave treatment. By performing such treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be efficiently removed. Also, a part of the hydrogen may be gettered by the conductor 242a and the conductor 242b. Alternatively, the step of performing heat treatment may be repeated a plurality of times while maintaining a reduced pressure state after microwave treatment. By repeatedly performing heat treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be removed more efficiently. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0348] Also, by performing microwave treatment, the film quality of the insulating film 250A can be modified, thereby suppressing the diffusion of hydrogen, water, impurities, and the like. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. to the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as forming a conductive film to be the conductor 260 or a post-treatment such as heat treatment.

[0349] Next, the conductive film 260A and the conductive film 260B are formed in order (see FIGS. 13A to 13D). The formation of the conductive film 260A and the conductive film 260B can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, the conductive film 260A is formed using the ALD method, and the conductive film 260B is formed using the CVD method.

[0350] Next, by CMP processing, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (conductor 260a and conductor 260b) (see FIGS. 14A to 14D). As a result, the oxide 230c is disposed so as to cover an opening reaching the oxide 230b and a part of the inner wall (side wall and bottom surface) of the groove of the oxide 230b. Further, the oxide 230d is disposed so as to cover the opening and the inner wall of the groove via the oxide 230c. Further, the insulator 250 is disposed so as to cover the opening and the inner wall of the groove via the oxide 230c and the oxide 230d. Further, the conductor 260 is disposed so as to embed the opening and the groove via the oxide 230c, the oxide 230d, and the insulator 250.

[0351] Next, a heat treatment may be performed. In the present embodiment, a treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere. By this heat treatment, the moisture concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced. Note that after the heat treatment, the film formation of the insulator 282 may be continuously performed without exposing to the atmosphere.

[0352] Next, an insulator 282 is formed on the oxide 230c, on the oxide 230d, on the insulator 250, on the conductor 260, and on the insulator 280 (see FIGS. 15B to 15D). The film formation of the insulator 282 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, it is preferable to form an aluminum oxide film by a sputtering method. By performing the film formation of the insulator 282 in an atmosphere containing oxygen using the sputtering method, oxygen can be added to the insulator 280 while forming the film. At this time, it is preferable to form the insulator 282 while heating the substrate. Further, by forming the insulator 282 in contact with the upper surface of the conductor 260, it is possible to suppress the absorption of oxygen possessed by the insulator 280 into the conductor 260 in a subsequent heat treatment, which is preferable.

[0353] Next, a part of the insulator 282, a part of the insulator 280, a part of the insulator 254, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, a part of the insulator 214, and a part of the insulator 212 are processed to form an opening reaching the insulator 211 (see FIGS. 16A to 16D). The opening may be formed so as to surround the transistor 200. Alternatively, the opening may be formed so as to surround a plurality of transistors 200. Therefore, in the opening, a part of the side surface of the insulator 282, a part of the side surface of the insulator 280, a part of the side surface of the insulator 254, a part of the side surface of the insulator 224, a part of the side surface of the insulator 222, a part of the side surface of the insulator 216, a part of the side surface of the insulator 214, and a part of the side surface of the insulator 212 are exposed.

[0354] For the processing of a part of the insulator 282, a part of the insulator 280, a part of the insulator 254, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, a part of the insulator 214, and a part of the insulator 212, a dry etching method or a wet etching method can be used. The processing by the dry etching method is suitable for fine processing. Also, the processing may be performed under different conditions respectively. Note that in this process, the film thickness of the region overlapping with the opening of the insulator 211 may become thin.

[0355] Next, an insulating film 287A is formed covering the insulator 282, the insulator 280, the insulator 254, the insulator 224, the insulator 222, the insulator 216, the insulator 214, and the insulator 212 (see FIGS. 17B to 17D). The insulating film 287A is preferably formed using the same conditions as those of the insulator 282. For example, the film formation of the insulating film 287A can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0356] Specifically, as the insulating film 287A, for example, it is preferable to form an aluminum oxide film by sputtering. By forming the insulating film 287A in an atmosphere containing oxygen using the sputtering method, oxygen can be added to the insulator 280 while forming the film. At this time, it is preferable to form the insulating film 287A while heating the substrate. Further, since the insulator 282 is formed in contact with the upper surface of the conductor 260, it is possible to suppress the absorption of oxygen in the insulator 280 by the conductor 260 in the film formation process of the insulating film 287A.

[0357] Subsequently, an anisotropic etching process is performed on the insulating film 287A to form the insulator 287 on the side surfaces of the insulator 282, the insulator 280, the insulator 254, the insulator 224, the insulator 222, the insulator 216, the insulator 214, and the insulator 212 (see FIGS. 18B to 18D).

[0358] Here, by bringing the side end of the insulator 282 into contact with the upper end of the insulator 287 and bringing the side end of the insulator 212 into contact with the lower end of the insulator 287, a structure for sealing the transistor 200 and the insulator 280 can be formed.

[0359] As the anisotropic etching process, it is preferable to perform a dry etching process. Thereby, the insulating film formed on a plane substantially parallel to the substrate surface can be removed, and the insulator 287 can be formed self-alignedly.

[0360] Next, an insulator 283 is formed to cover the insulator 282, the insulator 287, and the insulator 211 (see FIGS. 19B to 19D). The film formation of the insulator 283 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulator 283 may be a multilayer. For example, using a sputtering method, a silicon nitride film may be formed, and then a silicon nitride film may be formed on the silicon nitride using a CVD method. As shown in FIGS. 19B to 19D, the insulator 283 is in contact with the insulator 211 at the bottom surface of the opening. That is, the transistor 200 is wrapped with the insulator 283 on the upper surface and the side surfaces and the insulator 211 on the lower surface. In this way, by wrapping the transistor 200 with the highly barrier insulators 283 and 211, it is possible to prevent moisture and hydrogen from entering from the outside.

[0361] Next, an insulator 284 may be formed on the insulator 283 (see FIGS. 19B to 19D). Note that the insulator 284 is preferably formed using a film formation method with high film covering properties. For example, the film formation of the insulator 284 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, it is preferable that the insulator 284 uses the same materials as the insulator 212 and the insulator 283.

[0362] Specifically, it is preferable to form a silicon nitride film using a CVD method. In particular, the insulator 284 is preferably formed by a CVD method using a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content.

[0363] Next, an insulating film that becomes the insulator 274 is formed on the insulator 284. The film formation of the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to form a silicon oxide film using a CVD method. Further, the insulating film is preferably formed by a film formation method using a gas in which the above-described hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulating film can be reduced.

[0364] Subsequently, a CMP process is performed on the insulating film that becomes the insulator 274 to form an insulator 274 with a flat upper surface (see FIGS. 19B to 19D).

[0365] Next, a heat treatment may be performed. In the present embodiment, a treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere. By this heat treatment, the oxygen added by the film formation of the insulator 282 can be diffused to the insulator 280, and further supplied to the oxide 230a and the oxide 230b through the oxide 230c. Note that the heat treatment is not limited to after the formation of the insulator 274, and may be performed after the film formation of the insulator 282, after the film formation of the insulator 284, or the like.

[0366] Next, openings reaching the conductor 242a and openings reaching the conductor 242b are formed in the insulator 254, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 (see FIGS. 20A and 20B). The openings may be formed using a lithography method. Note that in FIG. 20A, the shape of the opening is circular in a top view, but it is not limited thereto. For example, the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are rounded in a top view.

[0367] Next, an insulating film that becomes the insulator 241a and the insulator 241b is formed, and the insulating film is anisotropically etched to form the insulator 241a and the insulator 241b. (See FIGS. 20A and 20B). The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film, an insulating film having a function of suppressing oxygen permeation is preferably used. For example, it is preferable to form an aluminum oxide film using the ALD method. Alternatively, it is preferable to form a silicon nitride film using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0368] Also, for the anisotropic etching of the insulating films that become the insulators 241a and 241b, for example, a dry etching method or the like may be used. By providing the insulator 241a or the insulator 241b on the sidewall portion of the opening, the permeation of oxygen from the outside can be suppressed, and the oxidation of the conductors 240a and 240b to be formed next can be prevented. Further, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0369] Next, a conductive film that becomes the conductors 240a and 240b is formed. The conductive film preferably has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The formation of the conductive film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0370] Next, by performing CMP processing, a part of the conductive film that becomes the conductors 240a and 240b is removed, and the upper surfaces of the insulators 284 and 274 are exposed. As a result, conductors 240a and 240b with a flat upper surface can be formed by the remaining conductive film only in the opening (see FIGS. 20A and 20B). Note that a part of the upper surface of the insulator 284 and a part of the upper surface of the insulator 274 may be removed by the CMP processing.

[0371] Next, a conductive film that becomes the conductors 246a and 246b is formed. The formation of the conductive film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0372] Next, the conductive film that becomes the conductors 246a and 246b is processed by a lithography method to form the conductor 246a in contact with the upper surface of the conductor 240a and the conductor 246b in contact with the upper surface of the conductor 240b. At this time, a part of the insulator 284 in a region where the conductors 246a and 246b do not overlap with the insulator 284 may be removed (see FIGS. 21B to 21D).

[0373] Next, an insulator 286 is formed on the conductor 246a, on the conductor 246b, and on the insulator 284 (see FIGS. 4A to 4D). The formation of the insulator 286 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulator 286 may be a multilayer. For example, silicon nitride may be formed using a sputtering method, and then silicon nitride may be formed on the silicon nitride using a CVD method.

[0374] As described above, a semiconductor device having the transistor 200 shown in FIGS. 4A to 4D can be manufactured. As shown in FIGS. 5 to 21, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device according to the present embodiment. When manufacturing a semiconductor device having the transistor 200 shown in FIGS. 1A to 1D, the semiconductor device may be manufactured without performing the steps shown in FIGS. 16 to 18.

[0375] <Application Example of Semiconductor Device> Hereinafter, with reference to FIGS. 22A and 22B, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, which is different from those shown in the previous <Configuration Example of Semiconductor Device> and the previous <Modification Example of Semiconductor Device>, will be described. In the semiconductor devices shown in FIGS. 22A and 22B, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device (see FIGS. 4A to 4D) shown in the <Modification Example of Semiconductor Device>. In this section, the materials described in detail in the <Configuration Example of Semiconductor Device> and the <Modification Example of Semiconductor Device> can be used as the constituent materials of the transistor 200.

[0376] Figures 22A and 22B show a configuration in which a plurality of transistors (transistors 200_1 to 200_n) are encapsulated by an insulator 283 and an insulator 211. In Figures 22A and 22B, the plurality of transistors appear to be arranged in the channel length direction, but this is not restrictive. The plurality of transistors may be arranged in the channel width direction or may be arranged in a matrix. Also, depending on the design, they may be arranged without regularity.

[0377] As shown in Figure 22A, a portion where the insulator 283 and the insulator 211 are in contact (hereinafter sometimes referred to as the sealing portion 265) is formed outside the plurality of transistors (transistors 200_1 to 200_n). The sealing portion 265 is formed so as to surround the plurality of transistors (also referred to as a transistor group). By adopting such a structure, the plurality of transistors can be wrapped by the insulator 283 and the insulator 211. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 will be provided on the substrate.

[0378] Also, a dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) may be provided overlapping the sealing portion 265. Since the above substrate is divided at the dicing line, the transistor group surrounded by the sealing portion 265 will be taken out as one chip.

[0379] Also, in Figure 22A, an example in which a plurality of transistors (transistors 200_1 to 200_n) are surrounded by one sealing portion 265 is shown, but this is not restrictive. As shown in Figure 22B, a configuration in which the plurality of transistors are surrounded by a plurality of sealing portions may be adopted. In Figure 22B, the plurality of transistors are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0380] In this way, by adopting a configuration in which a plurality of transistors (transistors 200_1 to 200_n) are surrounded by a plurality of sealing portions, the contact area between the insulator 283 and the insulator 212 increases, so that the adhesion between the insulator 283 and the insulator 212 can be further improved. As a result, the plurality of transistors can be more reliably sealed.

[0381] In this case, a dicing line may be provided overlapping the sealing portion 265a or the sealing portion 265b, or a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0382] According to one aspect of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Also, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Also, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Also, according to one aspect of the present invention, a low-power consumption semiconductor device can be provided.

[0383] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0384] (Embodiment 2) In this embodiment, one form of the semiconductor device will be described with reference to FIGS. 23 and 24.

[0385] [Memory device 1] An example of a semiconductor device (memory device) according to one aspect of the present invention is shown in FIG. 23. In the semiconductor device of one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor element 100 is provided above the transistor 300 and the transistor 200. Note that, as the transistor 200, the transistor 200 described in the previous embodiment can be used.

[0386] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, by using this in a memory device, it is possible to hold the stored content for a long time. That is, since it does not require a refresh operation or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

[0387] In the semiconductor device shown in FIG. 23, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Also, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor element 100.

[0388] Also, the memory device shown in FIG. 23 can form a memory cell array by arranging it in a matrix.

[0389] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. The transistor 300 may be either p-channel type or n-channel type.

[0390] Here, in the transistor 300 shown in FIG. 23, the semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. Also, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with a conductor 316 via an insulator 315. Note that the conductor 316 may be made of a material for adjusting the work function. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate, it is also called a FIN type transistor. Note that an insulator that functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Also, here, the case where a convex portion is formed by processing a part of the semiconductor substrate is shown, but an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0391] Note that the transistor 300 shown in FIG. 23 is an example, and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0392] <Capacitor element 100> The capacitor element 100 is provided above the transistor 200. The capacitor element 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, it is preferable that the insulator 130 is an insulator that can be used as the insulator 286 shown in the above embodiment.

[0393] Also, for example, the conductor 112 provided on the conductor 240 and the conductor 110 can be formed simultaneously. Note that the conductor 112 functions as a plug or wiring that is electrically connected to the capacitor element 100, the transistor 200, or the transistor 300.

[0394] In FIG. 23, the conductor 112 and the conductor 110 are shown in a single layer structure, but the structure is not limited thereto, and a stacked structure of two or more layers may be used. For example, between a conductor having barrier properties and a conductor having high conductivity, a conductor having barrier properties and a conductor having high adhesiveness to the conductor having high conductivity may be formed.

[0395] Further, the insulator 130 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc., and can be provided in a laminated or single-layer form.

[0396] For example, it is preferable to use a laminated structure of a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor element 100 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and can improve the dielectric strength by having an insulator with high dielectric strength, thereby suppressing the electrostatic breakdown of the capacitor element 100.

[0397] Examples of the high dielectric constant (high-k) material (material with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0398] On the other hand, examples of the material with high dielectric strength (material with a low relative dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin.

[0399] <Wiring layer> A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the respective structures. Also, a plurality of wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral collectively for a plurality of structures. Also, in this specification etc., a wiring and a plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0400] For example, on the transistor 300, as an interlayer film, insulators 320, 322, 324, and 326 are laminated in order. Also, in the insulators 320, 322, 324, and 326, a capacitor element 100, or conductors 328 and 330 that are electrically connected to the transistor 200, etc. are embedded. Note that the conductors 328 and 330 function as plugs or wiring.

[0401] Also, the insulator that functions as an interlayer film may function as a planarization film that covers the uneven shape below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0402] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 23, insulators 350, 352, and 354 are laminated in order. Also, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0403] Similarly, conductors such as conductor 218 and the conductor (conductor 205) that constitutes transistor 200 are embedded in insulator 210, insulator 211, insulator 212, insulator 214, and insulator 216. Note that conductor 218 functions as a plug or wiring that is electrically connected to capacitor element 100 or transistor 300. Further, insulator 150 is provided on conductor 120 and insulator 130.

[0404] Here, similarly to insulator 241a and insulator 241b shown in the above embodiment, insulator 217 is provided in contact with the side surface of conductor 218 that functions as a plug. Insulator 217 is provided in contact with the inner wall of the opening formed in insulator 210, insulator 211, insulator 212, insulator 214, and insulator 216. That is, insulator 217 is provided between conductor 218 and insulator 210, insulator 211, insulator 212, insulator 214, and insulator 216. Note that since conductor 205 can be formed in parallel with conductor 218, insulator 217 may be formed in contact with the side surface of conductor 205.

[0405] As insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride may be used. Since insulator 217 is provided in contact with insulator 211, insulator 212, insulator 214, and insulator 222, it is possible to suppress impurities such as water or hydrogen from being mixed into oxide 230 through conductor 218 from insulator 210 or insulator 216. In particular, silicon nitride is suitable because it has high blocking properties against hydrogen. Further, it is possible to prevent oxygen contained in insulator 210 or insulator 216 from being absorbed by conductor 218.

[0406] Insulator 217 can be formed in the same manner as insulator 241a and insulator 241b. For example, silicon nitride may be deposited using the PEALD method, and an opening reaching conductor 356 may be formed using anisotropic etching.

[0407] Examples of insulators that can be used as an interlayer film include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. that have insulating properties.

[0408] For example, by using a material with a low relative permittivity for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0409] For example, it is preferable that the insulators such as insulator 150, insulator 210, insulator 352, and insulator 354 have an insulator with a low relative permittivity. For example, the insulator preferably has silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure that is thermally stable and has a low relative permittivity can be obtained by combining them with a resin. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0410] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for insulators such as insulator 214, insulator 211, insulator 212, and insulator 350, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

[0411] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, silicon oxynitride or silicon nitride can be used.

[0412] As a conductor that can be used for wiring and plugs, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0413] For example, as the conductor 328, conductor 330, conductor 356, conductor 218, conductor 112, etc., a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials can be used in a single layer or in a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Alternatively, it is preferable to form it with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be lowered.

[0414] <Wiring or plug of the layer provided with the oxide semiconductor> In addition, when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and a conductor provided on the insulator having the excess oxygen region.

[0415] For example, in FIG. 23, an insulator 241 may be provided between an insulator 224 having excess oxygen, an insulator 280, and a conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, the insulator 283, and the insulator 284, the insulator 224 and the transistor 200 can be structured to be sealed by the insulator having a barrier property.

[0416] That is, by providing the insulator 241, it is possible to suppress the absorption of the excess oxygen in the insulator 224 and the insulator 280 by the conductor 240. Further, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 240.

[0417] Note that, as the insulator 241, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen may be used. For example, it is preferable to use silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide. In particular, silicon nitride is preferable because of its high blocking property against hydrogen. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0418] Also, as in the above-described embodiment, the transistor 200 is preferably sealed with an insulator 211, an insulator 212, an insulator 214, an insulator 287, an insulator 282, an insulator 283, and an insulator 284. With such a configuration, it is possible to reduce the mixing of hydrogen contained in the insulator 274, the insulator 150, etc. into the insulator 280, etc.

[0419] Here, the conductor 240 penetrates the insulator 284, the insulator 283, and the insulator 282, and the conductor 218 penetrates the insulator 214, the insulator 212, and the insulator 211. However, as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. Thereby, hydrogen mixed inside the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284 can be reduced through the conductor 240 and the conductor 218. In this way, the transistor 200 can be more reliably sealed with the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, the insulator 284, the insulator 241, and the insulator 217, and impurities such as hydrogen contained in the insulator 274 and the like can be reduced from entering from the outside.

[0420] In addition, the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 are preferably formed by a film forming method using a gas in which hydrogen atoms are reduced or removed, as shown in the previous embodiment. Thereby, the hydrogen concentration of the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 can be reduced.

[0421] In this way, the hydrogen concentration of the silicon-based insulating film in the vicinity of the transistor 200 can be reduced, and the hydrogen concentration of the oxide 230 can be reduced.

[0422] <Dicing line> Hereinafter, a dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in chip form by dividing a large-area substrate for each semiconductor element will be described. As a dividing method, for example, first, a groove (dicing line) for dividing the semiconductor element is formed in the substrate, and then cutting is performed at the dicing line to divide (split) the substrate into a plurality of semiconductor devices.

[0423] Here, for example, as shown in FIG. 23, it is preferable to design such that the region where the insulator 283 and the insulator 211 are in contact overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 254, 224, 222, 216, 214, and 212 in the vicinity of the region that becomes the dicing line provided at the outer edge of the memory cell having a plurality of transistors 200.

[0424] That is, in the above-described openings provided in the insulators 282, 280, 254, 224, 222, 216, 214, and 212, the insulator 211 and the insulator 283 are in contact. Further, openings may be provided in the insulators 282, 280, 254, 224, 222, 216, and 214 so that the insulator 212 and the insulator 283 are in contact. For example, at this time, the insulator 212 and the insulator 283 may be formed using the same material and the same method. By providing the insulator 212 and the insulator 283 using the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use silicon nitride.

[0425] With this structure, the transistor 200 can be surrounded by the insulators 211, 212, 214, 287, 282, 283, and 284. Since at least one of the insulators 211, 212, 214, 287, 282, 283, and 284 has a function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into a plurality of chips by dividing the circuit region in which the semiconductor element shown in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side surface direction of the divided substrate and diffusing into the transistor 200.

[0426] In addition, this structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which the channel in the transistor 200 is formed. By this oxygen, the oxygen deficiency in the oxide in which the channel in the transistor 200 is formed can be reduced. As a result, the oxide in which the channel in the transistor 200 is formed can be an oxide semiconductor having stable characteristics with a low defect level density. That is, the variation in the electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved.

[0427] In the memory device shown in FIG. 23, the shape of the capacitance element 100 is a planar type, but the memory device shown in this embodiment is not limited to this. For example, as shown in FIG. 24, the shape of the capacitance element 100 may be a cylinder type. Note that the structure of the memory device shown in FIG. 24 below the insulator 150 is the same as that of the semiconductor device shown in FIG. 23.

[0428] The layer provided with the capacitance element 100 shown in FIG. 24 includes the insulator 150 on the insulator 130, the insulator 142 on the insulator 150, the conductor 115 disposed in the opening formed in the insulator 150 and the insulator 142, the insulator 145 on the conductor 115 and the insulator 142, the conductor 125 on the insulator 145, and the insulator 152 on the conductor 125 and the insulator 145. Here, at least a part of the conductor 115, the insulator 145, and the conductor 125 is disposed in the opening formed in the insulator 150 and the insulator 142.

[0429] The conductor 115 functions as the lower electrode of the capacitor element 100, the conductor 125 functions as the upper electrode of the capacitor element 100, and the insulator 145 functions as the dielectric of the capacitor element 100. The capacitor element 100 is configured such that at the openings of the insulator 150 and the insulator 142, not only the bottom surface but also the side surfaces have the upper electrode and the lower electrode facing each other with the dielectric interposed therebetween, and the capacitance per unit area can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitor element 100 can be. By increasing the capacitance per unit area of the capacitor element 100 in this way, miniaturization or high integration of the semiconductor device can be promoted.

[0430] The insulator 152 may be an insulator that can be used for the insulator 280. Further, the insulator 142 preferably functions as an etching stopper when forming the opening of the insulator 150, and an insulator that can be used for the insulator 214 may be used.

[0431] The shape of the openings formed in the insulator 150 and the insulator 142 as viewed from above may be a quadrilateral, a polygon other than a quadrilateral, a shape in which the corners are curved in a polygon, or a circular shape including an ellipse. Here, in a top view, it is preferable that the area where the opening overlaps with the transistor 200 is larger. By adopting such a configuration, the occupied area of the semiconductor device having the capacitor element 100 and the transistor 200 can be reduced.

[0432] The conductor 115 is disposed in contact with the openings formed in the insulator 142 and the insulator 150. The upper surface of the conductor 115 preferably substantially coincides with the upper surface of the insulator 142. Further, the lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by a film formation method such as an ALD method or a CVD method. For example, a conductor that can be used for the conductor 205 may be used.

[0433] The insulator 145 is arranged to cover the conductor 115 and the insulator 142. For example, it is preferable to form the insulator 145 using the ALD method, the CVD method, or the like. The insulator 145 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc., and can be provided in a laminated or single-layer form. For example, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 145.

[0434] Also, for the insulator 145, it is preferable to use a material with high dielectric breakdown strength such as silicon oxynitride, or a high dielectric constant (high-k) material. Alternatively, a laminated structure of a material with high dielectric breakdown strength and a high dielectric constant (high-k) material may be used.

[0435] Note that examples of high dielectric constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, nitrides containing silicon and hafnium, etc. By using such high-k materials, it is possible to sufficiently ensure the capacitance of the capacitive element 100 even if the insulator 145 is thickened. By thickening the insulator 145, the leakage current generated between the conductor 115 and the conductor 125 can be suppressed.

[0436] On one hand, examples of materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, resins, and the like. For example, an insulating film laminated in the order of silicon nitride formed by ALD method, silicon oxide formed by PEALD method, and silicon nitride formed by ALD method can be used. By using such an insulator with high dielectric strength, the dielectric strength can be improved, and the electrostatic breakdown of the capacitor element 100 can be suppressed.

[0437] The conductor 125 is arranged to fill the openings formed in the insulator 142 and the insulator 150. Also, the conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by using ALD method or CVD method, etc. For example, a conductor that can be used for the conductor 205 can be used.

[0438] Also, the conductor 153 is provided on the insulator 154 and covered by the insulator 156. The conductor 153 can use a conductor that can be used for the conductor 112, and the insulator 156 can use an insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the upper surface of the conductor 140 and functions as a terminal of the capacitor element 100, the transistor 200, or the transistor 300.

[0439] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0440] (Embodiment 3) <Modification example of semiconductor device> In the present embodiment, an example of a semiconductor device, which is an aspect of the present invention, will be described with reference to FIGS. 25A to 25D.

[0441] FIG. 25A shows a top view of a semiconductor device according to an aspect of the present invention. FIGS. 25B to 25D are cross-sectional views of the semiconductor device. Here, FIG. 25B is a cross-sectional view corresponding to the portion indicated by the dashed line A1 - A2 in FIG. 25A. FIG. 25C is a cross-sectional view corresponding to the portion indicated by the dashed line A3 - A4 in FIG. 25A. FIG. 25D is a cross-sectional view corresponding to the portion indicated by the dashed line A5 - A6 in FIG. 25A. In the top view of FIG. 25A, some elements are omitted for clarity of the figure.

[0442] In the semiconductor device shown in FIGS. 25A to 25D, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device shown in the previous embodiment. Also in this item, the materials described in detail in the previous embodiment can be used for the constituent materials of the semiconductor device.

[0443] <<Modification Example 2 of Semiconductor Device>> The semiconductor device shown in FIGS. 25A to 25D is a modification of the semiconductor device shown in FIGS. 4A to 4D. The semiconductor device shown in FIGS. 25A to 25D is different from the semiconductor device shown in FIGS. 4A to 4D in that it does not have the insulator 211 and the insulator 287.

[0444] It is preferable to form at least a part of the structure constituting the transistor 200 shown in FIGS. 25A to 25D and a part of the structure provided around the transistor 200 by a sputtering method. For example, the insulator 212, the insulator 214, the insulator 216, the oxide film that becomes the oxide 230a, the oxide film that becomes the oxide 230b, the oxide films that become the oxides 243a and 243b, the insulator 254, the insulating film that becomes the insulator 280, the oxide film that becomes the oxide 230c, the oxide film that becomes the oxide 230d, the insulator 282, the insulator 283, etc. may be formed by a sputtering method. The film formed by the sputtering method is preferable because the hydrogen concentration in the film is low. Therefore, a transistor 200 with a low hydrogen concentration can be manufactured.

[0445] Note that the insulating films that become the insulator 222, the insulator 224, and the insulator 250, the insulating films that become the insulator 284, the insulator 274, the conductive films that become the conductor 242a and the conductor 242b, and the conductive films that become the conductor 260 (conductor 260a and conductor 260b) may also be formed by a sputtering method.

[0446] With the above configuration, even without providing the insulator 287 formed using a material having a function of capturing and fixing hydrogen, the transistor 200 with a low hydrogen concentration can be manufactured. In addition, processes for reducing the hydrogen concentration in the film, such as heat treatment, can be reduced, and the manufacturing process time of the semiconductor device can be shortened.

[0447] The formation of the insulator 212, the insulator 214, and the insulator 216 is preferably performed continuously without exposing to the atmospheric environment. By forming the film without opening to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering onto the insulator 212, the insulator 214, and the insulator 216, and it is preferable because the interfaces and the vicinity of the interfaces between the insulator 212 and the insulator 214, and between the insulator 214 and the insulator 216 can be kept clean.

[0448] Also, the formation of the oxide film that becomes the oxide 230a, the oxide film that becomes the oxide 230b, and the oxide films that become the oxides 243a and 243b is preferably performed continuously without exposing to the atmospheric environment. By forming the film without opening to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering onto the oxide film that becomes the oxide 230a, the oxide film that becomes the oxide 230b, and the oxide films that become the oxides 243a and 243b, and it is preferable because the interfaces and the vicinity of the interfaces between the oxide film that becomes the oxide 230a and the oxide film that becomes the oxide 230b, and between the oxide film that becomes the oxide 230b and the oxide films that become the oxides 243a and 243b can be kept clean.

[0449] In addition, the formation of the insulating films that become the insulator 254 and the insulator 280 is preferably performed continuously without exposing them to the atmospheric environment. By forming the films without exposing them to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulator 254 and the insulating film that becomes the insulator 280, and it is preferable because the interface and the vicinity of the interface between the insulator 254 and the insulating film that becomes the insulator 280 can be kept clean.

[0450] Note that for continuous film formation, for example, a multi-chamber type film forming apparatus may be used. By performing continuous film formation, it is possible to shorten the manufacturing process time of the semiconductor device, which is preferable. An explanation of the apparatus capable of continuous film formation will be described later.

[0451] Also, for example, as the insulator 212 and the insulator 283, it is preferable to use silicon nitride or the like, and as the insulator 214 and the insulator 282, it is preferable to use aluminum oxide or the like. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 212 and the insulator 214. Also, it is possible to suppress the mixing of impurities such as water and hydrogen from the outside of the transistor 200 into the transistor 200 through the insulator 282 and the insulator 283. Thus, it is preferable to form the transistor 200 in a structure surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0452] With the above configuration, the hydrogen concentration in the transistor 200 can be lowered. For example, the transistor 200 has a hydrogen concentration obtained by SIMS of 20 atoms / cm 3 less than, preferably 19 atoms / cm 3It has a region with a concentration less than [specific value]. Specifically, the region is included in the insulator 224, the oxide 230a, the oxide 230c, etc. That is, at least one of the insulator 224, the oxide 230a, the oxide 230b, and the oxide 230c has a hydrogen concentration obtained by SIMS of less than [specific value], preferably less than [specific value]. 20 atoms / cm 3 Moreover, the region is not limited to the transistor 200 and may be included in a structure provided around the transistor 200. As a structure provided around the transistor 200, for example, there is an insulator 280. 19 atoms / cm 3 In the transistor 200 shown in FIGS. 25A to 25D, the layers 244a and 244b shown in FIGS. 4A to 4D are not illustrated. Depending on the method of removing the layer 244A shown in the previous embodiment, the layers 244a and 244b may not be observed by cross-sectional TEM or the like.

[0453] Note that the layers 244a and 244b may be detectable using EDX. For example, in the side surface of the oxide 230b in the region overlapping with the conductor 242a or the conductor 242b, a region where the concentration of the main component (excluding oxygen) of the layer 244a or the layer 244b obtained by elemental analysis using EDX is equal to or higher than the detection lower limit and 1.0 atomic% or less is detected. Or, the concentration of the main component (excluding oxygen) of the layer 244a or the layer 244b in the side surface of the oxide 230b in the region overlapping with the conductor 242a or the conductor 242b is higher than the concentration of the main component (excluding oxygen) of the layer 244a or the layer 244b on the upper surface of the insulator 224 in the region not overlapping with the oxide 230b.

[0454] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0455] (Embodiment 4)

[0456] In the present embodiment, one form of the semiconductor device will be described with reference to FIGS. 26 to 29. In this embodiment, one form of the semiconductor device will be described with reference to FIGS. 26 to 29.

[0457] [Memory device 2] An example of a semiconductor device (memory device) according to an aspect of the present invention is shown in FIG. 26.

[0458] [Configuration example of memory device]< FIG. 26 is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 shown in FIG. 26 has a capacitor device 292 in addition to the transistor 200 shown in FIGS. 25A to 25D. FIG. 26 corresponds to a cross-sectional view in the channel length direction of the transistor 200.

[0459] In the semiconductor device shown in FIG. 26, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device shown in the previous embodiment. In this item as well, the materials described in detail in the previous embodiment can be used for the constituent materials of the semiconductor device.

[0460] The capacitor device 292 includes a conductor 242b, an insulator 293 provided on the conductor 242b, and a conductor 294 provided on the insulator 293. That is, the capacitor device 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. One of the pair of electrodes of the capacitor device 292, that is, the conductor 242b, can also serve as the source electrode or the drain electrode of the transistor. Therefore, in the manufacturing process of the capacitor device 292, a part of the manufacturing process of the transistor can be shared, so that a highly productive semiconductor device can be obtained. In addition, it is possible to reduce the area where the transistor and the capacitor device are arranged.

[0461] As the conductor 294, for example, a material that can be used for the conductor 240a and the conductor 240b may be used.

[0462] As the insulator 293, for example, a laminated structure of zirconium oxide, aluminum oxide, and zirconium oxide may be used. Further, for example, a material that can be used for the insulator 130 may be used, and it may be provided in a laminated or single-layer form.

[0463] Also, a wiring layer may be provided on the memory device 290. For example, in FIG. 26, on the transistor 200 and the capacitor device 292, the insulator 284 and the insulator 160 are sequentially laminated as an interlayer film. Further, a conductor 166 electrically connected to the transistor 200 is embedded in the insulator 283, the insulator 284, and the insulator 160. Note that the conductor 166 functions as a plug or a wiring.

[0464] A wiring layer may be provided on the insulator 160 and the conductor 166. For example, in FIG. 26, the insulator 162 and the insulator 164 are sequentially laminated. Further, a conductor 168 is formed in the insulator 162 and the insulator 164. The conductor 168 functions as a plug or a wiring.

[0465] The insulator 160 and the insulator 164 preferably have an insulator with a low relative permittivity. For example, as the insulator 160 and the insulator 164, an insulator that can be used for the insulator 352 or the like may be used.

[0466] As the insulator 162, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used. For example, as the insulator 162, an insulator that can be used for the insulator 350 or the like may be used.

[0467] Note that the memory device 290 may have a stacked structure. FIG. 27 shows a cross-sectional view of a configuration in which five memory devices 290 are stacked. As shown in FIG. 27, the memory device 290 is electrically connected to different memory devices 290 via the conductor 240 and the conductor 166.

[0468] As shown in FIG. 27, a plurality of memory devices (memory devices 290_1 to 290_5) may be encapsulated in a comprehensive manner by the insulator 283 and the insulator 212. By encapsulating the plurality of memory devices in a comprehensive manner, the process can be simplified. Note that by forming a film of a part of the structure constituting the transistor 200 and a part of the structure provided around the transistor 200 using a sputtering method, the hydrogen concentration of the transistor 200 can be reduced. Therefore, even when different transistors 200 are fabricated above the transistor 200, the hydrogen concentration of the transistor 200 located below can be kept low. Therefore, when the memory devices 290 are stacked, the hydrogen concentration in the transistor 200 can be reduced by encapsulating the plurality of memory devices in a comprehensive manner without individually encapsulating the memory devices 290.

[0469] Note that the encapsulation of the plurality of memory devices by the insulator 283 and the insulator 212 may be performed in a comprehensive manner including all of the plurality of memory devices, or may be performed in a partial inclusion manner.

[0470] Note that the plurality of memory devices may be arranged side by side in the channel length direction, may be arranged side by side in the channel width direction, or may be arranged in a matrix. Also, depending on the design, they may be arranged without regularity.

[0471] Also, when the same material is used for the insulator 214 and the insulator 282, either the insulator 214 or the insulator 282 may not be provided. Thereby, the number of steps can be reduced.

[0472] As shown in FIG. 27, by stacking a plurality of memory devices (memory devices 290_1 to 290_5), the memory devices can be integrated and arranged without increasing the occupied area of the memory devices. That is, a 3D memory device can be configured.

[0473] In FIG. 27, a configuration in which each layer has one memory device is illustrated, but the present invention is not limited thereto. As shown in the previous <Application Examples of Semiconductor Devices>, the number of memory devices included in each layer may be plural, and the plural memory devices may be arranged in the channel length direction, may be arranged in the channel width direction, or may be arranged in a matrix. Further, depending on the design, they may be arranged without regularity.

[0474] <Modification Example of Memory Device> Hereinafter, with reference to FIGS. 28A, 28B, and 29, an example of a semiconductor device having a transistor 200 and a capacitor device 292 according to one aspect of the present invention, which is different from that shown in the previous <Configuration Example of Memory Device>, will be described. In the semiconductor devices shown in FIGS. 28A, 28B, and 29, the same reference numerals are given to the structures having the same functions as the structures constituting the semiconductor devices shown in the previous embodiments and FIG. 26. In this section, as the constituent materials of the transistor 200 and the capacitor device 292, the materials described in detail in the previous embodiments and the previous <Configuration Example of Memory Device> can be used.

[0475] <<Modification Example 1 of Memory Device>> Hereinafter, an example of a semiconductor device having a memory device 600 will be described with reference to FIGS. 28A and 28B. The memory device 600 includes a transistor 200a, a transistor 200b, a capacitor device 292a, and a capacitor device 292b.

[0476] FIG. 28A is a top view of a semiconductor device having a memory device 600. FIG. 28B is a cross-sectional view of a portion indicated by a one-dot chain line A1 - A2 in FIG. 28A, and is also a cross-sectional view in the channel length direction of the transistor 200a and the transistor 200b. In the top view of FIG. 28A, some elements are omitted for clarity of the drawing.

[0477] As shown in FIG. 28B, the memory device 600 has a line-symmetric configuration with the one-dot chain line of A3 - A4 as the axis of symmetry. One of the source electrode or the drain electrode of the transistor 200a and one of the source electrode or the drain electrode of the transistor 200b are configured such that the conductor 242c serves both functions. Also, the conductor that is electrically connected to the transistor 200a and functions as a plug, and the conductor that is electrically connected to the transistor 200b and functions as a plug are configured such that the conductor 240c serves both functions. In this way, by configuring the connection of the two transistors, the two capacitive devices, and the wiring and the plug as described above, a semiconductor device capable of miniaturization or high integration can be provided.

[0478] Regarding the respective configurations and effects of the transistor 200a, the transistor 200b, the capacitive device 292a, and the capacitive device 292b, reference can be made to the configuration examples of the semiconductor devices shown in FIGS. 25A to 25D and FIG. 26.

[0479] <<Modification Example 2 of Memory Device>> FIG. 29 shows an example in which the memory unit 470 has a transistor layer 413 having a transistor 200T and four memory device layers (memory device layers 415_1 to 415_4).

[0480] The memory device layers 415_1 to 415_4 each have a plurality of memory devices 420. For the memory device 420, for example, the memory device 290 shown in FIG. 26, or the memory device 600 shown in FIGS. 28A and 28B can be used.

[0481] The memory device 420 is electrically connected to the memory devices 420 included in different memory device layers and the transistor 200T included in the transistor layer 413 via the conductor 424 and the conductor 166.

[0482] The memory unit 470 is encapsulated by insulators 212, 214, 282, and 283 (hereinafter referred to as the encapsulation structure for convenience). An insulator 274 is provided around the insulator 283. Also, a conductor 440 is provided on the insulators 274, 283, and 212 and is electrically connected to the element layer 411.

[0483] Note that the insulators 212 and 283 are preferably made of a material having a high hydrogen blocking function. Also, the insulators 214 and 282 are preferably made of a material having a function of capturing or fixing hydrogen.

[0484] For example, materials having a high hydrogen blocking function include silicon nitride or silicon oxynitride. Also, materials having a function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0485] Note that there is no particular limitation on the crystal structure of the materials used for the insulators 212, 214, 282, and 283, but an amorphous or crystalline structure may be used. For example, it is preferable to use an amorphous aluminum oxide film as a material having a function of capturing or fixing hydrogen. Amorphous aluminum oxide may capture and fix a larger amount of hydrogen than highly crystalline aluminum oxide.

[0486] Also, an insulator 280 is provided inside the encapsulation structure. The insulator 280 has a function of releasing oxygen by heating. Or, the insulator 280 has an excess oxygen region.

[0487] Here, the following model can be considered for the excess oxygen in the insulator 280 with respect to the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.

[0488] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. In the diffusion of the hydrogen, it is presumed that excess oxygen in the insulator 280 reacts with the hydrogen in the oxide semiconductor to form an OH bond and diffuses through the insulator 280. When the hydrogen atom having the OH bond reaches a material (typically, the insulator 282) having a function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom bonded to an atom (e.g., a metal atom, etc.) in the insulator 282 and is captured or fixed in the insulator 282. On the other hand, the oxygen atom having the OH bond is presumed to remain in the insulator 280 as excess oxygen. That is, in the diffusion of the hydrogen, it is highly probable that the excess oxygen in the insulator 280 plays a bridging role.

[0489] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0490] As an example, an insulator 280 having excess oxygen is formed on the oxide semiconductor, and then the insulator 282 is formed. After that, it is preferable to perform a heat treatment. Specifically, the heat treatment is performed at a temperature of 350°C or higher, preferably 400°C or higher, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.

[0491] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280 and the insulator 282. That is, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

[0492] After the above heat treatment, an insulator 283 is formed. Since the insulator 283 has a function of having a high blocking property against hydrogen, it is possible to suppress the hydrogen diffused outward or the hydrogen existing outside from entering inside, specifically, into the oxide semiconductor or the insulator 280 side.

[0493] Note that, regarding the above heat treatment, although an example of the configuration in which the heat treatment is performed after forming the insulator 282 has been illustrated, the present invention is not limited thereto. For example, the above heat treatment may be performed after forming the transistor layer 413, or after forming the memory device layers 415_1 to 415_3. Further, when hydrogen is diffused outward by the above heat treatment, hydrogen is diffused above or in the lateral direction of the transistor layer 413. Similarly, when the heat treatment is performed after forming the memory device layers 415_1 to 415_3, hydrogen is diffused above or in the lateral direction.

[0494] Note that, by adopting the above manufacturing process, the insulator 212 and the insulator 283 are adhered to each other to form the above-described sealing structure.

[0495] As described above, by adopting the above structure and the above manufacturing process, a semiconductor device using an oxide semiconductor with a reduced hydrogen concentration can be provided. For example, the oxide 230b or the oxide 230c included in the transistor 200T or the memory device 420 has a region where the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 and preferably less than 1×10 19 atoms / cm 3 .

[0496] As described above, a semiconductor device with good reliability can be provided. Further, according to an aspect of the present invention, a semiconductor device having good electrical characteristics can be provided.

[0497] The configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0498] (Embodiment 5) In the present embodiment, an apparatus that can be used when manufacturing a semiconductor device according to an aspect of the present invention will be described with reference to FIG. 30.

[0499] When manufacturing a semiconductor device according to an aspect of the present invention, it is preferable to use a so-called multi-chamber device having a plurality of processing chambers in which different film types can be continuously formed. In each processing chamber, film formation processes such as sputtering, CVD, and ALD can be performed respectively. For example, when one processing chamber is used as a processing chamber for performing sputtering (also referred to as a sputtering chamber), a gas supply device, a gas purification device connected to the gas supply device, a vacuum pump, a target, etc. can be connected to the sputtering chamber.

[0500] In addition, in each processing chamber, cleaning processing, plasma processing, reverse sputtering processing, etching processing, ashing processing, heat treatment, etc. may be performed. By appropriately performing different processes in each processing chamber, insulating films, conductive films, and semiconductor films can be formed without opening to the atmosphere.

[0501] Typical examples of the semiconductor film used in an aspect of the present invention include oxide semiconductor films. In particular, an oxide semiconductor film with a low impurity concentration and a low defect level density (less oxygen deficiency) can be used to fabricate a transistor with excellent electrical characteristics. Here, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0502] An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier concentration can be lowered. Therefore, a transistor in which a channel formation region is formed in the oxide semiconductor film is less likely to have an electrical characteristic (also referred to as normally on) in which the threshold voltage is negative. In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic may have a low trap level density because of its low defect level density. Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has an extremely small off-current, and even for an element with a channel width of 1×10 6 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10-13 The following characteristics of A can be obtained.

[0503] Typical examples of impurities in the oxide semiconductor film include water and hydrogen. In this specification and the like, reducing or removing water and hydrogen from the oxide semiconductor film may be referred to as dehydration or dehydrogenation. Adding oxygen to the oxide semiconductor film may be referred to as oxygen addition, and a state in which oxygen is added and has an excess of oxygen compared to the stoichiometric composition may be referred to as an excess oxygen state.

[0504] Here, by continuously forming films of different film types without exposing to the atmosphere, an oxide semiconductor film with a reduced concentration of impurities (especially hydrogen and water) and substantially high-purity intrinsic properties can be formed, which is composed of an oxide semiconductor, an insulator or conductor located under the oxide semiconductor, and an insulator or conductor located above the oxide semiconductor.

[0505] First, the details of a configuration example of an apparatus that can be used when manufacturing a semiconductor device according to an aspect of the present invention will be described with reference to FIG. 30. By using the apparatus shown in FIG. 30, a semiconductor film, an insulator or conductor located under the semiconductor film, and an insulating film or conductive film located above the semiconductor film can be continuously formed. Therefore, impurities (especially hydrogen and water) that can enter the semiconductor film can be suppressed. Further, the apparatus shown in FIG. 30 is not limited to the continuous film formation of a stacked structure having a semiconductor film, but can also perform continuous film formation of insulating films made of different materials, continuous film formation of conductive films made of different materials, continuous film formation of a stacked structure of an insulating film and a conductive film, and the like.

[0506] FIG. 30 schematically shows a top view of a single-wafer multi-chamber apparatus 4000.

[0507] The apparatus 4000 includes an atmospheric-side substrate supply chamber 4010, an atmospheric-side substrate transfer chamber 4012 for transferring the substrate from the atmospheric-side substrate supply chamber 4010, a load lock chamber 4020a for loading the substrate and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 4020b for unloading the substrate and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 4029 for transferring the substrate in a vacuum, a transfer chamber 4039, transfer chambers 4030a and 4030b connecting the transfer chamber 4029 and the transfer chamber 4039, and processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e for film formation or heating.

[0508] Note that the plurality of processing chambers can each perform different processes in parallel. Therefore, a laminated structure of different film types can be easily fabricated. Note that the parallel processing can be performed at most the number of processing chambers. For example, the apparatus 4000 shown in FIG. 30 is an apparatus having seven processing chambers. Therefore, using one apparatus (also referred to as in-situ in this specification), seven film formation processes can be continuously performed without atmospheric exposure.

[0509] On the other hand, in the laminated structure, the number of laminations that can be fabricated without atmospheric exposure does not necessarily equal the number of processing chambers. For example, in the required laminated structure, when there are a plurality of layers of the same material, since the layer can be provided in one processing chamber, a laminated structure with a larger number of laminations than the number of installed processing chambers can be fabricated.

[0510] Also, the atmospheric-side substrate supply chamber 4010 includes a cassette port 4014 for accommodating the substrate and an alignment port 4016 for aligning the substrate. Note that the cassette port 4014 may have a plurality (for example, three in FIG. 30).

[0511] In addition, the atmospheric-side substrate transfer chamber 4012 is connected to the load lock chamber 4020a and the unload lock chamber 4020b. The transfer chamber 4029 is connected to the load lock chamber 4020a, the unload lock chamber 4020b, the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4024a, and the processing chamber 4024b. The transfer chamber 4030a and the transfer chamber 4030b are connected to the transfer chamber 4029 and the transfer chamber 4039. The transfer chamber 4039 is connected to the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4034a, the processing chamber 4034b, the processing chamber 4034c, the processing chamber 4034d, and the processing chamber 4034e.

[0512] Note that a gate valve 4028 or a gate valve 4038 is provided at the connection part of each chamber, and except for the atmospheric-side substrate supply chamber 4010 and the atmospheric-side substrate transfer chamber 4012, each chamber can be independently maintained in a vacuum state. In addition, the atmospheric-side substrate transfer chamber 4012 has a transfer robot 4018. The transfer chamber 4029 has a transfer robot 4026, and the transfer chamber 4039 has a transfer robot 4036. The transfer robot 4018, the transfer robot 4026, and the transfer robot 4036 have a plurality of movable parts and an arm for holding a substrate, and can transfer the substrate to each chamber.

[0513] Note that the number of transfer chambers, processing chambers, load lock chambers, unload lock chambers, and transfer chambers is not limited to the above numbers, and an appropriate optimal number can be provided according to the installation space and process conditions.

[0514] In particular, when there are a plurality of transfer chambers, it is preferable to have two or more transfer chambers between one transfer chamber and another transfer chamber. For example, as shown in FIG. 30, when having the transfer chamber 4029 and the transfer chamber 4039, it is preferable that the transfer chamber 4030a and the transfer chamber 4030b are arranged in parallel between the transfer chamber 4029 and the transfer chamber 4039.

[0515] By arranging the transfer chambers 4030a and 4030b in parallel, for example, the process of the transfer robot 4026 loading a substrate into the transfer chamber 4030a and the process of the transfer robot 4036 loading a substrate into the transfer chamber 4030b can be performed simultaneously. Also, the process of the transfer robot 4026 unloading a substrate from the transfer chamber 4030b and the process of the transfer robot 4036 unloading a substrate from the transfer chamber 4030a can be performed simultaneously. That is, by driving a plurality of transfer robots simultaneously, the production efficiency is improved.

[0516] Also, in FIG. 30, an example is shown where one transfer chamber has one transfer robot and is connected to a plurality of processing chambers, but it is not limited to this structure. One transfer chamber may have a plurality of transfer robots.

[0517] Also, one or both of the transfer chambers 4029 and 4039 are connected to a vacuum pump and a cryopump via valves. Therefore, the transfer chambers 4029 and 4039 are evacuated from atmospheric pressure to a low vacuum or medium vacuum (from several 100 Pa to about 0.1 Pa) using a vacuum pump, and then the valve is switched, and they can be evacuated from the medium vacuum to a high vacuum or ultra-high vacuum (from 0.1 Pa to 1×10 -7 Pa or so) using a cryopump.

[0518] Also, for example, two or more cryopumps may be connected in parallel to one transfer chamber. By having a plurality of cryopumps, it becomes possible to evacuate using other cryopumps even when one cryopump is in the regeneration process. Note that regeneration is a process of releasing the molecules (or atoms) trapped in the cryopump. Since the evacuation ability of the cryopump decreases when too many molecules (or atoms) are trapped, it is advisable to perform regeneration regularly.

[0519] The processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e can each perform different processes in parallel. That is, for each processing chamber, film formation processes such as sputtering, CVD, MBE, PLD, ALD, heat treatment, or plasma treatment can be performed on the installed substrate. Further, in the processing chamber, a film formation process may be performed after heat treatment or plasma treatment.

[0520] By having a plurality of processing chambers, the apparatus 4000 can transport the substrate without exposing it to the atmosphere between processes, thus suppressing the adsorption of impurities to the substrate. Further, since different film formation processes, heat treatment, or plasma treatment can be performed for each processing chamber, the order of film formation, heat treatment, etc. can be freely constructed.

[0521] Each processing chamber may be connected to a vacuum pump via a valve. As the vacuum pump, for example, a dry pump, a mechanical booster pump, etc. can be used.

[0522] Each processing chamber may also be connected to a power source capable of generating plasma. As the power source, a DC power source, an AC power source, a high-frequency (RF, microwave, etc.) power source may be provided. Further, a pulse generator may be connected to the DC power source.

[0523] The processing chamber may also be connected to a gas purification device via a gas supply device. Note that the gas supply device and the gas purification device may be provided in the number corresponding to the number of gas species.

[0524] For example, when performing a film formation process by sputtering in the processing chamber, the processing chamber may include a target, a backing plate connected to the target, a cathode disposed opposite the target via the backing plate, a sputter shield, a substrate stage, etc. Further, for example, the substrate stage may include a substrate holding mechanism for holding the substrate, a back heater for heating the substrate from the back surface, etc.

[0525] Note that the substrate stage is held in a state approximately perpendicular to the floor surface during film formation, and in a state approximately horizontal to the floor surface during substrate transfer. Here, by making the substrate stage approximately perpendicular to the floor surface, the probability of dust or particles that may be mixed in during film formation adhering to the substrate can be suppressed more than when it is held in a horizontal state. However, if the substrate stage is held perpendicular (90°) to the floor surface, there is a possibility that the substrate may fall. Therefore, the angle of the substrate stage with respect to the floor surface is preferably 80° or more and less than 90°.

[0526] Note that the configuration of the substrate stage is not limited to the above configuration. For example, the substrate stage may be configured to be approximately horizontal with respect to the floor surface. In the case of such a configuration, the target may be disposed below the substrate stage, and the substrate may be disposed between the target and the substrate stage. Further, the substrate stage may be provided with a jig for fixing the substrate so that the substrate does not fall, or a mechanism for fixing the substrate.

[0527] Further, by providing an anti-deposition plate in the processing chamber, it is possible to suppress the deposition of particles sputtered from the target in an unnecessary region. Further, it is desirable to process the anti-deposition plate so that the accumulated sputtering particles do not peel off. For example, a blasting process for increasing the surface roughness, or unevenness may be provided on the surface of the anti-deposition plate.

[0528] The backing plate has a function of holding the target, and the cathode has a function of applying a voltage (for example, a negative voltage) to the target.

[0529] Note that a conductor, an insulator, or a semiconductor can be used for the target. For example, when the target is an oxide semiconductor such as a metal oxide, an oxide semiconductor film can be formed in the processing chamber. Further, even when the target is a metal oxide, an oxynitride semiconductor film can also be formed by using nitrogen gas as a film-forming gas.

[0530] In addition, each processing chamber may be connected to a gas supply device via a gas heating mechanism. The gas heating mechanism is connected to a gas purification device via the gas supply device. As the gas introduced into the processing chamber, a gas with a dew point of -80°C or lower, preferably -100°C or lower, and more preferably -120°C or lower can be used. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) can be used. Further, the gas introduced into the processing chamber can be heated to 40°C or higher and 400°C or lower by the gas heating mechanism. Note that the gas heating mechanism, the gas supply device, and the gas purification device may be provided in the number corresponding to the number of gas types.

[0531] In addition, each processing chamber may be connected to a turbo molecular pump and a vacuum pump via a valve. Further, a cryotrap may be provided in each processing chamber.

[0532] Note that the cryotrap is a mechanism capable of adsorbing molecules (or atoms) with a relatively high melting point such as water. The turbo molecular pump stably exhausts large-sized molecules (or atoms) and has a low maintenance frequency, so it is excellent in productivity, but has a low exhaust capacity for hydrogen and water. Therefore, a cryotrap can be used to enhance the exhaust capacity for water and the like. The temperature of the refrigerator of the cryotrap is set to 100K or lower, preferably 80K or lower. Further, when the cryotrap has a plurality of refrigerators, it is preferable to change the temperature for each refrigerator because it becomes possible to exhaust efficiently. For example, the temperature of the first-stage refrigerator may be set to 100K or lower, and the temperature of the second-stage refrigerator may be set to 20K or lower.

[0533] Note that the exhaust method of the processing chamber is not limited to this, and it may have the same configuration as the exhaust method (the exhaust method of the cryopump and the vacuum pump) shown in the connected transfer chamber. Note that the exhaust method of the transfer chamber may have the same configuration (the exhaust method of the turbo molecular pump and the vacuum pump) as that of the processing chamber.

[0534] In particular, as an exhaust method for a processing chamber for forming an oxide semiconductor film, a configuration combining a vacuum pump and a cryo-trap may be used. As an exhaust method provided in a processing chamber for forming an oxide semiconductor film, it preferably has a function capable of adsorbing at least water molecules.

[0535] In addition, in the processing chamber for forming an oxide semiconductor film, the partial pressure of hydrogen molecules is 1×10 -2 Pa or less, and the partial pressure of water molecules is preferably 1×10 -4 Pa or less. Also, the pressure in the standby state of the processing chamber for forming an oxide semiconductor film is 8.0×10 -5 Pa or less, preferably 5.0×10 -5 Pa or less, and more preferably 1.0×10 -5 Pa or less. Further, the values of the partial pressure of hydrogen molecules and the partial pressure of water molecules are the values in both the standby state and the film-forming state (plasma discharge state) of the sputtering chamber.

[0536] Note that the total pressure and partial pressure of the processing chamber can be measured using a mass spectrometer. For example, the quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

[0537] By setting the partial pressure of hydrogen molecules, the partial pressure of water molecules, and the pressure in the standby state of the processing chamber within the above ranges, the concentration of impurities in the formed oxide semiconductor film can be reduced.

[0538] In particular, by using each processing chamber for film formation by sputtering, a part of the structure of the transistor 200 shown in the previous embodiment can be fabricated by a laminated structure formed by in-situ continuous film formation.

[0539] In the method for manufacturing the transistor 200, the insulator 212, the insulator 214, and the insulator 216 are continuously formed by using the apparatus 4000. Also, the oxide film 230A, the oxide film 230B, and the oxide film 243A are continuously formed by using the apparatus 4000. Further, the insulator 254 and the insulating film that becomes the insulator 280 are continuously formed by using the apparatus 4000.

[0540] That is, the insulator 212, the insulator 214, and the insulator 216 can be continuously formed without exposing them to the atmosphere. Also, the oxide film 230A, the oxide film 230B, and the oxide film 243A can be continuously formed without exposing them to the atmosphere. Further, the insulator 254 and the insulating film that becomes the insulator 280 can be continuously formed without exposing them to the atmosphere.

[0541] With the above configuration, it becomes possible to form a laminated film from which impurities (typically, water, hydrogen, etc.) are thoroughly removed. Also, since each interface of the above laminated film is not exposed to the atmosphere, the impurity concentration is reduced.

[0542] Also, for example, when performing heat treatment in a processing chamber, the processing chamber may include a plurality of heating stages capable of storing substrates. Note that the heating stages may have a multi-stage configuration. By increasing the number of stages of the heating stages, a plurality of substrates can be heat-treated simultaneously, so that productivity can be improved.

[0543] As a heating mechanism that can be used in the processing chamber, for example, a heating mechanism that heats using a resistance heating element or the like may be used. Alternatively, it may be a heating mechanism that heats by heat conduction or heat radiation from a medium such as heated gas. For example, RTA (Rapid Thermal Anneal) such as GRTA (Gas Rapid Thermal Anneal) and LRTA (Lamp Rapid Thermal Anneal) can be used. LRTA heats the object to be processed by the radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. GRTA performs heat treatment using high-temperature gas. As the gas, an inert gas is used.

[0544] The load lock chamber 4020a may be provided with a substrate transfer stage, a back heater for heating the substrate from the back surface, and the like. The load lock chamber 4020a raises the pressure from a reduced pressure state to atmospheric pressure, and when the pressure in the load lock chamber 4020a reaches atmospheric pressure, the substrate transfer stage receives the substrate from the transfer robot 4018 provided in the atmospheric-side substrate transfer chamber 4012. Then, after evacuating the load lock chamber 4020a to a reduced pressure state, the transfer robot 4026 provided in the transfer chamber 4029 receives the substrate from the substrate transfer stage.

[0545] In addition, the load lock chamber 4020a is connected to a vacuum pump and a cryopump via valves. The unload lock chamber 4020b may have the same configuration as the load lock chamber 4020a.

[0546] Since the atmospheric-side substrate transfer chamber 4012 has a transfer robot 4018, the transfer robot 4018 can transfer substrates between the cassette port 4014 and the load lock chamber 4020a. Also, a mechanism for suppressing the entry of dust or particles such as a HEPA filter (High Efficiency Particulate Air Filter) may be provided above the atmospheric-side substrate transfer chamber 4012 and the atmospheric-side substrate supply chamber 4010. Further, the cassette port 4014 can store a plurality of substrates.

[0547] By using the above-described apparatus 4000 to continuously form an insulating film, a semiconductor film, and a conductive film without exposing to the atmosphere, the entry of impurities into the semiconductor film can be preferably suppressed.

[0548] As described above, by using the apparatus according to one aspect of the present invention, a laminated structure having a semiconductor film can be fabricated by continuous film formation. Therefore, impurities such as hydrogen and water incorporated into the semiconductor film can be suppressed, and a semiconductor film with a low defect level density can be fabricated.

[0549] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0550] (Embodiment 6) In this embodiment, with reference to FIGS. 31A, 31B, 32A to 32H, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a storage device (hereinafter sometimes referred to as an OS memory device) to which a capacitive element is applied according to one aspect of the present invention will be described. The OS memory device is a storage device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.

[0551] <Configuration Example of Storage Device> FIG. 31A shows an example of the configuration of an OS memory device. The storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0552] The column circuit 1430 has, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. The wiring is the wiring connected to the memory cells included in the memory cell array 1470, which will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 has, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0553] A low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the storage device 1400. Also, a ...

Claims

【Claim 1】 a first insulator; a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a first layer and a second layer in contact with a side surface of the first oxide; a second insulator on the first insulator, on the first layer, on the second layer, on the first conductor, and on the second conductor; a third insulator on the second insulator; a second oxide disposed between the first conductor and the second conductor and disposed on the first oxide; a fourth insulator on the second oxide; a third conductor on the fourth insulator, and having each of the first layer and the second layer has a metal included in the first conductor and the second conductor; a semiconductor device, wherein the first insulator in a region in contact with the second insulator has a region where the concentration of the metal is lower than that of the first layer or the second layer.

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