Semiconductor device

Abstract

To provide a semiconductor device that is improved in reliability.SOLUTION: A semiconductor device 100 includes: a semiconductor layer 101 including a first principal surface 101a and a second principal surface 101b facing away from the first principal surface 101a; a first electrode layer 102 formed on the first principal surface 101a; a second electrode layer 103 formed on the second principal surface 101b; an insulating film 104 covering an end portion of the first electrode layer 102; a plating layer 105 covering at least a portion other than the end portion of the first electrode layer 102; and a mold layer 106 covering the insulating film 104.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This application corresponds to Japanese Patent Application No. 2020-082728 filed with the Japan Patent Office on May 8, 2020, and the entire disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a technique related to a vertical semiconductor device using a SiC semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment of the present invention provides a semiconductor device with improved reliability.

Means for Solving the Problems

[0005] One embodiment of the present invention provides a semiconductor device including a semiconductor layer having a first main surface and a second main surface facing away from the first main surface, a first electrode layer formed on the first main surface, a second electrode layer formed on the second main surface, an insulating film covering an end portion of the first electrode layer, a plating layer covering at least a part of the first electrode layer other than the end portion, and a mold layer covering the insulating film.

[0006] One embodiment of the present invention provides a method of manufacturing a semiconductor device, including: forming a first electrode layer on a first main surface of a semiconductor layer; forming a second electrode layer on a second main surface of the semiconductor layer, the second main surface being opposite to the first main surface; forming an insulating film covering an end portion of the first electrode layer; forming a plating layer covering at least a part of the first electrode layer other than the end portion; and forming a mold layer covering the insulating film.

[0007] One embodiment of the present invention provides a semiconductor device, including: a semiconductor layer having a main surface; a main surface electrode disposed on the main surface; an insulating film partially covering the main surface electrode so as to expose a part of the main surface electrode; a mold layer covering the insulating film so as to expose the main surface electrode; and a pad electrode disposed on the main surface electrode so as to be electrically connected to the main surface electrode.

[0008] One embodiment of the present invention provides a semiconductor device, including: a semiconductor layer having a main surface; a main surface electrode disposed on the main surface; a photosensitive resin layer covering a peripheral portion of the main surface electrode so as to expose an inner portion of the main surface electrode; a thermosetting resin layer covering the peripheral portion of the main surface electrode with the photosensitive resin layer interposed therebetween so as to expose the inner portion of the main surface electrode; and a pad electrode disposed on the inner portion of the main surface electrode.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15A

Figure 15B

Figure 15C

Figure 16A

Figure 16B

Figure 16C

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. The embodiments described below are all examples showing comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement positions of the components, connection forms of the components, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present invention. Among the components in the following embodiments, the components not described in the independent claims are described as optional components.

[0011] Each of the accompanying drawings is a schematic diagram and is not necessarily strictly illustrated. Therefore, for example, scales and the like in the accompanying drawings do not necessarily match. In the accompanying drawings, substantially the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted or simplified.

[0012] In this specification, terms indicating the relationship between elements such as vertical and horizontal, terms indicating the shape of elements such as rectangular, and numerical ranges are not expressions representing only strict meanings, but are expressions meaning including substantially equivalent ranges.

[0013] In addition, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by the relative positional relationship based on the stacking order in the stacked structure. Specifically, in this specification, one main surface side of the semiconductor layer is described as the upper side (above), and the other main surface side is described as the lower side (below). When the semiconductor device (vertical transistor) is actually used, the first main surface side may be the lower side (below), and the second main surface side may be the upper side (above). Alternatively, the semiconductor device (vertical transistor) may be used in a posture where the first main surface and the second main surface are inclined or orthogonal to the horizontal plane.

[0014] In addition, the terms "upper" and "lower" are applicable not only when the two components are spaced apart from each other with another component intervening between them, but also when the two components are arranged in close contact with each other.

[0015] Hereinafter, the configuration of the semiconductor device according to the first embodiment will be described. FIG. 1 is a plan view of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 (a cross-sectional view taken along line II-II in FIG. 1).

[0016] The semiconductor device 100 shown in FIG. 1 is a semiconductor chip that functions as a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). The semiconductor device 100 is, for example, a power semiconductor device used for power supply and control. Specifically, the semiconductor device 100 includes a semiconductor layer 101, a first electrode layer 102, a second electrode layer 103, an insulating film 104, a plating layer 105, and a mold layer 106.

[0017] The semiconductor layer 101 is a SiC semiconductor layer containing a SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. The semiconductor layer 101 is formed in a plate shape with a rectangular shape in plan view. In this specification, plan view means viewing from a direction perpendicular to the first main surface 101a or the second main surface 101b (viewing from the z-axis direction in the figure). The length of one side of the semiconductor layer 101 is, for example, 1 mm or more and 10 mm or less, but may be 2 mm or more and 5 mm or less.

[0018] The semiconductor layer 101 has a first main surface 101a and a second main surface 101b facing away from the first main surface 101a. The semiconductor layer 101 also includes a semiconductor substrate 101c constituting the second main surface 101b and an epitaxial layer 101d located on the semiconductor substrate 101c. The epitaxial layer 101d is obtained by epitaxial growth of the semiconductor substrate 101c.

[0019] The thickness of the semiconductor substrate 101c is, for example, 100 μm or more and 350 μm or less. The thickness of the epitaxial layer 101d is, for example, 5 μm or more and 20 μm or less. The thickness t1 of the semiconductor layer 101 (that is, the total thickness of the semiconductor substrate 101c and the epitaxial layer 101d) is preferably 200 μm or less. The semiconductor layer 101 is not limited to a SiC semiconductor layer, and may be a semiconductor layer made of other wide bandgap semiconductors such as GaN, or may be a Si semiconductor layer.

[0020] The first electrode layer 102 is formed on the first main surface 101a. The first electrode layer 102 may be referred to as the "first main surface electrode". The first electrode layer 102 includes a first electrode layer 102g that functions as a gate electrode and a first electrode layer 102s that functions as a source electrode. The first electrode layer 102 is formed of, for example, aluminum. The first electrode layer 102 may be formed of other materials such as titanium, nickel, copper, silver, gold, titanium nitride, and tungsten.

[0021] The first electrode layer 102s may have an area of 50% or more of the area of the semiconductor substrate 101c (the first main surface 101a) in plan view. Preferably, the first electrode layer 102s may have an area of 70% or more of the area of the semiconductor substrate 101c (the first main surface 101a) in plan view. On the other hand, the first electrode layer 102g may have an area of 20% or less of the area of the semiconductor substrate 101c (the first main surface 101a) in plan view. Preferably, the first electrode layer 102g may have an area of 10% or less of the area of the semiconductor substrate 101c (the first main surface 101a) in plan view.

[0022] The first electrode layer 102s is disposed in a region including the center position of the semiconductor substrate 101c in plan view. The first electrode layer 102g is disposed in a region avoiding the first electrode layer 102s. However, the first electrode layer 102g may be disposed in a region including the center position of the semiconductor substrate 101c in plan view, and the first electrode layer 102s may be disposed so as to surround the periphery of the first electrode layer 102g.

[0023] The second electrode layer 103 is formed on the second main surface 101b. The second electrode layer 103 may be referred to as the "second main surface electrode". The second electrode layer 103 functions as a drain electrode. The second electrode layer 103 is formed of, for example, a laminated film of titanium, nickel, and gold. The second electrode layer 103 may be formed of other materials such as aluminum, copper, silver, titanium nitride, and tungsten.

[0024] The insulating film 104 covers the entire circumference of the outer peripheral portion of the first electrode layer 102 (that is, both end portions in the x-axis direction and both end portions in the y-axis direction). The outer peripheral portion of the first electrode layer 102 may be referred to as the peripheral edge portion of the first electrode layer 102. The insulating film 104 includes a first portion 104a and a second portion 104b. The first portion 104a rides on the first electrode layer 102. More specifically, the first portion 104a rides on the peripheral edge portion of the first electrode layer 102. The second portion 104b is located outside the first portion 104a and covers a region other than the first electrode layer 102. That is, the second portion 104b does not ride on the first electrode layer 102.

[0025] The first part 104a further includes an inner end portion 104a1 and a flat portion 104a2. The inner end portion 104a1 is the end portion of the portion of the first part 104a located inside the semiconductor layer 101 in a plan view. The inner end portion 104a1 is inclined obliquely downward toward the inner part of the first electrode layer 102 in a cross-sectional view. The flat portion 104a2 is located outside the inner end portion 104a1 (on the peripheral side of the semiconductor layer 101) and has a substantially uniform thickness.

[0026] The insulating film 104 is, for example, an organic film containing a photosensitive resin. The insulating film 104 is formed of, for example, polyimide, PBO (polybenzoxazole), or the like. The insulating film 104 may be an inorganic film formed of silicon nitride (SiN), silicon oxide (SiO2), or the like. The insulating film 104 may have a single-layer structure or a laminated structure in which a plurality of types of materials are laminated. When the insulating film 104 has a laminated structure, the insulating film 104 may include both an organic film and an inorganic film. In this case, it is preferable that the insulating film 104 includes an inorganic film and an organic film laminated in this order from the first main surface 101a side. The thickness of the insulating film 104 is at most about 10 μm.

[0027] The plating layer 105 is a metal layer that covers at least a part of the first electrode layer 102. The plating layer 105 covers at least a part other than the end portion of the first electrode layer 102 (that is, the portion covered by the insulating film 104). As shown in FIG. 1, in a plan view, the plating layer 105 is surrounded by the mold layer 106. The plating layer 105 includes the plating layer 105 on the first electrode layer 102g side (the first plating layer) and the plating layer 105 on the first electrode layer 102s side (the second plating layer).

[0028] The plating layer 105 formed on the first electrode layer 102g functions as a gate pad (pad electrode) having a rectangular shape in plan view. The plating layer 105 formed on the first electrode layer 102s functions as a source pad (pad electrode). A pad is a portion to which a bonding wire is bonded when the semiconductor device 100 is packaged. Further, the plating layer 105 also functions as a support member for the mold layer 106.

[0029] The plating layer 105 is formed of, for example, a material different from that of the first electrode layer 102. The plating layer 105 is formed of, for example, copper or a copper alloy having copper as a main component. The plating layer 105 may be formed of other metal materials. The thickness t2 of the plating layer 105 is larger than the thickness of the insulating film 104. More specifically, the thickness t2 of the plating layer 105 is larger than the maximum thickness of the insulating film 104 located on the first electrode layer 102. Thereby, the topmost portion of the plating layer 105 is higher than the topmost portion of the insulating film 104. The thickness t2 of the plating layer 105 is, for example, 30 μm or more and 100 μm or less. The thickness t2 of the plating layer 105 may be 100 μm or more and 200 μm or less.

[0030] The side surface 105a of the plating layer 105 extends vertically or substantially vertically. The side surface 105a does not necessarily extend linearly in a cross-sectional view and may include curves or irregularities. The side surface 105a is located in a region where both the first electrode layer 102 and the insulating film 104 overlap each other. More specifically, the side surface 105a is located on the flat portion 104a2 of the insulating film 104. That is, the plating layer 105 covers the inner end portion 104a1 and the flat portion 104a2 of the first portion 104a. By positioning the side surface 105a on the flat portion 104a2, the plating layer 105 can be formed stably as compared with the case where the side surface 105a is positioned on the inner end portion 104a1 having a relatively large thickness variation.

[0031] The mold layer 106 is a resin layer that covers at least a part of the insulating film 104. In this form, the mold layer 106 also covers a part of the first main surface 101a. The mold layer 106 is located at the outer peripheral portion on the first main surface 101a side of the semiconductor layer 101. The outer peripheral portion of the semiconductor layer 101 (first main surface 101a) may be referred to as the peripheral edge portion of the semiconductor layer 101 (first main surface 101a).

[0032] In plan view, the mold layer 106 is in a rectangular ring shape along the outer peripheral portion of the semiconductor layer 101. Also, the mold layer 106 is also located between the gate pad (the plating layer 105 on the first electrode layer 102g) and the source pad (the plating layer 105 on the first electrode layer 102s). That is, the mold layer 106 is formed only on the first main surface 101a of the semiconductor layer 101, and exposes the second main surface 101b and the side surfaces of the semiconductor layer 101.

[0033] The inner surface of the mold layer 106 is in direct contact with the side surface 105a of the plating layer 105. The inner surface of the mold layer 106 includes the inner surface on the first electrode layer 102g side (the first inner surface) and the inner surface on the first electrode layer 102s side (the second inner surface). The mold layer 106 is formed of, for example, a thermosetting resin (epoxy resin). The mold layer 106 may be formed of an epoxy resin containing carbon and glass fibers, etc. The thickness t3 of the mold layer 106 is, for example, 30 μm or more and 100 μm or less. The thickness t3 of the mold layer 106 may be 100 μm or more and 200 μm or less. The upper surface of the mold layer 106 and the upper surface of the plating layer 105 are flush or substantially flush.

[0034] The source pad may have an area of 50% or more of the area of the semiconductor substrate 101c (the first main surface 101a) in a plan view. Preferably, the source pad may have an area of 70% or more of the area of the semiconductor substrate 101c (the first main surface 101a) in a plan view. On the other hand, the gate pad may have an area of 20% or less of the area of the semiconductor substrate 101c (the first main surface 101a) in a plan view. Preferably, the gate pad may have an area of 10% or less of the area of the semiconductor substrate 101c (the first main surface 101a) in a plan view.

[0035] The source pad is disposed in a region including the center position of the semiconductor substrate 101c in a plan view. The gate pad is disposed in a region avoiding the source pad. However, the gate pad may be disposed in a region including the center position of the semiconductor substrate 101c in a plan view, and the source pad may be disposed so as to surround the periphery of the gate pad.

[0036] Next, the detailed configuration of the outer peripheral portion (in other words, the end portion) of the semiconductor device 100 will be described. FIG. 3 is a diagram showing the detailed configuration of the outer peripheral portion of the semiconductor device 100 (a cross-sectional view showing the details of the region III in FIG. 2). In FIG. 3, in addition to the first electrode layer 102s, the gate finger 102a and the outer peripheral source contact 102b are also shown.

[0037] The end portion of the first electrode layer 102s is covered with an insulating film 104. Specifically, the insulating film 104 includes a first insulating film 104c located on the first electrode layer 102s and a second insulating film 104d located on the first insulating film 104c. The first insulating film 104c is an inorganic film formed of silicon nitride, silicon oxide, or the like. The second insulating film 104d is an organic film formed of polyimide, PBO, or the like.

[0038] Further, the insulating film 104 includes a third insulating film 104e located under the outer peripheral source contact 102b. More specifically, the third insulating film 104e is located between the outer peripheral source contact 102b and the semiconductor layer 101. The third insulating film 104e is an inorganic film formed of silicon nitride, silicon oxide, or the like.

[0039] In a general semiconductor device, such an insulating film 104 is provided to suppress the intrusion of moisture into the end portion of the first electrode layer 102s and the occurrence of ion migration. However, when a reliability test such as a durability test in a high-temperature and high-humidity environment or a temperature cycle test is performed, the insulating film 104 may deteriorate, and moisture may intrude from the deteriorated portion or ion migration may occur at the deteriorated portion. That is, the deterioration of the insulating film 104 can cause a failure of the semiconductor device.

[0040] Therefore, in the semiconductor device 100, the insulating film 104 is further covered with the mold layer 106. Thereby, the deterioration of the insulating film 104 is suppressed, and the reliability of the semiconductor device 100 is improved.

[0041] The end portion of the first electrode layer 102s, the gate finger 102a, and the outer peripheral source contact 102b are basically covered by the first insulating film 104c. However, in the example of FIG. 3, the outermost end portion of the first electrode layer 102s, the gate finger 102a, and the outer peripheral source contact 102b are covered by the second insulating film 104d, and the first insulating film 104c is omitted. With such a configuration, the stress is relaxed.

[0042] Next, the detailed structure of the semiconductor layer 101 will be described. FIG. 4 is a diagram showing the detailed configuration of the semiconductor layer 101. In FIG. 4, the semiconductor layer 101 is not shaded to represent a cross section from the viewpoint of visibility of the drawing. As shown in FIGS. 3 and 4, specifically, the semiconductor layer 101 includes a semiconductor substrate 101c and an epitaxial layer 101d.

[0043] The semiconductor device 100 shown in FIG. 4 is an example of a switching device and includes a vertical transistor 2. The vertical transistor 2 is, for example, a vertical MISFET. As shown in FIG. 4, the semiconductor device 100 includes a semiconductor layer 101, a gate electrode 20, a source electrode 30, and a drain electrode 40. The drain electrode 40 corresponds to the second electrode layer 103.

[0044] The semiconductor layer 101 includes a semiconductor layer 101 mainly containing SiC (silicon carbide). Specifically, the semiconductor layer 101 is an n-type SiC semiconductor layer containing a SiC single crystal. The SiC single crystal is, for example, a 4H-SiC single crystal.

[0045] The 4H-SiC single crystal has an off-angle inclined at an angle within 10° with respect to the [11-20] direction from the (0001) plane. The off-angle may be 0° or more and 4° or less. The off-angle may exceed 0° and be less than 4°. The off-angle is set, for example, to 2° or 4°, in the range of 2° ± 0.2° or in the range of 4° ± 0.4°.

[0046] The semiconductor layer 101 is formed in a rectangular parallelepiped chip shape. The semiconductor layer 101 has a first main surface 101a and a second main surface 101b. The semiconductor layer 101 has a semiconductor substrate 101c and an epitaxial layer 101d. The semiconductor substrate 101c contains a SiC single crystal. The lower surface of the semiconductor substrate 101c is the second main surface 101b. This second main surface 101b is the carbon plane (000-1) plane where the carbon of the SiC crystal is exposed. The epitaxial layer 101d is laminated on the upper surface of the semiconductor substrate 101c and is an n - -type SiC semiconductor layer. The upper surface of the epitaxial layer 101d is the first main surface 101a. This first main surface 101a is the silicon plane (0001) plane where the silicon of the SiC crystal is exposed.

[0047] The drain electrode 40 is connected to the second main surface 101b of the semiconductor layer 101. The semiconductor substrate 101c is provided as an n + -type drain region. The epitaxial layer 101d is an n -It is provided as a drain drift region of the type.

[0048] The n-type impurity concentration of the semiconductor substrate 101c is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the epitaxial layer 101d is lower than that of the semiconductor substrate 101c, for example, 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less. In this specification, "impurity concentration" means the peak value of the impurity concentration.

[0049] The epitaxial layer 101d of the semiconductor layer 101 includes a deep well region 15, a body region 16, a source region 17, and a contact region 18 as shown in FIG. 4.

[0050] The deep well region 15 is formed in a region along the source trench 32 in the semiconductor layer 101. The deep well region 15 is also referred to as a breakdown voltage holding region. The deep well region 15 is a p - -type semiconductor region. The p-type impurity concentration of the deep well region 15 is, for example, 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The p-type impurity concentration of the deep well region 15 is, for example, higher than the n-type impurity concentration of the epitaxial layer 101d.

[0051] The deep well region 15 includes a side wall portion 15a along the side wall 32a of the source trench 32 and a bottom wall portion 15b along the bottom wall 32b of the source trench 32. The thickness (length in the z-axis direction) of the bottom wall portion 15b is, for example, equal to or greater than the thickness (length in the x-axis direction) of the side wall portion 15a. At least a part of the bottom wall portion 15b may be located within the semiconductor substrate 101c.

[0052] The body region 16 is a p-type semiconductor region provided in the surface layer portion of the first main surface 101a of the semiconductor layer 101. - The body region 16 is provided between the gate trench 22 and the source trench 32 in a plan view. The body region 16 is provided in a strip shape extending along the y-axis direction in a plan view. The body region 16 is continuous with the deep well region 15.

[0053] The p-type impurity concentration of the body region 16 is, for example, 1.0×10 16 cm -3 or more and 1.0×10 19 cm -3 or less. The p-type impurity concentration of the body region 16 may be equal to the impurity region of the deep well region 15. The p-type impurity concentration of the body region 16 may be higher than the p-type impurity concentration of the deep well region 15.

[0054] The source region 17 is an n-type semiconductor region provided in the surface layer portion of the first main surface 101a of the semiconductor layer 101. The source region 17 is a part of the body region 16. The source region 17 is provided in a region along the gate trench 22. The source region 17 is in contact with the gate insulating layer 23. + The source region 17 is provided in a strip shape extending along the y-axis direction in a plan view. The width (length in the x-axis direction) of the source region 17 is, for example, 0.2 μm or more and 0.6 μm or less. As an example, the width of the source region 17 may be about 0.4 μm. The n-type impurity concentration of the source region 17 is, for example, 1.0×10

[0055] cm 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0056] The contact region 18 is a p-type semiconductor region provided in the surface layer portion of the first main surface 101a of the semiconductor layer 101. +It is a semiconductor region of a certain type. The contact region 18 may be regarded as a part (high-concentration part) of the body region 16. The contact region 18 is provided in a region along the source trench 32. The contact region 18 is in contact with the barrier formation layer 33. Also, the contact region 18 is connected to the source region 17.

[0057] The contact region 18 is provided in a strip shape extending along the y-axis direction in plan view. The width (length in the x-axis direction) of the contact region 18 is, for example, 0.1 μm or more and 0.4 μm or less. As an example, the width of the contact region 18 may be about 0.2 μm. The p-type impurity concentration of the contact region 18 is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0058] On the first main surface 101a of the semiconductor layer 101, a plurality of trench gate structures 21 and a plurality of trench source structures 31 are provided. The trench gate structures 21 and the trench source structures 31 are alternately provided one by one along the x-axis direction. In FIG. 4, only the range where one trench gate structure 21 is sandwiched between two trench source structures 31 is shown.

[0059] Both the trench gate structure 21 and the trench source structure 31 are provided in a strip shape extending along the y-axis direction. For example, the x-axis direction is the [11-20] direction, and the y-axis direction is the [1-100] direction. The x-axis direction may be the [1-100] direction ([-1100] direction). In this case, the y-axis direction may be the [11-20] direction.

[0060] The trench gate structures 21 and the trench source structures 31 are alternately arranged along the x-axis direction and form a stripe structure in plan view. The distance between the trench gate structures 21 and the trench source structures 31 is, for example, 0.3 μm or more and 1.0 μm or less.

[0061] As shown in FIG. 4, the trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20.

[0062] The gate trench 22 is formed by digging down the first main surface 101a of the semiconductor layer 101 toward the second main surface 101b. The gate trench 22 is an elongated groove-shaped recess with a rectangular cross-sectional shape in the xz cross-section and extending along the y-axis direction. The gate trench 22 has a length on the order of millimeters in the longitudinal direction (y-axis direction). The gate trench 22 has a length of, for example, 1 mm or more and 10 mm or less. The length of the gate trench 22 may be 2 mm or more and 5 mm or less. The total extension of one or more gate trenches 22 per unit area may be 0.5 μm / μm2 or more and 0.75 μm / μm2 or less.

[0063] The gate insulating layer 23 is provided in a film shape along the side wall 22a and the bottom wall 22b of the gate trench 22. The gate insulating layer 23 partitions a concave space inside the gate trench 22. The gate insulating layer 23 includes, for example, silicon oxide. The gate insulating layer 23 may include at least one of impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0064] The thickness of the gate insulating layer 23 is, for example, 0.01 μm or more and 0.5 μm or less. The thickness of the gate insulating layer 23 may be uniform or may vary depending on the site. For example, the gate insulating layer 23 includes a side wall portion 23a along the side wall 22a of the gate trench 22 and a bottom wall portion 23b along the bottom wall 22b of the gate trench 22. The thickness of the bottom wall portion 23b may be thicker than the thickness of the side wall portion 23a. The thickness of the bottom wall portion 23b is, for example, 0.01 μm or more and 0.2 μm or less. The thickness of the side wall portion 23a is, for example, 0.05 μm or more and 0.5 μm or less. Further, the gate insulating layer 23 may include an upper surface portion provided on the upper surface of the source region 17 outside the gate trench 22. The thickness of the upper surface portion may be thicker than the thickness of the side wall portion 23a.

[0065] The gate electrode 20 is an example of the control electrode of the vertical transistor 2. The gate electrode 20 is embedded in the gate trench 22. A gate insulating layer 23 is provided between the gate electrode 20 and the side wall 22a and the bottom wall 22b of the gate trench 22. That is, the gate electrode 20 is embedded in a concave space partitioned by the gate insulating layer 23. The gate electrode 20 is, for example, a conductive layer containing conductive polysilicon. The gate electrode 20 may contain at least one of metals such as titanium, nickel, copper, aluminum, silver, gold, tungsten, or conductive metal nitrides such as titanium nitride.

[0066] The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. The aspect ratio of the trench gate structure 21 is, for example, the same as the aspect ratio of the gate trench 22. The aspect ratio of the trench gate structure 21 is, for example, 0.25 or more and 15.0 or less. The width of the trench gate structure 21 is, for example, 0.2 μm or more and 2.0 μm or less. As an example, the width of the trench gate structure 21 may be about 0.4 μm. The depth of the trench gate structure 21 is, for example, 0.5 μm or more and 3.0 μm or less. As an example, the depth of the trench gate structure 21 may be about 1.0 μm.

[0067] As shown in FIG. 4, the trench source structure 31 includes a deep well region 15, a source trench 32, a barrier formation layer 33, and a source electrode 30.

[0068] The source trench 32 is formed by digging down the first main surface 101a of the semiconductor layer 101 toward the second main surface 101b. The source trench 32 is an elongated groove-shaped recess having a rectangular cross-sectional shape in the xz cross-section and extending along the y-axis direction. The source trench 32 is, for example, deeper than the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located closer to the second main surface 101b side than the bottom wall 22b of the gate trench 22.

[0069] The barrier forming layer 33 is provided in a film shape along the side wall 32a and the bottom wall 32b of the source trench 32. The barrier forming layer 33 partitions a concave space inside the source trench 32. The barrier forming layer 33 is formed using a material different from that of the source electrode 30. The barrier forming layer 33 has a potential barrier higher than the potential barrier between the source electrode 30 and the deep well region 15.

[0070] The barrier forming layer 33 is an insulating barrier forming layer. In this case, the barrier forming layer 33 contains at least one of non-doped silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The barrier forming layer 33 may be formed using the same material as the gate insulating layer 23. In this case, the barrier forming layer 33 may have the same film thickness as the gate insulating layer 23.

[0071] For example, when the barrier forming layer 33 and the gate insulating layer 23 are formed using silicon oxide, they can be formed simultaneously by a thermal oxidation treatment method. The barrier forming layer 33 may be a conductive barrier forming layer. In this case, the barrier forming layer 33 contains at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0072] The source electrode 30 is embedded in the source trench 32. A barrier forming layer 33 is provided between the source electrode 30 and the side wall 32a and the bottom wall 32b of the source trench 32. That is, the source electrode 30 is embedded in the concave space partitioned by the barrier forming layer 33.

[0073] The source electrode 30 is, for example, a conductive layer containing conductive polysilicon. The source electrode 30 may be n-type polysilicon doped with n-type impurities or p-type polysilicon doped with p-type impurities. The source electrode 30 may contain at least one of metals such as titanium, nickel, copper, aluminum, silver, gold, tungsten, or conductive metal nitrides such as titanium nitride. The source electrode 30 may be formed using the same material as the gate electrode 20. In this case, the source electrode 30 and the gate electrode 20 can be formed in the same process.

[0074] The aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31. The width of the trench source structure 31 is, for example, the sum of the width of the source trench 32 and the width of the side wall portion 15a of the deep well region 15 located on both sides of the source trench 32. The width of the trench source structure 31 is, for example, 0.6 μm or more and 2.4 μm or less.

[0075] As an example, the width of the trench source structure 31 may be about 0.8 μm. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15. The depth of the trench source structure 31 is, for example, 1.5 μm or more and 11 μm or less. As an example, the depth of the trench source structure 31 may be about 2.5 μm.

[0076] The aspect ratio of the trench source structure 31 is larger than the aspect ratio of the trench gate structure 21. For example, the aspect ratio of the trench source structure 31 is 1.5 or more and 4.0 or less. By increasing the depth of the trench source structure 31, the breakdown voltage holding effect due to the super junction (SJ) structure can be enhanced.

[0077] The drain electrode 40 corresponds to the second electrode layer 103. The drain electrode 40 may contain at least one of titanium, nickel, copper, aluminum, gold, or silver. For example, the drain electrode 40 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in order from the second main surface 101b of the semiconductor layer 101. The drain electrode 40 may have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer laminated in order from the second main surface 101b of the semiconductor layer 101. The AlCu layer is an alloy layer of aluminum and copper.

[0078] The drain electrode 40 may have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer laminated in order from the second main surface 101b of the semiconductor layer 101. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may include a single-layer structure composed of a TiN layer or a laminated structure including a Ti layer and a TiN layer instead of the Ti layer.

[0079] The semiconductor device 100 configured as described above can switch between an on state in which a drain current flows and an off state in which no drain current flows according to the gate voltage applied to the gate electrode 20 of the vertical transistor 2. The gate voltage is, for example, a voltage of 10V or more and 50V or less. As an example, the gate voltage may be 30V. The source voltage applied to the source electrode 30 is a reference voltage such as a ground voltage (0V). The drain voltage applied to the drain electrode 40 is a voltage having a magnitude equal to or greater than the source voltage. The drain voltage is, for example, a voltage having a magnitude of 0V or more and 10000V or less. The drain voltage may be a voltage having a magnitude of 1000V or more.

[0080] When a gate voltage is applied to the gate electrode 20, p -A channel is formed in a portion of the gate insulating layer 23 of the body region 16 of the [type]. As a result, a current path is formed from the source electrode 30 through the contact region 18, the source region 17, the channel of the body region 16, the epitaxial layer 101d, and the semiconductor substrate 101c to the drain electrode 40 in this order. Since the drain electrode 40 is at a higher potential than the source electrode 30, the drain current flows from the drain electrode 40 through the semiconductor substrate 101c, the epitaxial layer 101d, the channel of the body region 16, the source region 17, and the contact region 18 to the source electrode 30 in this order. Thus, the drain current flows along the thickness direction of the semiconductor device 100.

[0081] p - type deep well region 15 and n - A pn junction is formed between the type epitaxial layer 101d. In the on state of the vertical transistor 2, p - A source voltage is applied to the type deep well region 15 via the source electrode 30, and n - A drain voltage greater than the source voltage is applied to the type epitaxial layer 101d via the drain electrode 40.

[0082] That is, a reverse bias voltage is applied to the pn junction between the deep well region 15 and the epitaxial layer 101d. Since the n-type impurity concentration of the epitaxial layer 101d is lower than the p-type impurity concentration of the deep well region 15, a depletion layer spreads from the interface between the deep well region 15 and the epitaxial layer 101d toward the drain electrode 40. Thereby, the breakdown voltage of the vertical transistor 2 can be increased.

[0083] The source electrode 30 is electrically connected to a first electrode layer 102s provided on the source electrode 30. The gate electrode 20 is insulated from the first electrode layer 102s by an insulating layer 61 and is electrically connected to a first electrode layer 102g via a gate finger (for example, the gate finger 102a in FIG. 3) provided above the outer peripheral portion of the semiconductor layer 101 or the like. The insulating layer 61 contains, for example, silicon oxide or silicon nitride as a main component.

[0084] Next, a method for manufacturing the semiconductor device 100 will be described. FIGS. 5A to 5F are cross-sectional views showing the method for manufacturing the semiconductor device 100. First, as shown in FIG. 5A, a semiconductor layer 101 is formed, and a first electrode layer 102 is formed on the first main surface 101a of the semiconductor layer 101. As the method for forming the semiconductor layer 101, various existing methods are used. The first electrode layer 102 is formed, for example, by a sputtering method, a vapor deposition method, or the like.

[0085] Next, as shown in FIG. 5B, the outer peripheral portion of the first electrode layer 102 is covered with an insulating film 104. The insulating film 104 is formed, for example, through a coating process and a photolithography process. In the coating process, a liquid photosensitive resin material that will become the insulating film 104 is applied to the first electrode layer 102 by a spin coating method. In the photolithography process, after the photosensitive resin material is cured by exposure, unnecessary portions of the photosensitive resin material are removed by an ashing method, a wet etching method, or the like. Thereby, the insulating film 104 is formed.

[0086] Next, as shown in FIG. 5C, a plating layer 105 is formed on the first electrode layer 102. The plating layer 105 is formed on the first electrode layer 102, for example, by an electrolytic plating method or an electroless plating method. The plating layer 105 is selectively formed on at least a part of the portion of the first electrode layer 102 that is not covered with the insulating film 104.

[0087] Next, as shown in FIG. 5D, a liquid resin material 106a (for example, a thermosetting resin) that will become the mold layer 106 is applied or printed on the entire surface on the first main surface 101a side of the semiconductor layer 101. As a result, the insulating film 104 and the plating layer 105 are covered with the resin material 106a. Also, the resin material 106a enters between the plating layer 105 on the first electrode layer 102g and the plating layer 105 on the first electrode layer 102s. The applied or printed resin material 106a is cured, for example, by heating.

[0088] Next, as shown in FIG. 5E, the upper surface (surface) of the resin material 106a is ground until the plating layer 105 is exposed. As a result, the upper surface (surface) of the plating layer 105 and the upper surface (surface) of the mold layer 106 are flush. That is, the upper surface (surface) of the plating layer 105 and the upper surface (surface) of the mold layer 106 consist of continuous ground surfaces.

[0089] Next, as shown in FIG. 5F, a second electrode layer 103 is formed on the second main surface 101b of the semiconductor layer 101. The second electrode layer 103 is formed, for example, by a sputtering method, a vapor deposition method, or the like. Finally, the wafer is singulated by being cut along the scribe line SL by a dicing blade. The dicing blade cuts the semiconductor layer 101 and the mold layer 106 simultaneously. As a result, the side surface of the semiconductor layer 101 and the side surface of the mold layer 106 are flush. That is, the side surface of the semiconductor layer 101 and the side surface of the mold layer 106 consist of continuous ground surfaces. As a result, a semiconductor device 100 as shown in FIG. 2 is obtained.

[0090] The second electrode layer 103 may be formed on the second main surface 101b of the semiconductor layer 101 at the stage of FIG. 5A. The lower surface of the second electrode layer 103, the upper surface of the plating layer 105, the side surface of the plating layer 105, and the upper surface of the mold layer 106 constitute the outer surface of the semiconductor device 100 (chip).

[0091] Next, the configuration of the semiconductor device according to the second embodiment will be described. FIG. 6 is a plan view of the semiconductor device shown in FIG. 8. FIG. 7 is a cross-sectional view of the semiconductor device shown in FIG. 8 (a cross-sectional view taken along line VII-VII of FIG. 6).

[0092] The semiconductor device 200 shown in FIG. 8 is a semiconductor chip that functions as a vertical Schottky barrier diode by utilizing the Schottky barrier generated by the junction of the semiconductor layer 201 and the first electrode layer 202. The semiconductor device 200 is, for example, a power semiconductor device used for power supply and control. Specifically, the semiconductor device 200 includes a semiconductor layer 201, a first electrode layer 202, a second electrode layer 203, an insulating film 204, a plating layer 205, and a mold layer 206.

[0093] The semiconductor layer 201 is a SiC semiconductor layer including a SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. In the semiconductor device 200, the entire semiconductor layer 201 corresponds to a semiconductor substrate (for example, the semiconductor substrate 101c). The conductivity type of the semiconductor layer 201 is, for example, n-type. The semiconductor layer 201 is formed in a plate shape with a rectangular shape in plan view. The length of one side of the semiconductor layer 201 is, for example, 1 mm or more and 10 mm or less, but may be 2 mm or more and 5 mm or less.

[0094] The semiconductor layer 201 has a first main surface 201a and a second main surface 201b facing away from the first main surface 201a. The thickness t4 of the semiconductor layer 201 (semiconductor substrate) is, for example, 100 μm or more and 350 μm or less. The thickness t4 of the semiconductor layer 201 is preferably 200 μm or less. The semiconductor layer 201 is not limited to a SiC semiconductor layer, and may be a semiconductor layer made of another wide bandgap semiconductor such as GaN, or may be a Si semiconductor layer. Of course, the semiconductor layer 201 may have a stacked structure including the aforementioned semiconductor substrate 101c and the aforementioned epitaxial layer 101d.

[0095] The first electrode layer 202 is formed on the first main surface 201a. The first electrode layer 202 functions as an anode of the Schottky barrier diode. The first electrode layer 202 is formed of, for example, aluminum. The first electrode layer 202 may be formed of other materials such as titanium, nickel, copper, silver, gold, titanium nitride, and tungsten.

[0096] The second electrode layer 203 is formed on the second main surface 201b. The second electrode layer 203 functions as a cathode of the Schottky barrier diode. The second electrode layer 203 is formed of, for example, a stacked film of titanium, nickel, and gold. The second electrode layer 203 may be formed of other materials such as aluminum, copper, silver, titanium nitride, and tungsten.

[0097] The insulating film 204 covers the entire circumference of the outer peripheral portion of the first electrode layer 202 (that is, both end portions in the X-axis direction and both end portions in the Y-axis direction, respectively). The insulating film 204 includes a first portion 204a and a second portion 204b. The first portion 204a rides on the first electrode layer 202. More specifically, the first portion 204a rides on the peripheral edge portion of the first electrode layer 202. The second portion 204b is located outside the first portion 204a and covers a region other than the first electrode layer 202. That is, the second portion 204b does not ride on the first electrode layer 202.

[0098] The first portion 204a further includes an inner end portion 204a1 and a flat portion 204a2. The inner end portion 204a1 is the end portion of the portion of the first portion 204a that is located on the inner side of the semiconductor layer 201 in a plan view. The inner end portion 204a1 slopes obliquely downward toward the inner side of the first electrode layer 202 in a cross-sectional view. The flat portion 104a2 is located outside the inner end portion 204a1 (on the peripheral edge side of the semiconductor layer 101) and has a substantially uniform thickness.

[0099] The insulating film 204 is, for example, an organic film containing a photosensitive resin. The insulating film 204 is formed of, for example, polyimide, PBO (polybenzoxazole), or the like. The insulating film 204 may be an inorganic film formed of silicon nitride, silicon oxide, or the like. The insulating film 204 may have a single-layer structure or a laminated structure in which a plurality of types of materials are laminated. When the insulating film 204 has a laminated structure, the insulating film 204 may include both an organic film and an inorganic film. In this case, the insulating film 204 preferably includes an inorganic film and an organic film laminated in this order from the first main surface 201a side. The thickness of the insulating film 204 is at most about 10 μm.

[0100] The plating layer 205 is a metal layer that covers at least a part of the first electrode layer 202. The plating layer 205 covers at least a part other than the end portion of the first electrode layer 202 (that is, the portion covered by the insulating film 204). As shown in FIG. 6, in plan view, the plating layer 205 is surrounded by the mold layer 206. The plating layer 205 formed on the first electrode layer 202 functions as a pad having a rectangular shape in plan view. A pad is a portion to which a bonding wire is bonded when the semiconductor device 200 is packaged. Further, the plating layer 205 also functions as a support member for the mold layer 206.

[0101] The plating layer 205 is formed of, for example, a material different from that of the first electrode layer 202. The plating layer 205 is formed of, for example, copper or a copper alloy mainly composed of copper. The plating layer 205 may be formed of other metal materials. The thickness t5 of the plating layer 205 is larger than the thickness of the insulating film 204. More specifically, the thickness t5 of the plating layer 205 is larger than the maximum thickness of the insulating film 204 located on the first electrode layer 202. Thereby, the top of the plating layer 205 is higher than the top of the insulating film 204. The thickness t5 of the plating layer 205 is, for example, 30 μm or more and 100 μm or less. The thickness t5 of the plating layer 205 may be 100 μm or more and 200 μm or less.

[0102] The side surface 205a of the plating layer 205 extends vertically or substantially vertically. The side surface 205a does not necessarily extend linearly in cross-sectional view and may include curves and irregularities. The side surface 205a is located in a region where both the first electrode layer 202 and the insulating film 204 overlap each other. More specifically, the side surface 205a is located on the flat portion 204a2 of the insulating film 204. That is, the plating layer 205 covers the inner end portion 204a1 and the flat portion 204a2 of the first portion 204a. By positioning the side surface 205a on the flat portion 204a2, the plating layer 205 can be formed stably as compared with the case where the side surface 205a is positioned on the inner end portion 204a1 having a relatively large thickness variation.

[0103] The mold layer 206 is a resin layer that covers a part of the insulating film 204. In this form, the mold layer 206 also covers a part of the first main surface 201a. The mold layer 206 is located at the outer peripheral portion on the first main surface 201a side of the semiconductor layer 201. In plan view, the mold layer 206 is in a rectangular ring shape along the outer peripheral portion of the semiconductor layer 201. The inner surface of the mold layer 206 is in direct contact with the side surface 205a of the plating layer 205. The mold layer 206 is formed only on the first main surface 201a of the semiconductor layer 201, and exposes the second main surface 201b and the side surfaces of the semiconductor layer 201.

[0104] The mold layer 206 is formed of, for example, a thermosetting resin (epoxy resin). The mold layer 106 may be formed of an epoxy resin containing carbon, glass fibers, and the like. The thickness t6 of the mold layer 206 is, for example, 30 μm or more and 100 μm or less, but may be 100 μm or more and 200 μm or less. The upper surface of the mold layer 206 and the upper surface of the plating layer 205 are flush or substantially flush.

[0105] Next, the detailed configuration of the outer peripheral portion (in other words, the end portion) of the semiconductor device 200 will be described. FIG. 8 is a diagram showing the detailed configuration of the outer peripheral portion of the semiconductor device 200 (a cross-sectional view showing the details of the region VIII in FIG. 7).

[0106] The end portion of the first electrode layer 202 is covered by the insulating film 204. Specifically, the insulating film 204 includes a first insulating film 204c located on the first electrode layer 202, a second insulating film 204d located on the first insulating film 204c, and a third insulating film 204e located under the first electrode layer 202. The third insulating film 204e is more specifically located between the first electrode layer 202 and the semiconductor layer 201. The first insulating film 204c is an inorganic film formed of silicon nitride, silicon oxide, or the like. The second insulating film 204d is an organic film formed of polyimide, PBO, or the like. The third insulating film 204e is an inorganic film formed of silicon nitride, silicon oxide, or the like.

[0107] In a general semiconductor device, such an insulating film 204 is provided to suppress the intrusion of moisture into the ends of the first electrode layer 202 and the occurrence of ion migration. However, when reliability tests such as endurance tests in a high-temperature and high-humidity environment or temperature cycle tests are performed, the insulating film 204 may deteriorate, and moisture may intrude from the deteriorated portion or ion migration may occur at the deteriorated portion. That is, the deterioration of the insulating film 204 can cause a failure of the semiconductor device.

[0108] Therefore, in the semiconductor device 200, the insulating film 204 is further covered with a mold layer 206. Thereby, the deterioration of the insulating film 204 is suppressed, and the reliability of the semiconductor device 200 is improved. As shown in FIG. 8, the outermost end of the first electrode layer 202 is covered with a second insulating film 204d, and the first insulating film 204c is omitted. With such a configuration, stress is relaxed. Since the manufacturing method of the semiconductor device 200 is the same as that of the semiconductor device 100, a detailed description of the manufacturing method of the semiconductor device 200 is omitted.

[0109] In the third embodiment, a semiconductor package having a semiconductor device is described. FIGS. 9 and 10 are diagrams showing an example of a semiconductor package according to the third embodiment. FIG. 10 is a diagram showing the internal structure of the semiconductor package 300 shown in FIG. 9 when viewed from the side opposite to FIG. 9.

[0110] The semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. The semiconductor package 300 includes a package body 301, terminals 302d, 302g, 302s, bonding wires 303g, bonding wires 303s, and a semiconductor device 100.

[0111] The package body 301 is rectangular parallelepiped-shaped, and terminals 302d, 302g, and 302s protrude from the bottom of the package body 301. Also, the package body 301 houses the semiconductor device 100. The package body 301 is, in other words, a sealing body that seals the semiconductor device 100. The package body 301 is formed of, for example, an epoxy resin. The package body 301 may be formed of an epoxy resin containing carbon, glass fiber, or the like.

[0112] Each of the terminals 302d, 302g, and 302s protrudes from the bottom of the package body 301 and is arranged in a row. The terminals 302d, 302g, and 302s are each formed of, for example, aluminum. The terminals 302d, 302g, and 302s may each be formed of another metallic material such as copper.

[0113] Inside the package body 301, a gate pad (the plating layer 105 on the first electrode layer 102g) included in the semiconductor device 100 is electrically connected to the terminal 302g by a bonding wire 303g. A source pad (the plating layer 105 on the first electrode layer 102s) included in the semiconductor device 100 is electrically connected to the terminal 302s by a bonding wire 303s. A drain electrode (the second electrode layer 103) included in the semiconductor device 100 is joined to a wide portion located inside the package body 301 of the terminal 302d by solder, a sintered layer made of silver or copper, or the like.

[0114] Instead of the semiconductor device 100, the semiconductor package 300 may include the semiconductor device 200. In this case, the semiconductor package 300 includes two terminals, and inside the package body 301, an anode (the first electrode layer 202) included in the semiconductor device 200 is electrically connected to one of the two terminals by a bonding wire or the like, and a cathode (the second electrode layer 203) is joined to a wide portion located inside the package body 401 of the other of the two terminals by solder, a sintered layer made of silver or copper, or the like.

[0115] The semiconductor package 300 as described above includes the semiconductor device 100 (or the semiconductor device 200), and thus has higher reliability than the case including a general semiconductor device.

[0116] Next, another example of the semiconductor package according to the third embodiment will be described. FIG. 11 is a diagram showing another example of the semiconductor package according to the third embodiment. The semiconductor package 400 shown in FIG. 11 is a so-called DIP (Dual In-line Package) type semiconductor package. The semiconductor package 400 includes a package body 401, a plurality of terminals 402, and the semiconductor device 100.

[0117] The package body 401 has a rectangular parallelepiped shape, and a plurality of terminals 402 protrude from the package body 401. Further, the package body 401 incorporates the semiconductor device 100. In other words, the package body 401 is a sealing body that seals the semiconductor device 100. The package body 401 is formed of, for example, an epoxy resin containing carbon and glass fibers.

[0118] The plurality of terminals 402 are arranged side by side along the long side of the package body 401. The plurality of terminals 402 are each formed of, for example, aluminum. The plurality of terminals 402 may each be formed of another metallic material such as copper.

[0119] Inside the package body 401, each of the gate pad (the plating layer 105 on the first electrode layer 102g), the source pad (the plating layer 105 on the first electrode layer 102s), and the drain electrode (the second electrode layer 103) included in the semiconductor device 100 is electrically connected to the corresponding terminal 402 by a bonding wire or the like. The semiconductor package 400 may include a plurality of semiconductor devices 100. That is, the package body 401 may incorporate a plurality of semiconductor devices 100.

[0120] Further, the semiconductor package 400 may include the semiconductor device 200 instead of, or in addition to, the semiconductor device 100. In this case, inside the package body 401, each of the anode (the first electrode layer 202) and the cathode (the second electrode layer 203) included in the semiconductor device 200 is electrically connected to the corresponding terminal 402 by a bonding wire or the like.

[0121] The semiconductor package 400 as described above includes the semiconductor device 100 (or the semiconductor device 200), and thus has higher reliability than the case of including a general semiconductor device.

[0122] As described above, bonding wires are used for the electrical connection between the terminals included in the semiconductor package 300 or the semiconductor package 400 and the semiconductor device 100 (or the semiconductor device 200). When the bonding wire is a wire made of aluminum, as shown in FIG. 12, it is preferable that a nickel layer is formed on the plating layer 105. FIG. 12 is a cross-sectional view of the semiconductor device 100 having a structure in which a nickel layer is formed on the plating layer 105.

[0123] In FIG. 12, as an example of the bonding wire, the bonding wire 303g and the bonding wire 303s are also shown together. The nickel layer 107 is an example of a metal layer formed of a metal material different from the metal material forming the plating layer 105. Although not shown, similarly for the semiconductor device 200, a nickel layer may be formed on the plating layer 205.

[0124] Further, as shown in FIG. 13, the plating layer 105 may be composed of a first plating layer 1051 made of copper and a second plating layer 1052 made of nickel. FIG. 13 is a cross-sectional view of the semiconductor device 100 including a two-layer plating layer. Thereby, it is not necessary to form an additional nickel layer as in the example of FIG. 12. In the example of FIG. 13, the upper surface of the second plating layer 1052 and the upper surface of the mold layer are flush.

[0125] Also, in the examples of FIGS. 12 and 13, a nickel layer is formed on the outermost surface of the plating layer 105, which is a joint portion with a bonding wire made of aluminum. However, other layer configurations may be formed on the outermost surface of the plating layer 105 instead of the nickel layer. For example, the outermost surface of the plating layer 105 may have a two-layer structure (i.e., a NiPd layer) in which a palladium layer is formed on the nickel layer.

[0126] Further, the outermost surface of the plating layer 105 may have a three-layer structure (e.g., a NiPdAu layer) in which still another metal layer is formed on this palladium layer. Such NiPd layers and NiPdAu layers are suitable not only when a bonding wire is joined to the plating layer 105 functioning as a source pad, but also when an external terminal is joined to the plating layer 105 functioning as a source pad by silver sintering.

[0127] The form of the semiconductor package including the semiconductor device 100 (or semiconductor device 200) is not limited to forms such as the semiconductor packages 300 and 400. As the semiconductor package, an SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package) may be adopted. Also, various semiconductor packages similar to these may be adopted as the semiconductor package.

[0128] As described above, the semiconductor device 100 includes a semiconductor layer 101, a first electrode layer 102, a second electrode layer 103, a plating layer 105, and a mold layer 106. The semiconductor layer 101 has a first main surface 101a and a second main surface 101b facing away from the first main surface 101a. The first electrode layer 102 is formed on the first main surface 101a. The second electrode layer 103 is formed on the second main surface 101b. The insulating film 104 covers the end portion of the first electrode layer 102. The plating layer 105 covers at least a part other than the end portion of the first electrode layer 102. The mold layer 106 covers the insulating film 104.

[0129] According to this semiconductor device 100, since the insulating film 104 covering the end portion of the first electrode layer 102 is further covered with the mold layer 106, deterioration of the insulating film 104 can be suppressed. That is, the semiconductor device 100 is a semiconductor device with improved reliability.

[0130] For example, in plan view, the mold layer 106 is annular along the outer peripheral portion of the semiconductor layer 101. In such a semiconductor device 100, the reliability is further improved by covering the outer peripheral portion of the semiconductor layer 101 with the mold layer 106. For example, the surface of the plating layer 105 and the surface of the mold layer 106 are flush. Such a semiconductor device 100 can be manufactured by applying or printing a resin material 106a on the first main surface 101a side of the semiconductor layer 101 and then grinding until the plating layer 105 is exposed.

[0131] For example, the plating layer 105 and the mold layer 106 are in direct contact. In such a semiconductor device 100, the plating layer 105 can be used as a support for the mold layer 106. For example, the semiconductor layer 101 is formed of SiC. Such a semiconductor device 100 can obtain a relatively high dielectric breakdown field strength.

[0132] For example, the semiconductor device 100 may function as a transistor. In this case, the second electrode layer 103 may be the drain electrode of the transistor. In this case, the first electrode layer 102 may include the source electrode of the transistor and the gate electrode of the transistor. In the first electrode layer 102, the gate electrode is insulated from the source electrode. Such a semiconductor device 100 can function as a transistor.

[0133] For example, the semiconductor device 200 functions as a Schottky barrier diode with the first electrode layer 202 as the anode and the second electrode layer 203 as the cathode. Such a semiconductor device 100 can function as a Schottky barrier diode. For example, the side surface of the semiconductor layer 101 and the side surface of the mold layer 106 are flush. Such a semiconductor device 100 can be manufactured by simultaneously cutting the semiconductor layer 101 and the mold layer 106.

[0134] For example, on the surface of the plating layer 105, a nickel layer 107 formed of a metal material different from the metal material forming the plating layer 105 is formed. The nickel layer 107 is an example of a metal layer. Such a semiconductor device 100 can be easily bonded with a bonding wire by forming the nickel layer 107 suitable for bonding the bonding wire on the surface of the plating layer 105.

[0135] The manufacturing method of the semiconductor device 100 includes the first to fifth steps. In the first step, the first electrode layer 102 is formed on the first main surface 101a of the semiconductor layer 101. In the second step, the second electrode layer 103 is formed on the second main surface 101b of the semiconductor layer 101, which faces away from the first main surface 101a. In the third step, an insulating film 104 covering the end of the first electrode layer 102 is formed. In the fourth step, a plating layer 105 covering at least a part other than the end of the first electrode layer 102 is formed. In the fifth step, a mold layer 106 covering the insulating film 104 is formed. According to this manufacturing method, a semiconductor device 100 with improved reliability can be manufactured.

[0136] For example, the step of forming the mold layer 106 covering the insulating film 104 (the fifth step) includes a step of forming the mold layer 106 so as to cover the plating layer 105 and a step of grinding the surface of the mold layer 106 so that the plating layer 105 is exposed. According to this manufacturing method, the semiconductor device 100 can be manufactured by grinding the surface of the mold layer 106 until the plating layer 105 is exposed.

[0137] In the above embodiment, an example of a semiconductor device (semiconductor device 100) in which a plating layer 105 functioning as a gate pad and a plating layer 105 functioning as a source pad are provided on the upper surface has been described. Here, the semiconductor device may further include a plating layer 105 functioning as a pad for current sensing and a plating layer 105 functioning as a pad for temperature sensing. FIG. 14 is a plan view of a semiconductor device according to a modified example having such a structure.

[0138] As shown in FIG. 14, the semiconductor device 100a includes a gate pad 105g (a plating layer 105 functioning as a gate pad; the same applies hereinafter), a source pad 105s, a current sensing pad 105c (pad electrode), and a pair of temperature sensing pads 105t (pad electrodes).

[0139] The semiconductor device 100a includes a first electrode layer 102s having a plurality of separated portions separated from each other. The current sensing pad 105c is a plating layer connected to a portion (separated portion) obtained by separating a part of the first electrode layer 102s included in the semiconductor device 100a. When a current flows between the source pad 105s and the second electrode layer 103 included in the semiconductor device 100a, a current smaller than the above current flows between the current sensing pad 105c and the second electrode layer 103. By monitoring such a current, an increase in the current can be detected.

[0140] The semiconductor device 100a includes a diode (temperature-sensitive diode) provided on the first main surface 101a of the semiconductor layer 101. One of the pair of temperature-sensing pads 105t is a plating layer electrically connected to the anode of the diode (temperature-sensitive diode) included in the semiconductor device 100a. The other of the pair of temperature-sensing pads 105t is a plating layer electrically connected to the cathode of the diode (temperature-sensitive diode). The temperature of the semiconductor device 100a can be detected based on the magnitude of the voltage between the pair of temperature-sensing pads 105t.

[0141] As described above, the present invention can also be realized as a semiconductor device 100a including the current-sensing pad 105c and the pair of temperature-sensing pads 105t. The present invention may also be realized as a semiconductor device including at least one of the current-sensing pad 105c and the pair of temperature-sensing pads 105t.

[0142] In the above embodiment, an example in which the mold layer 106 and the semiconductor layer 101 are simultaneously cut by a dicing blade has been described, but the present invention is not limited to this. For example, a two-step dicing process may be combined. FIGS. 15A to 15C are cross-sectional views for explaining a dicing process according to a modified example having such a two-step dicing process.

[0143] First, as shown in FIG. 15A, the entire mold layer 106 and a part of the semiconductor layer 101 are cut by a first dicing blade DB1 having a first width w1. Then, as shown in FIG. 15B, the entire semiconductor substrate 101c is cut by a second dicing blade DB2 having the same rotation axis as the first dicing blade DB1 and a second width w2 smaller than the first width w1. As shown in FIG. 15C, the semiconductor device 100b singulated by this method has the side surface of the mold layer 106 positioned inside compared to the side surface of the semiconductor layer 101 and has a step in the vicinity of the boundary between the mold layer 106 and the semiconductor layer 101.

[0144] Dicing may be performed with the wafer upside down. That is, dicing may be performed with the back surface (carbon surface) of the semiconductor substrate 101c facing upward. The rotational direction of the dicing blade is preferably the direction of cutting from the carbon surface toward the silicon surface. FIGS. 16A to 16C are cross-sectional views for explaining a dicing process according to another modification having such a two-step dicing process.

[0145] First, as shown in FIG. 16A, the entire semiconductor layer 101 and a part of the mold layer 106 are cut by a first dicing blade DB1 having a first width w1. Then, as shown in FIG. 16B, the entire mold layer 106 is cut by a second dicing blade DB2 having the same rotation axis as the first dicing blade DB1 and a second width w2 smaller than the first width w1. As shown in FIG. 16C, in the semiconductor device 100c singulated by this method, the side surface of the semiconductor layer 101 is located inside rather than the side surface of the mold layer 106c, and has a step in the vicinity of the boundary between the mold layer 106 and the semiconductor layer 101.

[0146] The two-step dicing process shown in FIGS. 15A to 15C and the two-step dicing process shown in FIGS. 16A to 16C are applicable not only to semiconductor devices functioning as transistors but also to semiconductor devices functioning as Schottky barrier diodes.

[0147] The semiconductor device according to the embodiment has been described above, but the present invention is not limited to the above embodiment. For example, all the numbers used in the above description are for illustration to specifically describe the present invention, and the present invention is not limited to the illustrated numbers.

[0148] In the above embodiments, the main materials of the components included in the semiconductor device were exemplified. However, other materials may be included in each layer of the stacked structure included in the semiconductor device as long as the same functions as the stacked structure of the above embodiments can be realized. Also, in the drawings, the corners and sides of each component are depicted linearly, but those with rounded corners and sides due to manufacturing reasons and the like are also included in the present invention. Further, a semiconductor device having a structure in which the conductivity type described in the above embodiments is reversed is also included in the present invention.

[0149] As described above, the semiconductor device according to one or more aspects has been explained based on the embodiments. However, the present invention is not limited to these embodiments. As long as the gist of the present invention is not deviated from, various modifications conceivable by those skilled in the art, the forms obtained by applying such modifications to the embodiments, and the forms constructed by combining the components in different embodiments are also included within the scope of the present invention.

[0150] Also, various changes, replacements, additions, omissions, etc. can be made within the scope of the claims or their equivalents in the above embodiments. For example, in the above embodiments, a power semiconductor device using a SiC substrate was explained, but the present invention is also applicable to a power semiconductor device (IGBT or MOSFET) using a Si substrate. The present invention can be applied as an industrial applicability to semiconductor devices, semiconductor packages, and the like.

[0151] Examples of features extracted from this specification and the drawings are shown below. Hereinafter, the alphanumerics in parentheses represent the corresponding components in the foregoing embodiments, but the scope of each item is not intended to be limited to the embodiments. Hereinafter, a semiconductor device with improved reliability is provided.

[0152] [A1]A semiconductor device (100, 100a, 100b, 100c, 200) comprising a semiconductor layer (100, 201) having a first main surface (101a, 201a) and a second main surface (101b, 201b) facing away from the first main surface (101a, 201a), a first electrode layer (102, 102g, 102s, 202) formed on the first main surface (101a, 201a), a second electrode layer (103, 203) formed on the second main surface (101b, 201b), an insulating film (104, 204) covering an end portion of the first electrode layer (102, 102g, 102s, 202), a plating layer (105, 205) covering at least a part of the first electrode layer (102, 102g, 102s, 202) other than the end portion, and a mold layer (106, 206) covering the insulating film (104, 204).

[0153] [A2]The semiconductor device (100, 100a, 100b, 100c, 200) according to A1, wherein in a plan view, the mold layer (106, 206) is annular along an outer peripheral portion of the semiconductor layer (100, 201).

[0154] [A3]The semiconductor device (100, 100a, 100b, 100c, 200) according to A1 or A2, wherein a surface of the plating layer (105, 205) and a surface of the mold layer (106, 206) are flush with each other.

[0155] [A4]The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A3, wherein the plating layer (105, 205) and the mold layer (106, 206) are in direct contact with each other.

[0156] [A5]The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A4, wherein the semiconductor layer (100, 201) is formed of SiC.

[0157] [A6] The semiconductor device (100, 100a, 100b, 100c, 200) functions as a transistor, the second electrode layer (103, 203) is the drain electrode (40) of the transistor, and the first electrode layer (102, 102g, 102s, 202) includes the source electrode (102s) of the transistor and the gate electrode (102g) of the transistor insulated from the source electrode (102s). The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A5.

[0158] [A7] The semiconductor device (100, 100a, 100b, 100c, 200) functions as a Schottky barrier diode with the first electrode layer (102, 102g, 102s, 202) as the anode and the second electrode layer (103, 203) as the cathode. The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A6.

[0159] [A8] The side surface of the semiconductor layer (100, 201) and the side surface of the mold layer (106, 206) are flush. The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A7.

[0160] [A9] A metal layer formed of a metal material different from the metal material forming the plating layer (105, 205) is formed on the surface of the plating layer (105, 205). The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A8.

[0161] [A10]A process of forming a first electrode layer (102, 102g, 102s, 202) on a first main surface (101a, 201a) of a semiconductor layer (100, 201); a process of forming a second electrode layer (103, 203) on a second main surface (101b, 201b) of the semiconductor layer (100, 201) that faces away from the first main surface (101a, 201a); a process of forming an insulating film (104, 204) that covers an end portion of the first electrode layer (102, 102g, 102s, 202); a process of forming a plating layer (105, 205) that covers at least a part of the first electrode layer (102, 102g, 102s, 202) other than the end portion; and a process of forming a mold layer (106, 206) that covers the insulating film (104, 204). A method for manufacturing a semiconductor device (100, 100a, 100b, 100c, 200).

[0162] [A11]The process of forming the mold layer (106, 206) that covers the insulating film (104, 204) includes a process of forming the mold layer (106, 206) so as to cover the plating layer (105, 205), and a process of grinding the surface of the mold layer (106, 206) so that the plating layer (105, 205) is exposed. A method for manufacturing a semiconductor device (100, 100a, 100b, 100c, 200) according to A10.

[0163] [B1]A semiconductor device (100, 100a, 100b, 100c, 200) including a semiconductor layer (101, 201) having a main surface (101a, 201a), a main surface electrode (102, 102g, 102s, 202) disposed on the main surface (101a, 201a), an insulating film (104, 204) that partially covers the main surface electrode (102, 102g, 102s, 202) so as to expose a part of the main surface electrode (102, 102g, 102s, 202), a mold layer (106, 206) that covers the insulating film (104, 204) so as to expose the main surface electrode (102, 102g, 102s, 202), and a pad electrode (105, 105c, 105g, 105s, 105t, 205) disposed on the main surface electrode (102, 102g, 102s, 202) so as to be electrically connected to the main surface electrode (102, 102g, 102s, 202).

[0164] [B2] The semiconductor device (100, 100a, 100b, 100c, 200) according to B1, wherein the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are in contact with the mold layers (106, 206).

[0165] [B3] The semiconductor device (100, 100a, 100b, 100c, 200) according to B1 or B2, wherein the insulating film (104, 204) covers the peripheral portion of the main surface electrode (102, 102g, 102s, 202) so as to expose the inner portion of the main surface electrode (102, 102g, 102s, 202), the mold layer (106, 206) covers the peripheral portion of the main surface electrode (102, 102g, 102s, 202) with the insulating film (104, 204) interposed therebetween so as to expose the inner portion of the main surface electrode (102, 102g, 102s, 202), and the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are disposed on the inner portion of the main surface electrode (102, 102g, 102s, 202).

[0166] [B4] The semiconductor device (100, 100a, 100b, 100c, 200) according to B3, wherein the mold layer (106, 206) partially exposes the insulating film (104, 204) on the inner portion side of the main surface electrode (102, 102g, 102s, 202), and the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are in contact with the main surface electrode (102, 102g, 102s, 202), the insulating film (104, 204), and the mold layer (106, 206) on the inner portion side of the main surface electrode (102, 102g, 102s, 202).

[0167] [B5] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B4, wherein the insulating film (104, 204) covers the main surface (101a, 201a) with a space inward from the periphery of the main surface (101a, 201a), and the mold layer (106, 206) covers the peripheral portion of the main surface (101a, 201a).

[0168] [B6] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B5, wherein the mold layer (106, 206) is formed in an annular shape surrounding the inner portion of the main surface (101a, 201a) in a plan view.

[0169] [B7] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B6, wherein the semiconductor layer (101, 201) includes a side surface, and the mold layer (106, 206) has a mold side surface continuous with the side surface of the semiconductor layer (101, 201).

[0170] [B8] The semiconductor device (100, 100a, 100b, 100c, 200) according to B7, wherein the side surface of the semiconductor layer (101, 201) is a ground surface, and the mold side surface of the mold layer (106, 206) is a ground surface.

[0171] [B9] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B8, wherein the mold layer (106, 206) has a mold main surface extending along the main surface (101a, 201a).

[0172] [B10] The semiconductor device (100, 100a, 100b, 100c, 200) according to B9, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) has an electrode surface continuous with the mold main surface of the mold layer (106, 206).

[0173] [B11] The semiconductor device (100, 100a, 100b, 100c, 200) according to B10, wherein the mold main surface of the mold layer (106, 206) is a ground surface, and the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205) is a ground surface.

[0174] [B12]The mold layers (106, 206) are thicker than the insulating films (104, 204), and the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are thicker than the insulating films (104, 204). The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B11.

[0175] [B13]The insulating films (104, 204) contain a photosensitive resin, and the mold layers (106, 206) contain a thermosetting resin. The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B12.

[0176] [B14]The pad electrodes (105, 105c, 105g, 105s, 105t, 205) contain a plating layer. The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B13.

[0177] [B15]The semiconductor layers (101, 201) contain a wide bandgap semiconductor. The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B14.

[0178] [B16]The semiconductor layers (101, 201) contain SiC. The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B15.

[0179] A semiconductor device (100, 100a, 100b, 100c, 200) including: a semiconductor layer (101, 201) having a main surface (101a, 201a); main surface electrodes (102, 102g, 102s, 202) disposed on the main surface (101a, 201a); photosensitive resin layers (104, 204) covering the peripheral portions of the main surface electrodes (102, 102g, 102s, 202) so as to expose inner portions of the main surface electrodes (102, 102g, 102s, 202); thermosetting resin layers (106, 206) covering the peripheral portions of the main surface electrodes (102, 102g, 102s, 202) with the photosensitive resin layers (104, 204) interposed therebetween so as to expose the inner portions of the main surface electrodes (102, 102g, 102s, 202); and pad electrodes (105, 105c, 105g, 105s, 105t, 205) disposed on the inner portions of the main surface electrodes (102, 102g, 102s, 202).

[0180] [B18] The semiconductor device (100, 100a, 100b, 100c, 200) according to B17, wherein the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are disposed on the main surface electrodes (102, 102g, 102s, 202) so as to be in contact with the thermosetting resin layers (106, 206), and have electrode surfaces exposed from the thermosetting resin layers (106, 206).

[0181] [B19] The semiconductor device (100, 100a, 100b, 100c, 200) according to B17 or B18, wherein the thermosetting resin layers (106, 206) partially expose the photosensitive resin layers (104, 204) on the inner portion side of the main surface electrodes (102, 102g, 102s, 202), and the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are in contact with the main surface electrodes (102, 102g, 102s, 202), the photosensitive resin layers (104, 204), and the thermosetting resin layers (106, 206) on the inner portion side of the main surface electrodes (102, 102g, 102s, 202).

[0182] [B20]The semiconductor layers (101, 201) are semiconductor devices (100, 100a, 100b, 100c, 200) according to any one of B17 to B19, including SiC.

[0183] [C1]A semiconductor device including a semiconductor layer having a main surface and side surfaces, a main surface electrode disposed on the main surface, an insulating film covering a peripheral portion of the main surface electrode so as to expose a part of the main surface electrode, a mold layer covering the peripheral portion of the main surface electrode with the insulating film interposed therebetween so as to expose the main surface electrode, and a pad electrode disposed on the main surface electrode so as to be electrically connected to the main surface electrode, wherein a peripheral portion of the main surface electrode, an outer end portion of the insulating film, and an outer end surface of the mold layer are arranged in this order from an inner portion of the main surface toward the side surfaces, and the outer end surface of the mold layer is flush with the side surfaces.

[0184] [C2]The semiconductor device according to C1, wherein the pad electrode is in contact with the mold layer.

[0185] [C3]The semiconductor device according to C1 or C2, wherein the insulating film covers the peripheral portion of the main surface electrode so as to expose an inner portion of the main surface electrode, the mold layer covers the peripheral portion of the main surface electrode with the insulating film interposed therebetween so as to expose an inner portion of the main surface electrode, and the pad electrode is disposed on the inner portion of the main surface electrode.

[0186] [C4]The mold layer partially exposes the insulating film on the inner portion side of the main surface electrode. The semiconductor device according to C3, wherein the pad electrode is in contact with the main surface electrode, the insulating film, and the mold layer on the inner portion side of the main surface electrode.

[0187] [C5]The semiconductor device according to any one of C1 to C4, wherein the insulating film covers the main surface with a space from the periphery of the main surface inward, and the mold layer covers the peripheral portion of the main surface.

[0188] [C6] The semiconductor device according to any one of C1 to C5, wherein the mold layer is formed in an annular shape surrounding the inner part of the main surface in a plan view.

[0189] [C7] The semiconductor device according to any one of C1 to C6, wherein the mold layer has a mold side surface continuous with the side surface of the semiconductor layer.

[0190] [C8] The semiconductor device according to C7, wherein the side surface of the semiconductor layer is a ground surface, and the mold side surface of the mold layer is a ground surface.

[0191] [C9] The semiconductor device according to any one of C1 to C8, wherein the mold layer has a mold main surface extending along the main surface.

[0192] [C10] The semiconductor device according to C9, wherein the pad electrode has an electrode surface continuous with the mold main surface of the mold layer.

[0193] [C11] The semiconductor device according to C10, wherein the mold main surface of the mold layer is a ground surface, and the electrode surface of the pad electrode is a ground surface.

[0194] [C12] The semiconductor device according to any one of C1 to C11, wherein the mold layer is thicker than the insulating film, and the pad electrode is thicker than the insulating film.

[0195] [C13] The semiconductor device according to any one of C1 to C12, wherein the insulating film contains a photosensitive resin, and the mold layer contains a thermosetting resin.

[0196] [C14] The semiconductor device according to any one of C1 to C13, wherein the pad electrode contains a plating layer.

[0197] [C15] The semiconductor device according to any one of C1 to C14, wherein the semiconductor layer contains a wide bandgap semiconductor.

Explanation of Reference Numerals

[0198] 100 Semiconductor device 100a Semiconductor device 100b Semiconductor device 100c Semiconductor device 101 Semiconductor layer 101a First main surface (main surface) 102 First electrode layer (main surface electrode) 102g First electrode layer (main surface electrode) 102s First electrode layer (main surface electrode) 104 Insulating film (photosensitive resin layer) 105 Plating layer (pad electrode) 105c Pad for current sense (pad electrode) 105g Gate pad (pad electrode) 105s Source pad (pad electrode) 105t Pad for temperature sense (pad electrode) 106 Mold layer (thermosetting resin layer) 200 Semiconductor device 201 Semiconductor layer 201a First main surface (main surface) 202 First electrode layer (main surface electrode) 204 Insulating film (photosensitive resin layer) 205 Plating layer (pad electrode) 206 Mold layer (thermosetting resin layer)

Claims

1. A semiconductor layer having a first main surface and a second main surface facing away from the first main surface, a first electrode layer formed on the first main surface, a second electrode layer formed on the second main surface, an insulating film covering an end portion of the first electrode layer, a plating layer covering at least a part of the first electrode layer other than the end portion, and a mold layer covering the insulating film. A semiconductor device.

2. The semiconductor device according to claim 1, wherein in a plan view, the mold layer is annular along an outer peripheral portion of the semiconductor layer.

3. The semiconductor device according to claim 1 or 2, wherein a surface of the plating layer and a surface of the mold layer are flush.

4. The semiconductor device according to any one of claims 1 to 3, wherein the plating layer and the mold layer are in direct contact.

5. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor layer is formed of SiC.

6. The semiconductor device functions as a transistor, the second electrode layer is a drain electrode of the transistor, and the first electrode layer includes a source electrode of the transistor and a gate electrode of the transistor insulated from the source electrode. The semiconductor device according to any one of claims 1 to 5.

7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device functions as a Schottky barrier diode having the first electrode layer and the second electrode layer as an anode and a cathode, respectively.

8. The semiconductor device according to any one of claims 1 to 7, wherein a side surface of the semiconductor layer and a side surface of the mold layer are flush.

9. The semiconductor device according to any one of claims 1 to 8, wherein a metal layer formed of a metal material different from the metal material forming the plating layer is formed on a surface of the plating layer.

10. A step of forming a first electrode layer on a first main surface of a semiconductor layer, a step of forming a second electrode layer on a second main surface of the semiconductor layer facing away from the first main surface, a step of forming an insulating film covering an end portion of the first electrode layer, a step of forming a plating layer covering at least a part of the first electrode layer other than the end portion, and a step of forming a mold layer covering the insulating film. A method for manufacturing a semiconductor device.

11. The step of forming the mold layer covering the insulating film includes a step of forming the mold layer so as to cover the plating layer. The method of manufacturing a semiconductor device according to claim 10, comprising a step of grinding the surface of the mold layer so that the plating layer is exposed.

Images