Semiconductor device

Abstract

To provide a semiconductor device that is improved in reliability.SOLUTION: A semiconductor device includes: a semiconductor layer which has a main surface; an active region which is provided on the semiconductor layer; a non-active region which is provided in a region of the semiconductor layer outside the active region; a plurality of gate structures which is formed in the active region; an insulating layer which is formed on the main surface such as to cover the plurality of gate structures; a gate main electrode which is arranged on the insulating layer such as to be electrically connected to the plurality of gate structures and overlaps with the non-active region in plan view; a current conductive electrode which is arranged on the insulating layer, with an interval kept from the gate main electrode; and a gate pad electrode which is arranged above the gate main electrode and the current conductive electrode such as to be electrically connected to the gate main electrode and overlaps with the active region and the non-active region in plan view.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This application corresponds to Japanese Patent Application No. 2020-082750 filed with the Japan Patent Office on May 8, 2020, and the entire disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a gate pad electrically connected to a gate electrode of an IGBT. Patent Document 2 discloses a technique related to a vertical semiconductor device including a semiconductor layer made of SiC.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The semiconductor device according to Patent Document 1 includes a gate pad for supplying power to a gate electrode. Since wire bonding is performed on the gate pad, a size equal to or larger than a certain value is required. However, the region directly under the gate pad is an inactive region where it cannot operate as a transistor. Therefore, when ensuring the size of the pad, there is a problem that the operating region (active region) that can operate as a transistor becomes narrow.

[0005]

Means for Solving the Problems

[0006] One embodiment of the present invention is a semiconductor device including a vertical transistor, having a first main surface and a second main surface opposite to the first main surface, a semiconductor layer containing SiC as a main component, a control electrode of the vertical transistor provided on the first main surface, a first main electrode of the vertical transistor provided on the first main surface at a distance from the control electrode, a second main electrode of the vertical transistor provided on the second main surface, a first electrode covering a part of the first main surface, a second electrode provided at a distance from the first electrode in a plan view, and a first electrode pad overlapping the first electrode in a plan view and electrically connected to the first electrode, and the first electrode provides a semiconductor device smaller than the first electrode pad in a plan view.

[0007] One embodiment of the present invention provides a semiconductor device including a main surface, a semiconductor layer containing SiC as a main component, a gate structure formed on the main surface, an insulating layer formed on the main surface so as to cover the gate structure, a gate main electrode disposed on the insulating layer and electrically connected to the gate structure, and a gate pad electrode including a connection portion disposed on the gate main electrode so as to be connected to the gate main electrode and having a first area connected to the gate main electrode in a plan view and an electrode surface having a second area exceeding the first area in a plan view.

[0008] One embodiment of the present invention provides a semiconductor device including a semiconductor layer having a main surface, an active region provided in the semiconductor layer, a non-active region provided in a region outside the active region in the semiconductor layer, a plurality of gate structures formed in the active region, an insulating layer formed on the main surface so as to cover the plurality of gate structures, a gate main electrode disposed on the insulating layer so as to be electrically connected to the plurality of gate structures and overlapping the non-active region in plan view, and a gate pad electrode disposed above the gate main electrode so as to be electrically connected to the gate main electrode and overlapping the active region and the non-active region in plan view. The semiconductor device may further include a current conducting electrode disposed on the insulating layer at a distance from the gate main electrode. The gate pad electrode may be disposed above the gate main electrode and the current conducting electrode.

[0009] The above-described, or further other objects, features, and effects of the present invention will become apparent from the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. Each of the embodiments described below shows comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement positions of the components, connection forms of the components, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present invention. Among the components in the following embodiments, the components not described in the independent claims are described as optional components.

[0012] Each of the accompanying drawings is a schematic diagram and is not necessarily drawn precisely. Therefore, for example, scales etc. in the accompanying drawings do not necessarily match. In the accompanying drawings, substantially the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted or simplified.

[0013] In this specification, terms indicating relationships between elements such as vertical and orthogonal, terms indicating the shapes of elements such as rectangular and cuboid, and numerical ranges are not expressions representing only strict meanings but are expressions meaning including substantially equivalent ranges. For example, in the shape of a polygon or a polygonal prism, the vertices may be rounded.

[0014] In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by the relative positional relationship based on the stacking order in the stacked structure. Specifically, one main surface side of the semiconductor layer is described as the upper side (above), and the other main surface side is described as the lower side (below). When the semiconductor device (vertical transistor) is actually used, the first main surface side may be the lower side (below), and the second main surface side may be the upper side (above). Alternatively, the semiconductor device (vertical transistor) may be used in a posture where the first main surface and the second main surface are inclined or orthogonal to the horizontal plane.

[0015] Also, the terms "upper" and "lower" are applicable not only when the two components are spaced apart from each other with another component intervening between them, but also when the two components are arranged in close contact with each other.

[0016] In this specification and the drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional orthogonal coordinate system. Also, in this specification, the "stacking direction" means the direction orthogonal to the main surface of the semiconductor layer. Also, "plan view" means when viewed from a direction perpendicular to the first main surface of the semiconductor layer.

[0017] FIG. 1 is a cross-sectional view showing a vertical transistor 2 included in a semiconductor device 1 according to the first embodiment. In FIG. 1, for the sake of clarity of the drawing, the cross-section of the semiconductor layer 10 is not shaded.

[0018] The semiconductor device 1 shown in FIG. 1 is an example of a switching device and includes a vertical transistor 2. The vertical transistor 2 is, for example, a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). As shown in FIG. 1, the semiconductor device 1 includes a semiconductor layer 10, a gate electrode 20, a source electrode 30, and a drain electrode 40.

[0019] The semiconductor device 1 includes a semiconductor layer 10 containing SiC (silicon carbide) as an example of a wide bandgap semiconductor as a main component. Specifically, the semiconductor layer 10 is an n-type SiC semiconductor layer containing a SiC single crystal. The SiC single crystal is, for example, a 4H-SiC single crystal. The 4H-SiC single crystal has an off angle inclined at an angle within 10° with respect to the [11-20] direction from the (0001) plane. The off angle may be 0° or more and 4° or less. The off angle may exceed 0° and be less than 4°. The off angle is set, for example, to 2° or 4°, or in the range of 2°±0.2° or 4°±0.4°.

[0020] In this embodiment, the semiconductor layer 10 is formed in a rectangular parallelepiped chip shape. The semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side. In this embodiment, the semiconductor layer 10 has a semiconductor substrate 13 and an epitaxial layer 14. The semiconductor substrate 13 is formed as an n + -type drain region. The epitaxial layer 14 is formed as an n - -type drain drift region.

[0021] The semiconductor substrate 13 contains a SiC single crystal. The lower surface of the semiconductor substrate 13 is the second main surface 12. The second main surface 12 is a carbon plane (000-1) plane where carbon of the SiC crystal is exposed. The epitaxial layer 14 is laminated on the upper surface of the semiconductor substrate 13 and is an n - -type SiC semiconductor layer containing a SiC single crystal. The upper surface of the epitaxial layer 14 is the first main surface 11. The first main surface 11 is a silicon plane (0001) plane where silicon of the SiC crystal is exposed.

[0022] The n-type impurity concentration of the semiconductor substrate 13 is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3The following holds. In this specification, "impurity concentration" means the peak value of the impurity concentration. The n-type impurity concentration of the epitaxial layer 14 is lower than the n-type impurity concentration of the semiconductor substrate 13. The n-type impurity concentration of the epitaxial layer 14 is, for example, 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less.

[0023] The thickness of the semiconductor substrate 13 is, for example, 1 μm or more and less than 1000 μm. The thickness of the semiconductor substrate 13 may be 5 μm or more. The thickness of the semiconductor substrate 13 may be 25 μm or more. The thickness of the semiconductor substrate 13 may be 50 μm or more. The thickness of the semiconductor substrate 13 may be 100 μm or more.

[0024] The thickness of the semiconductor substrate 13 may be 700 μm or less. The thickness of the semiconductor substrate 13 may be 500 μm or less. The thickness of the semiconductor substrate 13 may be 400 μm or less. The thickness of the semiconductor substrate 13 may be 300 μm or less. The thickness of the semiconductor substrate 13 may be 250 μm or less. The thickness of the semiconductor substrate 13 may be 200 μm or less. The thickness of the semiconductor substrate 13 may be 150 μm or less. The thickness of the semiconductor substrate 13 may be 100 μm or less. In the vertical transistor 2, current flows in the thickness direction (i.e., the stacking direction) of the semiconductor substrate 13. Therefore, by reducing the thickness of the semiconductor substrate 13, a reduction in the resistance value due to shortening of the current path can be achieved.

[0025] The thickness of the epitaxial layer 14 is, for example, 1 μm or more and 100 μm or less. The thickness of the epitaxial layer 14 may be 5 μm or more. The thickness of the epitaxial layer 14 may be 10 μm or more. The thickness of the epitaxial layer 14 may be 50 μm or less. The thickness of the epitaxial layer 14 may be 40 μm or less. The thickness of the epitaxial layer 14 may be 30 μm or less. The thickness of the epitaxial layer 14 may be 20 μm or less. The thickness of the epitaxial layer 14 may be 15 μm or less. The thickness of the epitaxial layer 14 may be 10 μm or less.

[0026] The semiconductor device 1 includes a plurality of trench gate structures 21 and a plurality of trench source structures 31 respectively formed on the first main surface 11 of the semiconductor layer 10. The trench gate structures 21 and the trench source structures 31 are alternately and repeatedly arranged one by one along the x-axis direction in a plan view, forming a stripe structure. In FIG. 1, only the range where one trench gate structure 21 is sandwiched between two trench source structures 31 is shown.

[0027] Both the trench gate structure 21 and the trench source structure 31 are formed in a strip shape extending along the y-axis direction. For example, the x-axis direction is the [11 - 20] direction, and the y-axis direction is the [1 - 100] direction. The x-axis direction may be the [-1100] direction ([1 - 100] direction). In this case, the y-axis direction may be the [11 - 20] direction. The distance between the trench gate structure 21 and the trench source structure 31 is, for example, 0.3 μm or more and 1.0 μm or less.

[0028] As shown in FIG. 1, the trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20. The gate trench 22 is formed by digging down the first main surface 11 of the semiconductor layer 10 toward the second main surface 12 side. The gate trench 22 has a rectangular cross-sectional shape in the xz cross-section and is a groove-shaped recessed portion extending in a strip shape along the y-axis direction.

[0029] The gate trench 22 may have a length on the order of millimeters in the longitudinal direction (y-axis direction). The gate trench 22 may have a length of, for example, 1 mm or more and 10 mm or less. The length of the gate trench 22 may be 2 mm or more and 5 mm or less. The total extension of one or more gate trenches 22 per unit area may be 0.5 μm / μm2 or more and 0.75 μm / μm2 or less.

[0030] The gate insulating layer 23 is provided in a film shape along the side wall 22a and the bottom wall 22b of the gate trench 22. The gate insulating layer 23 partitions a concave space inside the gate trench 22. The gate insulating layer 23 includes, for example, silicon oxide. The gate insulating layer 23 may contain at least one of impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0031] The thickness of the gate insulating layer 23 is, for example, 0.01 μm or more and 0.5 μm or less. The thickness of the gate insulating layer 23 may be uniform or may vary depending on the site. For example, the gate insulating layer 23 includes a side wall portion 23a and a bottom wall portion 23b. The side wall portion 23a is formed along the side wall 22a of the gate trench 22. The bottom wall portion 23b is formed along the bottom wall 22b of the gate trench 22.

[0032] The thickness of the bottom wall portion 23b may be greater than the thickness of the side wall portion 23a. The thickness of the bottom wall portion 23b is, for example, 0.01 μm or more and 0.2 μm or less. The thickness of the side wall portion 23a is, for example, 0.05 μm or more and 0.5 μm or less. Further, the gate insulating layer 23 may include an upper surface portion formed on the upper surface of the first main surface 11 outside the gate trench 22. The thickness of the upper surface portion may be greater than the thickness of the side wall portion 23a.

[0033] The gate electrode 20 is an example of a control electrode of the vertical transistor 2. The gate electrode 20 is embedded in the gate trench 22. A gate insulating layer 23 is provided between the gate electrode 20 and the side wall 22a and the bottom wall 22b of the gate trench 22. That is, the gate electrode 20 is embedded in a concave space partitioned by the gate insulating layer 23. The gate electrode 20 is, for example, a conductive layer containing conductive polysilicon. The gate electrode 20 may contain at least one of metals such as titanium, nickel, copper, aluminum, silver, gold, tungsten, or conductive metal nitrides such as titanium nitride.

[0034] The width of the trench gate structure 21 is, for example, 0.2 μm or more and 2.0 μm or less. As an example, the width of the trench gate structure 21 may be about 0.4 μm. The depth of the trench gate structure 21 is, for example, 0.5 μm or more and 3.0 μm or less. As an example, the depth of the trench gate structure 21 may be about 1.0 μm.

[0035] The aspect ratio of the trench gate structure 21 is, for example, 0.25 or more and 15.0 or less. The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. In this form, the aspect ratio of the trench gate structure 21 is the same as the aspect ratio of the gate trench 22.

[0036] As shown in FIG. 1, the trench source structure 31 includes a source trench 32, a deep well region 15, a barrier formation layer 33, and a source electrode 30. The source trench 32 is formed by digging down the first main surface 11 of the semiconductor layer 10 toward the second main surface 12 side. The source trench 32 has a rectangular cross-sectional shape in the xz cross-section and is a groove-shaped recess extending in a strip shape along the y-axis direction. In this form, the source trench 32 is deeper than the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located closer to the second main surface 12 side than the bottom wall 22b of the gate trench 22.

[0037] The deep well region 15 is formed in a region along the source trench 32 in the semiconductor layer 10. The deep well region 15 is also referred to as a breakdown voltage holding region. The deep well region 15 is a p - -type semiconductor region. The p-type impurity concentration in the deep well region 15 is, for example, 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The p-type impurity concentration in the deep well region 15 is, for example, higher than the n-type impurity concentration in the epitaxial layer 14.

[0038] The deep well region 15 includes a side wall portion 15a along the side wall 32a of the source trench 32 and a bottom wall portion 15b along the bottom wall 32b of the source trench 32. The thickness (length in the z-axis direction) of the bottom wall portion 15b is, for example, equal to or greater than the thickness (length in the x-axis direction) of the side wall portion 15a. At least a part of the bottom wall portion 15b may be located within the semiconductor substrate 13.

[0039] The source electrode 30 is an example of a first main electrode of the vertical transistor 2. The source electrode 30 is embedded in the source trench 32. The source electrode 30 is, for example, a conductive layer containing conductive polysilicon. The source electrode 30 may be n-type polysilicon doped with n-type impurities or p-type polysilicon doped with p-type impurities. The source electrode 30 may contain at least one of metals such as titanium, nickel, copper, aluminum, silver, gold, tungsten, or conductive metal nitrides such as titanium nitride. The source electrode 30 may be formed of the same material as the gate electrode 20. In this case, the source electrode 30 and the gate electrode 20 are formed in the same process.

[0040] The barrier formation layer 33 is interposed between the source electrode 30 and the source trench 32. The barrier formation layer 33 is formed in a film shape along the side wall 32a and the bottom wall 32b of the source trench 32 between the source electrode 30 and the source trench 32. That is, the source electrode 30 is embedded in the concave space partitioned by the barrier formation layer 33. The barrier formation layer 33 partitions the concave space inside the source trench 32. The barrier formation layer 33 is formed using a material different from that of the source electrode 30. The barrier formation layer 33 has a potential barrier higher than the potential barrier between the source electrode 30 and the deep well region 15.

[0041] The barrier formation layer 33 may be an insulating barrier formation layer. In this case, the barrier formation layer 33 contains at least one of non-doped silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The barrier formation layer 33 may be formed using the same material as the gate insulating layer 23. In this case, the barrier formation layer 33 may have the same film thickness as the gate insulating layer 23. For example, the barrier formation layer 33 and the gate insulating layer 23 may be formed of silicon oxide. In this case, the barrier formation layer 33 and the gate insulating layer 23 are formed simultaneously by a thermal oxidation treatment method.

[0042] The barrier formation layer 33 may be a conductive barrier formation layer. In this case, the barrier formation layer 33 contains at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0043] The width of the trench source structure 31 is, for example, 0.6 μm or more and 2.4 μm or less. As an example, the width of the trench source structure 31 may be about 0.8 μm. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15. The depth of the trench source structure 31 is, for example, 1.5 μm or more and 11 μm or less. As an example, the depth of the trench source structure 31 may be about 2.5 μm.

[0044] The aspect ratio of the trench source structure 31 is larger than the aspect ratio of the trench gate structure 21. The aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31. In this form, the width of the trench source structure 31 is the sum of the width of the source trench 32 and the widths of the side wall portions 15a of the deep well regions 15 located on both sides of the source trench 32. For example, the aspect ratio of the trench source structure 31 is 1.5 or more and 4.0 or less. By increasing the depth of the trench source structure 31, the breakdown voltage holding effect by the super junction (SJ) structure can be enhanced.

[0045] As shown in FIG. 1, the semiconductor device 1 includes a body region 16, a source region 17, and a contact region 18, which are respectively formed in the epitaxial layer 14 of the semiconductor layer 10. The aforementioned deep well region 15, body region 16, source region 17, and contact region 18 may be regarded as components of the epitaxial layer 14.

[0046] The body region 16 is a p-type semiconductor region provided in the surface layer portion of the first main surface 11 of the semiconductor layer 10. The body region 16 is formed in the region between the gate trench 22 and the source trench 32 in a plan view. The body region 16 is formed in a strip shape extending along the y-axis direction in a plan view. The body region 16 is continuous with the deep well region 15. - The p-type impurity concentration of the body region 16 is, for example, 1.0×10

[0047] cm 16 or more and 1.0×10 -3 cm 19 or less. The p-type impurity concentration of the body region 16 may be equal to the impurity region of the deep well region 15. The p-type impurity concentration of the body region 16 may be higher than the p-type impurity concentration of the deep well region 15. -3 The p-type impurity concentration of the body region 16 may be higher than the p-type impurity concentration of the deep well region 15.

[0048] The source region 17 is an n-type semiconductor region provided in the surface layer portion of the first main surface 11 of the semiconductor layer 10 in the body region 16. + The source region 17 is provided in a region along the gate trench 22. The source region 17 is in contact with the gate insulating layer 23 and faces the gate electrode 20 with the gate insulating layer 23 interposed therebetween. Specifically, the source region 17 is in contact with the side wall portion 23a of the gate insulating layer 23. The source region 17 may be in contact with the upper surface portion of the gate insulating layer 23.

[0049] In plan view, the source region 17 is formed in a strip shape extending along the y-axis direction. The width (length in the x-axis direction) of the source region 17 is, for example, 0.2 μm or more and 0.6 μm or less. As an example, the width of the source region 17 may be about 0.4 μm. The n-type impurity concentration of the source region 17 is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0050] The contact region 18 is a p-type semiconductor region provided in the surface layer portion of the first main surface 11 of the semiconductor layer 10. The contact region 18 may be regarded as a part (high concentration portion) of the body region 16. The contact region 18 is formed in a region along the source trench 32. The contact region 18 is in contact with the barrier formation layer 33 and faces the source electrode 30 with the barrier formation layer 33 interposed therebetween. The contact region 18 is electrically connected to the body region 16. The contact region 18 is electrically connected to the source region 17. + In plan view, the contact region 18 is formed in a strip shape extending along the y-axis direction. The width (length in the x-axis direction) of the contact region 18 is, for example, 0.1 μm or more and 0.4 μm or less. As an example, the width of the contact region 18 may be about 0.2 μm. The p-type impurity concentration of the contact region 18 is, for example, 1.0×10

[0051] cm 18 or more and 1.0×10 -3 cm 21 or less.-3 The following is the case.

[0052] The semiconductor device 1 includes a drain electrode 40 connected to the second main surface 12 of the semiconductor layer 10. The drain electrode 40 is an example of the second main electrode of the semiconductor device 1 (vertical transistor 2). The drain electrode 40 may contain at least one of titanium, nickel, copper, aluminum, gold, or silver. For example, the drain electrode 40 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in order from the second main surface 12 of the semiconductor layer 10.

[0053] The drain electrode 40 may have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer laminated in order from the second main surface 12 of the semiconductor layer 10. The AlCu layer is an alloy layer of aluminum and copper. The drain electrode 40 may have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer laminated in order from the second main surface 12 of the semiconductor layer 10. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may include a single-layer structure having a TiN layer instead of the Ti layer, or a laminated structure having a Ti layer and a TiN layer.

[0054] In the semiconductor device 1 configured as described above, an on state in which a drain current flows and an off state in which no drain current flows can be switched according to the gate voltage applied to the gate electrode 20 of the vertical transistor 2. The gate voltage is, for example, a voltage of 10 V or more and 50 V or less. As an example, the gate voltage may be 30 V. The source voltage applied to the source electrode 30 is a reference voltage such as a ground voltage (0 V), for example. The drain voltage applied to the drain electrode 40 is equal to or higher than the source voltage. The drain voltage is, for example, 0 V or more and 10000 V or less. The drain voltage may be 1000 V or more. It may be so.

[0055] When a gate voltage is applied to the gate electrode 20, p -A channel is formed in a portion of the gate insulating layer 23 of the body region 16 of the [[TYPE]]. As a result, a current path is formed between the source electrode 30 and the drain electrode 40 through the channel of the body region 16. The current path connects the contact region 18, the source region 17, the channel of the body region 16, the epitaxial layer 14, and the semiconductor substrate 13 between the source electrode 30 and the drain electrode 40.

[0056] The drain electrode 40 may be at a higher potential than the source electrode 30. In this case, the drain current flows from the drain electrode 40 toward the source electrode 30. That is, the drain current passes through the drain electrode 40, the semiconductor substrate 13, the epitaxial layer 14, the channel of the body region 16, the source region 17, and the contact region 18 in this order and flows into the source electrode 30. Thus, the drain current flows along the thickness direction of the semiconductor device 1.

[0057] In this form, a pn junction is formed between the p - -type deep well region 15 and the n - -type epitaxial layer 14. In the on state of the vertical transistor 2, the source voltage is applied to the p - -type deep well region 15 through the source electrode 30, and a drain voltage higher than the source voltage is applied to the n - -type epitaxial layer 14 through the drain electrode 40.

[0058] That is, a reverse bias voltage is applied to the pn junction between the deep well region 15 and the epitaxial layer 14. Therefore, the depletion layer spreads from the interface (interface) between the deep well region 15 and the epitaxial layer 14 toward the drain electrode 40. Thereby, the breakdown voltage of the vertical transistor 2 can be increased.

[0059] Next, a pad structure for supplying a predetermined voltage to the gate electrode 20 and the source electrode 30 will be described. FIG. 2 is a cross-sectional view of the semiconductor device 1 shown in FIG. 1. FIG. 3 is a plan view of the semiconductor device 1 shown in FIG. 1. Specifically, FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 3. In FIG. 2, illustration of the specific configuration of the semiconductor layer 10 shown in FIG. 1 is omitted. Also, in FIG. 2, hatching representing the cross-section of the semiconductor layer 10 is not provided.

[0060] As shown in FIGS. 2 and 3, the semiconductor device 1 includes a main surface gate electrode 50, a main surface source electrode 55, an insulating layer 60, a gate pad 70, a source pad 75, and a mold layer 80. The pad structure is provided above the first main surface 11 of the semiconductor layer 10.

[0061] FIG. 4 is a plan view taken along line IV-IV shown in FIG. 2. Specifically, FIG. 4 is a plan view of the semiconductor device 1 as viewed from the positive side of the z-axis, looking through the gate pad 70, the source pad 75, and the mold layer 80 shown in FIG. 3. For example, the positive side of the z-axis is the side of the first main surface 11 when it is assumed that the second main surface 12 (or the surface of the drain electrode 40) is located on the xy plane where z = 0. FIG. 5 is a plan view of the semiconductor device 1 as viewed from the positive side of the z-axis, looking through the main surface gate electrode 50, the main surface source electrode 55, and the insulating layer 60 shown in FIG. 4 respectively, and the gate pad 70, the source pad 75, and the mold layer 80 shown in FIG. 3 respectively.

[0062] As shown in FIGS. 3 to 5, the semiconductor layer 10 (semiconductor device 1) has a rectangular shape in plan view. In plan view, the length of one side of the semiconductor layer 10 (semiconductor device 1) is, for example, 1 mm or more and 10 mm or less. In plan view, the length of one side of the semiconductor layer 10 (semiconductor device 1) may be 2 mm or more and 5 mm or less.

[0063] The semiconductor device 1 includes an active region 3 and an inactive region 4 (outer region). The active region 3 is indicated by a two-dot chain line in FIGS. 3 and 5. The active region 3 is the main region where the drain current of the vertical transistor 2 flows. That is, the active region 3 is the operating region of the vertical transistor 2. Specifically, the active region 3 substantially coincides with the region covered by the main surface source electrode 55.

[0064] In this form, the active region 3 is separated in a plan view into a region on one side (left side of the paper) in the x-axis direction of the semiconductor layer 10 and a region on the other side (right side of the paper) in the x-axis direction. In the active region 3, the planar area of the region on one side (left side of the paper) may be different from the planar area of the region on the other side (right side of the paper). In this form, an example is shown in which the planar area of the region on one side (left side of the paper) is less than the planar area of the region on the other side (right side of the paper).

[0065] As shown in FIG. 5, the active region 3 includes a plurality of gate electrodes 20 (trench gate structure 21) and a plurality of source electrodes 30 (trench source structure 31). In FIG. 5, the plurality of gate electrodes 20 and the plurality of source electrodes 30 are schematically illustrated to the extent that the number of the gate electrodes 20 and the source electrodes 30 can be counted. However, the actual number of the gate electrodes 20 and the source electrodes 30 is much larger than the number shown.

[0066] The inactive region 4 is a region that does not operate as the vertical transistor 2. The inactive region 4 is a frame-shaped (annular) region surrounding the active region 3. In this form, the inactive region 4 separates the active region 3 into a region on one side (left side of the paper) and a region on the other side (right side of the paper). That is, the inactive region 4 surrounds the region on one side (left side of the paper) of the active region 3 in a plan view. Also, the inactive region 4 surrounds the region on one side (left side of the paper) of the active region 3 in a plan view.

[0067] As shown in FIG. 5, a gate finger portion 20b described later is provided in the non-active region 4. In the examples shown in FIGS. 3 to 5, the active region 3 is divided into two by the non-active region 4, but the active region 3 may be a single undivided region. The shape and arrangement of the active region 3 can be appropriately adjusted according to the layout of the gate finger portion 20b.

[0068] As shown in FIG. 4, the active region 3 is included in the region covered by the main surface source electrode 55. As shown in FIG. 3, the active region 3 includes a part of the region covered by the gate pad 70. The region covered by the main surface gate electrode 50 is included in the non-active region 4 and not included in the active region 3.

[0069] The main surface gate electrode 50 is an example of a first electrode that covers a part of the first main surface 11. The main surface gate electrode 50 includes at least one of, for example, metals such as conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or metal nitrides such as titanium nitride. The main surface gate electrode 50 may be formed using the same material as the gate electrode 20.

[0070] The main surface gate electrode 50 is electrically connected to the gate electrode 20. As shown in FIG. 2, the main surface gate electrode 50 is provided in a line shape on the insulating layer 60 (specifically, the lower insulating layer 61 described later). The main surface gate electrode 50 is connected to the gate electrode 20 (not shown in FIG. 2) via a via conductor that penetrates the insulating layer 60 (specifically, the lower insulating layer 61).

[0071] As shown in FIG. 4, the main surface gate electrode 50 includes a power receiving portion 50a, a power supply portion 50b, and a connection portion 50c. The power receiving portion 50a of the main surface gate electrode 50 is provided in the inner part of the first main surface 11 in a plan view. Specifically, the power receiving portion 50a is provided on a region located between the region on one side (left side of the paper surface) and the region on the other side (right side of the paper surface) of the active region 3 in the non-active region 4 in a plan view.

[0072] The power receiving portion 50a is located directly below the gate pad 70 described later and is a portion connected to the gate pad 70 (specifically, the columnar portion 71 described later). In a plan view, the portion of the main surface gate electrode 50 that overlaps the columnar portion 71 corresponds to the power receiving portion 50a. The power receiving portion 50a of the main surface gate electrode 50 is smaller than the gate pad 70 in a plan view. The shape of the power receiving portion 50a in a plan view (the shape of the columnar portion 71 in a plan view) is, for example, a square or a rectangle. The length of one side of the power receiving portion 50a is 5 μm or more and 50 μm or less. As an example, the shape of the power receiving portion 50a in a plan view may be a square of about 20 μm × 20 μm.

[0073] The power supply portion 50b is a portion that extends along the outer periphery of the semiconductor layer 10 (the periphery of the first main surface 11) in a plan view. In the example shown in FIG. 4, the power supply portion 50b extends along the x-axis direction of the semiconductor layer 10. In this form, two power supply portions 50b are provided so as to sandwich the inner portion of the first main surface 11 from the positive side and the negative side in the y-axis direction in a plan view. The power supply portion 50b may be provided so as to surround the inner portion of the first main surface 11 (for example, the main surface source electrode 55 described later) over the entire circumference of the semiconductor layer 10.

[0074] The connection portion 50c is a portion connected to the power receiving portion 50a and the power supply portion 50b. In the example shown in FIG. 4, the connection portion 50c is drawn out from the power receiving portion 50a to the positive side and the negative side in the y-axis direction so as to be connected to the power supply portion 50b and extends to the power supply portion 50b. The region where the power receiving portion 50a, the power supply portion 50b, and the connection portion 50c are provided becomes the non-active region 4. Therefore, it is desirable that the power receiving portion 50a, the power supply portion 50b, and the connection portion 50c be formed as small as possible.

[0075] In this form, the main surface gate electrode 50 is electrically connected to each of the plurality of gate electrodes 20 via the power supply portion 50b. Specifically, a through hole is provided in an insulating layer 60 described later (specifically, a lower insulating layer 61 described later) located directly below the power supply portion 50b, and the power supply portion 50b is connected to a gate finger portion 20b (see FIG. 5) described later through the through hole.

[0076] As shown in FIG. 5, the plurality of gate electrodes 20 (trench gate structures 21) are formed in an elongated shape extending in the y-axis direction. The plurality of gate electrodes 20 may be divided into a positive-side portion and a negative-side portion in the y-axis direction at the central portion in the y-axis direction.

[0077] As shown in FIG. 5, the semiconductor device 1 includes a gate finger portion 20b formed on the semiconductor layer 10 (first main surface 11) so as to be electrically connected to the plurality of gate electrodes 20. Specifically, the gate finger portion 20b is interposed between the semiconductor layer 10 (first main surface 11) and an insulating layer 60 described later. The gate finger portion 20b extends in the x-axis direction along the periphery of the first main surface 11 (the outer periphery of the semiconductor device 1) in a plan view.

[0078] In this form, two gate finger portions 20b are provided so as to sandwich the plurality of gate electrodes 20 from the positive side and the negative side in the y-axis direction in a plan view. The gate finger portion 20b is connected to both ends of the plurality of gate electrodes 20 in the y-axis direction. The gate finger portion 20b may be connected to only one end of the plurality of gate electrodes 20 in the y-axis direction. The power supply portion 50b described above is connected to the gate finger portion 20b through a through hole provided in an insulating layer 60 described later (specifically, a lower insulating layer 61 described later).

[0079] The main surface source electrode 55 is an example of a second electrode that covers a part of the first main surface 11. The main surface source electrode 55 is provided at an interval from the main surface gate electrode 50 in a plan view. The main surface source electrode 55 is formed, for example, in substantially the entire region of the first main surface 11 of the semiconductor layer 10 (semiconductor device 1) excluding the region where the main surface gate electrode 50 is provided and the periphery of the region in a plan view. In a plan view, the main surface source electrode 55 is larger than the main surface gate electrode 50.

[0080] Specifically, the main surface source electrode 55 includes a first portion disposed on the region on one side (left side in the drawing) of the active region 3 and a second portion separated from the first portion and disposed on the region on the other side (right side in the drawing) of the active region 3. The planar area of the second portion is larger than the first planar area of the first portion. The total value of the planar area of the first portion and the planar area of the second portion is larger than the planar area of the main surface gate electrode 50.

[0081] The main surface source electrode 55 includes at least one of, for example, metals such as conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or metal nitrides such as titanium nitride. The main surface source electrode 55 may be formed using the same material as the source electrode 30. The main surface source electrode 55 may be formed using the same material as the main surface gate electrode 50. In this case, the main surface gate electrode 50 and the main surface source electrode 55 can be formed in the same process.

[0082] A plurality of source electrodes 30 are provided directly under the main surface source electrode 55, and the main surface source electrode 55 is electrically connected to the source electrodes 30. Therefore, as shown in FIG. 1, the main surface source electrode 55 is directly connected to the upper surfaces of the plurality of source electrodes 30 respectively. As shown in FIG. 2, the lower part of the main surface source electrode 55 is the active region 3, and the MOSFET structure shown in FIG. 1 is periodically formed in the active region 3.

[0083] In plan view, the main surface source electrode 55 has an area of 50% or more of the area of the semiconductor layer 10 (the first main surface 11). Preferably, in plan view, the main surface source electrode 55 has an area of 70% or more of the area of the semiconductor layer 10 (the first main surface 11). On the other hand, in plan view, the main surface gate electrode 50 has an area of 20% or less of the area of the semiconductor layer 10 (the first main surface 11). Preferably, in plan view, the main surface gate electrode 50 has an area of 10% or less of the area of the semiconductor layer 10 (the first main surface 11).

[0084] The main surface source electrode 55 is disposed in a region including the central position of the semiconductor layer 10 (the first main surface 11) in a plan view. The main surface gate electrode 50 is disposed in a region avoiding the main surface source electrode 55. The main surface gate electrode 50 may be disposed in a region including the central position of the semiconductor layer 10 (the first main surface 11). In this case, the main surface source electrode 55 may be disposed so as to surround the periphery of the main surface gate electrode 50.

[0085] As shown in FIG. 2, the insulating layer 60 includes a lower insulating layer 61, side insulating layers 62, an upper insulating layer 63, and end insulating layers 65. In FIG. 4, the unshaded portions around the main surface gate electrode 50 correspond to the side insulating layers 62 and the end insulating layers 65. The lower insulating layer 61 is an interlayer insulating film and is provided on the first main surface 11. Specifically, the lower insulating layer 61 collectively covers the plurality of trench gate structures 21. As shown in FIG. 1, the lower insulating layer 61 is provided to prevent contact between the main surface source electrode 55 and the gate electrode 20.

[0086] The lower insulating layer 61 has a plurality of source contact holes 61b. A part of the main surface source electrode 55 is filled in the plurality of source contact holes 61b. Thereby, the main surface source electrode 55 is electrically connected to the plurality of source electrodes 30 in the plurality of source contact holes 61b.

[0087] Although not shown in FIG. 2, as described above, the lower insulating layer 61 is provided with a through hole for connecting the power supply portion 50b (see FIG. 4) of the main surface gate electrode 50 to the gate finger portion 20b (see FIG. 5). A part of the power supply portion 50b is filled in the through hole of the lower insulating layer 61. The power supply portion 50b is connected to the gate finger portion 20b in the through hole. Thereby, the main surface gate electrode 50 is electrically connected to the gate electrode 20.

[0088] The side insulating layer 62 is formed on the lower insulating layer 61 and provided to prevent contact between the main surface gate electrode 50 and the main surface source electrode 55. As shown in FIG. 4, the side insulating layer 62 is provided so as to surround the main surface gate electrode 50.

[0089] The upper insulating layer 63 is formed on the upper surface 56 of the main surface source electrode 55. Specifically, the upper insulating layer 63 covers a portion along the power receiving portion 50a of the main surface gate electrode 50 on the main surface source electrode 55. The upper insulating layer 63 covers a part of the power receiving portion 50a so as to partially expose the upper surface 52 of the power receiving portion 50a. That is, the upper insulating layer 63 has a through hole 64 that exposes the upper surface 52 of the power receiving portion 50a. As shown in FIG. 2, a part of the upper insulating layer 63 rides up from above the lower insulating layer 61 onto the power receiving portion 50a.

[0090] More specifically, the upper insulating layer 63 includes a flat portion 63a, a first end portion 63b, and a second end portion 63c. The flat portion 63a is provided on the upper surface 56 of the main surface source electrode 55 and is a portion having a substantially uniform thickness. A part of the flat portion 63a is also provided on the upper surface 52 of the power receiving portion 50a.

[0091] The first end portion 63b is provided on the upper surface 52 of the power receiving portion 50a of the main surface gate electrode 50. The second end portion 63c is provided on the upper surface 56 of the main surface source electrode 55. The first end portion 63b and the second end portion 63c are each a portion having a non-uniform thickness. The first end portion 63b and the second end portion 63c are each inclined, for example, so that the thickness gradually decreases. The first end portion 63b and the second end portion 63c may have an inclined surface having a certain inclination angle, or may have a curved surface that is convex or concave.

[0092] In plan view, the size and shape of the through hole 64 substantially match the size and shape of the power receiving portion 50a of the main surface gate electrode 50. Specifically, in plan view, the size of the through hole 64 is smaller than the power receiving portion 50a because a part of the upper insulating layer 63 rides up on the power receiving portion 50a.

[0093] The end insulating layer 65 is provided on the first main surface 11 along the outer periphery of the main surface source electrode 55. For example, the end insulating layer 65 is formed in an annular shape so as to cover the entire circumference of the main surface source electrode 55 in plan view. As shown in FIG. 2, the end insulating layer 65 has a portion that rides on the lower insulating layer 61 and an electrode covering portion that rides on the main surface source electrode 55 (upper surface 56).

[0094] The electrode covering portion of the end insulating layer 65 has a flat portion 65a and an end portion 65b. The flat portion 65a is a portion having a substantially uniform thickness. The end portion 65b is a portion having a non-uniform thickness. The end portion 65b is inclined, for example, such that the thickness gradually decreases. The end portion 65b may have an inclined surface having a constant inclination angle, or may have a curved surface that is convex or concave. The end insulating layer 65 may cover the power supply portion 50b of the main surface gate electrode 50 shown in FIG. 4.

[0095] The lower insulating layer 61 contains, for example, silicon oxide or silicon nitride as a main component. The lower insulating layer 61, the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

[0096] The side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may each contain a photosensitive resin. The side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may each be made of an organic material such as polyimide or PBO (polybenzoxazole). The thickness of the upper insulating layer 63 and the end insulating layer 65 is, for example, 3 μm or more and 20 μm or less. The thickness of the upper insulating layer 63 and the end insulating layer 65 may preferably be 5 μm or more and 15 μm or less. The thickness of the upper insulating layer 63 and the end insulating layer 65 may more preferably be 5 μm or more and 10 μm or less. The lower insulating layer 61, the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may be formed of the same insulating material (for example, an inorganic insulating material such as silicon oxide or silicon nitride).

[0097] The gate pad 70 is an example of a first electrode pad. In plan view, the gate pad 70 overlaps the main surface gate electrode 50 and is electrically connected to the main surface gate electrode 50. The gate pad 70 completely covers the power receiving portion 50a of the main surface gate electrode 50. That is, in plan view, the power receiving portion 50a of the main surface gate electrode 50 is located inside the gate pad 70.

[0098] In plan view, the gate pad 70 overlaps a part of the main surface source electrode 55. That is, a part of the main surface source electrode 55 is located directly below the gate pad 70. In this configuration, since the main surface source electrode 55 is drawn out to the region overlapping the gate pad 70 in plan view, a part of the region where the gate pad 70 overlaps the main surface source electrode 55 can be used as the active region 3. Thereby, while securing the area of the gate pad 70, more area of the active region 3 can be secured.

[0099] As shown in FIG. 2, the gate pad 70 includes a columnar portion 71 and a wide portion 72. The columnar portion 71 is an example of a first conductive layer provided on the main surface gate electrode 50. The columnar portion 71 extends in a columnar shape in the normal direction (z-axis direction) of the upper surface 52 of the power receiving portion 50a of the main surface gate electrode 50.

[0100] The columnar portion 71 covers the upper surface 52 of the power receiving portion 50a. The columnar portion 71 further covers a part of the flat portion 63a and the first end portion 63b of the upper insulating layer 63. The height (length in the z-axis direction) of the columnar portion 71 is greater (longer) than the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 71 is greater (longer) than the maximum thickness of the portion of the upper insulating layer 63 located on the power receiving portion 50a. As a result, the topmost portion of the columnar portion 71 is higher than the topmost portion of the upper insulating layer 63.

[0101] The columnar portion 71 has a side surface 74 that extends vertically or substantially vertically. The side surface 74 does not necessarily have to extend linearly in a cross-sectional view and may extend in a curved shape or an uneven shape. The side surface 74 is located above the region where the power receiving portion 50a and the upper insulating layer 63 overlap in a plan view. Specifically, the side surface 74 is located on the flat portion 63a of the upper insulating layer 63. That is, the columnar portion 71 covers the power receiving portion 50a and the upper insulating layer 63. By positioning the side surface 74 on the flat portion 63a, the columnar portion 71 can be formed more stably compared to the case where it is positioned on the first end portion 63b where the thickness variation is relatively large.

[0102] The wide portion 72 is an example of a second conductive layer provided at the upper end of the columnar portion 71. The wide portion 72 is a portion where the size of the upper end of the columnar portion 71 is enlarged in the xy plane. The size and shape of the wide portion 72 in a plan view match the size and shape of the gate pad 70 in a plan view. In a plan view, the wide portion 72 is larger than the columnar portion 71. In a plan view, the columnar portion 71 is located inside the wide portion 72.

[0103] In a plan view, the contour of the wide portion 72 is formed at a certain interval from the contour of the columnar portion 71 toward the peripheral side of the semiconductor layer 10. The wide portion 72 (gate pad 70) overlaps a part of the active region 3 and the non-active region 4 in a plan view. That is, the wide portion 72 (gate pad 70) overlaps the trench gate structure 21 and the trench source structure 31 in a plan view.

[0104] The wide portion 72 has an upper surface 73 that is used for electrical connection between the semiconductor device 1 (vertical transistor 2) and other circuits. In this form, the upper surface 73 of the wide portion 72 is formed in an island shape in plan view and is connected to a power supply circuit that supplies a gate voltage. That is, the gate pad 70 is not formed in a line shape in this form, unlike the main surface gate electrode 50. For example, a metal wire is connected to the upper surface 73 of the wide portion 72 by wire bonding. The metal wire contains at least one kind of metal such as aluminum, copper, or gold. In this form, an aluminum wire is wedge-bonded to the gate pad (the upper surface 73 of the wide portion 72). bonded.

[0105] In order to perform wire bonding appropriately, the wide portion 72 needs to have a size of a certain level or more. The shape of the wide portion 72 in plan view is, for example, square. In this case, the size of the wide portion 72 may be, for example, 800 μm × 800 μm or more and 1 mm × 1 mm or less. In this case, the connection direction of the metal wire to the wide portion 72 can be set in any direction. Of course, the size of the wide portion 72 may be larger than 1 mm × 1 mm. Also, the shape of the wide portion 72 in plan view may be rectangular. In this case, the size of the wide portion 72 may be 400 μm × 800 μm or more.

[0106] In plan view, the area of the wide portion 72 (that is, the area of the gate pad 70) is larger than the area of the power receiving portion 50a of the main surface gate electrode 50. In other words, in plan view, the connection area of the connection portion of the main surface gate electrode 50 and the gate pad 70 is less than the area of the upper surface 73 of the gate pad 70. The area of the wide portion 72 is 200 times or more and 40000 times or less the area of the power receiving portion 50a. The area of the wide portion 72 may be 400 times or more the area of the power receiving portion 50a. As an example, the area of the wide portion 72 may be about 2500 times the area of the power receiving portion 50a.

[0107] The columnar portion 71 contains a metal material such as copper or a copper alloy having copper as a main component. The wide portion 72 contains a metal material such as copper or a copper alloy having copper as a main component. The wide portion 72 is formed using, for example, the same conductive material as the columnar portion 71. The wide portion 72 may be formed of a conductive material different from that of the columnar portion 71.

[0108] The height (length in the z-axis direction) of the gate pad 70 is the sum of the height (length in the z-axis direction) of the columnar portion 71 and the thickness (length in the z-axis direction) of the wide portion 72. The height of the gate pad 70 is, for example, more than 0 mm and 1 mm or less (for example, several tens of μm or more and several hundreds of μm or less). As shown in FIG. 2, the height of the columnar portion 71 is greater (longer) than the thickness of the wide portion 72. The height of the columnar portion 71 may be equal to or less than the thickness of the wide portion 72.

[0109] In plan view, the source pad 75 overlaps the main surface source electrode 55 and is electrically connected to the main surface source electrode 55. The source pad 75 is provided on the main surface source electrode 55. The source pad 75 extends in a thick plate shape in the normal direction (z-axis direction) of the upper surface 56 of the main surface source electrode 55. In plan view, the area of the source pad 75 is smaller than the area of the main surface source electrode 55.

[0110] The source pad 75 covers the upper surface 56 of the main surface source electrode 55. Further, the source pad 75 covers a part of the flat portion 63a and the second end portion 63c of the upper insulating layer 63. Furthermore, the source pad 75 covers a part of the flat portion 65a and the end portion 65b of the end insulating layer 65. The thickness (length in the z-axis direction) of the source pad 75 is greater (longer) than the thickness (length in the z-axis direction) of each of the upper insulating layer 63 and the end insulating layer 65.

[0111] Specifically, the thickness of the source pad 75 is greater (longer) than the maximum thickness of the portion of the upper insulating layer 63 located on the main surface source electrode 55 and the maximum thickness of the portion of the end insulating layer 65 located on the main surface source electrode 55. Thereby, the top of the source pad 75 is higher than the top of the upper insulating layer 63 and the top of the end insulating layer 65.

[0112] The source pad 75 has side surfaces 77 that extend vertically or substantially vertically. The side surfaces 77 do not necessarily have to extend linearly in a cross-sectional view, and may extend in a curved or uneven shape. The side surfaces 77 are located in a region where the main surface source electrode 55 and the upper insulating layer 63 overlap in a plan view, or in a region where the main surface source electrode 55 and the end insulating layer 65 overlap in a plan view.

[0113] Specifically, the side surfaces 77 are located on the flat portions 63a of the upper insulating layer 63 or on the flat portions 65a of the end insulating layer 65. That is, the source pad 75 is in contact with the main surface source electrode 55 and the upper insulating layer 63, or the main surface source electrode 55 and the end insulating layer 65. In this form, the source pad 75 is in contact with the main surface source electrode 55, the upper insulating layer 63, and the end insulating layer 65. Thereby, similar to the case of the columnar portion 71, the source pad 75 can be formed stably.

[0114] The source pad 75 has an upper surface 76 that is used for electrical connection between the semiconductor device 1 (vertical transistor 2) and other circuits. In this form, the upper surface 76 of the source pad 75 is connected to a power supply circuit that supplies a source voltage. For example, a metal wire is connected to the upper surface 76 of the source pad 75 by wire bonding. The metal wire contains at least one kind of metal such as aluminum, copper, gold, etc. In this form, an aluminum wire is wedge-bonded to the source pad 75.

[0115] The source pad 75 is provided at a distance from the gate pad 70 in a plan view. Thereby, a short circuit due to contact between the source pad 75 and the gate pad 70 can be suppressed. The source pad 75 is formed of a conductive material. Specifically, the source pad 75 includes a metal material such as copper or a copper alloy mainly composed of copper. The source pad 75 is formed of, for example, the same material as the gate pad 70. In this case, the source pad 75 can be formed in the same process as the gate pad 70. The source pad 75 may be formed of a material different from that of the gate pad 70.

[0116] The source pad 75 has an area of 50% or more of the area of the semiconductor layer 10 (the first main surface 11) in a plan view. Preferably, the source pad 75 has an area of 70% or more of the area of the semiconductor layer 10 (the first main surface 11) in a plan view. On the other hand, the gate pad 70 has an area of 20% or less of the area of the semiconductor layer 10 (the first main surface 11) in a plan view. Preferably, the gate pad 70 has an area of 10% or less of the area of the semiconductor layer 10 (the first main surface 11) in a plan view.

[0117] The source pad 75 is disposed in a region including the center position of the semiconductor layer 10 (the first main surface 11) in a plan view. The gate pad 70 is disposed in a region avoiding the source pad 75. The gate pad 70 may be disposed in a region including the center position of the semiconductor layer 10 (the first main surface 11). In this case, the source pad 75 may be disposed so as to surround the periphery of the gate pad 70.

[0118] The semiconductor device 1 includes a mold layer 80 filled between the source pad 75 and the gate pad 70. Specifically, the mold layer 80 fills the space between the gate pad 70 and the source pad 75. Also, the mold layer 80 covers the upper insulating layer 63 and the end insulating layer 65. Further, the mold layer 80 is provided in an annular shape along the outer periphery of the semiconductor layer 10 (the periphery of the first main surface 11) in a plan view.

[0119] The mold layer 80 is formed of an insulating material. The mold layer 80 may contain a thermosetting resin. For example, the mold layer 80 contains an epoxy resin. For example, the mold layer 80 may contain an epoxy resin containing carbon, glass fibers, etc. The thickness (length in the z-axis direction) of the mold layer 80 is, for example, more than 0 mm and 1 mm or less (for example, more than several tens of μm and several hundreds of μm or less). The thickness of the mold layer 80 may be greater than the thickness of the semiconductor layer 10.

[0120] In this form, the mold layer 80 has an upper surface 81 formed flush with the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75. That is, no step is formed at each boundary portion between the upper surface 73 of the gate pad 70, the upper surface 76 of the source pad 75, and the upper surface 81 of the mold layer 80. In this case, the upper surface 73 of the gate pad 70 may be a ground surface. Also, the upper surface 76 of the source pad 75 may be a ground surface. Also, the upper surface 81 of the mold layer 80 may be a ground surface. That is, the upper surface 81 of the mold layer 80 may form a single ground surface with the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75.

[0121] Hereinafter, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. FIGS. 6A to 6G are cross-sectional views showing one step of the method for manufacturing the semiconductor device shown in FIG. 1. Hereinafter, the method for manufacturing the structure above the semiconductor layer 10 in particular will be mainly described. Regarding the method for forming the trench gate structure 21, the trench source structure 31, and each well region (each semiconductor region) in the semiconductor layer 10, a known method can be used.

[0122] First, as shown in FIG. 6A, a lower insulating layer 61 is formed on a first main surface 11 of a semiconductor layer 10 (semiconductor wafer). The lower insulating layer 61 has a plurality of source contact holes 61b. For example, in this step, first, an insulating film containing silicon oxide or the like is formed by plasma CVD (Chemical Vapor Deposition). Next, a part of the formed insulating film is removed by photolithography and etching. Thereby, the lower insulating layer 61 having a plurality of source contact holes 61b is formed.

[0123] Next, as shown in FIG. 6B, a main surface gate electrode 50 and a main surface source electrode 55 are formed. For example, in this step, first, a metal film is formed on the entire first main surface 11 so as to cover the lower insulating layer 61 by vapor deposition or sputtering. Next, a part of the formed metal film is removed by photolithography and etching. Thereby, the metal film is patterned, and the main surface gate electrode 50 and the main surface source electrode 55 are formed. The main surface gate electrode 50 and the main surface source electrode 55 may be formed in different steps by repeating a film formation step of a metal film using different materials and a patterning step of the metal film.

[0124] Next, as shown in FIG. 6C, a side insulating layer 62, an upper insulating layer 63, and an end insulating layer 65 are formed. The upper insulating layer 63 has a through hole 64. For example, this step includes a coating step and an exposure and development step. In the coating step, a liquid photosensitive resin material serving as the source of each insulating layer is applied to the upper surface 52 of the main surface gate electrode 50 and the upper surface 56 of the main surface source electrode 55 by spin coating. In the exposure and development step, after the photosensitive resin material is cured by exposure, unnecessary portions of the photosensitive resin material are removed by ashing or wet etching. Thereby, the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 are formed.

[0125] Next, as shown in FIG. 6D, the columnar portion 71 is formed on the power receiving portion 50a of the main surface gate electrode 50, and the lower source pad 75a is formed on the main surface source electrode 55. For example, in this step, by electrolytic plating or electroless plating, a metal plating layer is selectively formed on at least a part of the portion of the main surface gate electrode 50 not covered by the upper insulating layer 63, and on at least a part of the portion of the main surface source electrode 55 not covered by the upper insulating layer 63.

[0126] A part of the metal plating layer is also formed on the flat portion 63a, the first end portion 63b, and the second end portion 63c of the upper insulating layer 63. Also, a part of the metal plating layer is formed on the flat portion 65a and the end portion 65b of the end insulating layer 65. The portion of the metal plating layer located on the power receiving portion 50a of the main surface gate electrode 50, as well as the portion located on the flat portion 63a and the first end portion 63b of the upper insulating layer 63, are formed as the columnar portion 71 that is part of the gate pad 70. The portion of the metal plating layer located on the main surface source electrode 55, as well as the portion located on the second end portion 63c of the upper insulating layer 63 and the end insulating layer 65, are formed as the lower source pad 75a that is part of the source pad 75.

[0127] Next, as shown in FIG. 6E, the lower mold layer 80a is formed. For example, this step includes a film forming step, a curing step, and a thinning step. In the film forming step, a liquid resin material (for example, an epoxy resin as an example of a thermosetting resin) that will become the lower mold layer 80a is applied or printed on the entire first main surface 11 of the semiconductor layer 10. In this step, the entire columnar portion 71 and the lower source pad 75a are covered by the resin material. The resin material also enters the space between the columnar portion 71 and the lower source pad 75a.

[0128] In the hardening process, the applied or printed resin material is hardened by heating. In the thinning process, the resin material is ground until the columnar portion 71 and the lower source pad 75a are exposed. As a result, as shown in FIG. 6E, the upper surfaces of the columnar portion 71, the upper surface of the lower mold layer 80a, and the upper surface of the lower source pad 75a are formed flush with each other.

[0129] Next, as shown in FIG. 6F, the gate wiring layer 72b and the source wiring layer 75b are formed. The gate wiring layer 72b and the source wiring layer 75b are each formed using, for example, the same material as the columnar portion 71 and the lower source pad 75a. The gate wiring layer 72b has the same size and the same shape as the wide portion 72 of the gate pad 70 in plan view. The source wiring layer 75b has the same size and the same shape as the lower source pad 75a in plan view. The gate wiring layer 72b and the source wiring layer 75b function as seed wirings that serve as film formation starting points in the next plating process.

[0130] Next, as shown in FIG. 6G, the wide portion 72a of the gate pad 70 is formed on the gate wiring layer 72b, and the upper source pad 75c of the source pad 75 is formed on the source wiring layer 75b. For example, in this process, a metal plating layer is selectively formed only on the upper surfaces of the gate wiring layer 72b and the source wiring layer 75b by an electrolytic plating method or an electroless plating method.

[0131] Next, as shown in FIG. 6H, the upper mold layer 80b is formed. For example, this process includes a film formation process, a hardening process, and a thinning process. In the film formation process, for example, the entire wide portion 72a and the entire upper source pad 75c are covered with a resin material (for example, an epoxy resin as an example of a thermosetting resin) by coating or printing.

[0132] In the curing process, the applied or printed resin material is cured by heating. In the thinning process, the resin material is ground until the wide portion 72a and the upper source pad 75c are exposed. As a result, as shown in FIG. 6H, the upper surface of the wide portion 72a, the upper surface of the upper mold layer 80b, and the upper surface of the upper source pad 75c are formed flush.

[0133] As a result, as shown in FIG. 6H, the wide portion 72 of the gate pad 70 is formed by the gate wiring layer 72b and the wide portion 72a. Also, the source pad 75 is formed by the lower source pad 75a, the source wiring layer 75b, and the upper source pad 75c. Further, the mold layer 80 is composed of a lower mold layer 80a and an upper mold layer 80b.

[0134] As described above, the gate pad 70 and the source pad 75 are formed by two-stage plating. In FIGS. 2 and the like described above, the illustration and description of the specific layer structure of the gate pad 70, the source pad 75, and the mold layer 80 are omitted. The description regarding the specific layer structure of the gate pad 70, the source pad 75, and the mold layer 80 is also applicable to FIGS. 2 and the like described above.

[0135] Next, the semiconductor layer 10 is thinned by polishing the second main surface 12a of the semiconductor layer 10. Next, a drain electrode 40 is formed on the second main surface 12 by vapor deposition or sputtering. Thereafter, the semiconductor layer 10 and the like are selectively cut together with the mold layer 80 to manufacture the semiconductor device 1 shown in FIG. 2.

[0136] The manufacturing method of the semiconductor device 1 is only an example and is not limited to the method described above. For example, the gate pad 70 and the source pad 75 may be formed by a film formation method other than the plating method.

[0137] As described above, the semiconductor device 1 according to the first embodiment is a semiconductor device including a vertical transistor 2. The semiconductor device 1 includes a semiconductor layer 10, a vertical transistor 2, a gate electrode 20, a source electrode 30, a drain electrode 40, a main surface gate electrode 50, a main surface source electrode 55, and a gate pad 70.

[0138] The semiconductor layer 10 has a first main surface 11 and a second main surface 12 opposite to the first main surface 11, and contains SiC as a main component. The vertical transistor 2 is provided on the first main surface 11. The gate electrode 20 is provided on the first main surface 11 as a gate electrode of the vertical transistor 2. The source electrode 30 is provided on the first main surface 11 at a distance from the gate electrode 20 as a source electrode of the vertical transistor 2.

[0139] The drain electrode 40 is provided on the second main surface 12 as a drain electrode of the vertical transistor 2. The main surface gate electrode 50 covers a part of the first main surface 11. The main surface source electrode 55 is provided at a distance from the main surface gate electrode 50 in a plan view. The gate pad 70 overlaps the main surface gate electrode 50 in a plan view and is electrically connected to the main surface gate electrode 50. The main surface gate electrode 50 is smaller than the gate pad 70 in a plan view. For example, the main surface gate electrode 50 is electrically connected to the gate electrode 20. The main surface source electrode 55 is electrically connected to the source electrode 30.

[0140] If the main surface gate electrode 50 is used as an electrode pad for wire bonding instead of the gate pad 70, the main surface gate electrode 50 needs to be formed to have the same size as the wide portion 72 of the gate pad 70. In this case, the region of the semiconductor layer 10 covered by the main surface gate electrode 50 is formed as an inactive region 4.

[0141] Therefore, since the size of the inactive region 4 is the same as the size of the main surface gate electrode 50 formed to be equivalent to the wide portion 72, the active region 3 becomes smaller. That is, the size of the inactive region 4 becomes extremely larger than the size of the inactive region 4 of the semiconductor device 1 according to this form. For this reason, since the active region 3 becomes smaller, the semiconductor layer 10 cannot be effectively utilized, and miniaturization and cost reduction become difficult.

[0142] On the other hand, according to the semiconductor device 1 according to this form, a gate pad 70 (wide portion 72) connected to the main surface gate electrode 50 is provided, and wire bonding is performed on the gate pad 70 (wide portion 72). Therefore, while reducing the size of the main surface gate electrode 50, a gate pad 70 having a sufficient size for appropriately performing wire bonding can be secured. Thereby, since the main surface gate electrode 50 can be reduced, the region not covered by the main surface gate electrode 50 can be expanded and utilized as the active region 3. Thus, a semiconductor device 1 capable of securing a wide operating region is realized.

[0143] For example, the gate pad 70 overlaps a part of the main surface source electrode 55 in a plan view. Thereby, the region directly under the wide portion 72 can be utilized as the active region 3. Also, the main surface source electrode 55 provided directly under the wide portion 72 of the gate pad 70 can easily secure an electrical connection portion to the plurality of source electrodes 30.

[0144] Hereinafter, a second embodiment will be described. In the second embodiment, the semiconductor device further includes an electrode for current detection and an electrode pad connected to the electrode for current detection, and the main difference from the first embodiment is that the electrode for current detection is smaller than the electrode pad. Hereinafter, the differences from the first embodiment will be mainly described, and the description of the common points will be omitted or simplified.

[0145] FIG. 7 is a cross-sectional view of the semiconductor device 101 according to the second embodiment. FIG. 8 is a plan view of the semiconductor device 101 shown in FIG. 7. FIG. 9 is a plan view of the upper surface of the electrode of the semiconductor device 101 taken along line IX-IX of FIG. 7. Specifically, FIG. 7 shows a cross-section taken along line VII-VII of FIG. 8. Specifically, FIG. 9 is a plan view of the semiconductor device 101 as viewed from the positive side of the z-axis, with the gate pad 70, source pad 75, current detection pad 170, and mold layer 80 shown in FIG. 8 being seen through. Although not shown in FIG. 7, the semiconductor device 101 includes a vertical transistor 2 that conducts current in the thickness direction of the semiconductor layer 10, as in the case of the first embodiment.

[0146] As shown in FIGS. 7 to 9, the semiconductor device 101 includes a main surface gate electrode 50, a main surface source electrode 55, and a current detection electrode 150. The main surface gate electrode 50 and the main surface source electrode 55 according to the second embodiment differ in arrangement or shape as compared with the case of the first embodiment, but their configurations are substantially the same as those in the case of the first embodiment. Therefore, the description of the main surface gate electrode 50 and the main surface source electrode 55 according to the second embodiment is omitted.

[0147] The current detection electrode 150 is an example of a third electrode. The current detection electrode 150 is arranged at a distance from the main surface gate electrode 50 and the main surface source electrode 55 in a plan view. In this form, the current detection electrode 150 is arranged in a region partitioned by the main surface gate electrode 50 and the main surface source electrode 55 in a plan view. The current detection electrode 150 corresponds to a part separated from a part of the main surface source electrode 55 according to the first embodiment.

[0148] The current detection electrode 150 includes at least one of, for example, metals such as conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or metal nitrides such as titanium nitride. The current detection electrode 150 is formed of, for example, the same material as the main surface gate electrode 50 and the main surface source electrode 55.

[0149] The current detection electrode 150 is electrically connected to N (N-number) source electrodes 30 out of the plurality of source electrodes 30 provided on the first main surface 11 of the semiconductor layer 10. N is a natural number. N is, for example, 10 or less. The vertical transistor 2 included in the semiconductor device 101 can flow a drain current from the drain electrode 40 provided on the second main surface 12 of the semiconductor layer 10 toward the plurality of source electrodes 30 provided on the first main surface 11 of the semiconductor layer 10. The current detection electrode 150 is an electrode for extracting the current (a component of the drain current) flowing through N source electrodes 30 out of the plurality of source electrodes 30. The N source electrodes 30 are used for detecting the current (drain current) flowing through the vertical transistor 2.

[0150] As shown in FIG. 7, the current detection electrode 150 is provided on the lower insulating layer 61. The current detection electrode 150 is electrically connected to one or more source electrodes 30 through one or more source contact holes 61b provided in the lower insulating layer 61. For example, the number of the source contact holes 61b corresponds to N. That is, by adjusting the number of the source contact holes 61b, the number N of the source electrodes 30 to which the current detection electrode 150 is connected can be adjusted.

[0151] The main surface source electrode 55 is electrically connected to M source electrodes 30 out of the plurality of source electrodes 30. M is a natural number greater than N. M is, for example, 100 times or more and 10,000 times or less of N. Therefore, a current of 1 / 10,000 or more and 1 / 100 or less of the current flowing through the main surface source electrode 55 flows through the current detection electrode 150 connected to the N source electrodes 30.

[0152] As a result, even if a large drain current flows between the drain electrode 40 and the plurality of source electrodes 30 of the semiconductor device 101 due to some factor, the current flowing through the current detection electrode 150 can be reduced. For example, the maximum amount of current flowing through the current detection electrode 150 can be suppressed to about 1 A. Thereby, an increase in current can be detected within the current detection range by using the current detection electrode 150. In other words, within the detection range of the current detection electrode 150, an increase or decrease in the drain current can be indirectly detected.

[0153] The current detection electrode 150 is smaller than the current detection pad 170 in plan view. The shape of the current detection electrode 150 in plan view is, for example, square or rectangular. The length of one side of the current detection electrode 150 is 5 μm or more and 50 μm or less. As an example, the current detection electrode 150 may have a square shape in plan view and have a size of about 20 μm × 20 μm. As shown in FIG. 9, the size of the current detection electrode 150 is the same as the size of the power receiving portion 50a of the main surface gate electrode 50. The size of the current detection electrode 150 may be smaller than the size of the power receiving portion 50a. The size of the current detection electrode 150 may be larger than the size of the power receiving portion 50a.

[0154] The current detection electrode 150 has an area that is 20% or less of the area of the semiconductor layer 10 (first main surface 11) in plan view. Preferably, the current detection electrode 150 has an area that is 10% or less of the area of the semiconductor layer 10 (first main surface 11). The current detection electrode 150 is disposed in a region that avoids the main surface source electrode 55 and the main surface gate electrode 50 in plan view. The current detection electrode 150 may be disposed in a region including the center position of the semiconductor layer 10. In this case, the main surface source electrode 55 may be disposed so as to surround the current detection electrode 150.

[0155] As shown in FIGS. 7 and 8, the semiconductor device 101 includes a gate pad 70, a source pad 75, and a current detection pad 170. The gate pad 70 and the source pad 75 according to the second embodiment are different in arrangement or shape as compared with the case of the first embodiment, respectively, but their configurations are substantially the same as those in the case of the first embodiment. Therefore, the description of the gate pad 70 and the source pad 75 according to the second embodiment is omitted.

[0156] The current detection pad 170 is an example of the second electrode pad. The current detection pad 170 overlaps the current detection electrode 150 and is electrically connected to the current detection electrode 150 in a plan view. In the semiconductor device 101 according to this embodiment, the current detection pad 170 connected to the current detection electrode 150 has the same configuration as the gate pad 70.

[0157] Specifically, as shown in FIG. 7, the current detection pad 170 includes a columnar portion 171 and a wide portion 172. The columnar portion 171 is an example of the first conductive layer provided on the current detection electrode 150. The columnar portion 171 extends in a columnar shape in the normal direction (z-axis direction) of the upper surface 152 of the current detection electrode 150. The columnar portion 171 is connected to the current detection electrode 150 through a through hole 164 provided in the upper insulating layer 63.

[0158] The columnar portion 171 covers the upper surface 152 of the current detection electrode 150. The columnar portion 171 further covers a part of the flat portion 63a and the first end portion 63b of the upper insulating layer 63. The height (length in the z-axis direction) of the columnar portion 171 is greater (longer) than the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 171 is greater (longer) than the maximum thickness of the portion of the upper insulating layer 63 located on the current detection electrode 150. Thereby, the top of the columnar portion 171 is higher than the top of the upper insulating layer 63.

[0159] The columnar portion 171 has a side surface 174 that extends vertically or substantially vertically. The side surface 174 does not necessarily have to extend linearly in a cross-sectional view, and may extend in a curved shape or an uneven shape. The side surface 174 is located above a region where the current detection electrode 150 and the upper insulating layer 63 overlap in a plan view. Specifically, the side surface 174 is located on the flat portion 63a of the upper insulating layer 63. That is, the columnar portion 171 covers the current detection electrode 150 and the upper insulating layer 63. Thereby, similar to the columnar portion 71 according to the first embodiment, the columnar portion 171 can be stably formed.

[0160] The wide portion 172 is an example of a second conductive layer provided at the upper end of the columnar portion 171. The wide portion 172 is a portion obtained by expanding the size of the upper end of the columnar portion 171 in the xy plane. The size and shape of the wide portion 172 in a plan view match the size and shape of the current detection pad 170 in a plan view. The wide portion 172 has an upper surface 173 that is used for electrical connection between the semiconductor device 101 (vertical transistor 2) and other circuits.

[0161] In this form, the upper surface 173 of the wide portion 172 is connected to a control circuit that controls the semiconductor device 101 (vertical transistor 2) based on the detected current. For example, a metal wire is connected to the upper surface 173 of the wide portion 172 by wire bonding. The metal wire contains at least one kind of metal such as aluminum, copper, or gold. In this form, an aluminum wire is wedge-bonded to the current detection pad 170 (the upper surface 173 of the wide portion 172).

[0162] In order to perform wire bonding appropriately, the wide portion 172 needs to have a size equal to or larger than a certain value. The planar shape of the wide portion 172 is, for example, a square. In this case, the size of the wide portion 172 may be 800 μm × 800 μm or more and 1 mm × 1 mm or less. In this case, the connection direction of the metal wire to the wide portion 172 can be set in an arbitrary direction. The size of the wide portion 172 may be larger than 1 mm × 1 mm.

[0163] The planar shape of the wide portion 172 may be rectangular. In this case, the size of the wide portion 172 may be 400 μm × 800 μm or more. The size of the wide portion 172 may be the same as the size of the wide portion 72 of the gate pad 70. The size of the wide portion 172 may be smaller than the size of the wide portion 72. The size of the wide portion 172 may be larger than the size of the wide portion 72.

[0164] In a plan view, the area of the wide portion 172 (i.e., the area of the current detection pad 170) is larger than the area of the current detection electrode 150. The area of the wide portion 172 is 200 times or more and 40000 times or less the area of the current detection electrode 150. The area of the wide portion 172 may be 400 times or more the area of the current detection electrode 150. As an example, the area of the wide portion 172 may be about 2500 times the area of the current detection electrode 150.

[0165] The columnar portion 171 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 172 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 172 is formed using, for example, the same conductive material as the columnar portion 171. The wide portion 172 may be formed using a conductive material different from that of the columnar portion 171. The current detection pad 170 is formed using, for example, the same material as the gate pad 70 and the source pad 75. Thereby, the current detection pad 170, the gate pad 70, and the source pad 75 can be formed in the same process.

[0166] The height (length in the z-axis direction) of the current detection pad 170 is the sum of the height (length in the z-axis direction) of the columnar portion 171 and the thickness (length in the z-axis direction) of the wide portion 172. The height of the current detection pad 170 is, for example, more than 0 mm and 1 mm or less (for example, several tens of μm or more and several hundreds of μm or less). As shown in FIG. 7, the height of the columnar portion 171 is larger (longer) than the thickness of the wide portion 172. The height of the columnar portion 171 may be equal to or less than the thickness of the wide portion 172.

[0167] The current detection pad 170 has an area that is 20% or less of the area of the semiconductor layer 10 (the first main surface 11) in a plan view. Preferably, the current detection pad 170 has an area that is 10% or less of the area of the semiconductor layer 10 (the first main surface 11) in a plan view. Also, the current detection pad 170 is disposed in a region avoiding the gate pad 70 and the source pad 75. The current detection pad 170 may be disposed in a region including the central position of the semiconductor layer 10 (the first main surface 11). In this case, the source pad 75 may be disposed so as to surround the periphery of the current detection pad 170.

[0168] In this form, as shown in FIG. 7, the semiconductor device 101 includes an active region 103 and a non-active region 104. The active region 103 is the main region where the drain current of the vertical transistor 2 flows. The active region 103 is a region that overlaps with the main surface source electrode 55 in a plan view. The active region 103 does not include a region that overlaps with either the main surface gate electrode 50 or the current detection electrode 150. On the other hand, a part of the region that overlaps with the gate pad 70 and the current detection pad 170 in a plan view is included in the active region 103.

[0169] The non-active region 104 is a region that does not operate as the vertical transistor 2. The non-active region 104 is a region other than the active region 103 in a plan view. As shown in FIG. 7, the non-active region 104 includes a current detection region 102. The current detection region 102 is a region that overlaps with the current detection electrode 150 in a plan view. In this form, the region that overlaps with the main surface gate electrode 50 or the current detection electrode 150 in a plan view is included in the non-active region 104.

[0170] Specifically, in a plan view, the current detection pad 170 overlaps a part of the main surface source electrode 55. That is, a part of the main surface source electrode 55 is located directly below the current detection pad 170. In this configuration, since the main surface source electrode 55 is drawn out to the region overlapping the current detection pad 170 in a plan view, a part of the region where the current detection pad 170 overlaps the main surface source electrode 55 can be used as the active region 103. As a result, while ensuring the area of the current detection pad 170, more area of the active region 103 can be secured.

[0171] As described above, the semiconductor device 101 according to the second embodiment further includes a plurality of source electrodes 30, a current detection electrode 150, and a current detection pad 170. The plurality of source electrodes 30 are arranged at intervals from each other in a plan view. The current detection electrode 150 is provided at a distance from the main surface gate electrode 50 and the main surface source electrode 55 in a plan view, and is electrically connected to N (N is a natural number) source electrodes 30. The current detection pad 170 overlaps the current detection electrode 150 in a plan view and is electrically connected to the current detection electrode 150. The main surface source electrode 55 is electrically connected to M (M is a natural number greater than N) source electrodes 30. The current detection electrode 150 is smaller than the current detection pad 170 in a plan view.

[0172] As described above, the number N of the source electrodes 30 to which the current detection electrode 150 is connected (that is, the source electrodes 30 included in the current detection region 102) may be, for example, 10 or less. On the other hand, as shown in FIG. 7, the number of the source electrodes 30 included in the range 105 directly below the wide portion 172 of the current detection pad 170 is much larger than 10.

[0173] Therefore, if the current detection electrode 150 is used as an electrode pad for wire bonding instead of the current detection pad 170, the current detection electrode 150 needs to be formed to have the same size as the wide portion 172 of the current detection pad 170. In this case, the range 105 directly below the wide portion 172 of the current detection pad 170 is formed as the non-active region 104.

[0174] Therefore, since the size of the non-active region 104 is the same as the size of the current detection electrode 150 formed to be the same as that of the wide portion 172, the active region 103 becomes smaller. That is, the size of the non-active region 104 is extremely larger than the size of the non-active region 104 of the semiconductor device 101 according to this form. For this reason, since the active region 103 becomes smaller, the semiconductor layer 10 cannot be effectively utilized, making it difficult to miniaturize and reduce costs.

[0175] On the other hand, according to the semiconductor device 101 according to this form, a current detection pad 170 (wide portion 172) connected to the current detection electrode 150 is provided, and wire bonding is performed on the current detection pad 170 (wide portion 172). Therefore, while reducing the size of the current detection electrode 150, a current detection pad 170 having a sufficient size for appropriately performing wire bonding can be secured. In addition, since the current detection electrode 150 can be reduced, the region not covered by the current detection electrode 150 can be expanded and utilized as the active region 103. Thus, a semiconductor device 101 capable of securing a wide operating region is realized.

[0176] The manufacturing method of the semiconductor device 101 according to this form is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment. Specifically, in each of the patterning processes of the main surface gate electrode 50, the main surface source electrode 55, and the current detection electrode 150, the patterning process of the insulating layer 60, and the patterning processes of the gate pad 70, the source pad 75, and the current detection pad 170, the semiconductor device 101 can be manufactured by adjusting each shape.

[0177] In the semiconductor device 101 according to this form, an example in which the gate pad 70 has the same configuration as the current detection pad 170 has been described, but the gate pad 70 may have the same configuration as the source pad 75.

[0178] FIG. 10 is a plan view of a modified example of the semiconductor device 101 according to the second embodiment (hereinafter referred to as semiconductor device 101a). FIG. 11 is a plan view of the upper surface of the electrode of the semiconductor device 101a shown in FIG. 10. FIGS. 10 and 11 respectively correspond to FIGS. 8 and 9 of the second embodiment.

[0179] In the semiconductor device 101a according to the modified example, in a plan view, the main surface gate electrode 50A and the gate pad 70a have the same size and the same shape. That is, in a plan view, the main surface gate electrode 50A is larger than the power receiving portion 50a of the main surface gate electrode 50 according to the second embodiment. The current detection electrode 150 and the current detection pad 170 are the same as those in the case of the second embodiment. That is, the semiconductor device 101a according to the modified example includes a current detection electrode 150 as an example of the first electrode, and includes a current detection pad 170 as an example of the first electrode pad.

[0180] As described above, in the semiconductor device 101a according to the modified example, a configuration for increasing the area in a plan view is applied only to the current detection electrode 150 (specifically, the current detection pad 170). Thereby, while securing the area of the pad for making an electrical connection to the current detection electrode 150, the current detection electrode 150 can be made smaller than the current detection pad 170. Therefore, a part of the region overlapping the current detection pad 170 in a plan view can be effectively used as an active region. Thus, a wider operating region can be secured.

[0181] Hereinafter, a third embodiment will be described. In the third embodiment, the semiconductor device further includes a diode having an electrode and an electrode pad connected to the electrode of the diode, and the main difference from the case of the first embodiment is that the electrode of the diode is smaller than the electrode pad. Hereinafter, the differences from the first embodiment will be mainly described, and the description of the common points will be omitted or simplified.

[0182] FIG. 12 is a cross-sectional view showing a main part of the semiconductor device 201 according to the third embodiment. FIG. 13 is a plan view of the semiconductor device 201 shown in FIG. 12. FIG. 14 is a plan view taken along line XIV-XIV shown in FIG. 12. Specifically, FIG. 12 shows a cross-section along line XII-XII of FIG. 13. Specifically, FIG. 14 is a plan view of the semiconductor device 201 when viewed from the positive side of the z-axis, with the gate pad 70, source pad 75, anode electrode pad 270, cathode electrode pad 275, and mold layer 80 shown in FIG. 13 being seen through.

[0183] As shown in FIG. 12, the semiconductor device 201 includes a diode 290 provided on the first main surface 11 of the semiconductor layer 10. In this embodiment, the diode 290 is a pn diode and includes a p-type semiconductor layer 291 and an n-type semiconductor layer 292. For example, the p-type semiconductor layer 291 includes polysilicon doped with p-type impurities, and the n-type semiconductor layer 292 includes polysilicon doped with n-type impurities. The p-type semiconductor layer 291 and the n-type semiconductor layer 292 are in contact with each other and constitute a pn diode having a pn junction.

[0184] The diode 290 is provided in a recess 293 provided in the first main surface 11 of the semiconductor layer 10. The recess 293 is formed by digging down the first main surface 11 of the semiconductor layer 10 toward the second main surface 12 side. For example, the recess 293 has the same depth as the depth of the gate trench 22. The recess 293 can be formed in the same process as the gate trench 22.

[0185] The recess 293 has an area of 20% or less of the area of the semiconductor layer 10 (first main surface 11) in plan view. Preferably, the recess 293 has an area of 10% or less of the area of the semiconductor layer 10 (first main surface 11) in plan view. The recess 293 is provided in a region avoiding the main surface source electrode 55 and the main surface gate electrode 50 in plan view. The recess 293 may be provided in a region including the central position of the semiconductor layer 10 (first main surface 11). In this case, the main surface source electrode 55 may be arranged so as to surround the periphery of the recess 293.

[0186] The semiconductor device 201 includes an insulating layer 223 formed to cover the bottom wall and the side walls of the recess 293. The insulating layer 223 is interposed between the semiconductor layer 10 and the diode 290. That is, the diode 290 is provided on the insulating layer 223. The insulating layer 223 contains, for example, silicon oxide. The insulating layer 223 may contain at least one of impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The insulating layer 223 contains, for example, the same material as the gate insulating layer 23 and has the same thickness as the gate insulating layer 23. Thereby, the insulating layer 223 can be formed in the same process as the gate insulating layer 23.

[0187] Note that either one or both of the recess 293 and the insulating layer 223 may not be provided in the semiconductor layer 10. The diode 290 may be provided on the first main surface 11 of the semiconductor layer 10. In this case, the diode 290 may be disposed on the insulating layer 223 covering the first main surface 11.

[0188] The diode 290 includes an anode electrode 250 and a cathode electrode 255. The temperature of the semiconductor device 201 can be detected based on the magnitude of the voltage between the anode electrode 250 and the cathode electrode 255. That is, the diode 290 is used as a temperature sensor (temperature-sensitive diode).

[0189] The anode electrode 250 is electrically connected to the p-type semiconductor layer 291. The anode electrode 250 contains, for example, at least one of metals such as conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or metal nitrides such as titanium nitride.

[0190] The cathode electrode 255 is electrically connected to the n-type semiconductor layer 292. As shown in FIG. 14, the cathode electrode 255 is provided at a distance from the anode electrode 250 in a plan view. In this form, the lower insulating layer 61 is provided between the cathode electrode 255 and the anode electrode 250. Also, the anode electrode 250 and the cathode electrode 255 are provided at distances from the main surface gate electrode 50 and the main surface source electrode 55, respectively, in a plan view.

[0191] As shown in FIG. 14, the main surface gate electrode 50 and the main surface source electrode 55 according to the third embodiment are different in arrangement or shape, respectively, as compared with the case of the first embodiment, but their configurations are substantially the same as those in the case of the first embodiment. Therefore, the description of the main surface gate electrode 50 and the main surface source electrode 55 according to the third embodiment is omitted.

[0192] The cathode electrode 255 contains, for example, at least one of metals such as conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, or metal nitrides such as titanium nitride. The cathode electrode 255 may be formed using the same material as the anode electrode 250.

[0193] As shown in FIGS. 12 and 13, the semiconductor device 201 includes a gate pad 70, a source pad 75, an anode electrode pad 270, and a cathode electrode pad 275. The gate pad 70 and the source pad 75 according to the third embodiment are different in arrangement or shape, respectively, as compared with the case of the first embodiment, but their configurations are substantially the same as those in the case of the first embodiment. Therefore, the description of the gate pad 70 and the source pad 75 according to the third embodiment is omitted.

[0194] The anode electrode pad 270 overlaps the anode electrode 250 in a plan view and is electrically connected to the anode electrode 250. In the semiconductor device 201 according to this form, the anode electrode pad 270 connected to the anode electrode 250 has the same configuration as the gate pad 70.

[0195] Specifically, as shown in FIG. 12, the anode electrode pad 270 includes a columnar portion 271 and a wide portion 272. The columnar portion 271 is an example of a first conductive layer provided on the anode electrode 250. The columnar portion 271 extends in a columnar shape in the normal direction (z-axis direction) of the upper surface 251 of the anode electrode 250.

[0196] The wide portion 272 is an example of a second conductive layer provided at the upper end of the columnar portion 271. The wide portion 272 is a portion obtained by expanding the size of the upper end of the columnar portion 271 in the xy plane. The size and shape of the wide portion 272 in plan view coincide with the size and shape of the anode electrode pad 270 in plan view. The wide portion 272 has an upper surface 273 that is used for electrical connection between the semiconductor device 201 (diode 290) and other circuits.

[0197] In this embodiment, the upper surface 273 of the wide portion 272 is connected to a voltmeter or the like that detects the voltages of the anode electrode 250 and the cathode electrode 255. For example, a metal wire is connected to the upper surface 273 of the wide portion 272 by wire bonding. The metal wire contains at least one kind of metal such as aluminum, copper, or gold. In this embodiment, an aluminum wire is wedge-bonded to the anode electrode pad 270 (the upper surface 273 of the wide portion 272).

[0198] In order to perform wire bonding appropriately, the wide portion 272 needs to have a size equal to or greater than a certain value. The shape and size of the wide portion 272 in plan view are, for example, the same as the shape and size of the wide portion 72 of the gate pad 70 in plan view. At least one of the shape and size of the wide portion 272 in plan view may be different from the shape and size of the wide portion 72 in plan view.

[0199] In a plan view, the area of the wide portion 272 (i.e., the area of the anode electrode pad 270) is larger than the area of the anode electrode 250. The area of the wide portion 272 may be 200 times or more and 40,000 times or less the area of the anode electrode 250. The area of the wide portion 272 may be 400 times or more the area of the anode electrode 250. As an example, the area of the wide portion 272 may be about 2,500 times the area of the anode electrode 250.

[0200] The columnar portion 271 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 272 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 272 is formed, for example, using the same conductive material as the columnar portion 271. The wide portion 272 may be formed using a conductive material different from that of the columnar portion 271.

[0201] The height (length in the z-axis direction) of the anode electrode pad 270 is the sum of the height (length in the z-axis direction) of the columnar portion 271 and the thickness (length in the z-axis direction) of the wide portion 272. The height of the anode electrode pad 270 is, for example, more than 0 mm and 1 mm or less (for example, several tens of μm or more and several hundreds of μm or less). As shown in FIG. 12, the height of the columnar portion 271 is larger (longer) than the thickness of the wide portion 272. The height of the columnar portion 271 may be equal to or less than the thickness of the wide portion 272.

[0202] The cathode electrode pad 275 overlaps the cathode electrode 255 in a plan view and is electrically connected to the cathode electrode 255. In the semiconductor device 201 according to this form, the cathode electrode pad 275 connected to the cathode electrode 255 has the same configuration as the gate pad 70 and the anode electrode pad 270.

[0203] Specifically, as shown in FIG. 12, the cathode electrode pad 275 includes a columnar portion 276 and a wide portion 277. The columnar portion 276 is an example of a first conductive layer provided on the cathode electrode 255. The columnar portion 276 extends in a columnar shape in the normal direction (z-axis direction) of the upper surface 256 of the cathode electrode 255.

[0204] The wide portion 277 is an example of the second conductive layer provided at the upper end of the columnar portion 276. The wide portion 277 is a portion where the size of the upper end of the columnar portion 276 is enlarged in the xy plane. The size and shape of the wide portion 277 in plan view coincide with the size and shape of the cathode electrode pad 275 in plan view.

[0205] The wide portion 277 has an upper surface 278 that is used for the electrical connection between the semiconductor device 201 (diode 290) and other circuits. In this form, the upper surface 278 of the wide portion 277 is connected to a voltmeter or the like that detects the voltages of the anode electrode 250 and the cathode electrode 255. For example, a metal wire is connected to the upper surface 278 of the wide portion 277 by wire bonding.

[0206] Regarding the shape, material, etc., the columnar portion 276 and the wide portion 277 of the cathode electrode pad 275 are the same as those of the columnar portion 276 and the wide portion 277 of the anode electrode pad 270, respectively. Therefore, the description of the shape, material, etc. of the cathode electrode pad 275 is omitted.

[0207] The anode electrode pad 270 and the cathode electrode pad 275 are formed, for example, using the same material as the gate pad 70 and the source pad 75. Thereby, the anode electrode pad 270, the cathode electrode pad 275, the gate pad 70, and the source pad 75 can be formed in the same process.

[0208] The semiconductor device 201 may include an insulating layer (not shown) that covers a part of the upper surface 251 of the anode electrode 250 and a part of the upper surface 256 of the cathode electrode 255. The insulating layer is made of an organic material such as polyimide or PBO, for example. In this case, the side surfaces of the columnar portion 271 of the anode electrode pad 270 and the side surfaces of the columnar portion 276 of the cathode electrode pad 275 may be provided on the flat portions of the insulating layer in the same manner as the side surfaces 74 of the columnar portion 71 according to the first embodiment.

[0209] The anode electrode pad 270 and the cathode electrode pad 275 each have an area of 20% or less of the area of the semiconductor layer 10 (the first main surface 11) in plan view. Preferably, the anode electrode pad 270 and the cathode electrode pad 275 have an area of 10% or less of the area of the semiconductor layer 10 (the first main surface 11) in plan view.

[0210] Also, the anode electrode pad 270 and the cathode electrode pad 275 are arranged in a region avoiding the gate pad 70 and the source pad 75. One of the anode electrode pad 270 and the cathode electrode pad 275 may be arranged in a region including the central position of the semiconductor layer 10 (the first main surface 11), or the source pad 75 may be arranged so as to surround the periphery of the anode electrode pad 270 and the cathode electrode pad 275.

[0211] In this embodiment, as shown in FIG. 12, the semiconductor device 201 includes an active region 203 and a non-active region 204. The active region 203 is the main region where the drain current of the vertical transistor 2 flows. The active region 203 is a region that overlaps the main surface source electrode 55 in plan view. The active region 203 does not include a region that overlaps either the main surface gate electrode 50 or the recess 293. A part of the region that overlaps the gate pad 70, the anode electrode pad 270, and the cathode electrode pad 275 in plan view is included in the active region 103.

[0212] The non-active region 204 is a region that does not operate as the vertical transistor 2. The non-active region 204 is a region other than the active region 203 in plan view. As shown in FIG. 12, a diode 290 is formed in the non-active region 204. In this embodiment, the region that overlaps the main surface gate electrode 50 or the recess 293 in plan view is included in the non-active region 204.

[0213] Specifically, the anode electrode pad 270 and the cathode electrode pad 275 each overlap a part of the main surface source electrode 55 in a plan view. That is, a part of the main surface source electrode 55 is located directly below the anode electrode pad 270 and directly below the cathode electrode pad 275, respectively. In this form, the main surface source electrode 55 is drawn out to the region overlapping the anode electrode pad 270 or the cathode electrode pad 275 in a plan view.

[0214] Therefore, a part of the region where the main surface source electrode 55 and the anode electrode pad 270 overlap, or a part of the region where the main surface source electrode 55 and the cathode electrode pad 275 overlap can be used as the active region 203. Thereby, while securing the areas of the anode electrode pad 270 and the cathode electrode pad 275, more area of the active region 203 can be secured.

[0215] As described above, the semiconductor device 201 according to this form includes the diode 290, the anode electrode pad 270, and the cathode electrode pad 275. The diode 290 includes the anode electrode 250 and the cathode electrode 255, and is provided on the first main surface 11. The anode electrode pad 270 overlaps the anode electrode 250 in a plan view and is electrically connected to the anode electrode 250. The cathode electrode pad 275 overlaps the cathode electrode 255 in a plan view and is electrically connected to the cathode electrode 255. The anode electrode 250 is smaller than the anode electrode pad 270 in a plan view. The cathode electrode 255 is smaller than the cathode electrode pad 275 in a plan view.

[0216] If the anode electrode 250 is used as an electrode pad for wire bonding instead of the anode electrode pad 270, the anode electrode 250 needs to have the same size as the wide portion 272. On the other hand, if the cathode electrode 255 is used as an electrode pad for wire bonding instead of the cathode electrode pad 275, the cathode electrode 255 needs to have the same size as the wide portion 277.

[0217] In these cases, the regions covered by the anode electrode 250 and the cathode electrode 255 are formed as the non-active region 204. For this reason, the size of the non-active region becomes the size of the anode electrode 250 and the cathode electrode 255 formed to be the same size as the wide portions 272 and 277, so that the active region 203 becomes smaller. That is, the size of the non-active region becomes extremely larger than the size of the non-active region 204 of the semiconductor device 201 according to this form. For this reason, the semiconductor layer 10 cannot be effectively utilized, and it becomes difficult to miniaturize and reduce the cost.

[0218] On the other hand, according to the semiconductor device 201 according to this form, an anode electrode pad 270 (wide portion 272) connected to the anode electrode 250 is provided, and a cathode electrode pad 275 (wide portion 277) connected to the cathode electrode 255 is provided. Wire bonding is performed for each of the anode electrode pad 270 (wide portion 272) and the cathode electrode pad 275 (wide portion 277).

[0219] Therefore, while reducing the anode electrode 250 and the cathode electrode 255 respectively, it is possible to secure the anode electrode pad 270 and the cathode electrode pad 275 each having a sufficient size to appropriately perform wire bonding. In addition, since the anode electrode 250 and the cathode electrode 255 can be reduced respectively, the region not covered by the anode electrode 250 or the cathode electrode 255 can be extended and utilized as the active region 203. In this way, a semiconductor device 201 capable of securing a wide operation region is realized.

[0220] The manufacturing method of the semiconductor device 201 according to this embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment. Specifically, in each of the patterning steps of the main surface gate electrode 50, the main surface source electrode 55, the anode electrode 250, and the cathode electrode 255, the patterning step of the insulating layer 60, and the patterning step of the gate pad 70, the source pad 75, the anode electrode pad 270, and the cathode electrode pad 275, the semiconductor device 201 can be manufactured by adjusting each shape.

[0221] In the semiconductor device 201 according to this embodiment, although an example in which the gate pad 70 has the same configuration as the anode electrode pad 270 and the cathode electrode pad 275 has been described, the gate pad 70 may have the same configuration as the source pad 75.

[0222] FIG. 15 is a plan view of a modified example of the semiconductor device 201 according to the third embodiment (hereinafter referred to as the semiconductor device 201a). FIG. 16 is a plan view showing the upper surface of the electrodes of the semiconductor device 201a shown in FIG. 15. FIGS. 15 and 16 respectively correspond to FIGS. 13 and 14 of the third embodiment.

[0223] In the semiconductor device 201a according to the modified example, in plan view, the main surface gate electrode 50A and the gate pad 70a have the same size and the same shape. That is, in plan view, the main surface gate electrode 50A is larger than the power receiving portion 50a of the main surface gate electrode 50 according to the third embodiment.

[0224] The anode electrode 250, the cathode electrode 255, the anode electrode pad 270, and the cathode electrode pad 275 are the same as in the case of the third embodiment. That is, the semiconductor device 201a according to the modified example includes the anode electrode 250 as an example of the first electrode and the anode electrode pad 270 as an example of the first electrode pad. The semiconductor device 201a according to the modified example includes the cathode electrode 255 as an example of the second electrode and the cathode electrode pad 275 as an example of the second electrode pad.

[0225] Thus, in the semiconductor device 201a according to the modification example, a configuration for increasing the area in a plan view is applied only to the anode electrode 250 and the cathode electrode 255 (specifically, the anode electrode pad 270 and the cathode electrode pad 275). That is, while securing the area of the pads for making electrical connections to the anode electrode 250 and the cathode electrode 255 respectively, the anode electrode 250 can be made smaller than the anode electrode pad 270, and the cathode electrode 255 can be made smaller than the cathode electrode pad 275.

[0226] As a result, a part of the region overlapping with the anode electrode pad 270 or the cathode electrode pad 275 in a plan view can be extended as an active region and effectively utilized. Therefore, a wider operating region can be secured.

[0227] Either one of the anode electrode pad 270 and the cathode electrode pad 275 may have the same configuration as the source pad 75. For example, the anode electrode 250 and the anode electrode pad 270 may have the same shape and size in a plan view. The cathode electrode 255 and the cathode electrode pad 275 may have the same shape and size in a plan view.

[0228] Hereinafter, as a fourth embodiment, a semiconductor package having a semiconductor device will be described. FIG. 17 is a rear view showing an example of a semiconductor package 300 according to the fourth embodiment. FIG. 18 is a front view showing the internal structure of the semiconductor package 300 shown in FIG. 17.

[0229] As shown in FIGS. 17 and 18, the semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. The semiconductor package 300 includes a package body 301, a terminal 302d, a terminal 302g, a terminal 302s, a bonding wire 303g, a bonding wire 303s, and a semiconductor device 1.

[0230] The package body 301 is rectangular parallelepiped. The package body 301 houses the semiconductor device 1. In other words, the package body 301 is a sealing body that seals the semiconductor device 1. The package body 301 may contain an epoxy resin. The package body 301 is formed of, for example, an epoxy resin containing carbon, glass fiber, or the like.

[0231] Each of the terminals 302d, 302g, and 302s protrudes from the bottom of the package body 301 and is arranged in a row along the bottom of the package body 301. The terminals 302d, 302g, and 302s are formed of, for example, aluminum, but may be formed of other metal materials such as copper.

[0232] Inside the package body 301, the gate pad 70 of the semiconductor device 1 is electrically connected to the terminal 302g by a bonding wire 303g or the like. The source pad 75 of the semiconductor device 1 is electrically connected to the terminal 302s by a bonding wire 303s or the like. The drain electrode 40 of the semiconductor device 1 is joined to the wide portion located inside the package body 301 of the terminal 302d by solder, a sintered layer made of silver or copper, or the like.

[0233] Instead of the semiconductor device 1, the semiconductor package 300 may include the semiconductor devices 101, 101a, 201, or 201a. In this case, the package body 301 may further include a terminal to which the current detection pad 170 of the semiconductor device 101 is connected. Also, the package body 301 may further include a plurality of terminals to which the anode electrode pad 270 and the cathode electrode pad 275 of the semiconductor device 201 are respectively connected.

[0234] As described above, by including the semiconductor devices 1, 101, 101a, 201, or 201a, the semiconductor package 300 can secure a wider operating region than in the case of including a general semiconductor device.

[0235] Other examples of the semiconductor package shown in FIG. 17 are described below. FIG. 19 is a front view showing another example of the semiconductor package 300 according to the fourth embodiment (hereinafter referred to as the semiconductor package 400). The semiconductor package 400 shown in FIG. 19 is a so-called DIP (Dual In-line Package) type semiconductor package. The semiconductor package 400 includes a package body 401, a plurality of terminals 402, and a semiconductor device 1.

[0236] The package body 401 has a rectangular parallelepiped shape. The package body 401 houses the semiconductor device 1. In other words, the package body 401 is a sealing body that seals the semiconductor device 1. The package body 401 may contain an epoxy resin. The package body 401 is formed, for example, of an epoxy resin containing carbon, glass fiber, or the like.

[0237] The plurality of terminals 402 protrude from the long side of the package body 401 and are arranged side by side along the long side of the package body 401. The plurality of terminals 402 are formed of, for example, aluminum, but may be formed of other metal materials such as copper.

[0238] Inside the package body 401, each of the gate pad 70, source pad 75, and drain electrode 40 of the semiconductor device 1 is electrically connected to the corresponding terminal 402 by a bonding wire or the like. The semiconductor package 400 may include a plurality of semiconductor devices 1. That is, the package body 401 may house a plurality of semiconductor devices 1.

[0239] Instead of or in addition to the semiconductor device 1, the semiconductor package 400 may include semiconductor devices 101, 101a, 201, or 201a. In this case, inside the package body 401, each of the current detection pad 170 of the semiconductor device 101, or the anode electrode pad 270 and cathode electrode pad 275 of the semiconductor device 201 is electrically connected to the corresponding terminal 402 by a bonding wire or the like.

[0240] As described above, by including the semiconductor devices 1, 101, 101a, 201, or 201a, the semiconductor package 400 can secure a wider operating region than when including a general semiconductor device.

[0241] FIG. 20 is a cross-sectional view showing a main part of the semiconductor device 501 according to the first modification of each of the above-described embodiments. As described above, bonding wires are used for the terminals of the semiconductor package 300 or 400 and the electrical connection of the semiconductor devices 1, 101, 101a, 201, or 201a. When the bonding wire is a wire made of aluminum, as shown in FIG. 20, nickel layers may be formed on the upper surface 73 of the gate pad 70, which is a metal plating layer, and the upper surface 76 of the source pad 75, respectively.

[0242] In FIG. 20, as an example of the bonding wire, bonding wires 303g and 303s are shown together. As shown in FIG. 20, the nickel layer 90 is an example of a metal layer formed of a metal material different from the metal material forming the gate pad 70 and the source pad 75. The nickel layer 90 is a layer containing nickel as a main component. Specifically, the nickel layer 90 is a metal layer made of pure nickel.

[0243] Similarly, in the case of the semiconductor devices 101, 101a, 201, or 201a, nickel layers 90 may be provided on the upper surfaces of the current detection pad 170, the anode electrode pad 270, and the cathode electrode pad 275.

[0244] FIG. 21 is a cross-sectional view showing a main part of the semiconductor device 601 according to the second modification of each of the above-described embodiments. As in the semiconductor device 601 shown in FIG. 21, the gate pad 70 may include a columnar portion 71 made of copper and a wide portion 672 made of nickel. The source pad 75 may include a lower source pad 75a made of copper and an upper source pad 675c made of nickel.

[0245] For example, the semiconductor device 601 shown in FIG. 21 can be manufactured by performing a plating method using nickel instead of copper in the plating process shown in FIG. 6G. In the example shown in FIG. 21, the upper surface 73 of the wide portion 672, the upper surface 76 of the upper source pad 675c, and the upper surface 81 of the mold layer 80 are formed flush.

[0246] In the example shown in FIG. 20 or FIG. 21, another layer may be formed on the outermost surface of the metal plating layer (specifically, the gate pad 70 and the source pad 75) that is the bonding portion of the bonding wire made of aluminum, instead of the nickel layer. For example, a two-layer structure (i.e., a NiPd layer) including a nickel layer and a palladium layer provided on the nickel layer may be provided on the metal plating layer. Further, a three-layer structure (for example, a NiPdAu layer) in which another metal layer such as a gold (Au) layer is formed on the upper surface of the two-layer structure may be formed. The NiPd layer and the NiPdAu layer are suitable not only when the bonding wire is bonded but also when the external terminal is bonded by silver sintering.

[0247] The form of the semiconductor package including the semiconductor devices 1, 101, 101a, 201, 201a, 501, or 601 is not limited to the forms such as the semiconductor packages 300 and 400. As the semiconductor package, an SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package) may be adopted. Also, various semiconductor packages similar to these may be adopted as the semiconductor package.

[0248] As described above, the semiconductor device according to one or more aspects has been described based on a plurality of embodiments, but the present invention is not limited to these embodiments. As long as the gist of the present invention is not deviated from, forms obtained by applying various modifications conceivable by those skilled in the art to this embodiment and forms constructed by combining components in different embodiments are also included in the scope of the present invention.

[0249] For example, in a plan view, the gate pad 70 may cover only a part of the main surface gate electrode 50. That is, the gate pad 70 does not have to completely cover the main surface gate electrode 50. Similar structures may be applied to the current detection pad 170, the anode electrode pad 270, and the cathode electrode pad 275, respectively.

[0250] For example, in each embodiment, the conductivity type of each semiconductor region or semiconductor layer may be inverted. That is, an n-type semiconductor may be provided instead of a p-type semiconductor, and a p-type semiconductor may be provided instead of an n-type semiconductor.

[0251] For example, in each embodiment, n + Instead of the type semiconductor substrate 13, a p + -type SiC semiconductor substrate may be used. Thereby, the vertical transistor 2 is formed as an IGBT (Insulated Gate Bipolar Transistor). That is, a semiconductor device including an IBGT as a vertical transistor can be provided. In this case, the "source" of the MISFET is read as the "emitter" of the IGBT. Also, the "drain" of the MISFET is read as the "collector" of the IGBT. The emitter of the IGBT is an example of the first main electrode, and the collector of the IGBT is an example of the second main electrode. The semiconductor device according to each embodiment can also achieve effects equivalent to the above-described effects even when it includes an IGBT instead of a MISFET.

[0252] Examples of features extracted from this specification and the drawings are shown below. Hereinafter, the alphanumerics in parentheses represent the corresponding components in the above-described embodiments, but are not intended to limit the scope of each item to the embodiments.

[0253] [A1]A method of manufacturing a semiconductor device (1, 101, 101a, 201, 201a) including a vertical transistor (2), the method having a first main surface (11) and a second main surface (12) opposite to the first main surface (11), and including: a first step of forming a control electrode (20) and a first main electrode (30) of the vertical transistor (2) on the first main surface (11) of a semiconductor layer (10) containing SiC as a main component with a space therebetween; a second step of forming a first electrode (50, 250) and a first electrode (55, 255) covering a part of the first main surface (11) with a space therebetween; and a third step of forming a first electrode pad (70) electrically connected to the first electrode (50, 250) so as to overlap the first electrode (50, 250) in a plan view, wherein the first electrode (50, 250) is smaller than the first electrode pad (70) in a plan view. A method of manufacturing a semiconductor device (1, 101, 101a, 201, 201a).

[0254] [A2]The third step includes: a fourth step of forming a first conductive layer (71) on the first electrode (50, 250); a fifth step of forming an insulating layer (80) along an outer periphery of the first conductive layer (71) in a plan view; and a sixth step of forming a second conductive layer (72) larger than the first conductive layer (71) on the first conductive layer (71) and the insulating layer (80). A method of manufacturing a semiconductor device (1, 101, 101a, 201, 201a) according to A1.

[0255] [A3]The sixth step includes: a seventh step of forming a wiring layer (72b) larger than the first conductive layer (71) on the first conductive layer (71) and the insulating layer (80); and an eighth step of selectively forming a metal plating layer (72a) on the wiring layer (72b). A method of manufacturing a semiconductor device (1, 101, 101a, 201, 201a) according to A2.

[0256] [A4]The fifth step is to mold with a resin material (80b) so as to cover the first conductive layer (71), and grind the molded resin material (80b) until the first conductive layer (71) is exposed, thereby forming the insulating layer (80). The method for manufacturing a semiconductor device (1, 101, 101a, 201, 201a) according to A2 or A3.

[0257] [B1]A semiconductor device (1, 101, 101a, 201, 201a) including a vertical transistor (2), having a first main surface (11) and a second main surface (12) opposite to the first main surface (11), a semiconductor layer (10) mainly containing SiC, a control electrode (20) of the vertical transistor (2) provided on the first main surface (11), a first main electrode (30) of the vertical transistor (2) provided on the first main surface (11) at an interval from the control electrode (20), a second main electrode (40) of the vertical transistor (2) provided on the second main surface (12), a first electrode (50, 250) covering a part of the first main surface (11), a first electrode (55, 255) provided at an interval from the first electrode (50, 250) in a plan view, and a first electrode pad (70) overlapping the first electrode (50, 250) in a plan view and electrically connected to the first electrode (50, 250). The first electrode (50, 250) is smaller than the first electrode pad (70) in a plan view. Semiconductor device (1, 101, 101a, 201, 201a).

[0258] [B2]The first electrode pad (70) overlaps a part of the first electrode (55, 255) in a plan view. The semiconductor device (1, 101, 101a, 201, 201a) according to B1.

[0259] [B3]The first electrode (50, 250) is electrically connected to the control electrode (20), and the first electrode (55, 255) is electrically connected to the first main electrode (30). The semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2.

[0260] [B4] Further, a plurality of the first main electrodes (30) arranged at intervals from each other in a plan view, a third electrode (150) provided at an interval from the first electrodes (50, 250) and the first electrodes (55, 255) in a plan view, and electrically connected to N (N is a natural number) of the first main electrodes (30), and a second electrode pad (170) that overlaps the third electrode (150) in a plan view and is electrically connected to the third electrode (150), wherein the first electrode (55, 255) is electrically connected to M (M is a natural number greater than N) of the first main electrodes (30), and the third electrode (150) is smaller than the second electrode pad (170) in a plan view, the semiconductor device (1, 101, 101a, 201, 201a) according to B3.

[0261] [B5] Further, a diode (290) including an anode electrode (250) and a cathode electrode (255) and provided on the first main surface (11), an anode electrode pad (270) that overlaps the anode electrode (250) in a plan view and is electrically connected to the anode electrode (250), and a cathode electrode pad (275) that overlaps the cathode electrode (255) in a plan view and is electrically connected to the cathode electrode (255), wherein the anode electrode (250) is smaller than the anode electrode pad (270) in a plan view, and the cathode electrode (255) is smaller than the cathode electrode pad (275) in a plan view, the semiconductor device (1, 101, 101a, 201, 201a) according to B3 or B4.

[0262] [B6] The semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2, comprising a plurality of the first main electrodes (30), wherein the first electrodes (50, 250) are electrically connected to one of the plurality of first main electrodes (30).

[0263] [B7] Further, it includes a diode (290) provided on the first main surface (11), and a second electrode pad that overlaps the first electrode (55, 255) in a plan view and is electrically connected to the first electrode (55, 255). The first electrode (50, 250) is the anode electrode (250) of the diode (290), and the first electrode (55, 255) is the cathode electrode (255) of the diode (290). In a plan view, the semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2, which is smaller than the second electrode pad (170).

[0264] [C1] A semiconductor device (1, 101, 101a, 201, 201a) including a semiconductor layer (10) having a main surface (11) and containing SiC as a main component, a gate structure (21) formed on the main surface (11), an insulating layer (61) formed on the main surface (11) so as to cover the gate structure (21), a gate main electrode (50) disposed on the insulating layer (61) and electrically connected to the gate structure (21), and a gate pad electrode (70) disposed on the gate main electrode (50) so as to be connected to the gate main electrode (50), including a connection portion connected to the gate main electrode (50) with a first area in a plan view and an electrode surface (73) having a second area exceeding the first area in a plan view.

[0265] [C2] The semiconductor device (1, 101, 101a, 201, 201a) according to C1, wherein the electrode surface (73) of the gate pad electrode (70) is exposed to the outside.

[0266] [C3] The semiconductor device (1, 101, 101a, 201, 201a) according to C1 or C2, wherein the gate main electrode (50) is formed in a line shape on the insulating layer (61).

[0267] [C4] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C3, wherein the second area of the electrode surface (73) exceeds the area of the gate main electrode (50).

[0268] [C5]The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C4, further comprising: an active region (3, 103, 203) provided in the semiconductor layer (10); and a non-active region (4, 104, 204) provided in a region outside the active region (3, 103, 203) in the semiconductor layer (10), wherein the gate structure (21) is formed in the active region (3, 103, 203), the gate main electrode (50) is formed in the non-active region (4, 104, 204) in a plan view, and the gate pad electrode (70) overlaps with the active region (3, 103, 203) and the non-active region (4, 104, 204) in a plan view.

[0269] [C6]The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C5, further comprising a current conduction electrode (55) disposed on the insulating layer (61) with a space from the gate main electrode (50).

[0270] [C7]The semiconductor device (1, 101, 101a, 201, 201a) according to C6, wherein the gate pad electrode (70) overlaps with a part of the current conduction electrode (55) in a plan view.

[0271] [C8]The semiconductor device (1, 101, 101a, 201, 201a) according to C6 or C7, further comprising a current conduction pad electrode (75) disposed on the current conduction electrode (55).

[0272] [C9]The semiconductor device (1, 101, 101a, 201, 201a) according to C8, wherein the current conduction pad electrode (75) overlaps with a part of the gate main electrode (50) in a plan view.

[0273] [C10]The semiconductor device (1, 101, 101a, 201, 201a) according to C8 or C9, wherein the current conduction pad electrode (75) includes an electrode surface (76) having a third area exceeding the second area of the gate pad electrode (70) in a plan view.

[0274] [C11] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C10, further comprising a first resin layer (63, 65) that partially covers the gate main electrode (50) so as to expose a part of the gate main electrode (50) on the insulating layer (61), wherein the gate pad electrode (70) is disposed on a portion of the gate main electrode (50) that is exposed from the first resin layer (63, 65).

[0275] [C12] The semiconductor device (1, 101, 101a, 201, 201a) according to C11, further comprising a second resin layer (80) that partially covers the first resin layer (63, 65) so as to expose a part of the gate main electrode (50) on the insulating layer (61), wherein the gate pad electrode (70) is disposed on a portion of the gate main electrode (50) that is exposed from the first resin layer (63, 65) and the second resin layer (80).

[0276] [C13] The semiconductor device (1, 101, 101a, 201, 201a) according to C12, wherein the first resin layer (63, 65) is made of a photosensitive resin layer, and the second resin layer (80) is made of a thermosetting resin layer.

[0277] [C14] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C13, wherein the gate structure (21) is a trench gate structure (21).

[0278] [C15]A semiconductor device (1, 101, 101a, 201, 201a) comprising: a semiconductor layer (10) having a main surface (11); an active region (3, 103, 203) provided in the semiconductor layer (10); a non-active region (4, 104, 204) provided in a region of the semiconductor layer (10) outside the active region (3, 103, 203); a plurality of gate structures (21) formed in the active region (3, 103, 203); an insulating layer (61) formed on the main surface (11) so as to cover the plurality of gate structures (21); a gate main electrode (50) disposed on the insulating layer (61) so as to be electrically connected to the plurality of gate structures (21) and overlapping the non-active region (4, 104, 204) in plan view; and a gate pad electrode (70) disposed on the gate main electrode (50) so as to be electrically connected to the gate main electrode (50) and overlapping the active region (3, 103, 203) and the non-active region (4, 104, 204) in plan view.

[0279] [C16]The semiconductor device (1, 101, 101a, 201, 201a) according to C15, wherein the gate main electrode (50) does not overlap the active region (3, 103, 203) in plan view.

[0280] [C17]The semiconductor device (1, 101, 101a, 201, 201a) according to C15 or C16, wherein the gate pad electrode (70) includes a connection portion connected to the gate main electrode (50) with a first area in plan view and an electrode surface (73) having a second area exceeding the first area in plan view.

[0281] [C18]The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C15 to C17, wherein the active region (3, 103, 203) includes a plurality of divided regions provided in the semiconductor layer (10) at intervals in plan view, and the non-active region (4, 104, 204) includes a portion located between the plurality of divided regions in the semiconductor layer (10) in plan view.

[0282] [C19] The gate main electrode (50) includes a portion that overlaps a portion located between the plurality of divided regions in the non-active region (4, 104, 204) in a plan view, and the gate pad electrode (70) includes a portion that overlaps a portion located between the plurality of divided regions in the non-active region (4, 104, 204) in a plan view. The semiconductor device (1, 101, 101a, 201, 201a) according to C18.

[0283] [C20] The gate pad electrode (70) overlaps the plurality of divided regions in a plan view. The semiconductor device (1, 101, 101a, 201, 201a) according to C19.

[0284] [D1] A semiconductor device (1, 101, 101a, 201, 201a) including a semiconductor layer (10) having a main surface (11) and containing SiC as a main component, a diode structure (290, 291, 292) formed on the main surface (11), an insulating layer (61) formed on the main surface (11) so as to cover the diode structure (290, 291, 292), and a pair of polarity electrodes (250, 255) disposed on the insulating layer (61) and including a first polarity electrode (250 / 255) on one side and a second polarity electrode (255 / 250) on the other side that are electrically connected to the diode structure (290, 291, 292), and a first polarity pad electrode (270 / 275) disposed on the first polarity electrode (250 / 255) so as to be connected to the first polarity electrode (250 / 255), the first polarity pad electrode (270 / 275) including a first connection portion connected to the first polarity electrode (250 / 255) with a first area in a plan view and a first electrode surface (272 / 278) having a second area exceeding the first area in a plan view.

[0285] [D2] The second area of the first polarity pad electrode (270 / 275) exceeds the area of the first polarity electrode (250 / 255) in a plan view. The semiconductor device (1, 101, 101a, 201, 201a) according to D1.

[0286] [D3]A semiconductor device (1, 101, 101a, 201, 201a) according to D1 or D2, further comprising a second-polarity pad electrode (275 / 270) disposed on the second-polarity electrode (255 / 250) so as to be connected to the second-polarity electrode (255 / 250), a second connection portion connected to the second-polarity electrode (255 / 250) in a third area in plan view, and a second electrode surface (278 / 272) having a fourth area exceeding the third area.

[0287] [D4]A semiconductor device (1, 101, 101a, 201, 201a) according to D3, wherein the fourth area of the second-polarity pad electrode (275 / 270) exceeds the area of the second-polarity electrode (255 / 250) in plan view.

[0288] [D5]The diode structure (290, 291, 292) includes a polysilicon layer, a first region (291 / 292) of a first conductivity type formed in the polysilicon layer, and a second region (292 / 291) of a second conductivity type formed in the polysilicon layer so as to form a pn junction with the first region (291 / 292). The first-polarity electrode (250 / 255) is electrically connected to the first region (291 / 292) of the diode structure (290, 291, 292), and the second-polarity electrode (255 / 250) is electrically connected to the second region (292 / 291) of the diode structure (290, 291, 292). A semiconductor device (1, 101, 101a, 201, 201a) according to any one of D1 to D4.

[0289] [D6]A semiconductor device (1, 101, 101a, 201, 201a) according to D5, further comprising a recess (293) formed in the main surface (11), wherein the diode structure (290, 291, 292) is disposed in the recess (293).

[0290] [D7]A semiconductor device (1, 101, 101a, 201, 201a) according to D6, wherein the diode structure (290, 291, 292) has an upper end located on the bottom wall side of the recess (293) with respect to the main surface (11).

[0291] [D8]The semiconductor device (1, 101, 101a, 201, 201a) according to any one of D1 to D7, further comprising: an active region (3, 103, 203) provided in the semiconductor layer (10); a non-active region (4, 104, 204) provided in a region outside the active region (3, 103, 203) in the semiconductor layer (10); and a gate structure (21) formed in the active region (3, 103, 203).

[0292] [D9]The semiconductor device (1, 101, 101a, 201, 201a) according to D8, wherein the diode structure (290, 291, 292) is formed in the non-active region (4, 104, 204).

[0293] [D10]The semiconductor device (1, 101, 101a, 201, 201a) according to any one of D1 to D9, wherein the diode structure (290, 291, 292) functions as a temperature-sensitive diode.

[0294] [E1]A semiconductor device including: a semiconductor layer having a main surface and containing SiC as a main component; a gate structure formed on the main surface; an insulating layer formed on the main surface so as to cover the gate structure; a gate main electrode disposed on the insulating layer and electrically connected to the gate structure; a gate pad electrode disposed on the gate main electrode so as to be connected to the gate main electrode, including a connection portion connected to the gate main electrode in a first area in plan view and an electrode surface having a second area exceeding the first area in plan view; a current conduction electrode disposed on the insulating layer with a space from the gate main electrode; and a current conduction pad electrode disposed on the current conduction electrode, wherein the current conduction pad electrode overlaps a part of the gate main electrode in plan view.

[0295] [E2]The semiconductor device according to E1, wherein the electrode surface of the gate pad electrode is exposed to the outside.

[0296] [E3] The semiconductor device according to E1 or E2, wherein the gate main electrode is formed in a line shape on the insulating layer.

[0297] [E4] The semiconductor device according to any one of E1 to E3, wherein the second area of the electrode surface exceeds the area of the gate main electrode.

[0298] [E5] The semiconductor device according to any one of E1 to E4, further comprising an active region provided in the semiconductor layer and a non-active region provided in a region outside the active region in the semiconductor layer, wherein the gate structure is formed in the active region, the gate main electrode is formed in the non-active region in a plan view, and the gate pad electrode overlaps the active region and the non-active region in a plan view.

[0299] [E6] The semiconductor device according to any one of E1 to E5, wherein the gate pad electrode overlaps a part of the current conduction electrode in a plan view.

[0300] [E7] The semiconductor device according to any one of E1 to E6, wherein the current conduction pad electrode includes an electrode surface having a third area that exceeds the second area of the gate pad electrode in a plan view.

[0301] [E8] The semiconductor device according to any one of E1 to E7, wherein the gate structure is a trench gate structure.

[0302] [E9] The semiconductor device according to any one of E1 to E8, wherein the gate main electrode is formed in a line shape in a plan view.

[0303] [E10] The active region includes a plurality of divided regions provided in the semiconductor layer with a gap therebetween in a plan view. The semiconductor device according to E5, wherein the non-active region includes a portion located between the plurality of divided regions in the semiconductor layer in a plan view.

[0304] [E11]The gate main electrode includes a portion overlapping a portion located between the plurality of divided regions in the non-active region in a plan view. The semiconductor device according to E10, wherein the gate pad electrode includes a portion overlapping a portion located between the plurality of divided regions in the non-active region in a plan view.

[0305] [E12]The semiconductor device according to E10 or E11, wherein the gate pad electrode overlaps the plurality of divided regions in a plan view.

[0306] [E13]The semiconductor device according to any one of E1 to E12, wherein at least one of the gate pad electrode and the current conduction pad electrode is made of copper or a copper alloy.

[0307] [E14]The active region provided in the semiconductor layer, and a non-active region provided in a region outside the active region in the semiconductor layer, and further includes the gate structure includes a plurality of gate structures, the plurality of gate structures are formed in the active region, the gate main electrode overlaps the non-active region in a plan view, The semiconductor device according to any one of E1 to E13, wherein the gate pad electrode overlaps the active region and the non-active region in a plan view.

[0308] [E15]The semiconductor device according to any one of E1 to E14, wherein in a plan view, the current conduction pad electrode is arranged so as to surround the gate pad electrode.

[0309] In a plan view, the area of the first portion of the active region disposed in a region between the first side of the semiconductor layer and the gate pad electrode is larger than the area of the second portion of the active region disposed in a region between the second side facing the first side of the semiconductor layer and the gate pad electrode. The semiconductor device according to any one of E5, E10 to E12, and E14.

[0310] [E17] A semiconductor layer having a main surface, an active region provided in the semiconductor layer, a non-active region provided in a region outside the active region in the semiconductor layer, a plurality of gate structures formed in the active region, an insulating layer formed on the main surface so as to cover the plurality of gate structures, a gate main electrode disposed on the insulating layer so as to be electrically connected to the plurality of gate structures and overlapping the non-active region in a plan view, and a gate pad electrode disposed on the gate main electrode so as to be electrically connected to the gate main electrode and overlapping the active region and the non-active region in a plan view. The active region includes a plurality of divided regions provided in the semiconductor layer at intervals in a plan view, the non-active region includes a portion located between the plurality of divided regions in the semiconductor layer in a plan view, the gate main electrode includes a portion overlapping a portion located between the plurality of divided regions in the non-active region in a plan view, and the gate pad electrode includes a portion overlapping a portion located between the plurality of divided regions in the non-active region in a plan view. A semiconductor device.

[0311] [E18] The gate main electrode is formed in a line shape in a plan view. The semiconductor device according to E17.

[0312] [E19] The gate pad electrode includes a connection portion connected to the gate main electrode with a first area in a plan view and an electrode surface having a second area exceeding the first area in a plan view. The semiconductor device according to E17 or E18.

[0313] The gate pad electrode overlaps with a plurality of the divided regions in a plan view, and the semiconductor device according to any one of E17 to E19.

[0314] [E21] The electrode surface of the gate pad electrode is exposed to the outside, and the semiconductor device according to E19.

[0315] [E22] The gate main electrode is formed in a line shape on the insulating layer, and the semiconductor device according to any one of E17 to E21.

[0316] [E23] The second area of the electrode surface exceeds the area of the gate main electrode, and the semiconductor device according to E19 or E21.

[0317] [E24] Further includes a current conduction electrode disposed on the insulating layer with a space from the gate main electrode, and the semiconductor device according to any one of E19, E21, and E23.

[0318] [E25] The gate pad electrode overlaps with a part of the current conduction electrode in a plan view, and the semiconductor device according to E24.

[0319] [E26] Further includes a current conduction pad electrode disposed on the current conduction electrode, and the semiconductor device according to E24 or E25.

[0320] [E27] The current conduction pad electrode overlaps with a part of the gate main electrode in a plan view, and the semiconductor device according to E26.

[0321] [E28] The current conduction pad electrode includes an electrode surface having a third area that exceeds the second area of the gate pad electrode in a plan view, and the semiconductor device according to E26 or E27.

[0322] [E29] The gate structure is a trench gate structure, and the semiconductor device according to any one of E17 to E28.

[0323] [E30]The semiconductor device according to any one of E17 to E29, wherein at least one of the gate pad electrode and the current conduction pad electrode is made of copper or a copper alloy.

[0324] [E31]The semiconductor device according to any one of E26 to E28 and E30, wherein in plan view, the current conduction pad electrode is arranged so as to surround the periphery of the gate pad electrode.

[0325] [E32]The semiconductor device according to any one of E17 to E31, wherein in plan view, the area of the first portion of the active region arranged in the region between the first side of the semiconductor layer and the gate pad electrode is larger than the area of the second portion of the active region arranged in the region between the second side of the semiconductor layer facing the first side and the gate pad electrode.

[0326] In addition, various changes, replacements, additions, omissions, etc. can be made to each of the above embodiments within the scope of the claims or their equivalents. The present invention can be used for semiconductor devices, semiconductor packages, etc. as industrial applications.

Explanation of Reference Numerals

[0327] 1 Semiconductor device 3 Active region 4 Non-active region 10 Semiconductor layer 11 First main surface (main surface) 21 Trench gate structure (gate structure) 50 Main surface gate electrode (gate main electrode) 55 Main surface source electrode (current conduction electrode) 61 Lower insulating layer (insulating layer) 62 Side insulating layer (first resin layer) 63 Upper insulating layer (first resin layer) 65 End insulating layer (first resin layer) 70 Gate pad (gate pad electrode) 73 Upper surface of gate pad (electrode surface) 75 Source pad (source pad electrode) Upper surface (electrode surface) of 76 source pads 80 Mold layer (second resin layer) 101 Semiconductor device 101a Semiconductor device 201 Semiconductor device 201a Semiconductor device 250 Anode electrode (first polarity electrode) 255 Cathode electrode (second polarity electrode) 290 Diode (diode structure) 293 Concave portion (recess)

Claims

1. A semiconductor layer having a main surface, an active region provided in the semiconductor layer, a non-active region provided in a region outside the active region in the semiconductor layer, a plurality of gate structures formed in the active region, an insulating layer formed on the main surface so as to cover the plurality of gate structures, a gate main electrode disposed on the insulating layer so as to be electrically connected to the plurality of gate structures and overlapping the non-active region in plan view, a current conducting electrode disposed on the insulating layer with a space from the gate main electrode, a gate pad electrode disposed above the gate main electrode and the current conducting electrode so as to be electrically connected to the gate main electrode and overlapping the active region and the non-active region in plan view, and the active region includes a plurality of divided regions provided in the semiconductor layer with a space therebetween in plan view, the non-active region includes a portion located between the plurality of divided regions in the semiconductor layer in plan view, the gate main electrode includes a portion overlapping a portion located between the plurality of divided regions in the non-active region in plan view, the gate pad electrode includes a portion overlapping a portion located between the plurality of divided regions in the non-active region in plan view, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the gate main electrode is formed in a line shape in plan view.

3. The semiconductor device according to claim 1 or 2, wherein the gate pad electrode includes a connection portion connected to the gate main electrode with a first area in plan view and an electrode surface having a second area exceeding the first area in plan view.

4. The semiconductor device according to any one of claims 1 to 3, wherein the gate pad electrode overlaps a plurality of the divided regions in plan view.

5. The semiconductor device according to claim 3, wherein the electrode surface of the gate pad electrode is exposed to the outside.

6. The semiconductor device according to any one of claims 1 to 5, wherein the gate main electrode is formed in a line shape on the insulating layer.

7. The semiconductor device according to claim 3 or 5, wherein the second area of the electrode surface exceeds the area of the gate main electrode.

8. The semiconductor device according to any one of claims 1 to 7, wherein the gate pad electrode overlaps a part of the current conducting electrode in a plan view.

9. The semiconductor device according to claim 3 or 7, further comprising a current conducting pad electrode disposed on the current conducting electrode.

10. The semiconductor device according to claim 9, wherein the current conducting pad electrode overlaps a part of the gate main electrode in a plan view.

11. The semiconductor device according to claim 9 or 10, wherein the current conducting pad electrode includes an electrode surface having a third area that exceeds the second area of the gate pad electrode in a plan view.

12. The semiconductor device according to any one of claims 1 to 11, wherein the gate structure is a trench gate structure.

13. The semiconductor device according to any one of claims 1 to 12, wherein at least one of the gate pad electrode and the current conducting pad electrode is made of copper or a copper alloy.

14. The semiconductor device according to any one of claims 9 to 11 and 13, wherein the current conducting pad electrode is disposed so as to surround the gate pad electrode in a plan view.

15. The semiconductor device according to any one of claims 1 to 14, wherein the area of the first portion of the active region disposed in the region between the first side of the semiconductor layer and the gate pad electrode is larger than the area of the second portion of the active region disposed in the region between the second side of the semiconductor layer facing the first side and the gate pad electrode.

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