Power semiconductor device with reduced strain

Abstract

To provide a power semiconductor device with reduced strain.SOLUTION: The semiconductor device includes: a drift layer including an active region; a conductive runner electrode provided on the drift layer along a runner electrode path; a metal runner extending along a metal runner path following a perimeter of the active region; and an insulating layer, a portion of which is located between the runner electrode and the metal runner. The width of the metal runner is narrower than that of the runner electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims priority to U.S. Patent Application No. 17 / 177,641, filed on February 17, 2021.

[0002] This disclosure relates to power semiconductor devices, and more particularly to a layout method for reducing the strain of power semiconductor devices.

Background Art

[0003] Power semiconductor devices handle high voltages and high currents, so they frequently experience large temperature fluctuations. Such large temperature fluctuations can cause large strains in various layers of the device, and in some cases, can lead to cracks, delamination, and failures. Therefore, there is a need for power semiconductor devices with reduced strain.

Summary of the Invention

Means for Solving the Problems

[0004] In one embodiment, a power semiconductor device includes a drift layer, an active region, an insulating layer, and a runner electrode. The runner electrode includes a conductive material provided along a runner electrode path. The runner electrode path is along the perimeter of the active region. The runner electrode includes one or more runner electrode strain - relaxation regions that are regions where no conductive material is provided. Providing one or more strain - relaxation regions reduces the strain caused by the runner electrode, and as a result, improves the reliability of the power semiconductor device.

[0005] In one embodiment, the power semiconductor device further includes a runner via and a metal runner. The runner via is along a runner via path, and the metal runner is along a metal runner path. The runner via is an opening in the insulating layer, and the runner electrode is exposed through the opening. The metal runner fills the runner via and makes electrical contact with the runner electrode.

[0006] In one embodiment, the runner via is segmented to provide a number of segmented runner vias separated by a portion of the insulating layer. By segmenting the runner via, the strain caused by the runner via may be reduced, improving the reliability of the power semiconductor device.

[0007] In one embodiment, any of the runner electrode path, the runner via path, and the metal runner path may be different from the others. By providing the runner electrode, the runner via, and the metal runner in this way, the strain caused by these layers may be reduced, thereby improving the performance of the power semiconductor device.

[0008] In one embodiment, the runner electrode, the runner via, and the metal runner path are defined by an inner edge and an outer edge. In various embodiments, one of the inner edge or the outer edge is not parallel to the path defining the runner electrode, the runner via, and / or the metal runner path. By providing the runner electrode, the runner via, and / or the metal runner path in this way, the strain may be reduced, thereby improving the reliability of the power semiconductor device.

[0009] In one embodiment, the switching power semiconductor device includes an electrode assembly configured such that the failure rate of the switching power semiconductor device when subjected to a thermal cycle test is less than 2000 ppm, and the temperature of the switching power semiconductor device is repeated between a minimum temperature of -40°C or less and a maximum temperature of 150°C or more.

[0010] In another aspect, to obtain additional advantages, any of the foregoing aspects may be combined individually or together, and / or various distinct aspects and features as described herein may be combined. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements, unless the contrary is stated herein.

[0011] Those skilled in the art will understand the scope of the present disclosure and recognize its additional aspects after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

[0012] The accompanying drawings, which are incorporated herein and form a part thereof, illustrate some aspects of the present disclosure and are useful in explaining the principles of the present disclosure together with the description herein.

Brief Description of the Drawings

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MODE FOR CARRYING OUT THE INVENTION

[0014] The embodiments described below represent the information necessary for those skilled in the art to implement the embodiments and show the best mode of implementing the embodiments. By reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize the applications of these concepts that are not specifically mentioned herein. It should be understood that these concepts and their applications are included within the scope of the present disclosure and the appended claims.

[0015] The terms first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. The term "and / or" as used herein includes any combination and all combinations of one or more of the associated listed items.

[0016] When an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it will be understood that it can be directly on or extend directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, no intervening elements are present. Similarly, when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it will be understood that it can be directly on or extend directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, no intervening elements are present. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that it can be directly connected or directly coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0017] Relative terms such as "lower" or "upper" or "top" or "bottom" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the drawings. It will be understood that these terms, as well as those described above, are intended to encompass various orientations of the device in addition to the orientation shown in the drawings.

[0018] The terms used in this specification are for the sole purpose of describing particular embodiments and are not intended to limit the disclosure. As used in this specification, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "comprises", "comprising", "includes", and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Further, the terms used in this specification should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0020] Embodiments of the present disclosure will be described herein with reference to schematic diagrams of embodiments. Thus, the actual dimensions of layers and elements may vary, for example, variations from the shape of the drawings as a result of manufacturing techniques and / or tolerances are expected. For example, regions illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularities. Accordingly, the regions shown in the drawings are schematic and their shapes are not intended to indicate the exact shape of the regions of the device and are not intended to limit the scope of the present disclosure. In addition, the size of a structure or region may be exaggerated relative to other structures or regions for purposes of illustration, and thus is provided to show the general structure of the subject matter and may or may not be drawn to scale. Common elements between the drawings may be denoted by common element numbers herein and may not be re-described later.

[0021] FIG. 1 shows a cross-sectional view of a power semiconductor die 10 according to an embodiment of the present disclosure. The power semiconductor die 10 includes a drift layer 12 and an insulating layer 14 on the drift layer 12. The drift layer 12 includes an active area 16 in its central portion. A runner electrode 18 surrounds the active area 16. The runner electrode 18 is separated from the drift layer 12 by a portion of the insulating layer 14. A metal runner 20 is on the runner electrode 18 on the surface of the insulating layer 14 on the opposite side of the drift layer 12. A runner via 22 electrically connects the metal runner 20 and the runner electrode 18 by providing an opening in the insulating layer 14 and is filled by a portion of the metal runner 20. An additional metal runner 24 is on a portion of the drift layer 12 outside the metal runner 20 on the surface of the insulating layer 14 on the opposite side of the drift layer 12. An additional runner via 26 electrically connects the additional metal runner 24 to the drift layer 12 by providing an opening in the insulating layer 14 and is filled by a portion of the additional metal runner 24. A passivation layer 27 is on the metal runner 20 and the additional metal runner 24. The passivation layer 27 electrically insulates and protects the metal runner 20 and the additional metal runner 24 from the environment.

[0022] Although not shown, the active area 16 of the drift layer 12 includes several implantation regions interconnected to provide one or more power semiconductor devices such as transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), diodes, etc.). The metal runner 20 is electrically coupled to one or more of these implants by the runner electrode 18, and the runner electrode 18 is coupled to one or more implants via an electrode mesh that extends from the runner electrode 18 into the active area 16 but is not shown in FIG. 1. An additional metal runner 24 is electrically coupled to one or more other implants by one or more implantation regions of the drift layer 12, which is also not shown in FIG. 1.

[0023] In an exemplary embodiment where the power semiconductor die 10 provides a MOSFET, the runner electrode 18 may be a runner for the gate electrode such that the metal runner 20 is coupled to the gate contact and distributes the gate current to the gate electrode. In this example, the additional metal runner 24 is coupled to the source contact and distributes the source current to one or more implantation regions of the drift layer 12. Those skilled in the art will understand that additional portions of the power semiconductor die 10 not directly related to the present disclosure are not shown in FIG. 1 to avoid obscuring the drawings.

[0024] In some embodiments, the drift layer 12 may include silicon carbide. However, the present disclosure is not limited to a particular material system for the drift layer 12. In various embodiments, the drift layer 12 may include silicon, gallium nitride, gallium arsenide, or any other semiconductor material. The insulating layer 14 may include any suitable electrical insulating material. In one embodiment, the insulating layer 14 includes a dielectric material such as silicon dioxide. The runner electrode 18 may include any suitable conductive material. In one embodiment, the runner electrode 18 includes doped polysilicon. The metal runner 20 and the additional metal runner 24 may include any suitable conductive metal such as copper, aluminum, tin, or a metal alloy. In various embodiments, a portion of the metal runner 20 filling the runner via 22 may be the same material as a portion of the metal runner 20 on the surface of the insulating layer 14, or it may be a different material, and they may be deposited together or separately. Similarly, a portion of the additional metal runner 24 filling the additional runner via 26 may be the same material as a portion of the additional metal runner 24 on the surface of the insulating layer 14, or it may be a different material, and they may be deposited together or separately.

[0025] FIG. 2 shows a top view of the power semiconductor die 10 according to an embodiment of the present disclosure. In particular, the passivation layer 27 and the metal runners 20 are not shown in order to avoid making the drawing difficult to understand. As shown, the runner electrodes 18, the metal runners 20 (not shown but still present), and the runner vias 22 surround the active area 16. The additional metal runners 24 and the additional runner vias 26 surround the runner electrodes 18, the metal runners 20, and the runner vias 22. The reason for providing the metal runners 20 and the additional metal runners 24 around the periphery of the power semiconductor die 10 as shown is to more preferably distribute current around the periphery of the power semiconductor die 10, and as a result, reduce resistance. For example, in the above example where the power semiconductor die 10 provides a MOSFET such that the metal runner 20 is a gate contact and the additional metal runner 24 is a source contact, it is important that the resistance of these contacts be minimized for the performance of the MOSFET. As shown in FIG. 2, an electrode mesh 28 is provided over the active area 16 and is electrically coupled to the runner electrodes 18. A central electrode 30 extends over the central portion of the active area 16. A pad electrode 32 is superimposed on the central electrode 30. A central electrode via 34 electrically couples the central electrode 30 and the pad electrode 32 to a metal contact pad, which is a metal layer provided over the pad electrode 32 on the insulating layer 14 and is used to couple an external circuit to the power semiconductor die 10. The metal contact pad is not shown in order to avoid making the drawing difficult to understand, but is provided directly over the pad electrode 32 in the same shape as the pad electrode 32.

[0026] Generally, during a thermal cycle, there are two areas in the power semiconductor die 10 that are subject to high levels of strain. First, the power semiconductor die 10 is subject to high levels of strain in the area that defines the pad electrode 32. To reduce the amount of strain in this area, as shown in FIG. 3, the pad electrode 32 can be provided only under the central electrode via 34. By significantly reducing the amount of material in the pad electrode 32, the strain caused by the pad electrode 32 may be significantly reduced. In applications where it is necessary to control the gate capacitance, as shown in FIG. 4, the pad electrode 32 may include an inner mesh portion as a solid line boundary. In both FIGS. 3 and 4, the runner electrode 18 may also be narrowed to reduce its width. By reducing the amount of material in the runner electrode 18, the strain caused by the runner electrode 18 may be similarly reduced. In various embodiments, the surface area of the pad electrode 32 decreases to less than 50% of the surface area of the pad electrode 32, less than 25% of the surface area of the pad electrode 32, and less than 10% of the surface area of the pad electrode 32.

[0027] In addition to the pad electrode 32, the corners of the power semiconductor die 10 are also subject to very high levels of strain during a thermal cycle. In particular, the runner electrode 18, the metal runner 20, the runner via 22, the additional metal runner 24, and the additional runner via 26 may all be subject to high levels of strain as they approach the corners of the power semiconductor die 10. This strain may cause delamination, cracking, and even breakage of various layers. This may cause the failure of the power semiconductor die 10.

[0028] To assist in the description of further embodiments of the present disclosure, FIG. 5A shows comprehensive features 38 of a semiconductor die according to an embodiment of the present disclosure. The comprehensive features 38 are defined by a path 40 that defines the general shape of the comprehensive features 38. The comprehensive features 38 also have a width defined as the distance between an inner edge 42I and an outer edge 42O. The material constituting the features is provided between the inner edge 42I and the outer edge 42O. In the simplest case, as shown in FIG. 5A, the inner edge 42I and the outer edge 42O are provided parallel to the path 40. However, in some cases, one of the inner edge 42I or the outer edge 42O may be provided so as not to be parallel to the path 40. Thus, FIG. 5B shows the inner edge 42I that is not parallel to the path 40, while FIG. 5C shows the outer edge 42O that is not parallel to the path 40. In particular, at least one of the inner edge 42I and the outer edge 42O is always parallel to the path 40. Unless otherwise specified, it can be assumed that both the inner edge 42I and the outer edge 42O are parallel to the path 40. When describing the following embodiments, to avoid making the drawings difficult to understand, the paths and edges of various features will be described but are not shown in the drawings. The paths and edges are defined as described herein with respect to FIGS. 5A - 5C. With respect to the metal runner 20 and the additional metal runner 24, their inner and outer edges are defined not by the edges within the runner vias 22 and the additional runner vias 24, respectively, but by the edges on the surface of the insulating layer 14 on the opposite side of the drift layer 12.

[0029] FIG. 6 shows a top view of a corner of the power semiconductor die 10 according to an embodiment of the present disclosure. The passivation layer 27 is not shown to avoid obscuring the drawing. As shown, the path of the runner electrode 18 does not follow the contour around the power semiconductor die 10, but rather provides a gentle curve to its corner. The path of the metal runner 20 and the path of the runner via 22 overlap the path of the runner electrode 18. Similarly, the additional metal runner 24 and the additional runner via 26 provide a gentle curve to the corner of the power semiconductor die 10 and have overlapping paths. Providing a gentle curve to the corners of the power semiconductor die 10 reduces the strain that would otherwise occur if those layers were to meet the corners along the perimeter of the power semiconductor die 10 such that they provide a 90-degree angle. However, even the power semiconductor die 10 shown in FIG. 5 is subject to relatively high levels of strain, and as a result, may have reliability issues during thermal cycling.

[0030] FIG. 7A shows a top view of a corner of the power semiconductor die 10 according to an embodiment of the present disclosure. To avoid obscuring the drawing, the passivation layer 27 and the metal runners 20 are not shown. As shown in FIG. 7, the runner electrode 18 includes a number of strain relief regions 36 that are regions where the conductive material of the runner electrode 18 is not provided. The strain relief regions 36 may be of any shape, and for that purpose, in FIG. 7A, they are shown in various shapes including ellipses, radial slots, staggered slots, etc. The different shapes shown in FIG. 7A represent different embodiments that may or may not be combined such that the strain relief regions 36 may all be of the same shape or of different shapes. As described above, the runner electrode 18 is defined by an inner edge and an outer edge, and a conductive material is provided between these edges. The strain relief regions 36 are provided between the inner edge and the outer edge of the runner electrode 18. In particular, the runner electrode 18 is separated from the electrode mesh 28. When the electrode mesh 28 forms a grid including areas where the conductive material is not provided, the runner electrode 18 is typically provided as a continuous layer of conductive material between the inner edge and the outer edge. By providing the strain relief regions 36 in the runner electrode 18, the strain caused by the runner electrode 18 may be interrupted, as a result of which the overall strain is reduced, and as a result, the reliability of the power semiconductor die 10 is improved. In one embodiment, the strain relief regions 36 are provided so as not to intersect the lines defining the path of any individual runner (each line of conductive material) in the electrode mesh 28. In other words, when each line of the conductive material of the electrode mesh 28 extends into the runner electrode 18, the strain relief regions 36 may be provided so as not to intersect any of these lines. This may prevent the strain relief regions 36 from interfering with the flow of current from the runner electrode 18 to the electrode mesh 28. In some embodiments, the insulating layer 14 may fill the voids in the runner electrode 18 left by the strain relief regions 36. As shown, the strain relief regions 36 may be of any shape including rectangles and circles, but may also be of any other arbitrary shape such as polygons or arbitrary shapes.

[0031] FIG. 7B shows a cross-sectional view taken along line A-A' of FIG. 7A to further illustrate the strain relaxation region 36. As shown, the strain relaxation regions 36 are regions where the conductive material of the runner electrode 18 is not provided so that the insulating layer 14 fills the regions. They do not affect the metal runners 20.

[0032] FIG. 8A shows a top view of a corner of the power semiconductor die 10 according to an embodiment of the present disclosure. To avoid obscuring the drawing, the passivation layer 27 is not shown. As shown in FIG. 8A, the runner via 22 and the additional runner via 26 are modified to reduce strain. This may be achieved in several ways, each of which may be used together or separately. The modification is described herein with respect to the runner via 22, but is equally applicable to the additional runner via 26 or any other via. First, FIG. 8A shows that the runner via 22 may be segmented such that it is provided as a plurality of runner via sections 38. In other words, the runner via 22 is no longer provided as a continuous opening in the insulating layer 14, but rather is dispersed by a portion of the insulating layer 14 that remains intact. In addition to or alternatively to segmenting the runner via 22, the runner via 22 may also be provided such that the path of the runner via 22 is not the same as the path of the runner electrode 18 or the path of the metal runner 20. In particular, the path of the runner via 22 may not completely overlap the path of the runner electrode 18 and / or the path of the metal runner 20, or may not be parallel thereto. The path of the runner via 22 may be provided in a meandering shape as shown, but may be provided in any manner such that it is different from and not parallel to the path of the runner electrode 18 and / or the path of the metal runner 20. Finally, in addition to or alternatively to segmenting the runner via 22 and providing the runner via 22 along a path different from that of the runner electrode 18 and the metal runner 20, the runner via 22 may be provided in a cross-hatch pattern, where the runner via 22 provides at least one first portion that overlaps at least one second portion. In some embodiments, the first portion is perpendicular to the second portion. Together or separately, these modifications to the runner via 22 may reduce the strain caused by the runner via 22, thereby improving the reliability of the power semiconductor die 10.

[0033] FIG. 8B shows a cross-sectional view of the power semiconductor die 10 along line B-B' to illustrate that the runner via 22 is segmented into two separate runner via sections separated by a portion of the insulating layer 14.

[0034] FIG. 9A shows a top view of a corner of the power semiconductor die 10 according to an embodiment of the present disclosure. To avoid obscuring the drawing, the passivation layer 27 is not shown. The embodiment shown in FIG. 9A combines the strain relief region 36 in the runner electrode 18 shown in FIG. 7A with a modification to the runner via 22 shown in FIG. 8A. The combination of these modifications may further reduce strain, thereby improving the reliability of the power semiconductor die 10.

[0035] FIG. 9B shows a cross-sectional view of the power semiconductor die 10 along line C-C' to illustrate the strain relief region 36 and the segmentation of the runner via 22.

[0036] FIG. 10 shows a top view of a corner of the power semiconductor die 10 according to an embodiment of the present disclosure. To avoid obscuring the drawing, the passivation layer 27 is not shown. In this embodiment, the path of the metal runner 20 is not the same as the path of the runner electrode 18 or the path of the runner via 22. In other words, the path of the metal runner 20 does not overlap or is not parallel to the path of the runner electrode 18 or the runner via 22. As shown, the path of the metal runner 20 is provided in a meandering shape. However, the path of the metal runner 20 may be provided in any manner without departing from the principles of the present disclosure. The inner edge of the runner electrode 18 is also not parallel to the path of the runner electrode 18, but rather is provided along the inner edge of the metal runner 20. Providing the metal runner 20 and the runner electrode 18 in this way may reduce strain, and as a result, improve the reliability of the power semiconductor die 10.

[0037] FIG. 11 shows a top view of the power semiconductor die 10 according to an embodiment of the present disclosure. To avoid obscuring the drawing, the passivation layer 27 is not shown. This embodiment essentially combines the changes to the runner via 22 described above with respect to FIG. 8A and the changes to the metal runner 20 described above with respect to FIG. 10. By combining these features, the strain may be further reduced, thereby further improving the reliability of the power semiconductor die 10.

[0038] The changes described above with respect to FIGS. 7-11 relate to the runner electrode 18, the metal runner 20, and the runner via 22, but the same changes can be made to the additional metal runner 24 and the additional runner via 26. Further, the same changes can be made to the central electrode 30, the central electrode via 34, and the pad electrode 32 to reduce the strain in these areas.

[0039] In addition to or separate from the improvements described above, the curvature of the paths of the runner electrode 18, the metal runner 20, the runner via 22, the additional metal runner 24, and the additional runner via 26 may be changed to reduce strain. In particular, the paths defining the runner electrode 18, the metal runner 20, the runner via 22, the additional metal runner 24, and the additional runner via 26 may provide chamfered corners with respect to the corners of the power semiconductor die 10, as shown in FIG. 12. Chamfering the paths of the runner electrode 18, the metal runner 20, the runner via 22, the additional metal runner 24, and the additional runner via 26 may move these layers away from the locations in the power semiconductor die 10 that are most subject to strain, thereby reducing the potential for complication and improving the reliability of the power semiconductor die 10.

[0040] In another embodiment, the paths of the runner electrode 18, the metal runner 20, the runner via 22, the additional metal runner 24, and the additional runner via 26 may provide a radius opposite to that of the corner of the power semiconductor die 10, as shown in FIG. 13. Again, this may space these layers away from the location of the power semiconductor die 10 that is subject to the highest degree of strain, which results in an improvement in the reliability of the power semiconductor die 10.

[0041] In addition to, or alternatively to, the improvements described above, any one of the runner electrode 18, the metal runner 20, the runner via 22, the additional metal runner 24, and the additional runner via 24 may be provided such that its inner edge is not parallel to its outer edge. FIG. 14 shows an additional metal runner having an outer edge that is not parallel to its inner edge. In particular, FIG. 14 shows an additional metal runner 24 having a wavy or serpentine outer edge together with a straight inner edge. The present disclosure contemplates inner edges and / or outer edges having any shape. Although not shown, similar modifications can be made to the metal runner 20.

[0042] In another embodiment, slots may be formed in the outer edges of the metal runner 20 and / or the additional metal runner 24, as shown in FIG. 15. The inner and outer edges of the metal runner 20 and / or the additional metal runner 24 may also be wavy, as shown in FIG. 16. Finally, the inner portion of the metal runner 20 and / or the additional metal runner 24 may be omitted to form slots or other areas, and the conductive material of the metal runner and / or the additional metal runner 24 is not provided between its inner edge and its outer edge, as shown in FIGS. 17 and 18. FIG. 17 shows an additional metal runner 24 having several areas where the conductive material is not provided, and FIG. 18 shows an additional metal runner 24 having a single continuous area where the conductive material is not provided.

[0043] Generally, the present disclosure contemplates changing any of the runner electrodes 18, metal runners 20, runner vias 22, additional metal runners 24, and additional runner vias 26, inner edges, and outer edges to reduce strain and, as a result, improve the reliability of the power semiconductor die 10. In particular, for strain-induced failures, one way to measure the reliability of the semiconductor die 10 is the failure rate of the semiconductor die 10 when subjected to a thermal cycle test. The thermal cycle test includes repeating the temperature of the semiconductor die 10 between a minimum temperature and a maximum temperature for a given number of cycles. In one embodiment, the minimum temperature is 40 °C or less, the maximum temperature is 150 °C or more, and the number of cycles is at least 1000. In other embodiments, the thermal cycle test may be more severe such that one or more of the conditions that the minimum temperature is -55 °C or less, the maximum temperature is 175 °C or more, and the number of cycles is 2000 or more, 3000 or more, or even 5000 or more are applied. One or more of the improvements described herein may enable a power semiconductor die 10 that has a failure rate of less than 2000 ppm when subjected to a thermal cycle test as described above. This is at least an order of magnitude less than conventional power semiconductor dies without the improvements of the present disclosure. In various embodiments, the improvements described herein may enable even greater reliability such that the power semiconductor die 10 has a failure rate of less than 1000 ppm, less than 500 ppm, less than 100 ppm, and less than 20 ppm.

[0044] It is contemplated that any of the foregoing aspects and / or various separate aspects and features as described herein may be combined to obtain additional advantages. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments, unless the present specification states to the contrary.

[0045] Those skilled in the art will recognize improvements and changes to the preferred embodiments of the present disclosure. All such improvements and changes are considered to be within the scope of the concepts disclosed herein and the scope of the appended claims.

Claims

1. A drift layer including an active region, A conductive runner electrode provided along a runner electrode path on the drift layer, A metal runner extending along a metal runner path along the periphery of the active region, An insulating layer, wherein a part of the insulating layer is between the runner electrode and the metal runner, and the insulating layer A semiconductor device comprising: The semiconductor device, wherein the width of the metal runner is narrower than the width of the runner electrode.

2. The semiconductor device further includes a runner via along a runner via path, the runner via is an opening of the insulating layer, and the runner electrode is exposed through the opening, The semiconductor device according to claim 1, wherein the runner via is segmented to provide a plurality of segmented runner vias separated by respective portions of the insulating layer.

3. The semiconductor device according to claim 2, wherein the metal runner path is not the same as the runner via path.

4. The runner electrode includes a conductive material between an inner runner electrode edge and an outer runner electrode edge, The semiconductor device according to any one of claims 1 to 3, wherein one or more of the inner runner electrode edge and the outer runner electrode edge are not parallel to the runner electrode path.

5. The semiconductor device further includes an electrode mesh on the active region and coupled to the runner electrode, the electrode mesh includes a grid of electrode mesh runners extending between opposing side surfaces of the inner runner electrode edge, The runner electrode includes one or more runner electrode strain relief regions, the one or more runner electrode strain relief regions are regions where the conductive material is not provided, The semiconductor device according to claim 4, wherein the one or more runner electrode strain relief regions are provided so as not to intersect a line defining any one path of the grid of the electrode mesh runners.

6. The semiconductor device according to claim 1, wherein the runner electrode includes a curved corner.

7. The semiconductor device according to claim 1, wherein the metal runner includes a curved corner.

8. An additional runner via extending along an additional runner via path, the additional runner via being an opening of the insulating layer, an additional metal runner that fills the additional runner via and is in electrical contact with the drift layer The semiconductor device according to claim 1, further comprising

9. The semiconductor device according to claim 8, wherein the additional metal runner includes a curved corner.

10. The semiconductor device according to claim 9, wherein the additional metal runner is located outside the runner electrode.

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