Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of simplifying its configuration.SOLUTION: In a cell region, a first conductivity type first impurity region and a second conductivity type second impurity region connected to a first electrode are formed on a surface layer of a base layer. In a temperature detection region 2, a diode element 40 having a first conductive type first component layer 42 formed on the surface layer of the base layer 21 and a second conductive type second component layer 41 formed on the surface layer of the base layer 21 and connected to the first component layer in the plane direction of the substrate is formed.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a SiC semiconductor device composed of silicon carbide (hereinafter also referred to as SiC) having a temperature detection element.

Background Art

[0002] Conventionally, for example, Patent Document 1 has proposed a SiC semiconductor device having a temperature detection element. Specifically, in this SiC semiconductor device, a semiconductor substrate made of SiC is provided, and semiconductor elements such as MOSFETs are formed on the semiconductor substrate. A temperature detection element is formed in a portion of the semiconductor substrate different from the portion where the semiconductor elements are formed. Note that MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. The temperature detection element is composed of a diode element in which a trench is formed in the semiconductor substrate and an n-type cathode layer and a p-type anode layer are embedded in the trench. More specifically, the temperature detection element is configured such that the cathode layer is disposed along the wall surface of the trench and the anode layer is disposed within the cathode layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in such a SiC semiconductor device, a cathode layer and an anode layer are sequentially embedded in a trench to form a temperature detection element. Therefore, in order to obtain a temperature detection element having desired diode characteristics, detailed control of the film thickness of the cathode layer and the anode layer is required, which tends to complicate the configuration and reduce the design freedom.

[0005] In view of the above points, an object of the present invention is to provide a SiC semiconductor device capable of improving the degree of design freedom.

Means for Solving the Problems

[0006] In claim 1 for achieving the above object, a semiconductor device having a cell region (1) in which a semiconductor element is formed and a temperature detection region (2) in which a temperature detection element is formed, the semiconductor device comprising: a substrate (11) having a first conductivity type or a second conductivity type and made of silicon carbide; a first conductivity type drift layer (19) formed on the substrate and having a lower impurity concentration than the substrate; a second conductivity type base layer (21) formed on the drift layer; a first electrode (28) formed on the opposite side of the substrate with the drift layer interposed therebetween and electrically connected to the semiconductor element formed in the cell region; and a second electrode (29) formed on the opposite side of the drift layer with the substrate interposed therebetween and electrically connected to the semiconductor element formed in the cell region. In the cell region, a first conductivity type first impurity region (22) and a second conductivity type second impurity region (23) that are connected to the first electrode and constitute the semiconductor element are formed in the surface layer portion of the base layer. In the temperature detection region, a first conductivity type first constituent layer (42) formed in the surface layer portion of the base layer and a second conductivity type second constituent layer (41) formed in the surface layer portion of the base layer and connected to the first constituent layer in the plane direction of the substrate are provided, and a diode element (40) having these is formed. The cell region includes a drift layer including a first conductivity type low concentration layer (13) disposed on the substrate and having a lower impurity concentration than the substrate, a second conductivity type first deep layer (15) formed in the drift layer and having a plurality of linear portions with one direction in the plane direction of the substrate as the longitudinal direction, a second conductivity type second deep layer (18) formed in the drift layer and disposed on the first deep layer, and a base layer disposed on the second deep layer. The temperature detection region includes a drift layer including a low concentration layer disposed on the substrate, a second conductivity type first deep layer (15) formed in the drift layer, and a base layer formed on the drift layer. The first deep layer in the temperature detection region is electrically connected to the first electrode via a second conductivity type extraction portion (70).

[0007] According to this, compared with the case where a first constituent layer and a second constituent layer are arranged in a trench to form a diode element, there is no need to form a trench, and the configuration can be simplified. Further, since the first constituent layer and the second constituent layer are formed in the surface layer portion of the base layer, for example, the first constituent layer and the second constituent layer can be easily formed by ion implantation or the like, and the impurity concentration, depth, etc. can also be easily changed. Therefore, the degree of freedom in design can be improved.

[0008] Note that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Modes for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals for description.

[0011] (First Embodiment) The first embodiment will be described with reference to the drawings. In this embodiment, as shown in FIG. 1, a SiC semiconductor device having a cell region 1, a temperature detection region 2, and an outer peripheral region 3, and having an inversion-type MOSFET with a trench gate structure formed in the cell region 1 will be described. Note that in FIG. 1, an example is shown in which the temperature detection region 2 is formed in a substantially central portion in the planar layout of the SiC semiconductor device, but the position where the temperature detection region 2 is formed can be appropriately changed and may be formed at an outer edge portion or the like. Further, in the outer peripheral region 3, pads 4 connected to a gate electrode 26 described later, pads 5 connected to a diode element 40 described later, and the like are formed.

[0012] Hereinafter, as shown in FIGS. 2 and 3, one direction in the plane direction of a substrate 11 described later will be defined as the X-axis direction, a direction intersecting one direction in the plane direction of the substrate will be defined as the Y-axis direction, and a direction orthogonal to the X-axis direction and the Y-axis direction will be defined as the Z-axis direction for description. Note that in this embodiment, the X-axis direction and the Y-axis direction are orthogonal to each other. Further, for example, in FIG. 3, the left-right direction of the paper surface corresponds to the X-axis direction, the depth direction of the paper surface corresponds to the Y-axis direction, and the up-down direction of the paper surface corresponds to the Z-axis direction.

[0013] As shown in FIGS. 2 and 3, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device includes an n + -type substrate 11 made of SiC. In this embodiment, as the substrate 11, for example, it has an off-angle of 0 to 8° with respect to the (0001) Si plane, and an n-type impurity concentration such as nitrogen or phosphorus is 1.0×10 19 / cm 3 and a thickness of about 300 μm is used. Note that the substrate 11 constitutes a drain region in this embodiment.

[0014] On the surface of the substrate 11, an n made of SiC -A buffer layer 12 of a type is formed. The buffer layer 12 is configured by performing epitaxial growth on the surface of the substrate 11. And the buffer layer 12 has an n-type impurity concentration that is the impurity concentration between the substrate 11 and a low-concentration layer 13 described later, and a thickness of about 1 μm.

[0015] On the surface of the buffer layer 12, for example, an n-type impurity concentration is 5.0 to 10.0×10 15 / cm 3 and a thickness of about 10 to 15 μm, and an n - -type low-concentration layer 13 made of SiC is formed. This low-concentration layer 13 may have a constant impurity concentration in the Z-axis direction, but it is preferably given a concentration distribution gradient such that the side of the low-concentration layer 13 closer to the substrate 11 has a higher concentration than the side farther from the substrate 11. For example, in the low-concentration layer 13, the impurity concentration of a portion about 3 to 5 μm from the surface of the substrate 11 is preferably made higher than that of other portions by about 2.0×10 15 / cm 3 . By adopting such a configuration, the internal resistance of the low-concentration layer 13 can be reduced, and the on-resistance can be reduced.

[0016] And the cell region 1 of the present embodiment has the following configuration on the low-concentration layer 13. That is, in the cell region 1, as shown in FIG. 2, a JFET portion 14 and a first deep layer 15 are formed on the surface layer portion of the low-concentration layer 13. In the present embodiment, the JFET portion 14 and the first deep layer 15 each have a linear portion extending along the X-axis direction and alternately arranged in the Y-axis direction. That is, the JFET portion 14 and the first deep layer 15 are each formed in a stripe shape extending along the X-axis direction in the normal direction to the surface of the substrate 11 (hereinafter, also simply referred to as the normal direction), and they are arranged alternately along the Y-axis direction. Note that the normal direction to the surface of the substrate 11 can also be described as when viewed from the normal direction to the surface of the substrate 11, or when viewed from the Z-axis direction.

[0017] The JFET section 14 has an n-type with a higher impurity concentration than the low-concentration layer 13, and its depth is set to 0.3 to 1.5 μm. In this embodiment, the JFET section 14 has an n-type impurity concentration of 7.0×10 16 ~5.0×10 17 / cm 3 . The first deep layer 15 has, for example, a p-type impurity concentration of boron or the like of 2.0×10 17 ~2.0×10 18 / cm 3 .

[0018] Also, the first deep layer 15 of this embodiment is formed shallower than the JFET section 14. That is, the first deep layer 15 is formed such that its bottom is located within the JFET section 14. In other words, the first deep layer 15 is formed such that the JFET section 14 is located between it and the low-concentration layer 13.

[0019] On the JFET section 14 and the first deep layer 15, a current dispersion layer 17 and a second deep layer 18 are formed. The current dispersion layer 17 is composed of an n-type impurity layer, and its thickness is set to 0.5 to 2 μm. Also, the n-type impurity concentration of the current dispersion layer 17 is, for example, 1.0×10 16 ~5.0×10 17 / cm 3 . Furthermore, the current dispersion layer 17 is connected to the JFET section 14. And in this embodiment, the low-concentration layer 13, the JFET section 14, and the current dispersion layer 17 are connected, and these constitute a drift layer 19.

[0020] The second deep layer 18 has, for example, a p-type impurity concentration of 2.0×10 17 ~2.0×10 18 / cm 3 , and its thickness is made equal to that of the current dispersion layer 17. Also, the second deep layer 18 is formed so as to be connected to the first deep layer 15.

[0021] The current dispersion layer 17 and the second deep layer 18 extend in a striped portion of the JFET section 14 and in a direction intersecting the longitudinal direction of the first deep layer 15. In the present embodiment, the current dispersion layer 17 and the second deep layer 18 extend with the Y-axis direction as the longitudinal direction and are arranged in a layout in which a plurality of them are arranged alternately in the X-axis direction. Note that the formation pitch of the current dispersion layer 17 and the second deep layer 18 is adjusted to the formation pitch of a trench gate structure described later, and the second deep layer 18 is formed so as to sandwich a gate trench 24 described later.

[0022] A p-type base layer 21 is formed on the current dispersion layer 17 and the second deep layer 18. Then, an n + -type source region 22 and a p + -type contact region 23 are formed in the surface layer portion of the base layer 21. The source region 22 is formed so as to be in contact with the side surface of a gate trench 24 described later, and the contact region 23 is formed on the side opposite to the gate trench 24 with the source region 22 interposed therebetween. Note that in the present embodiment, the source region 22 corresponds to a first impurity region, and the contact region 23 corresponds to a second impurity region.

[0023] The base layer 21 has, for example, a p-type impurity concentration of 3.0×10 17 / cm 3 or less. The source region 22 has an n-type impurity concentration in the surface layer portion, that is, a surface concentration of, for example, 1.0×10 21 / cm 3 or more. The contact region 23 has a p-type impurity concentration in the surface layer portion, that is, a surface concentration of, for example, 1.0×10 21 / cm 3 or more.

[0024] In this embodiment, as described above, in the cell region 1, a semiconductor substrate 10 is formed by laminating a substrate 11, a buffer layer 12, a low-concentration layer 13, a JFET section 14, a first deep layer 15, a current dispersion layer 17, a second deep layer 18, a base layer 21, a source region 22, a contact region 23, etc. Hereinafter, the surface of the semiconductor substrate 10 on the side of the substrate 11 is defined as the other surface 10b of the semiconductor substrate 10, and the surface on the side of the source region 22 and the contact region 23 is defined as one surface 10a of the semiconductor substrate 10. And the source region 22 and the contact region 23 are in a state of being exposed from one surface 10a of the semiconductor substrate 10.

[0025] In the semiconductor substrate 10, a gate trench 24 is formed from one surface 10a side so as to penetrate through the base layer 21 etc. and reach the current dispersion layer 17 and the bottom surface is located within the current dispersion layer 17. Note that the gate trench 24 is formed so as not to reach the JFET section 14 and the first deep layer 15. That is, the gate trench 24 is formed so that the JFET section 14 and the first deep layer 15 are located below the bottom surface.

[0026] Also, a plurality of gate trenches 24 are extended so as to extend along the Y-axis direction and are arranged at equal intervals in the X-axis direction to be formed in a stripe shape. That is, in this embodiment, the gate trench 24 is formed so that the longitudinal direction is orthogonal to the longitudinal direction of the first deep layer 15. Also, the gate trench 24 is formed so as to be sandwiched by the second deep layer 18 in the normal direction.

[0027] A gate insulating film 25 is formed on the inner wall surface of the gate trench 24. And a gate electrode 26 composed of doped Poly-Si is formed on the surface of the gate insulating film 25. Thereby, a trench gate structure is formed. Also, the gate electrode 26 is electrically connected to a pad 4 via a gate wiring (not shown).

[0028] On one surface 10a of the semiconductor substrate 10, an interlayer insulating film 27 is formed so as to cover the gate electrode 26, the gate insulating film 25, etc. The interlayer insulating film 27 is composed of BPSG (abbreviation for Borophosphosilicate Glass) or the like.

[0029] In the interlayer insulating film 27, a contact hole 27a for exposing the source region 22 and the contact region 23 is formed. Note that the pattern of the contact hole 27a formed in the interlayer insulating film 27 is arbitrary, and examples thereof include a pattern in which a plurality of square ones are arranged, a pattern in which rectangular line-shaped ones are arranged, or a pattern in which line-shaped ones are arranged side by side. In the present embodiment, the contact hole 27a is in a line shape along the longitudinal direction of the gate trench 24.

[0030] On the interlayer insulating film 27, an upper electrode 28 that is electrically connected to the source region 22 and the contact region 23 through the contact hole 27a is formed. Note that in the present embodiment, the upper electrode 28 corresponds to the first electrode.

[0031] The upper electrode 28 of the present embodiment is composed of, for example, a plurality of metals such as Ni / Al. And the portion that contacts the portion constituting the n-type SiC (that is, the source region 22) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the n-type SiC. Also, at least the portion that contacts the p-type SiC (that is, the contact region 23) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the p-type SiC.

[0032] On the other surface 10b side of the semiconductor substrate 10, as shown in FIG. 1, a lower electrode 29 that is electrically connected to the substrate 11 is formed. In the present embodiment, the lower electrode 29 corresponds to the second electrode. In the SiC semiconductor device of the present embodiment, with such a structure, in the cell region 1, a MOSFET having a trench gate structure of an n-channel type inversion mode is configured.

[0033] The above is the configuration of the cell region 1. Next, the configuration of the temperature detection region 2 will be described. In the temperature detection region 2, as shown in FIG. 3, a JFET section 14 and a first deep layer 15 are formed on the low-concentration layer 13. Note that the JFET section 14 in the temperature detection region 2 has the same thickness as the JFET section 14 between the first deep layer 15 and the low-concentration layer 13 in the cell region 1, and is formed over the entire low-concentration layer 13. And the first deep layer 15 is formed over the entire JFET section 14. That is, in the temperature detection region 2, the first deep layer 15 is laminated and arranged on the JFET section 14.

[0034] Over the first deep layer 15, a current dispersion layer 17 similar to that in the cell region 1 is formed over the entire surface, and a base layer 21 similar to that in the cell region 1 is formed over the current dispersion layer 17. On the surface layer portion of the base layer 21, + a p + -type anode layer 41 and an n

[0035] -type cathode layer 42 are provided, and a diode element 40 is formed as a temperature detection element in which the anode layer 41 and the cathode layer 42 are connected in the plane direction of the semiconductor substrate 10. Note that in this embodiment, the anode layer 41 corresponds to the second constituent layer, and the cathode layer 42 corresponds to the first constituent layer.

[0036] Similarly, the cathode layer 42 has a lower surface on the substrate 11 side that is at the same depth as the lower surface of the source region 22 and has the same thickness as the source region 22. Also, the cathode layer 42 has the same n-type impurity concentration as the source region 22. And since the cathode layer 42 of the present embodiment has the same thickness and the same impurity concentration as the source region 22 as described above, it is formed in the same process as the source region 22. In the present embodiment, the source region 22 and the cathode layer 42 are simultaneously formed by performing ion implantation from one surface 10a of the semiconductor substrate 10. For this reason, the source region 22 and the cathode layer 42 are composed of an ion implantation layer.

[0037] Here, in the present embodiment, as shown in FIGS. 3 and 4, a frame-shaped isolation trench 51 is formed so as to surround the temperature detection region 2. That is, in the present embodiment, the region surrounded by the isolation trench 51 is the temperature detection region 2, and the temperature detection region 2 is partitioned from the cell region 1 and the outer peripheral region 3 by the isolation trench 51. Note that FIG. 3 corresponds to a cross section taken along line III-III in FIG. 4.

[0038] Further, in the temperature detection region 2 of the present embodiment, partition trenches 52 are formed so as to partition the temperature detection region 2 into a plurality of constituent regions 2a. Specifically, the partition trenches 52 are formed so as to communicate with the isolation trench 51 and are formed in a so-called ladder shape together with the isolation trench 51. The partition trenches 52 of the present embodiment are provided in two numbers so that the temperature detection region 2 is partitioned into three constituent regions 2a and each constituent region 2a is arranged along the X-axis direction.

[0039] The isolation trench 51 and the partition trenches 52 are formed to have the same depth as the gate trench 24 and are formed such that the bottom surfaces are located within the current dispersion layer 17. For this reason, the isolation trench 51 and the partition trenches 52 are simultaneously formed when the gate trench 24 is formed. Note that since the isolation trench 51 and the partition trenches 52 are formed as described above, the JFET portion 14 and the first deep layer 15 are arranged below the bottom surfaces of the isolation trench 51 and the partition trenches 52.

[0040] And in the isolation trench 51 and the partition trench 52, a gate insulating film 53 and a floating gate electrode 54 are embedded. Note that the floating gate electrode 54 is not connected to the pad 4 to which the gate electrode 26 is connected and is in a floating state. Also, in FIG. 4, the gate insulating film 53 and the floating gate electrode 54 are omitted from the illustration.

[0041] And the anode layer 41 and the cathode layer 42 are formed in each constituent region 2a, respectively. In the present embodiment, in each constituent region 2a, the anode layer 41 and the cathode layer 42 are formed in order along the arrangement direction (i.e., the X-axis direction) of the constituent region 2a.

[0042] On one surface 10a of the semiconductor substrate 10, an interlayer insulating film 27 is formed in the same manner as in the cell region 1. In the interlayer insulating film 27, contact holes 27b for exposing the anode layer 41 and the cathode layer 42 are formed. Note that an arbitrary pattern is adopted for the pattern of the contact holes 27b formed in the interlayer insulating film 27, similar to the contact holes 27a. In the present embodiment, the contact holes 27b are in a line shape along the longitudinal direction of the isolation trench 51.

[0043] On the interlayer insulating film 27, a first main electrode 61 connected to the anode layer 41 which is one end portion of the diode element 40 is formed, and a second main electrode 62 connected to the cathode layer 42 which is the other end portion of the diode element 40 is formed. And the first main electrode 61 and the second main electrode 62 are electrically connected to the pad 5 via connection wirings (not shown). Also, on the interlayer insulating film 27, connection electrodes 63 for connecting the anode layer 41 and the cathode layer 42 formed in each constituent region 2a are formed. And in the present embodiment, the diode element 40 as a temperature detection element is configured by connecting the anode layer 41 and the cathode layer 42 formed in each constituent region 2a in order via the connection electrodes 63.

[0044] Note that FIG. 4 shows a plan view of one surface 10a side of the semiconductor substrate 10 in the temperature detection region 2 with the interlayer insulating film 27 and the electrodes 61 to 63 omitted. Also, in FIG. 4, the region surrounded by a dotted line is the region where the portions of the anode layer 41 and the cathode layer 42 connected to the electrodes 61 to 63 via the contact hole 27b are located.

[0045] Regarding the configuration of the outer peripheral region 3, detailed description is omitted, but a plurality of p-type guard rings are provided so as to surround the cell region 1. Note that the planar layout of the guard ring is, for example, a rectangular shape or a circular shape with rounded corners in the Z-axis direction.

[0046] The above is the configuration of the SiC semiconductor device in this embodiment. Note that in this embodiment, n + -type, n-type, n - -type correspond to the first conductivity type, and p - -type, p-type, p + -type correspond to the second conductivity type. Next, the operation and effects of the above SiC semiconductor device will be described.

[0047] In the SiC semiconductor device as described above, in the off state before the gate voltage is applied to the gate electrode 26, an inversion layer is not formed in the base layer 21. Therefore, even if a positive voltage, for example, 1600 V is applied to the lower electrode 29, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device is in an off state where no current flows between the upper electrode 28 and the lower electrode 29.

[0048] Also, when the SiC semiconductor device is in the off state, an electric field is applied between the drain and the gate, and electric field concentration may occur at the bottoms of the gate insulating films 25 and 53. However, in the SiC semiconductor device, the first deep layer 15 and the JFET section 14 are provided at positions deeper than the gate trenches 24, the isolation trenches 51, and the partition trenches 52. Therefore, the depletion layer formed between the first deep layer 15 and the JFET section 14 suppresses the rise of the equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to enter the gate insulating films 25 and 53. Thus, in the present embodiment, it is possible to suppress the breakdown of the gate insulating films 25 and 53 when the device is off.

[0049] When a predetermined gate voltage, for example, 20 V, is applied to the gate electrode 26, a channel is formed on the surface of the base layer 21 in contact with the gate trench 24. As a result, a current flows between the upper electrode 28 and the lower electrode 29, and the SiC semiconductor device enters the on state. In the present embodiment, since the electrons passing through the channel flow through the current dispersion layer 17, the JFET section 14, and the low-concentration layer 13 to the substrate 11, it can be said that a drift layer 19 having the current dispersion layer 17, the JFET section 14, and the low-concentration layer 13 is formed.

[0050] Also, in the temperature detection region 2, a constant current is passed through the diode element 40 as indicated by the arrow A in FIG. 5. Then, when a switching operation is performed in the cell region 1 or the temperature of the semiconductor substrate 10 changes according to the surrounding environment. In this case, the forward voltage of the diode element 40 changes depending on the temperature of the semiconductor substrate 10. Therefore, in the above SiC semiconductor device, the temperature of the semiconductor substrate 10 is detected based on the forward voltage of the diode element 40.

[0051] In this case, in the present embodiment, the temperature detection region 2 is partitioned from the cell region 1 and the outer peripheral region 3 by the isolation trench 51. Therefore, it is possible to suppress current from flowing from the cell region 1 into the temperature detection region 2 and suppress a decrease in detection accuracy.

[0052] In addition, in this embodiment, the temperature detection region 2 is divided into a plurality of constituent regions 2a. Therefore, as indicated by arrow B in FIG. 5, it is difficult for leakage current to flow from the anode layer 41 through the base layer 21 to a different anode layer 41. Accordingly, variations in the forward voltage can be suppressed, and further suppression of a decrease in detection accuracy can be achieved.

[0053] Furthermore, in the temperature detection region 2, an n-type current dispersion layer 17 is disposed between the p-type base layer 21 and the p-type first deep layer 15. Therefore, as indicated by arrow C in FIG. 5, it is difficult for leakage current to flow from the anode layer 41, through the base layer 21 and the current dispersion layer 17, back to the base layer 21 again. Accordingly, variations in the forward voltage can be suppressed, and further suppression of a decrease in detection accuracy can be achieved.

[0054] According to the present embodiment described above, the diode element 40 is composed of an anode layer 41 and a cathode layer 42 formed on the surface layer portion of the base layer 21. Therefore, for example, the anode layer 41 and the cathode layer 42 can be easily formed by ion implantation or the like, and the impurity concentration, depth, etc. can also be easily changed. Accordingly, an improvement in the degree of design freedom can be achieved.

[0055] (1) In this embodiment, the anode layer 41 has the same thickness and the same impurity concentration as the contact region 23, and the cathode layer 42 has the same thickness and the same impurity concentration as the source region 22. Therefore, the anode layer 41 can be formed in the same process as the contact region 23, and the cathode layer 42 can be formed in the same process as the source region 22. Accordingly, a SiC semiconductor device including the diode element 40 as a temperature detection element can be configured without increasing the manufacturing process, and thus simplification of the configuration can be achieved.

[0056] (2) In this embodiment, the temperature detection region 2 is partitioned from the cell region 1 and the outer peripheral region 3 by the isolation trench 51. Therefore, current flowing from the cell region 1 into the temperature detection region 2 can be suppressed, and a decrease in detection accuracy can be suppressed.

[0057] (3) In this embodiment, the temperature detection region 2 is divided into a plurality of constituent regions 2a. Therefore, it is difficult for leakage current to flow from the anode layer 41 through the base layer 21 to a different anode layer 41. Accordingly, variations in the forward voltage are suppressed, and further suppression of a decrease in detection accuracy can be achieved.

[0058] (4) In this embodiment, in the temperature detection region 2, an n-type current dispersion layer 17 is disposed between the p-type base layer 21 and the p-type first deep layer 15. Therefore, it is difficult for leakage current to flow again from the anode layer 41, through the base layer 21 and the current dispersion layer 17, to the base layer 21. Accordingly, variations in the forward voltage are suppressed, and further suppression of a decrease in detection accuracy can be achieved.

[0059] (5) In this embodiment, the isolation trench 51 and the partition trench 52 are formed to the same depth as the gate trench 24. Therefore, the isolation trench and the partition trench 52 can be formed in the same process as the gate trench 24, and an increase in the manufacturing process can be suppressed.

[0060] (6) In this embodiment, the anode layer 41 and the cathode layer 42 are formed on the semiconductor substrate 10 to constitute the diode element 40. Therefore, for example, improvement in temperature responsiveness can be achieved as compared with the case where the p-type and n-type polysilicon or the like is disposed on one surface 10a of the semiconductor substrate 10 via an insulating film to constitute the diode element 40.

[0061] (Second Embodiment) The second embodiment will be described. This embodiment is the same as the first embodiment except that a drawing portion is formed, and thus the description thereof will be omitted here.

[0062] In the SiC semiconductor device of this embodiment, as shown in FIGS. 6 and 7, a drawing portion 70 is formed. The drawing portion 70 of this embodiment includes a portion disposed between the cell region 1 and the temperature detection region 2, and has a frame shape in a planar shape that surrounds the isolation trench 51. The drawing portion 70 is formed with a second deep layer 18 similar to the cell region 1 so as to be connected to the first deep layer 15 of the temperature detection region 2, and a contact region 23 that is connected to the second deep layer 18 via the base layer 21 is formed on the surface layer portion of the base layer 21. That is, the drawing portion 70 is composed of a p-type layer connected to the first deep layer 15. Note that FIG. 6 corresponds to a cross-sectional view taken along line IV-IV in FIG. 7.

[0063] Further, a contact hole 27c for exposing the contact region 23 constituting the drawing portion 70 is formed in the interlayer insulating film 27. The contact region 23 constituting the drawing portion 70 is electrically connected to the upper electrode 28 through the contact hole 27c. Thereby, the first deep layer 15 of the temperature detection region 2 is electrically connected to the upper electrode 28 via the drawing portion 70. That is, the drawing portion 70 of this embodiment connects the first deep layer 15 of the temperature detection region 2 and the upper electrode 28.

[0064] According to the embodiment described above, the diode element 40 includes an anode layer 41 having the same thickness and the same impurity concentration as the contact region 23, and a cathode layer 42 having the same thickness and the same impurity concentration as the source region 22. For this reason, the same effect as that of the first embodiment can be obtained.

[0065] (1) In this embodiment, the first deep layer 15 of the temperature detection region 2 is electrically connected to the upper electrode 28 through a drawing portion 70 formed at a position closer to the upper electrode 28 in the cell region 1. Therefore, when avalanche breakdown occurs or the like, the surge current caused by holes can be drawn from the first deep layer 15 to the upper electrode 28 through the drawing portion 70. Thus, it is possible to suppress the surge current from reaching the diode element 40 and protect the diode element 40.

[0066] (2) In this embodiment, the drawing portion 70 is formed so as to surround the temperature detection region 2. Therefore, compared with the case where the drawing portions 70 are arranged at intervals around the temperature detection region 2, the surge current can be drawn out efficiently.

[0067] (3) In this embodiment, the drawing portion 70 is configured using the same contact region 23 and second deep layer 18 as those in the cell region 1. Therefore, a manufacturing process only for forming the drawing portion 70 becomes unnecessary, and an increase in the manufacturing process can also be suppressed.

[0068] (Third Embodiment) The third embodiment will be described. This embodiment is obtained by adding the formation location of the drawing portion 70 to the second embodiment. Since the rest is the same as the second embodiment, the description is omitted here.

[0069] In the SiC semiconductor device of this embodiment, as shown in FIGS. 8 and 9, the drawing portion 70 is also formed in the temperature detection region 2. In this embodiment, the temperature detection region 2 is in a state where three constituent regions 2a are arranged side by side in the X-axis direction. And the drawing portion 70 is formed in the central constituent region 2a among the three constituent regions 2a. Note that the drawing portion 70 arranged in the temperature detection region 2 is electrically connected to the upper electrode 28 in a cross section different from that in FIG. 8. Also, FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG. 9.

[0070] According to the present embodiment described above, the diode element 40 includes an anode layer 41 having the same thickness and the same impurity concentration as the contact region 23, and a cathode layer 42 having the same thickness and the same impurity concentration as the source region 22. Therefore, the same effects as those of the first embodiment can be obtained.

[0071] (1) In this embodiment, the extraction portion 70 is disposed in the temperature detection region 2. Therefore, it is possible to further suppress the surge current from reaching the diode element 40, and further protect the diode element 40.

[0072] (Other embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and variations within an equivalent range. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, fall within the scope and spirit of the present disclosure.

[0073] In each of the above embodiments, an SiC semiconductor device in which an n-channel type trench gate structure MOSFET having the first conductivity type as n-type and the second conductivity type as p-type is formed in the cell region 1 has been described. However, the semiconductor element formed in the cell region 1 can be appropriately changed. For example, it may be a p-channel type trench gate structure MOSFET in which the conductivity types of the respective components are inverted with respect to the n-channel type. Further, the semiconductor element formed in the cell region 1 may have a configuration in which an IGBT having the same structure is formed in addition to the MOSFET. In the case of an IGBT, except that the n-type drain region (i.e., the substrate 11) in each of the above embodiments is changed to a p-type collector region, it is the same as the MOSFET described in the first embodiment. + type drain region (i.e., the substrate 11) to a p + type collector region, it is the same as the MOSFET described in the first embodiment.

[0074] Also, in each of the above embodiments, the partition trench 52 may not be formed, or the separation trench 51 may not be formed. Further, the separation trench 51 and the partition trench 52 may not have the same depth as the gate trench 24.

[0075] And in each of the above embodiments, an example in which the first deep layer 15 extends along the X-axis direction has been described, but the first deep layer 15 may extend in the Y-axis direction.

[0076] Furthermore, in each of the above embodiments, a configuration may be adopted in which the JFET portion 14, the first deep layer 15, the current dispersion layer 17, the second deep layer 18, etc. are not provided, and the drift layer 19 may be composed of only the low-concentration layer 13.

[0077] Also, in each of the above embodiments, the anode layer 41 may have a thickness different from that of the contact region 23, or may have an impurity concentration different from that of the contact region 23. Similarly, the cathode layer 42 may have a thickness different from that of the source region 22, or may have an impurity concentration different from that of the source region 22.

Explanation of Reference Numerals

[0078] 1 Cell region 2 Temperature detection region 11 Substrate 19 Drift layer 21 Base layer 22 Source region (first impurity region) 23 Contact region (second impurity region) 28 Upper electrode (first electrode) 29 Lower electrode (second electrode) 40 Diode element 41 Anode layer (second constituent layer) 42 Cathode layer (first constituent layer)

Claims

【Claim 1】 A semiconductor device having a cell region (1) in which a semiconductor element is formed and a temperature detection region (2) in which a temperature detection element is formed, a substrate (11) made of silicon carbide and having a first conductivity type or a second conductivity type, a first conductivity type drift layer (19) formed on the substrate and having a lower impurity concentration than the substrate, a second conductivity type base layer (21) formed on the drift layer, a first electrode (28) formed on the opposite side of the substrate with the drift layer interposed therebetween and electrically connected to the semiconductor element formed in the cell region, a second electrode (29) formed on the opposite side of the drift layer with the substrate interposed therebetween and electrically connected to the semiconductor element formed in the cell region, in the cell region, a first conductivity type first impurity region (22) and a second conductivity type second impurity region (23) that are connected to the first electrode and constitute the semiconductor element are formed in the surface layer portion of the base layer, in the temperature detection region, a first conductivity type first constituent layer (42) formed in the surface layer portion of the base layer and a second conductivity type second constituent layer (41) formed in the surface layer portion of the base layer and connected to the first constituent layer in the plane direction of the substrate are provided, and a diode element (40) is formed, the cell region includes, the drift layer including a first conductivity type low concentration layer (13) disposed on the substrate and having a lower impurity concentration than the substrate, a second conductivity type first deep layer (15) formed in the drift layer and having a plurality of linear portions with one direction in the plane direction of the substrate as the longitudinal direction, a second conductivity type second deep layer (18) formed in the drift layer and disposed on the first deep layer, and the base layer disposed on the second deep layer, the temperature detection region includes, the drift layer including the low concentration layer disposed on the substrate, a second conductivity type first deep layer (15) formed in the drift layer, and the base layer formed on the drift layer, a silicon carbide semiconductor device in which the first deep layer in the temperature detection region is electrically connected to the first electrode through a second conductivity type extraction portion (70).

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