Semiconductor device

Abstract

To provide a semiconductor device capable of reducing malfunction due to current noise and satisfactorily protecting a switching element from overcurrent, and a semiconductor module equipped with the semiconductor device.SOLUTION: A semiconductor device 1 includes a semiconductor substrate 6, a switching element formed on the semiconductor substrate 6, and a temperature sense diode 20 that is provided on the surface side of the semiconductor substrate 6 independently of the switching element and has temperature-dependent characteristics. Further, a semiconductor module equipped with the semiconductor device 1 is provided.SELECTED DRAWING: Figure 5B

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In a switching device, for example, if an overcurrent continues to flow during a short circuit, thermal breakdown may occur. To prevent this problem, for example, Patent Document 1 discloses a semiconductor device including a semiconductor switching element, a semiconductor drive circuit, a sense element formed in the semiconductor switching element, and an overcurrent detection unit formed in the semiconductor drive circuit. The sense element includes a sense terminal through which a current proportional to the main current of the semiconductor switching element flows, and a sense resistor connected between the main terminal and the sense terminal of the semiconductor switching element for converting the sense current into a voltage. The overcurrent detection unit detects the sense current flowing through the above-described sense element, and when the sense current exceeds a predetermined value, turns off the semiconductor switching element to protect the semiconductor switching element from overcurrent.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Since the overcurrent protection method of Patent Document 1 turns off the semiconductor switching element based on the sense current, it is easily affected by noise, and sometimes the sense current with noise may be erroneously detected as an overcurrent. To prevent such malfunction due to noise, instead of immediately turning off the semiconductor switching element even when the sense current exceeds a predetermined threshold value, there is a method of turning it off after a certain waiting time (mask time) has elapsed.

[0005] However, there are still problems with the method of providing this waiting time. Although a certain waiting time is required to consider the influence of noise (for example, about 500 n seconds), as the on-resistance of the device is reduced, the time for the device to be destroyed by overcurrent becomes shorter than the waiting time, and there are cases where the overcurrent protection system itself does not work.

[0006] Therefore, an embodiment of the present invention provides a semiconductor device that can reduce malfunction due to current noise and can well protect a switching element from overcurrent.

Means for Solving the Problems

[0007] An embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sensing element provided independently of the switching element on the surface side of the semiconductor substrate and having characteristics depending on temperature.

[0008] Further, an embodiment of the present invention provides a single-function semiconductor device including a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sensing element provided independently of the switching element on the surface side of the semiconductor substrate and having characteristics depending on temperature.

[0009] According to the above configuration, if a temperature change occurs on the surface side of the semiconductor substrate, the characteristics (voltage value, resistance value, etc.) of the temperature sensing element change accordingly. Therefore, by monitoring the change in the characteristics of the temperature sensing element, the temperature change of the semiconductor substrate can be detected. By utilizing this relationship, for example, when an overcurrent flows through the switching element due to a short circuit or the like, the temperature rise of the semiconductor substrate due to the overcurrent is detected, and based on the detection result, it can be determined whether an overcurrent is flowing through the switching element. Moreover, since the monitoring target is not the sense current flowing through the switching element, even when noise enters and superimposes on the sense current, it is not misdetected as an overcurrent due to the superimposed current. Therefore, malfunction due to current noise can be reduced.

[0010] One embodiment of the present invention includes a first electrode and a second electrode that are paired with each other on the semiconductor substrate, and only the temperature sensing element is provided as a circuit element in the electric circuit between the first electrode and the second electrode.

[0011] In one embodiment of the present invention, the temperature sensing element includes a pn diode formed of a polysilicon layer formed on the semiconductor substrate.

[0012] Polysilicon can be easily formed in a desired shape and position by established semiconductor manufacturing techniques. Therefore, by forming a polysilicon layer (pn diode) near the surface, which is the heat generating part of the semiconductor substrate, the temperature change of the semiconductor substrate can be detected with high accuracy. For example, by constantly applying a constant current to the pn diode and monitoring the forward voltage V F of the pn diode, the temperature change of the semiconductor substrate can be detected.

[0013] In one embodiment of the present invention, the switching element includes a planar gate type MISFET having a gate electrode formed along the surface of the semiconductor substrate, and the polysilicon layer is formed in the same layer as the gate electrode.

[0014] According to this configuration, since the polysilicon layer (pn diode) can be formed in the same process as the gate electrode, an increase in the number of processes associated with the formation of the pn diode can be suppressed. In addition, since the pn diode can be disposed on the semiconductor substrate via a relatively thin gate insulating film compared to a relatively thick film such as an interlayer insulating film, the position of the pn diode can be brought closer to the immediate vicinity of the current path on the surface side of the semiconductor substrate. Thereby, the accuracy of detecting the temperature change of the semiconductor substrate can be improved.

[0015] In one embodiment of the present invention, the pn diode includes a p-type region and an n-type region surrounding the p-type region in a plan view.

[0016] According to this configuration, since the p-type region and the n-type region do not overlap in plan view, no separate wiring or the like is required, and contacts can be easily made to either the p-type region or the n-type region.

[0017] In one embodiment of the present invention, the switching element includes a trench gate type MISFET having a gate trench formed in the semiconductor substrate and a gate electrode embedded in the gate trench, and the polysilicon layer is embedded in a second trench formed independently of the gate trench in the semiconductor substrate.

[0018] According to this configuration, since the second trench can be formed in the same process as the gate trench and the polysilicon layer (pn diode) can be formed in the same process as the gate electrode, an increase in the number of processes associated with the formation of the pn diode can be suppressed. Further, since the pn diode is configured to be embedded in the surface portion of the semiconductor substrate, the position of the pn diode can be brought close to the vicinity of the current path on the surface side of the semiconductor substrate. Thereby, the accuracy of detecting the temperature change of the semiconductor substrate can be improved.

[0019] In one embodiment of the present invention, the gate trench and the second trench are formed with the same width as each other.

[0020] According to this configuration, the etching rates when forming the gate trench and the second trench can be made substantially the same, so that finally, the gate trench and the second trench having substantially the same depth as each other can be formed. By making the depth of the second trench substantially the same as that of the gate trench in which the channel of the MISFET is formed, an increase in the temperature of the semiconductor substrate due to overcurrent can be detected quickly.

[0021] In one embodiment of the present invention, the temperature sensing element includes a pn diode formed of an impurity region formed in the surface portion of the semiconductor substrate.

[0022] The impurity region can be easily formed at a desired position by established semiconductor manufacturing techniques. Therefore, by forming an impurity region (pn diode) in the immediate vicinity of the current path on the surface side, which is the heat generating part of the semiconductor substrate, the temperature change of the semiconductor substrate can be detected with high accuracy. For example, by constantly applying a constant current to the pn diode and monitoring the forward voltage V F of the pn diode, the temperature change of the semiconductor substrate can be detected. Also, since a pn diode composed of an impurity region operates well even in a high temperature region (for example, 200 °C or higher), it is particularly effective for power devices such as SiC and GaN.

[0023] In one embodiment of the present invention, the pn diode includes a p-type region and an n-type region surrounding the p-type region in a plan view.

[0024] According to this configuration, since the p-type region and the n-type region do not overlap in a plan view, no separate wiring for routing is required, and contacts can be easily made to either the p-type region or the n-type region.

[0025] In one embodiment of the present invention, the temperature sensing element includes a series connection unit in which a plurality of the pn diodes are connected in series.

[0026] According to this configuration, since the amount of temperature change of the forward voltage V F increases in proportion to the number of connected pn diodes, the detection sensitivity of the temperature change can be improved. For example, when the fluctuation range of the forward voltage V F per pn diode is X mV / °C, if five of these pn diodes are connected in series to form a series connection unit, the total fluctuation range of the series connection unit can be made 5X mV / °C.

[0027] In one embodiment of the present invention, the temperature sensing element includes a configuration in which at least a pair of the series connection units are connected in parallel in opposite directions to each other.

[0028] According to this configuration, since there is no distinction between the polarities of the anode side and the cathode side at the terminals of the aggregate of pn diodes, the degree of freedom in wiring such as bonding wires can be improved when assembling a module or the like.

[0029] In one embodiment of the present invention, the temperature sensing element includes a reverse series connection unit in which at least a pair of the pn diodes are connected in series in opposite directions to each other.

[0030] According to this configuration, since a reverse bias is applied to at least one of the pair of pn diodes, the resistance of the entire reverse series connection unit increases. Therefore, the current required for monitoring temperature changes can be significantly suppressed, and power saving can be achieved.

[0031] In one embodiment of the present invention, the temperature sensing element includes a configuration in which a plurality of the reverse series connection units are connected in series.

[0032] According to this configuration, further power saving can be achieved.

[0033] In one embodiment of the present invention, the temperature sensing element includes a configuration in which at least a pair of the pn diodes are connected in parallel in opposite directions to each other.

[0034] According to this configuration, since there is no distinction between the polarities of the anode side and the cathode side at the terminals of the pair of pn diodes, the degree of freedom in wiring such as bonding wires can be improved when assembling a module or the like.

[0035] In one embodiment of the present invention, the temperature sensing element is disposed at a peripheral portion of the semiconductor substrate.

[0036] According to this configuration, a relatively large area can be secured in a portion other than the installation area of the temperature sensing element, so that the area of the terminal for the switching element can be increased. Therefore, even if the chip size is small, wiring members such as a bonding plate or a relatively thick bonding wire can be connected to the terminal.

[0037] In one embodiment of the present invention, the semiconductor substrate includes a SiC semiconductor substrate.

[0038] According to this configuration, a SiC switching element with low on-resistance can be well protected from overcurrent.

[0039] One embodiment of the present invention provides a semiconductor module including the semiconductor device, and a circuit electrically connected to the switching element and the temperature sensing element, the circuit configured to cut off the current path of the switching element when it is determined that an overcurrent is flowing through the switching element based on a change in characteristics of the temperature sensing element.

[0040] According to this configuration, since the above semiconductor device is provided, it is possible to realize a semiconductor module that can reduce malfunction due to current noise and can well protect the switching element from overcurrent.

Brief Description of the Drawings

[0041]

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DETAILED DESCRIPTION OF THE INVENTION

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0043] FIG. 1 is a schematic external view of a semiconductor device 1 according to an embodiment of the present invention.

[0044] The semiconductor device 1 is a discrete semiconductor device and has a single function by the switching element SW. The switching element SW may be, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), or may be other devices such as an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Field Effect Transistor), a bipolar transistor, or a thyristor. In this embodiment, the case where the switching element SW is a MISFET is shown. On the surface of the semiconductor device 1 formed as a chip having a rectangular shape in plan view, a source pad 2 and a gate pad 3 are formed. The source pad 2 covers substantially the entire area of the surface, and the gate pad 3 is disposed in the inner region of the source pad 2. Although not shown, a drain electrode is formed on the back surface of the semiconductor device 1.

[0045] In addition to the above-described switching element SW, the semiconductor device 1 is provided with a temperature sensing element TS. The temperature sensing element TS is disposed on the surface side of the semiconductor device 1. The temperature sensing element TS is independent of the switching element SW and does not directly contribute to the switching operation by the switching element SW.

[0046] Next, an overview of the overcurrent protection method in the semiconductor module 4 including the semiconductor device 1 will be described. FIG. 2 is a circuit diagram of the semiconductor module 4 including the semiconductor device 1 of FIG. 1.

[0047] The semiconductor module 4 includes the semiconductor device 1 and a gate driver G / D as an example of a second semiconductor device of the present invention having a short-circuit protection circuit 5. The semiconductor module 4 may include semiconductor chips (ICs, discrete components, etc.) other than those shown in FIG. 2.

[0048] The short-circuit protection circuit 5 is electrically connected to the gate G of the switching element SW and the temperature sensing element TS independently. The short-circuit protection circuit 5 constantly monitors the characteristics of the temperature sensing element TS. For example, when a short circuit occurs in the switching element SW and an overcurrent flows, the characteristics of the temperature sensing element TS change due to the accompanying heat generation. The short-circuit protection circuit 5 senses the change in the characteristics as the occurrence of a short circuit in the switching element SW and turns off the gate G of the switching element SW. Thereby, the drain current Id flowing between the source-drain (S-D) of the switching element SW is cut off, and the switching element SW is protected.

[0049] FIG. 3 is a diagram showing more specifically the planar structure of the semiconductor device 1 of FIG. 1.

[0050] The semiconductor device 1 includes a semiconductor substrate 6 that defines its outer shape, and has a structure in which a switching element SW and a temperature sensing element TS are formed on the semiconductor substrate 6.

[0051] The semiconductor substrate 6 has a quadrangular shape in plan view, and substantially the entire surface thereof is covered by a source pad 2 having a substantially quadrangular shape in plan view. A cell region 7 constituting the switching element SW is formed in most of the area below the source pad 2. The gate pad 3 is disposed on at least one side of the outer periphery of the semiconductor substrate 6. A gate finger 8 is connected to the gate pad 3. The gate finger 8 extends to the central portion of the semiconductor substrate 6 to distribute the cell region 7 to one side and the other side, and extends to the peripheral portion of the semiconductor substrate 6 to surround the cell region 7.

[0052] In the inner region of the cell region 7, a temperature sensing region 9 that constitutes the temperature sensing element TS is formed. The temperature sensing region 9 is surrounded by the cell region 7. The position of the temperature sensing region 9 may be, for example, the peripheral portion of the semiconductor substrate 6. If the temperature sensing region 9 is arranged at the peripheral portion of the semiconductor substrate 6, a relatively wide region can be secured on the semiconductor substrate 6 for the portion other than the temperature sensing region 9, so that the area of the source pad 2 can be increased. Therefore, even if the chip size is small, wiring members such as a bonding plate and a relatively thick bonding wire can be connected to the source pad 2.

[0053] In a plan view, a first electrode 10 and a second electrode 11 are provided so as to sandwich the temperature sensing region 9. That is, on the semiconductor substrate 6, the paired first electrode 10 and second electrode 11 are arranged at intervals from each other, and the temperature sensing region 9 is formed in the region between the first electrode 10 and the second electrode 11. The first electrode 10 and the second electrode 11 are arranged side by side, for example, along one side of the semiconductor substrate 6 where the gate pad 3 is arranged. Thereby, it becomes easy to draw out wiring members such as bonding wires from each of the gate pad 3, the first electrode 10, and the second electrode 11 in the same direction (in FIG. 3, the left direction of the paper surface). Further, the first electrode 10 and the second electrode 11, as well as the source pad 2, the gate pad 3, and the gate finger 8 are made of an electrode film of the same material, and can be formed simultaneously, for example, by forming the electrode film on the semiconductor substrate 6 and then patterning the electrode film. <Cell structure> FIG. 4A is a schematic plan view showing the structure (planar gate structure) of the cell region 7 of the semiconductor device 1 in FIG. 3. FIG. 4B is a cross-sectional view (cross-sectional view taken along line B-B) of FIG. 4A.

[0054] The semiconductor substrate 6 may be, for example, a SiC substrate, or may be other substrates such as a GaN substrate or a Si substrate. Further, the semiconductor substrate 6 may be an epitaxial substrate including a base substrate and an epitaxial layer grown thereon by crystal growth. In this embodiment, the case where the semiconductor substrate 6 is an n-type SiC epitaxial substrate is shown. The n-type SiC epitaxial substrate has an n + -type base substrate and an n + -type epitaxial layer on the n - -type base substrate may be included. The impurity concentration of the n + -type base substrate is, for example, 1.0×10 18 cm -3 ~1.0×10 20 cm -3 , and the impurity concentration of the n - -type epitaxial layer is, for example, 5.0×10 14 cm -3 ~5.0×10 16 cm -3 may be. Examples of the n-type impurity include N (nitrogen), As (arsenic), P (phosphorus), etc.

[0055] As shown in FIGS. 4A and 4B, in the cell region 7, a plurality of p-type body regions 12 are formed on the surface portion of the semiconductor substrate 6. The plurality of p-type body regions 12 may be formed, for example, in a matrix shape (row and column shape) in a plan view as shown in FIG. 4A, or may be formed in other shapes such as a stripe shape or a honeycomb shape. A line partitioning each unit cell 13 of the switching element SW is set between adjacent p-type body regions 12. The p-type impurity concentration of the p-type body region 12 is, for example, 1×10 15 cm -3 ~1×10 20 cm -3 may be. Examples of the p-type impurity include B (boron), Al (aluminum), etc.

[0056] On the surface portion of the inner region of the p-type body region 12, an n + -type source region 14 is formed at a distance from the periphery of the p-type body region 12. The n +The n-type impurity concentration of the n-type source region 14 is higher than that of the n-type semiconductor substrate 6, for example, 1×10 18 cm -3 ~5×10 21 cm -3 and may be so.

[0057] n + In the inner region of the n-type source region 14, a p + type body contact region 15 is formed. The p + type body contact region 15 penetrates the n + type source region 14 in the depth direction. The p-type impurity concentration of the p-type body contact region 15 is higher than that of the p-type body region 12, for example, 1×10 + cm 18 ~5×10 -3 cm 21 cm -3 and may be so.

[0058] On the surface of the semiconductor substrate 6, a gate insulating film 16 is formed. The gate insulating film 16 may be made of, for example, silicon oxide (SiO2). The thickness of the gate insulating film 16 may be, for example, 300 Å to 600 Å.

[0059] On the gate insulating film 16, a gate electrode 17 is formed. The gate electrode 17 faces the peripheral portion of the p-type body region 12 (the portion surrounding the n + type source region 14 in plan view) with the gate insulating film 16 interposed therebetween. The gate electrode 17 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may be made of p-type polysilicon. The thickness of the gate electrode 17 may be, for example, 6000 Å to 12000 Å.

[0060] An interlayer insulating film 18 covering the gate electrode 17 is formed on the entire surface of the semiconductor substrate 6. The interlayer insulating film 18 may be made of, for example, silicon oxide (SiO2), or may have a structure in which films made of a plurality of silicon oxides are laminated as will be described later (see FIGS. 7I to 7L). The thickness of the interlayer insulating film 18 (total thickness in the case of a plurality of films) may be, for example, 1000 Å to 2000 Å. Although not shown, wirings electrically connecting the source pad 2 and the n + -type source region 14 and the p + -type body contact region 15, and a wiring electrically connecting the gate pad 3 and the gate electrode 17 are formed to penetrate therethrough, respectively. <Temperature sense element structure> FIG. 5A is a schematic plan view showing the structure of the temperature sense region 9 of the semiconductor device 1 in FIG. 3. FIG. 5B is a cross-sectional view (cross-section taken along line B-B) of FIG. 5A. FIG. 5C is a view showing a modification of the structure of FIG. 5B.

[0061] As shown in FIGS. 5A and 5B, a p-type region 19 is formed in the surface portion of the semiconductor substrate 6 in the temperature sense region 9. The p-type region 19 may be an impurity region having the same conductivity type as the p-type body region 12, and its p-type impurity concentration and depth may also be the same as those of the p-type body region 12.

[0062] On the surface of the semiconductor substrate 6, the gate insulating film 16 of the cell region 7 extends to the temperature sense region 9 and is formed. On the gate insulating film 16 in the temperature sense region 9, a temperature sense diode 20 (pn diode) as an example of the temperature sense element TS is formed. The temperature sense diode 20 faces the semiconductor substrate 6 with the gate insulating film 16 interposed therebetween. For example, as shown in FIG. 5B, the entire temperature sense diode 20 may face a single impurity region (in this embodiment, the p-type region 19) of the semiconductor substrate 6.

[0063] The temperature sense diode 20 is composed of, for example, a single-layer polysilicon layer 21. The temperature sense diode 20 composed of the polysilicon layer 21 may be formed in the same layer as the gate electrode 17 by being formed in the same process as the gate electrode 17. That is, the polysilicon layer 21 may be formed with a thickness of 6000 Å to 12000 Å, similar to the gate electrode 17. Of course, the polysilicon layer 21 may be formed in a separate process from the gate electrode 17, or may have a thickness different from that of the gate electrode 17.

[0064] The temperature sense diode 20 includes a p-type region 22 and an n + -type region 23 surrounding the p-type region 22. As long as the p-type region 22 is surrounded by the n + -type region 23, since the p-type region 22 and the n + -type region 23 do not overlap in plan view, no separate wiring or the like is required, and contacts can be easily made to either the p-type region 22 or the n + -type region 23.

[0065] The p-type region 22 and the n + -type region 23 may each be formed so as to reach from the front surface to the back surface of the polysilicon layer 21 as shown in FIG. 5B, or may be selectively formed on the surface portion of the polysilicon layer 21 (not shown). Note that the p-type region 22 does not have to be surrounded by the n + -type region 23. For example, the p-type region 22 and the n + -type region 23 may be formed adjacent to each other and may have a part of a non-shared periphery. Also, the p-type impurity concentration of the p-type region 22 may be, for example, 1×10 15 cm -3 ~1×10 20 cm -3 (the same as the p-type body region 12). The n + -type impurity concentration of the n-type region 23 may be, for example, 1×10 18 cm -3 ~5×10 21 cm -3 (the same as the n + -type source region 14).

[0066] The temperature sense diode 20 may further include a p + -type contact region 24 and a p-type outer peripheral region 25. The p + -type contact region 24 is formed inside the p-type region 22 with a gap from the periphery of the p-type region 22. The p-type outer peripheral region 25 may be formed so as to surround the n + -type region 23. The p + -type contact region 24 and the p-type outer peripheral region 25 may each be formed to reach from the front surface to the back surface of the polysilicon layer 21 as shown in FIG. 5B, or may be selectively formed on the surface portion of the polysilicon layer 21 (not shown). Also, the p + -type impurity concentration of the p-type contact region 24 may be, for example, 1×10 18 cm -3 ~5×10 21 cm -3 (the same as the p + -type body contact region 15). The p-type impurity concentration of the p-type outer peripheral region 25 may be, for example, 1×10 15 cm -3 ~1×10 20 cm -3 (the same as the p-type body region 12).

[0067] Note that the temperature sense diode 20 may have a configuration including a p-type base layer 26 made of p-type polysilicon (p-type doped polysilicon) having a conductivity type opposite to that of the gate electrode 17, and an n + -type region 23 and a p + -type contact region 24 selectively formed on the surface portion of the p-type base layer 26, as shown in FIG. 5C.

[0068] The temperature sense diode 20 is covered by an interlayer insulating film 18 on the semiconductor substrate 6. The first electrode 10 is connected as an anode electrode to the p + -type contact region 24 through a contact hole 27 of the interlayer insulating film 18. The second electrode 11 is connected as a cathode electrode to the n +It is connected to the type region 23. The first electrode 10 and the second electrode 11 connected to both ends of the temperature sense diode 20 are formed separately from the source pad 2 and the gate pad 3 for the switching element SW as described above. Therefore, the temperature sense diode 20 is electrically independent of the switching element SW.

[0069] Polysilicon can be easily formed into a desired shape and position by established semiconductor manufacturing techniques. Therefore, the temperature sense diode 20 can be formed near the switching element SW, near the surface which is the heat generating part of the semiconductor substrate 6, and the temperature change of the semiconductor substrate 6 can be detected with high accuracy. For example, by applying a constant current to this temperature sense diode 20 and monitoring the forward voltage V F of the temperature sense diode 20, the temperature change of the semiconductor substrate 6 can be detected. As the constant current, for example, 1 μA can be applied and the forward voltage V F can be monitored. The current may be a constant current in the range of 1 μA to 100 μA.

[0070] The second electrode 11 integrally includes, on the interlayer insulating film 18, an annular contact portion 30 having an opening portion 29 in part, and a linear lead-out portion 31 extending from the contact portion 30. The contact portion 30 surrounds the p-type region 22 in plan view. Also, the contact hole 28 is formed in an annular shape with a part opened along the contact portion 30.

[0071] The first electrode 10 integrally includes, on the interlayer insulating film 18, a contact portion 32 surrounded by the contact portion 30 of the second electrode 11, and a linear lead-out portion 33 extending through the opening portion 29 from the contact portion 32. The contact portion 32 is disposed on the p + type contact region 24. Also, the contact hole 27 is formed so as to overlap below the contact portion 32.

[0072] Next, a method for manufacturing the semiconductor device 1 will be described. FIG. 6 is a flowchart of the manufacturing process of the semiconductor device 1. FIGS. 7A to 7L are diagrams showing a part of the manufacturing process of the semiconductor device 1 in the order of the process. Note that FIGS. 7A to 7L do not respectively correspond to each step in FIG. 6. Hereinafter, the manufacturing process of the semiconductor device 1 will be described according to the flow of FIG. 6, and FIGS. 7A to 7L will be referred to as necessary.

[0073] To manufacture the semiconductor device 1, for example, an n-type epitaxial layer is formed on an n-type underlying substrate by epitaxial growth (step S1). Thereby, the semiconductor substrate 6 is formed. + type underlying substrate - type epitaxial layer is formed (step S1). Thereby, the semiconductor substrate 6 is formed.

[0074] Next, a p-type body region 12 and a p-type region 19 are formed by selectively implanting p-type impurities into the semiconductor substrate 6 (step S2). Similarly, an n-type source region 14 and a p-type body contact region 15 are formed by selectively implanting n-type impurities and p-type impurities into the semiconductor substrate 6 (steps S3 and S4). + type source region + type body contact region is formed (steps S3 and S4).

[0075] Next, as shown in FIG. 7A, a gate insulating film 16 is formed on the surface of the semiconductor substrate 6 by thermally oxidizing the semiconductor substrate 6 (step S5). Next, a polysilicon layer 21 serving as a base for the gate electrode 17 and the temperature sense diode 20 is formed, for example, by CVD method (step S6). Next, a hard mask 34 (for example, having a thickness of about 9000 Å) made of silicon oxide (SiO2) is formed, for example, by CVD method (step S7).

[0076] Next, as shown in FIG. 7B, a resist film 35 for lithography of the hard mask 34 is formed (step S8). The resist film 35 is formed so as to cover the hard mask 34 on a region 36 where the p-type region 22 and the n-type region 23 are to be formed. + type region

[0077] Next, as shown in FIG. 7C, the hard mask 34 is selectively etched through the resist film 35 (step S9). The etching may be performed, for example, by wet etching with hydrofluoric acid. After the etching, the resist film 35 is removed.

[0078] Next, as shown in FIG. 7D, an n-type impurity (for example, phosphorus) is deposited on the region 37 (the region other than the region 36 of the polysilicon layer 21) exposed from the hard mask 34 of the polysilicon layer 21, and diffused at about 1000° C., for example, whereby the n-type impurity is introduced into the region 37 (step S10). As a result, the region 37 including the gate electrode 17 portion of the polysilicon layer 21 becomes n-type polysilicon, while the region 36 remains in an undoped state.

[0079] Next, as shown in FIG. 7E, the hard mask 34 remaining on the polysilicon layer 21 is removed by etching (step S11). The etching may be performed, for example, by wet etching with hydrofluoric acid.

[0080] Next, as shown in FIG. 7F, boron, which is a p-type impurity, is implanted into the entire surface of the polysilicon layer 21 in a state where the gate electrode 17 portion of the polysilicon layer 21 is selectively covered with a mask (not shown) (step S12). As a result, the region from the surface of the polysilicon layer 21 to the middle in the thickness direction becomes a p-type region 38.

[0081] Next, as shown in FIG. 7G, after a mask (not shown) for selectively exposing the region where the n + -type region 23 of the polysilicon layer 21 is to be formed is formed by lithography, an n-type impurity is implanted into the region 36 through the mask (step S13). As a result, the n + -type region 23 is formed. At this time, the n + -type region 23 may be formed only from the surface of the polysilicon layer 21 to the middle in the thickness direction, as shown in FIG. 7G.

[0082] Next, as shown in FIG. 7H, the p+ After a mask (not shown) that selectively exposes the area where the p-type contact region 24 is to be formed is formed by lithography, p-type impurities are implanted into the region 36 through the mask (step S14). As a result, p + -type contact region 24 is formed. At this time, the p + -type contact region 24 may be formed only up to the middle in the thickness direction from the surface of the polysilicon layer 21 as shown in FIG. 7H.

[0083] Next, as shown in FIG. 7I, after a hard mask 39 that selectively covers the area where the temperature sense diode 20 and the gate electrode 17 of the polysilicon layer 21 are to be formed is formed, the polysilicon layer 21 is selectively etched through the hard mask 39. As a result, the temperature sense diode 20 and the gate electrode 17 (not shown in FIG. 7I) are formed.

[0084] Next, as shown in FIG. 7J, a plurality of insulating films are formed, for example, by CVD method while leaving the hard mask 39. The plurality of insulating films may include, for example, a lower silicon oxide film 40 (for example, NSG (Non-doped Silicate Glass) film) and an upper silicon oxide film 41 (for example, PSG (Phosphorus Silicate Glass) film, BPSG (Boron Phosphorus Silicate Glass) film, etc.) as shown in FIG. 7J. As a result, an interlayer insulating film 18 composed of the hard mask 39, the silicon oxide film 40, and the silicon oxide film 41 is formed (step S15).

[0085] Next, as shown in FIG. 7K, contact holes 27 and 28 are formed by selectively etching the interlayer insulating film 18 (step S16).

[0086] Next, as shown in FIG. 7L, the semiconductor substrate 6 is heat-treated (reflowed) (step S17). The heat treatment is performed, for example, at 900°C to 1200°C for 5 to 15 minutes in a nitrogen (N2) atmosphere. As a result, the p-type region 38 remaining on the surface portion of the polysilicon layer 21, n + -type region 23 and p + -type contact region 24 diffuse until they reach the back surface of the polysilicon layer 21.

[0087] Thereafter, by forming various wirings, source pad 2, gate pad 3, first electrode 10, second electrode 11, passivation film, etc., the semiconductor device 1 is obtained.

[0088] Next, the operation of the semiconductor device 1 in the semiconductor module 4 and the overcurrent protection method will be described more specifically.

[0089] The electrical circuit configuration in the semiconductor module 4 is as shown in FIG. 2. A voltage is applied to the semiconductor device 1 connected in such a manner by a gate driver G / D. Specifically, mainly referring to FIGS. 3 and 4B, a bias voltage with the drain electrode side being positive is applied between the source pad 2 and the drain electrode (not shown). As a result, a reverse voltage is applied to the pn junction at the interface between the n-type semiconductor substrate 6 and the p-type body region 12. As a result, between the n + -type source region 14 and the semiconductor substrate 6, that is, between the source and drain, is in a cut-off state. In this state, when a predetermined voltage with the gate pad 3 side being positive is applied between the source pad 2 and the gate pad 3, a bias to the p-type body region 12 is applied to the gate electrode 17. As a result, electrons are induced at the peripheral portion of the p-type body region 12, and an inversion channel is formed. Through this inversion channel, between the n + -type source region 14 and the semiconductor substrate 6 becomes conductive. Thus, the source-drain becomes conductive and a drain current Id flows.

[0090] On the one hand, referring to FIGS. 5A and 5B, a constant current is applied to the temperature sense diode 20 by the gate driver G / D. Also, the short-circuit protection circuit 5 of the gate driver G / D constantly monitors the forward voltage V F of the temperature sense diode 20. Under normal conditions, the I-V characteristics of the temperature sense diode 20 depict a curve shown by the solid line in FIG. 8, for example.

[0091] When a short circuit occurs in the switching element SW (MISFET) in FIGS. 4A and 4B and an overcurrent flows, a temperature rise occurs on the surface side of the semiconductor substrate 6. This temperature rise is also transmitted to the temperature sense region 9 (see FIG. 5B) formed on the semiconductor substrate 6 common to the cell region 7. Therefore, in the temperature sense region 9, the forward voltage V F of the temperature sense diode 20 decreases with this temperature rise. For example, like the curve shown by the dashed line in FIG. 8, the turn-on voltage of the temperature sense diode 20 shifts to the low voltage side. The short-circuit protection circuit 5 senses this decrease in the forward voltage V F as the occurrence of a short circuit in the switching element SW and turns off the voltage applied to the gate pad 3. As a result, the drain current Id flowing between the source-drain (S-D) of the switching element SW is cut off, and the switching element SW is protected.

[0092] In this way, when an overcurrent flows through the switching element SW due to, for example, a short circuit, the temperature rise of the semiconductor substrate 6 caused by the overcurrent is reflected in the forward voltage V FBased on the decrease, it can be detected, and according to the detection result, it is possible to determine whether an overcurrent is flowing through the switching element SW. Moreover, since the monitoring target is not the sense current flowing through the switching element SW, even when noise enters and superimposes on the sense current, it will not be erroneously detected as an overcurrent due to the superimposed current. Therefore, malfunction due to current noise can be reduced. Also, different from the conventional overcurrent protection method, either no fixed waiting time (mask time) is provided, or if provided, it only takes a short time, so it is very effective for low on-resistance devices (such as SiC, GaN, etc.) where the time for the device to be destroyed by overcurrent is relatively short.

[0093] Also, in this embodiment, as shown in FIG. 5B, since the temperature sense diode 20 is composed of the polysilicon layer 21 in the same layer as the gate electrode 17, an increase in the number of processes associated with the formation of the temperature sense diode 20 can be suppressed. Also, the temperature sense diode 20 can be disposed on the semiconductor substrate 6 via the relatively thin gate insulating film 16 compared to relatively thick films such as the interlayer insulating film 18. Therefore, the position of the temperature sense diode 20 can be brought close to the immediate vicinity of the current path on the surface side of the semiconductor substrate 6. Thereby, the accuracy of detecting the temperature change of the semiconductor substrate 6 can be improved.

[0094] FIG. 9A is a schematic plan view showing the structure of the temperature sense region 9 of the semiconductor device 1 in FIG. 3. FIG. 9B is a cross-sectional view (cross-sectional view taken along line B - B) of FIG. 9A. FIGS. 9A and 9B show another example of the structure of the temperature sense region 9. In FIGS. 9A and 9B, the same components as those shown in FIGS. 5A and 5B described above are denoted by the same reference numerals, and the description thereof is omitted.

[0095] In FIGS. 5A and 5B, the temperature sense diode 20 was composed of the polysilicon layer 21 on the semiconductor substrate 6, but the temperature sense diode 42 (pn diode) in FIGS. 9A and 9B is composed of impurity regions selectively formed on the surface portion of the semiconductor substrate 6. Specifically, the temperature sense diode 42 includes a p-type region 43 and an n +including a p-type region 43 and an n-type region 44. If the p-type region 43 is surrounded by the n + -type region 44, since the p-type region 43 and the n + -type region 44 do not overlap in plan view, no separate routing wiring or the like is required, and contacts can be easily made to either the p-type region 43 or the n + -type region 44.

[0096] The p-type region 43 is part of the p-type region 19. On the other hand, the n + -type region 44 is formed in a floating state on the surface portion of the p-type region 19. This n + -type region 44 may be formed in the same process as the n + -type source region 14 (see FIG. 4B). That is, the n + -type region 44 may have an n + -type impurity concentration of 1×10 18 cm -3 ~5×10 21 cm -3 and may be formed at the same depth.

[0097] The temperature sense diode 42 may further include a p + -type contact region 45 and a p-type outer peripheral region 46. The p + -type contact region 45 is formed in an inner region of the p-type region 43 with a gap from the periphery of the p-type region 43, and the p-type outer peripheral region 46 may be formed so as to surround the n + -type region 44. The p-type outer peripheral region 46 is part of the p-type region 19 and is electrically connected to the p-type region 43 through the p-type region 19 below the n + -type region 44. On the other hand, the p + -type contact region 45 is formed in a floating state on the surface portion of the p-type region 19. This p + -type contact region 45 may be formed in the same process as the p + -type body contact region 15 (see FIG. 4B). That is, the p + -type contact region 45 may be the same as the p + -type body contact region 15 and may be 1×1018 cm -3 ~5×10 21 cm -3 It may have a p-type impurity concentration of, and may also be formed at the same depth.

[0098] The first electrode 10 is connected to the p-type contact region 45 as an anode electrode through the contact hole 27 of the interlayer insulating film 18. The second electrode 11 is connected to the n-type region 44 as a cathode electrode through the contact hole 28 of the interlayer insulating film 18. + type region 44. + connected.

[0099] As described above, the temperature sense diode 42 can also perform the same function as the aforementioned temperature sense diode 20. Furthermore, since the temperature sense diode 42 is formed on the semiconductor substrate 6 itself, the pn junction can be brought closer to the current path on the surface side, which is the heat generation part of the semiconductor substrate 6, than in the case of the temperature sense diode 20. Thereby, the temperature change of the semiconductor substrate 6 can be detected with high accuracy. Also, since it is a pn diode composed of an impurity region, it operates well even in a high-temperature region (for example, 200 °C or higher), and thus is particularly effective for power devices such as SiC and GaN.

[0100] Next, variations in the connection form when a plurality of temperature sense diodes 20 and 42 are provided will be described. FIGS. 10 to 14 are diagrams each showing an example of the connection form of the temperature sense diodes 20 and 42. In FIGS. 10 to 14, among the components shown in FIGS. 5A and 9A described above, reference numerals are attached only to the elements necessary for the description.

[0101] First, as shown in FIG. 10, a plurality of temperature sense diodes 20, 42 may include a series connection unit 47 configured by connecting one first electrode 10 (anode) and the other second electrode 11 (cathode) in series. The series connection unit 47 may be composed of two temperature sense diodes 20, 42 as shown in FIG. 10, or may be composed of three or more temperature sense diodes 20, 42 (not shown).

[0102] According to the configuration of FIG. 10, the amount of temperature change (shift amount) of the forward voltage V shown in FIG. 8 increases in proportion to the number of connections of the temperature sense diodes 20, 42, so the detection sensitivity of temperature change can be improved. For example, when the swing width of the forward voltage V per one of the temperature sense diodes 20, 42 is X mV / °C, if five temperature sense diodes 20, 42 are connected in series to form the series connection unit 47, the total swing width of the series connection unit 47 can be made 5X mV / °C. F Next, as shown in FIG. 11, at least a pair of series connection units 47 may be connected in parallel in opposite directions to each other. That is, the terminal first electrode 10 of one series connection unit 47 may be connected to the terminal second electrode 11 of the other series connection unit 47 to form a terminal 48, and the terminal second electrode 11 of one series connection unit 47 may be connected to the terminal first electrode 10 of the other series connection unit 47 to form a terminal 49. F According to the configuration of FIG. 11, the distinction between the polarities of the anode side and the cathode side disappears at the terminals 48, 49 of the aggregate of the temperature sense diodes 20, 42 combined with a plurality of series connection units 47. Therefore, when assembling a semiconductor module 4 (see FIG. 2) or the like, the degree of freedom of wiring such as bonding wires can be improved. That is, even if a reverse bias is applied to one series connection unit 47, at that time, a forward bias is applied to the other series connection unit 47, so at least one of them can function as a temperature sense diode.

[0103]

[0104]

[0105] ​​Next, as shown in FIG. 12, the plurality of temperature sense diodes 20, 42 may include an inverse series connection unit 50 configured by connecting one and the other of the first electrodes 10 (anodes) or one and the other of the second electrodes 11 (cathodes) in series. The inverse series connection unit 50 may be composed of two temperature sense diodes 20, 42 as shown in FIG. 12, or may be composed of three or more temperature sense diodes 20, 42 (not shown). Further, as shown in FIG. 13, a plurality of these inverse series connection units 50 may be connected in inverse series.

[0106] According to the configurations of FIGS. 12 and 13, since a reverse bias is applied to at least one of the temperature sense diodes 20, 42 constituting the inverse series connection unit 50, the total resistance of the inverse series connection unit 50 increases. Therefore, the current required for monitoring the temperature change of the temperature sense diodes 20, 42 can be significantly suppressed, and power saving can be achieved.

[0107] Next, as shown in FIG. 14, the temperature sense diodes 20, 42 may include a configuration in which at least one pair is connected in parallel in opposite directions. That is, the first electrode 10 of one temperature sense diode 20, 42 may be connected to the second electrode 11 of the other temperature sense diode 20, 42 to form a terminal 51, and the second electrode 11 of one temperature sense diode 20, 42 may be connected to the first electrode 10 of the other temperature sense diode 20, 42 to form a terminal 52.

[0108] According to the configuration of FIG. 14, similar to the configuration of FIG. 11, there is no distinction in the polarities of the anode side and the cathode side at the terminals 51, 52 of the aggregate of the temperature sense diodes 20, 42. Therefore, when assembling a semiconductor module 4 (see FIG. 2) or the like, the degree of freedom in wiring such as bonding wires can be improved. That is, even if a reverse bias is applied to one temperature sense diode 20, 42, at that time, a forward bias is applied to the other temperature sense diode 20, 42, so at least one of them can function as a temperature sense diode.

[0109] As described above, the connection forms of the plurality of temperature sense diodes 20 and 42 are not limited to the configurations shown in FIGS. 10 to 14, and appropriate forms can be adopted. Further, the concepts of the connection forms shown above (series, series + anti-parallel, anti-series, multiple anti-series, anti-parallel, etc.) can also be applied to the temperature sense diodes 66 shown in FIGS. 16A to 16C described later.

[0110] FIG. 15A is a schematic plan view showing the structure (trench gate structure) of the cell region 7 of the semiconductor device 1 in FIG. 3. FIG. 15B is a cross-sectional view (cross-section taken along line B-B) of FIG. 15A. FIGS. 15A and 15B show another example of the structure of the cell region 7. In FIGS. 15A and 15B, the same components as those shown in FIGS. 4A and 4B described above are denoted by the same reference numerals, and the description thereof is omitted.

[0111] As shown in FIGS. 15A and 15B, in the cell region 7, a gate trench 53 is formed in the semiconductor substrate 6. The gate trench 53 partitions each unit cell 54 of the switching element SW. The gate trench 53 may be formed, for example, in a lattice shape in a plan view as shown in FIG. 15A, or may be formed in other shapes such as a stripe shape or a honeycomb shape.

[0112] A p-type body region 55 is formed on the surface portion of each unit cell 54, and an n + type source region 56 is formed on the surface portion of the p-type body region 55. The p-type impurity concentration of the p-type body region 55 may be, for example, 1×10 15 cm -3 ~1×10 20 cm -3 . Further, the n-type impurity concentration of the n + type source region 56 is higher than the impurity concentration of the n-type semiconductor substrate 6, and may be, for example, 1×10 18 cm -3 ~5×10 21 cm -3 .

[0113] n + In the inner region of the type source region 56, p +A p-type body contact region 57 is formed. p + The p-type body contact region 57 is an n + type source region 56 and is formed by penetrating in the depth direction. p + The p-type impurity concentration of the p-type body contact region 57 is higher than that of the p-type body region 55, for example, 1×10 18 cm -3 ~5×10 21 cm -3 It may be.

[0114] A gate insulating film 58 is formed on the inner surface of the gate trench 53 and the surface of the semiconductor substrate 6. The gate insulating film 58 may be made of, for example, silicon oxide (SiO2). The thickness of the gate insulating film 58 may be, for example, 300 Å to 600 Å.

[0115] A gate electrode 59 is embedded in the gate trench 53. The gate electrode 59 faces the p-type body region 55 on the side surface of the gate trench 53 with the gate insulating film 58 interposed therebetween. The gate electrode 59 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may be made of p-type polysilicon.

[0116] Next, the structure of the temperature sense region 9 when the cell region 7 is shown in FIGS. 15A and 15B will be described. FIG. 16A is a schematic plan view showing the structure of the temperature sense region 9 of the semiconductor device 1 in FIG. 3. FIG. 16B is a cross-sectional view (cross-section taken along line B-B) of FIG. 16A. FIG. 16C is a cross-sectional view (cross-section taken along line C-C) of FIG. 16A. In FIGS. 16A to 16C, the same components as those shown in FIGS. 5A and 5B described above are denoted by the same reference numerals, and the description thereof is omitted.

[0117] As shown in FIGS. 16A to 16C, the temperature sense region 9 is partitioned by the gate trench 53, and its periphery is surrounded by the gate trench 53. The temperature sense region 9 may be, for example, rectangular in plan view with four sides surrounded by the gate trench 53 as shown in FIG. 16A.

[0118] In the temperature sensing region 9, an n + -type region 60 is formed on the surface portion of the semiconductor substrate 6, and a p-type region 61 is formed below the n + -type region 60. The p-type region 61 is in contact with the n + -type region 60. The n + -type region 60 may have the same n-type impurity concentration and depth as the n + -type source region 56. Also, the p-type region 61 may have the same p-type impurity concentration and depth as the p-type body region 55, but with respect to the depth, as shown in FIGS. 16B and 16C, it may be deeper than the p-type body region 55 and may have a protruding portion 62 that selectively protrudes downward.

[0119] In the inner region of the temperature sensing region 9, a temperature sensing trench 63, which is an example of the second trench of the present invention, is formed. That is, the temperature sensing trench 63 is independent of the gate trench 53 that surrounds the temperature sensing region 9. This temperature sensing trench 63 may be formed, for example, with the same width as the gate trench 53.

[0120] The temperature sensing trench 63 may be formed to penetrate the p-type region 61, but as shown in FIGS. 16B and 16C, by being formed on the protruding portion 62, it does not penetrate the p-type region 61, and its bottom may be disposed inside the p-type region 61 (protruding portion 62).

[0121] Also, the temperature sensing trench 63 is formed in an annular shape in plan view, and a closed region 64 is partitioned inside it. In the closed region 64, a p + -type contact region 65 is formed. The p + -type contact region 65 may be formed on the entire surface of the closed region 64 as shown in FIG. 16A, or may be selectively formed only on a part of the closed region 64 (not shown). The p + -type contact region 65 may have the same p-type impurity concentration and depth as the p + -type body contact region 57.

[0122] On the inner surface of the temperature sensing trench 63, the gate insulating film 58 of the cell region 7 is formed so as to extend to the temperature sensing region 9. Then, inside the gate insulating film 58, a temperature sensing diode 66 (pn diode) as an example of the temperature sensing element TS is formed.

[0123] The temperature sensing diode 66 is made of a buried polysilicon layer 67 buried in the temperature sensing trench 63. The temperature sensing diode 66 made of the buried polysilicon layer 67 may be formed in the same process as the gate electrode 59, or may be formed in a process separate from the gate electrode 59.

[0124] The temperature sensing diode 66 includes a p-type region 68 and a n-type + That is, the p-type region 68 is embedded to the bottom in a certain region of the annular temperature sensing trench 63, and an n-type region 69 is disposed adjacent to the p-type region 68. + The p-type region 69 may be embedded in other regions of the temperature sensing trench 63 to the bottom. + If the p-type region 68 and the n-type region 69 are adjacent to each other in the lateral direction, + Since the p-type regions 68 and n-type regions 69 do not overlap in a plan view, no separate wiring is required. + Contact can easily be made to either of the mold areas 69 .

[0125] The p-type impurity concentration of the p-type region 68 is, for example, 1×10 15 cm -3 ~1×10 20 cm -3 (same as p-type body region 55) + The n-type impurity concentration of the n-type region 69 is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 (n + The source region 56 may be the same as the source region 56.

[0126] The temperature sensing diode 66 further includes a+ The semiconductor device may include a contact region 70. + The n-type contact region 70 is formed in contact with the p-type region 68. + The p-type region 68 is separated from the p-type region 69. + The p-type contact region 70 may be embedded to the bottom of the temperature sensing trench 63 and laterally adjacent to the p-type region 68 as shown in FIG. 16C, or may be disposed between the p-type region 68 and the n-type contact region 70 (not shown). + The p-type region 69 may be selectively formed on the surface of the p-type region 68 at a position away from the boundary with the p-type region 69. + The p-type impurity concentration of the contact region 70 is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 (p + The contact region 57 may be the same as the body contact region 57.

[0127] The first electrode 10 in FIG. 3 is an anode electrode. + 3 is connected to the n-type contact region 70 as a cathode electrode. + It is connected to the mold region 69 .

[0128] As described above, the above temperature sensing diode 66 can also fulfill the same function as the previously described temperature sensing diode 20. Furthermore, since the temperature sensing diode 66 (pn diode) is embedded in the surface portion of the semiconductor substrate 6, the pn junction can be brought closer to the current path on the surface side, which is the heat generating portion of the semiconductor substrate 6, than in the case of the temperature sensing diode 20. This makes it possible to detect temperature changes in the semiconductor substrate 6 with high accuracy.

[0129] Although one embodiment of the present invention has been described above, the present invention can be embodied in other forms.

[0130] For example, a configuration may be adopted in which the conductivity type of each semiconductor portion of the semiconductor device 1 is inverted. That is, in the semiconductor device 1, a p-type portion may be n-type, and an n-type portion may be p-type.

[0131] In addition to the aforementioned temperature sense diodes 20 and 42 (pn diodes), a Schottky barrier diode or the like can also be adopted as the temperature sense element TS.

[0132] In addition, various design changes can be made within the scope of the matters described in the claims.

Explanation of Reference Numerals

[0133] 1 Semiconductor device 2 Source pad 3 Gate pad 4 Semiconductor module 5 Short-circuit protection circuit 6 Semiconductor substrate 7 Cell region 9 Temperature sense region 10 First electrode 11 Second electrode 12 p-type body region 13 Unit cell 14 n + -type source region 16 Gate insulating film 17 Gate electrode 20 Temperature sense diode 21 Polysilicon layer 22 p-type region 23 n + -type region 24 p + -type contact region 25 p-type outer peripheral region 26 p-type base layer 42 Temperature sense diode 43 p-type region 44 n + -type region 45 p + -type contact region 46 p-type outer peripheral region 47 Series connection unit 48 Terminal 49 Terminal 50 Inverse series connection unit 51 Terminal 52 Terminal 53 Gate Trench 54 Unit Cell 55 p-Type Body Region 56 n + -Type Source Region 58 Gate Insulating Film 59 Gate Electrode 63 Temperature Sense Trench 66 Temperature Sense Diode 67 Embedded Polysilicon Layer 68 p-Type Region 69 n + -Type Region 70 p + -Type Contact Region SW Switching Element TS Temperature Sense Element G / D Gate Driver

Claims

1. A planar rectangular semiconductor chip composed of a semiconductor substrate having a front surface and a back surface facing the front surface, a switching element formed on the semiconductor substrate, which performs a switching operation between a first electrode provided on the front surface side and a second electrode provided on the back surface side of the semiconductor substrate in response to a signal input to a control electrode formed on the front surface side of the semiconductor substrate; a gate finger extending from the control electrode along the outer periphery of the semiconductor chip and extending so as to cross the central portion of the semiconductor chip; a temperature sense element provided on the front surface side and capable of outputting a signal dependent on temperature; including a third electrode and a fourth electrode electrically connected to the temperature sense element, wherein the control electrode, the third electrode, and the fourth electrode have the same size and the same shape as each other, the control electrode is disposed at the central portion of one side of the semiconductor chip, and the third electrode and the fourth electrode are arranged side by side on one side of the control electrode along the side where the control electrode is disposed, the temperature sense element is disposed adjacent to the gate finger, a semiconductor device.

2. The semiconductor device according to claim 1, including a diode element capable of outputting a signal dependent on temperature as the temperature sense element.

3. The semiconductor device according to claim 2, wherein the anode and the cathode of the diode element are respectively connected to the third electrode and the fourth electrode.

4. The switching element is a MISFET in which the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode, the source electrode has regions separated into two by the gate finger crossing the central portion of the semiconductor chip, the semiconductor device according to claim 1, wherein the third electrode and the fourth electrode are disposed adjacent to the periphery of one of the two separated regions of the source electrode.

5. The semiconductor device according to any one of claims 1 to 3, wherein the switching element is a MISFET in which the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode.

6. The semiconductor device according to any one of claims 1 to 5, wherein the third electrode and the fourth electrode are connected to terminals electrically independent from the terminals to which the first electrode and the second electrode of the switching element are respectively connected.

7. The semiconductor device according to claim 1 or 2, wherein the temperature sensing element includes a series connection unit in which at least a pair of pn diodes are connected in series or in reverse series.

8. The semiconductor device according to claim 1 or 2, wherein the temperature sensing element has at least a pair of pn diodes connected in antiparallel.

9. The semiconductor device according to claim 1 or 2, wherein the temperature sensing element has series connection units in which at least a pair of pn diodes are connected in series, and the series connection units are connected in parallel with each other in opposite directions.

10. The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor substrate includes a SiC semiconductor layer.

11. The semiconductor device according to claim 10, wherein the temperature sensing element is formed in a polysilicon layer on the SiC semiconductor layer.

12. The semiconductor device according to claim 11, wherein the polysilicon layer forming the temperature sensing element has the same thickness as the gate electrode of the switching element.

13. The semiconductor device according to claim 11 or 12, wherein the polysilicon layer forming the temperature sensing element includes a first conductivity type impurity region and a second conductivity type impurity region which are selectively introduced.

14. The semiconductor device according to claim 11 or 12, wherein the polysilicon layer forming the temperature sensing element includes a second conductivity type base layer and a first conductivity type impurity region selectively introduced on the surface of the base layer.

15. The semiconductor device according to any one of claims 1 to 14, wherein the switching element includes a trench gate type MISFET having a gate trench that forms a unit cell on the semiconductor chip, a gate electrode embedded in the gate trench, a first conductivity type body region formed on the surface portion of the unit cell, a second conductivity type source region formed on the surface portion of the body region, and a second conductivity type drain region formed on the side opposite to the source region with respect to the body region.

16. The semiconductor device according to any one of claims 1 to 15, wherein the temperature sensing element is disposed in a temperature sensing region between the third electrode and the fourth electrode.

17. The semiconductor device according to any one of claims 1 to 10, wherein the temperature sensing element includes a first conductivity type region formed in the semiconductor substrate and a second conductivity type region surrounding the first conductivity type region.

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