Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device in which on-resistance can be reduced.SOLUTION: A silicon carbide semiconductor device 100 includes a silicon carbide substrate 10 having a first main surface 1 and a second main surface 2 opposite the first main surface. The silicon carbide substrate includes a drift region 11 of a first conductivity type, a body region 12 of a second conductivity type, provided on the drift region, and a source region 13 of the first conductivity type. A plurality of gate trenches 5 reaching the drift region are provided. The silicon carbide semiconductor device further includes a gate electrode 82 provided on a gate insulating film 81 inside the gate trenches between the silicon carbide substrate and the gate insulating film, an interlayer insulating film 83 covering the gate electrode and provided with a plurality of contact holes 90, and a source electrode 60. The gate trenches extend along a first axis parallel to the first main surface, and, in plan view perpendicular to the first main surface, a plurality of first contact holes are aligned along a second axis perpendicular to the first axis, and a plurality of first gate trenches 5A are aligned along the second axis between two of the first contact holes adjacent with each other along the second axis.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device.

Background Art

[0002] As one of silicon carbide semiconductor devices, a trench-type MOSFET (metal oxide semiconductor field effect transistor) has been disclosed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, there has been an increasing demand for further reduction of on-resistance.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of reducing on-resistance.

Means for Solving the Problems

[0006] The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type. A plurality of gate trenches are provided on the first main surface, the gate trenches including side surfaces that penetrate the source region and the body region and reach the drift region, and bottom surfaces that are continuous with the side surfaces. A gate insulating film that contacts the side surfaces and the bottom surfaces of the gate trenches, a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the gate insulating film and the silicon carbide substrate, an interlayer insulating film that covers the gate electrode and has a plurality of contact holes reaching the source region, and a source electrode provided on the interlayer insulating film and in the contact holes and electrically connected to the source region. The gate trenches extend along a first axis parallel to the first main surface, and in a plan view perpendicular to the first main surface, a plurality of first contact holes among the plurality of contact holes are arranged along a second axis perpendicular to the first axis, and a plurality of first gate trenches among the plurality of gate trenches are arranged along the second axis between two adjacent first contact holes along the second axis.

Advantages of the Invention

[0007] According to the present disclosure, the on-resistance can be reduced.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Mode for Carrying Out the Invention

[0009] The mode for carrying out the invention will be described below.

[0010] [Description of Embodiments of the Present Disclosure] First, the embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Also, in crystallography, when an index is negative, it is usually expressed by attaching "-" (bar) above the number, but in the present disclosure, a negative sign is attached before the number. Further, in the following description, the XYZ orthogonal coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the posture of the silicon carbide semiconductor device. Also, the XY plane view is referred to as a plan view, and depending on the viewing point, the +Z direction may be referred to as upward, upper, or top, and the -Z direction may be referred to as downward, lower, or bottom.

[0011] 〔1〕 A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type. A plurality of gate trenches are provided on the first main surface, the gate trenches including side surfaces that penetrate the source region and the body region to reach the drift region and bottom surfaces that are continuous with the side surfaces. A gate insulating film is provided in contact with the side surfaces and the bottom surfaces of the gate trenches, and a gate electrode is provided on the gate insulating film so as to sandwich the gate insulating film between the gate insulating film and the silicon carbide substrate. An interlayer insulating film is provided to cover the gate electrode and has a plurality of contact holes that reach the source region. A source electrode is provided on the interlayer insulating film and within the contact holes and is electrically connected to the source region. The gate trenches extend along a first axis parallel to the first main surface, and in a plan view perpendicular to the first main surface, a plurality of first contact holes among the plurality of contact holes are arranged along a second axis perpendicular to the first axis, and a plurality of first gate trenches among the plurality of gate trenches are arranged along the second axis between two adjacent first contact holes along the second axis.

[0012] A plurality of first gate trenches are arranged along the second axis between two adjacent first contact holes along the second axis. Therefore, a wider current path is obtained between the first main surface and the second main surface as compared with the case where only one gate trench is provided between two adjacent first contact holes along the second axis. For this reason, the on-resistance can be reduced.

[0013] 〔2〕 In 〔1〕, the plurality of first contact holes may be provided at a constant pitch along the second axis. In this case, it is easy to uniformly flow current between the first main surface and the second main surface.

[0014] 〔3〕In 〔1〕 or 〔2〕, a shield region is provided below the body region, in contact with the body region, and having the second conductivity type. The shield region may overlap with the first contact hole in the plan view. In this case, a depletion layer spreads in the vicinity of the interface between the shield region and the drift region, and it is easy to obtain a high breakdown voltage.

[0015] 〔4〕In any one of 〔1〕 to 〔3〕, the silicon carbide substrate may be provided between the bottom surface of the plurality of first gate trenches and the second main surface, and may have an electric field relaxation region having the second conductivity type. In this case, it is easy to relieve the electric field concentration at the portion of the gate insulating film in contact with the bottom surface of the gate trench.

[0016] 〔5〕In any one of 〔1〕 to 〔3〕, the silicon carbide substrate may be provided between the bottom surface and the second main surface for each of the plurality of first gate trenches, and may have a plurality of electric field relaxation regions having the second conductivity type. Also in this case, it is easy to relieve the electric field concentration at the portion of the gate insulating film in contact with the bottom surface of the gate trench.

[0017] 〔6〕In any one of 〔1〕 to 〔5〕, the gate electrode may include a plurality of potential control portions each located in a corresponding one of the plurality of first gate trenches, and a connection portion connecting adjacent potential control portions. When the distance between the plurality of first gate trenches is small, it is easier to form a gate electrode having potential control portions and a connection portion than to form a gate electrode for each first gate trench. Also, since the gate electrode can be made smaller, an increase in the internal gate resistance can be suppressed, and variations in the switching waveforms between the plurality of gate electrodes can be suppressed.

[0018] 〔7〕In any one of 〔1〕 to 〔6〕, a plurality of the second contact holes among the plurality of the contact holes are arranged along the second axis, and among the plurality of the gate trenches, a plurality of the second gate trenches are arranged along the second axis between two adjacent second contact holes along the second axis. The plurality of the first contact holes and the plurality of the second contact holes are arranged along the first axis, and the plurality of the first gate trenches and the plurality of the second gate trenches may be arranged along the first axis. In this case, a current path between the first main surface and the second main surface can also be obtained between the first gate trench and the second gate trench.

[0019] 〔8〕In 〔7〕, the first contact hole and the second contact hole may be connected to each other. In this case, the first contact hole and the second contact hole can be integrally formed.

[0020] 〔9〕In any one of 〔1〕 to 〔8〕, in a cross-sectional view perpendicular to the first axis, the angle between the virtual plane including the bottom surface and the side surface may be 45° or more and 65° or less. In this case, it is easy to form the gate trench with high accuracy by thermal etching.

[0021] 〔10〕In any one of 〔1〕 to 〔9〕, the side surface of the gate trench may include the {0-33-8} plane. By including the {0-33-8} plane on the side surface of the gate trench, good mobility can be obtained on the side surface of the gate trench, and the channel resistance can be reduced.

[0022] [Embodiments of the Present Disclosure] (First Embodiment) The first embodiment will be described. The first embodiment relates to a so-called vertical MOS type field effect transistor (FET) using silicon carbide, and this MOS type FET is an example of a silicon carbide semiconductor device. FIG. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0023] As shown in FIGS. 1 and 2, the silicon carbide semiconductor device 100 according to the first embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0024] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction as viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains, for example, an n-type impurity such as nitrogen (N) and has an n-type conductivity type (first conductivity type).

[0025] The first main surface 1 is a {0001} plane or a plane in which the {0001} plane is inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is a (000-1) plane or a plane in which the (000-1) plane is inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less.

[0026] The silicon carbide epitaxial layer 40 mainly includes a drift region 11, a body region 12, a source region 13, a shield region 14, and a contact region 18.

[0027] The drift region 11 contains an n-type impurity such as nitrogen or phosphorus (P), and has an n-type conductivity type. The drift region 11 is provided on the silicon carbide single crystal substrate 50. The drift region 11 mainly has a first region 11A and a second region 11B.

[0028] The body region 12 contains a p-type impurity such as aluminum (Al), and has a p-type conductivity type. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.

[0029] The source region 13 contains an n-type impurity such as nitrogen or phosphorus, and has an n-type conductivity type. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0030] A plurality of gate trenches 5 defined by a side surface 3 and a bottom surface 4 are provided on the first main surface 1. The gate trench 5 extends along, for example, the Y-axis. The side surface 3 penetrates through the source region 13, the body region 12, and a part of the drift region 11, and reaches the drift region 11. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the drift region 11. For example, the bottom surface 4 is parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y-axis, the angle θ1 of the side surface 3 with respect to the virtual plane 31 including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane on which excellent mobility can be obtained. Also, the gate trench 5 with the angle θ1 of 45° or more and 65° or less is easily formed with high precision by thermal etching of the silicon carbide epitaxial layer 40. The Y-axis is an example of the first axis, and the X-axis is an example of the second axis.

[0031] As shown in FIG. 1, the plurality of gate trenches 5 include a plurality of first gate trenches 5A and a plurality of second gate trenches 5B. The plurality of first gate trenches 5A are arranged along the X-axis, and the plurality of second gate trenches 5B are also arranged along the X-axis. The plurality of first gate trenches 5A and the plurality of second gate trenches 5B are arranged along the Y-axis. The second gate trench 5B is on the -Y side of the first gate trench 5A. There may be other gate trenches 5 on the +Y side of the first gate trench 5A, and there may be other gate trenches 5 on the -Y side of the second gate trench 5B. The plurality of gate trenches 5 may be provided in an array.

[0032] The contact region 18 contains a p-type impurity such as aluminum and has a p-type conductivity type. The contact region 18 penetrates the source region 13 and contacts the body region 12. The contact region 18 constitutes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between trench pairs 6 formed by two adjacent gate trenches 5 along the X-axis. A plurality of contact regions 18 may be arranged at regular intervals along the X-axis. Between two adjacent trench pairs 6 along the X-axis, the contact region 18 and the source region 13 may be alternately provided along the Y-axis. Between two adjacent trench pairs 6 along the X-axis, the contact region 18 may be intermittently provided along the Y-axis. A part of the contact region 18 may be between the first gate trench 5A and the second gate trench 5B. When a plurality of gate trenches 5 are provided along the Y-axis, a part of the contact region 18 may be between adjacent gate trenches 5 along the Y-axis.

[0033] The shield region 14 contains p-type impurities such as aluminum and has a p-type conductivity type. In a plan view perpendicular to the first main surface 1, the shield region 14 is between adjacent gate trenches 5 along the X-axis. The shield region 14 is away from the gate trench 5. The body region 12 is exposed on the side surface 3 of the gate trench 5. The shield region 14 is farther from the gate trench 5 than the body region 12 along the X-axis. The shield region 14 is below the body region 12 and in contact with the body region 12. In a plan view perpendicular to the first main surface 1, the shield region 14 overlaps the contact region 18. The shield region 14 may be in contact with the body region 12 and the contact region 18. The shield region 14 may extend along the Y-axis. A plurality of shield regions 14 may be arranged at regular intervals along the X-axis. A plurality of shield regions 14 may be provided in a stripe shape. The lower end surface of the shield region 14 may be closer to the second main surface 2 than the bottom surface 4. The contact region 18, the body region 12, and the shield region 14 are electrically connected to each other.

[0034] The first region 11A of the drift region 11 is exposed on the side surface 3 and is in contact with the body region 12 and the shield region 14. The thickness of the first region 11A is, for example, 0.1 μm or more and 0.6 μm or less. The second region 11B of the drift region 11 may be in contact with the silicon carbide single crystal substrate 50. The first region 11A is between the second region 11B and the body region 12. The lower end surface of the first region 11A is in contact with the upper end surface of the second region 11B. The second region 11B may be exposed on the side surface 3. The second region 11B may be exposed on the bottom surface 4. The lower end surface of the first region 11A may be on a virtual plane 31 including the bottom surface 4, or may be closer to the first main surface 1 than the virtual plane 31.

[0035] The second effective concentration of the n-type impurities in the second region 11B is lower than the first effective concentration of the n-type impurities in the first region 11A. For example, the second effective concentration is 1×10 16 cm -3 or more and 1×10 17 cm -3 or less, and the first effective concentration is 1×10 17 cm -3 or more and 1×10 18cm -3 The following applies. The first region 11A may be called a current diffusion region.

[0036] Along the Z axis, between the bottom surface 4 and the second main surface 2, there are a silicon carbide single crystal substrate 50 and a drift region 11, and the conductivity type of the silicon carbide substrate 10 between the bottom surface 4 and the second main surface 2 is n-type. Along the Z axis, there is no semiconductor with a p-type conductivity type between the bottom surface 4 and the second main surface 2.

[0037] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is composed of a material containing, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the second region 11B at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 is in contact with the first region 11A and the second region 11B at the side surface 3. If the gate insulating film 81 is in contact with the first region 11A at the side surface 3, it does not have to be in contact with the second region 11B. The gate insulating film 81 may be in contact with the source region 13 at the first main surface 1.

[0038] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is composed of, for example, polysilicon (poly-Si) containing a conductive impurity. The gate electrode 82 extends along the Y axis. The gate electrode 82 has two potential control portions 82A and a connecting portion 82B. Each of the potential control portions 82A is in the gate trench 5. The connecting portion 82B connects adjacent potential control portions 82A. The potential control portion 82A faces the side surface 3 and the bottom surface 4 and controls the potential of the body region 12. The connecting portion 82B may face the first main surface 1. The two potential control portions 82A are electrically connected to each other via the connecting portion 82B. The gate electrode 82 does not have to have the connecting portion 82B. In this case, the potential control portion 82A may be regarded as the gate electrode.

[0039] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface with a continuously changing curvature. The upper surface of the interlayer insulating film 83 may be a curved surface that protrudes in the +Z direction above the gate trench 5.

[0040] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at a constant pitch P1 along the X axis. The contact holes 90 extend along the Y axis. The contact holes 90 are arranged such that the trench pair 6 is positioned between adjacent contact holes 90 along the X axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0041] The contact hole 90 includes a first contact hole 90A and a second contact hole 90B. The plurality of first contact holes 90A and the plurality of second contact holes 90B are arranged side by side along the Y axis. The first contact hole 90A is provided such that two first gate trenches 5A are positioned between adjacent first contact holes 90A along the X axis. The second contact hole 90B is provided such that two second gate trenches 5B are positioned between adjacent second contact holes 90B along the X axis. In the present embodiment, the first contact hole 90A and the second contact hole 90B are connected to each other.

[0042] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is composed of a material containing, for example, titanium nitride (TiN).

[0043] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 is in ohmic contact with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and the side surface of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0044] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing, for example, nickel silicide. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0045] A buffer layer containing an n-type impurity such as nitrogen and having an n-type conductivity type may be provided between the silicon carbide single crystal substrate 50 and the drift region 11. Also, a passivation film covering a part of the source electrode 60 may be provided.

[0046] The effective concentration of the p-type impurity in the contact region 18 may be higher than the effective concentration of the p-type impurity in the body region 12. For example, the effective concentration of the p-type impurity in the contact region 18 is, for example, 1×10 18 cm -3 or more and 1×10 20 cm -3 or less, and the effective concentration of the p-type impurity in the body region 12 is 5×10 17 cm-3 is 1×10 18 cm -3 or less.

[0047] The effective concentration of the n-type impurities in the source region 13 may be higher than the effective concentration of the p-type impurities in the body region 12. The effective concentration of the n-type impurities in the source region 13 is, for example, 1×10 19 cm -3 or so. Also, the effective concentration of the p-type impurities in the shield region 14 is, for example, 5×10 17 cm -3 or more and 5×10 18 cm -3 or less.

[0048] In the present disclosure, the effective concentration of the impurities of the first conductivity type is the concentration obtained by subtracting the concentration of the impurities of the second conductivity type from the concentration of the impurities of the first conductivity type, and the effective concentration of the impurities of the second conductivity type is the concentration obtained by subtracting the concentration of the impurities of the first conductivity type from the concentration of the impurities of the second conductivity type. The effective concentration can be measured, for example, using a scanning capacitance microscope (SCM).

[0049] In the silicon carbide semiconductor device 100, the gate trench 5 extends along the Y axis. In plan view, a plurality of contact holes 90 are arranged along the X axis, and two first gate trenches 5A are arranged along the X axis between two adjacent contact holes 90 along the X axis. A second gate trench 5B is also arranged along the X axis between two adjacent contact holes 90 along the X axis. Therefore, a wider current path is obtained between the first main surface 1 and the second main surface 2 as compared with the case where only one gate trench 5 is provided between two adjacent contact holes 90 along the X axis. For this reason, according to the first embodiment, the on-resistance can be reduced.

[0050] When the shield region 14 overlaps the contact hole 90 in plan view, a depletion layer spreads in the vicinity of the interface between the shield region 14 and the drift region 11, and a high breakdown voltage is easily obtained.

[0051] Also, when the distance between the gate trenches 5 is small, it is easier to form the gate electrode 82 having the potential control portion 82A and the connection portion 82B than to form a gate electrode for each gate trench 5. Further, since the gate electrode 82 can be made smaller, an increase in the internal gate resistance can be suppressed, and variations in the switching waveforms among the plurality of gate electrodes 82 can be suppressed.

[0052] When a plurality of first gate trenches 5A and a plurality of second gate trenches 5B are arranged along the Y axis, a current path between the first main surface 1 and the second main surface 2 can also be obtained between the first gate trench 5A and the second gate trench 5B. In this case, the first contact hole 90A and the second contact hole 90B may be connected to each other or may be separated from each other. When the first contact hole 90A and the second contact hole 90B are connected to each other, the first contact hole 90A and the second contact hole 90B can be integrally formed.

[0053] The plurality of contact holes 90 may be provided at a constant pitch along the X axis. In this case, it is easy to uniformly flow a current between the first main surface 1 and the second main surface 2.

[0054] (Second Embodiment) The second embodiment will be described. The second embodiment is mainly different from the first embodiment in terms of the configuration of the silicon carbide epitaxial layer 40. FIGS. 3 to 5 are cross-sectional views showing the configuration of the silicon carbide semiconductor device according to the second embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIGS. 4 and 5. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 corresponds to a cross-sectional view taken along line V-V in FIG. 3.

[0055] In the silicon carbide semiconductor device 200 according to the second embodiment, as shown in FIGS. 3 to 5, the silicon carbide epitaxial layer 40 has an electric field relaxation region 21 and a connection region 26. A part of the drift region 11 is replaced by the electric field relaxation region 21 and the connection region 26.

[0056] The electric field relaxation region 21 contains p-type impurities such as aluminum and has a p-type conductivity type. The electric field relaxation region 21 is between the bottom surface 4 of the two gate trenches 5 that constitute the trench pair 6 and the second main surface 2. The upper end surface of the electric field relaxation region 21 is between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the electric field relaxation region 21 is away from the bottom surface 4 of the gate trench 5. The electric field relaxation region 21 is between the shield regions 14 adjacent along the X axis. The electric field relaxation region 21 extends along the Y axis, similar to the gate trench 5. In a plan view perpendicular to the first main surface 1, each of the electric field relaxation regions 21 overlaps with the two gate trenches 5. The lower end surface of the electric field relaxation region 21 may be closer to the first main surface 1 than the lower end surface of the shield region 14.

[0057] The connection region 26 contains p-type impurities such as aluminum and has a p-type conductivity type. The connection region 26 is intermittently provided along the Y axis between the shield region 14 and the electric field relaxation region 21. The connection region 26 is in contact with the shield region 14 and the electric field relaxation region 21 and electrically connects the shield region 14 and the electric field relaxation region 21. For example, the upper end surface of the connection region 26 is flush with the upper end surface of the electric field relaxation region 21, and the lower end surface of the connection region 26 is flush with the lower end surface of the electric field relaxation region 21.

[0058] Other configurations of the second embodiment are the same as those of the first embodiment.

[0059] The same effect as that of the first embodiment can also be obtained by the second embodiment. According to the second embodiment, since the electric field relaxation region 21 is provided, the electric field concentration at the portion of the gate insulating film 81 in contact with the bottom surface 4 of the gate trench 5 can be alleviated.

[0060] (Third Embodiment) A description will be given of the third embodiment. The third embodiment is mainly different from the first embodiment in terms of the configuration of the silicon carbide epitaxial layer 40. FIGS. 6 to 8 are cross-sectional views showing the configuration of the silicon carbide semiconductor device according to the third embodiment. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIGS. 7 and 8. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIG. 6. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG. 6.

[0061] In the silicon carbide semiconductor device 300 according to the third embodiment, as shown in FIGS. 6 to 8, the silicon carbide epitaxial layer 40 has an electric field relaxation region 22, a connection region 26, and a connection region 27. A part of the drift region 11 is replaced by the electric field relaxation region 22, the connection region 26, and the connection region 27.

[0062] The electric field relaxation region 22 contains a p-type impurity such as aluminum and has a p-type conductivity type. The electric field relaxation region 22 is located between the bottom surface 4 and the second main surface 2 for each gate trench 5. The upper end surface of the electric field relaxation region 22 is between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the electric field relaxation region 22 is away from the bottom surface 4 of the gate trench 5. There are two electric field relaxation regions 22 between adjacent shield regions 14 along the X axis. The electric field relaxation region 22 extends along the Y axis in the same manner as the gate trench 5. In a plan view perpendicular to the first main surface 1, each of the electric field relaxation regions 22 overlaps one gate trench 5. The lower end surface of the electric field relaxation region 22 may be closer to the first main surface 1 than the lower end surface of the shield region 14.

[0063] The connection region 26 contains a p-type impurity such as aluminum and has a p-type conductivity type. The connection region 26 is intermittently provided along the Y axis between the shield region 14 and the electric field relaxation region 22. The connection region 26 is in contact with the shield region 14 and the electric field relaxation region 22 and electrically connects the shield region 14 and the electric field relaxation region 22. For example, the upper end surface of the connection region 26 is flush with the upper end surface of the electric field relaxation region 22, and the lower end surface of the connection region 26 is flush with the lower end surface of the electric field relaxation region 22.

[0064] The connection region 27 contains p-type impurities such as aluminum and has a p-type conductivity type. The connection region 27 is intermittently provided along the Y-axis between two electric field relaxation regions 22 provided between adjacent shield regions 14 along the X-axis. The connection region 27 is in contact with the two electric field relaxation regions 22 and electrically connects the two electric field relaxation regions 22. For example, the upper end surface of the connection region 27 is flush with the upper end surface of the electric field relaxation region 22, and the lower end surface of the connection region 27 is flush with the lower end surface of the electric field relaxation region 22.

[0065] Other configurations of the third embodiment are the same as those of the first embodiment.

[0066] The same effects as those of the first embodiment can also be obtained by the third embodiment. According to the third embodiment, since the electric field relaxation region 22 is provided, the electric field concentration at the portion in contact with the bottom surface 4 of the gate trench 5 of the gate insulating film 81 can be relaxed. In addition, since current can flow between adjacent electric field relaxation regions 22, the on-resistance can be reduced more than in the second embodiment.

[0067] In the above-described embodiment, two gate trenches 5 are arranged along the X-axis between two adjacent contact holes 90 along the X-axis. However, the number of gate trenches 5 arranged between two adjacent contact holes 90 along the X-axis may be three or more. The number of potential control portions 82A included in the gate electrode 82 may also be three or more. Further, in the third embodiment, three or more electric field relaxation regions 22 may be arranged between two shield regions 14.

[0068] Although the embodiments have been described in detail above, the present disclosure is not limited to specific embodiments, and various modifications and changes are possible within the scope described in the claims.

Description of Reference Numerals

[0069] 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 5A First gate trench 5B Second Gate Trench 6 Trench Pairs 10 Silicon Carbide Substrate 11 Drift Region 11A First Region 11B Second Region 12 Body Region 13 Source Region 14 Shield Region 18 Contact Region 21, 22 Electric Field Relaxation Region 26, 27 Connection Region 31 Virtual Plane 40 Silicon Carbide Epitaxial Layer 50 Silicon Carbide Single Crystal Substrate 60 Source Electrode 61 Contact Electrode 62 Source Wiring 70 Drain Electrode 81 Gate Insulating Film 82 Gate Electrode 82A Potential Control Unit 82B Connection Unit 83 Interlayer Insulating Film 84 Barrier Metal Film 90 Contact Hole 90A First Contact Hole 90B Second Contact Hole 100, 200, 300 Silicon Carbide Semiconductor Devices θ1 Angle

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein the silicon carbide substrate has a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, and a plurality of gate trenches are provided on the first main surface, penetrating the source region and the body region and reaching the drift region, and having a side surface and a bottom surface continuous with the side surface; a gate insulating film in contact with the side surface and the bottom surface of the gate trench; a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the gate insulating film and the silicon carbide substrate; an interlayer insulating film covering the gate electrode and provided with a plurality of contact holes reaching the source region; a source electrode provided on the interlayer insulating film and in the contact holes and electrically connected to the source region, and the gate trench extends along a first axis parallel to the first main surface, in a plan view perpendicular to the first main surface, a plurality of first contact holes among the plurality of contact holes are arranged along a second axis perpendicular to the first axis, and a plurality of first gate trenches among the plurality of gate trenches are arranged along the second axis between two adjacent first contact holes along the second axis. A silicon carbide semiconductor device.

2. The silicon carbide semiconductor device according to claim 1, wherein the plurality of first contact holes are provided at a constant pitch along the second axis.

3. A shield region provided under the body region, in contact with the body region, and having the second conductivity type, wherein the shield region overlaps the first contact hole in the plan view. The silicon carbide semiconductor device according to claim 1 or claim 2.

4. The silicon carbide substrate is provided between the bottom surface of the plurality of first gate trenches and the second main surface, and has an electric field relaxation region having the second conductivity type. The silicon carbide semiconductor device according to claim 1 or claim 2.

5. The silicon carbide substrate is provided between the bottom surface and the second main surface for each of the plurality of first gate trenches, and has a plurality of electric field relaxation regions having the second conductivity type. The silicon carbide semiconductor device according to claim 1 or claim 2.

6. The gate electrode is a plurality of potential control parts each of which is in a plurality of the first gate trenches, a connecting part that connects adjacent ones of the potential control parts, The silicon carbide semiconductor device according to claim 1 or claim 2, which has

7. A plurality of the second contact holes among the plurality of the contact holes are arranged along the second axis, Among the plurality of the gate trenches, a plurality of the second gate trenches are arranged along the second axis between two adjacent ones of the second contact holes along the second axis, The plurality of the first contact holes and the plurality of the second contact holes are arranged along the first axis, The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the plurality of the first gate trenches and the plurality of the second gate trenches are arranged along the first axis.

8. The silicon carbide semiconductor device according to claim 7, wherein the first contact hole and the second contact hole are connected to each other.

9. In a cross-sectional view perpendicular to the first axis, an angle between a virtual plane including the bottom surface and the side surface is 45° or more and 65° or less. The silicon carbide semiconductor device according to claim 1 or claim 2.

10. The side surface of the gate trench includes a {0-33-8} plane. The silicon carbide semiconductor device according to claim 1 or claim 2.

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