Vertical field-effect transistor structure and method for producing vertical field-effect transistor structure
The vertical field effect transistor structure addresses non-uniform threshold voltage issues by adjusting doping profiles, achieving consistent performance and reduced resistance through controlled dopant gradients.
Patent Information
- Application Number
- JP2024218681
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-12-15
- Filing Date
- 2024-12-13
- Publication Date
- 2025-07-08
AI Technical Summary
Conventional FinMOS transistors exhibit non-uniform local threshold voltage due to varying fin width, leading to inconsistent transistor performance.
A vertical field effect transistor structure with adjustable doping profiles in the channel region to achieve a predetermined local threshold voltage profile along the depth of each fin structure, using ion implantation to control dopant gradients.
The solution ensures a uniform or controlled local threshold voltage across the fin structure, enhancing transistor performance and reducing on-resistance.
Smart Images
Figure 2025102704000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a vertical field effect transistor structure and a method for manufacturing the vertical field effect transistor structure.
Background Art
[0002] Figures 1a to 1d show a schematic cross-sectional view of a conventional FinMOS known to the applicant as internal prior art, as well as profiles of the charge density, fin width, and threshold voltage Uth of the attribution.
[0003] The conventional FinMOS schematically shown in Figure 1a includes a substrate wafer 10 having a first wafer surface 10a and a second wafer surface 10b facing opposite to the first wafer surface 10a. This FinMOS has a silicon carbide layer 12 that is epitaxially grown and n-type doped on the first wafer surface 10a. On the side of the silicon carbide layer 12 facing opposite to the substrate wafer 10, a fin structure 14 is structured from the silicon carbide layer 12, and the fin structure 14 fixed to the silicon carbide layer 12 is formed in a (substantially) strip shape. For each of the (substantially) strip-shaped fin structures 14, a longitudinal direction oriented parallel to the first wafer surface 10a can be defined, and in this longitudinal direction, the fin structure 14 has its maximum spread. The longitudinal direction of the fin structure 14 is that of the silicon carbide layer 12
[0004]
Number
[0005] It is typical to be directed perpendicular to. Each of the fin structures 14 has an n-type doped source region 16 at an end facing away from the substrate wafer 10. Further, each of the fin structures has a p-type doped channel region 18, and this channel region 18 is adjacent to the respective source region 16. There is a gate electrode 20 between two adjacent fin structures 14, and in this regard, a gate dielectric 22 electrically insulates the fin structure 14 and the silicon carbide layer 12 from the gate electrode 20. The conventional FinMOS shown in FIG. 1a further has a source electrode 24 disposed on the side of the fin structure 14 facing away from the substrate wafer 10 and a drain electrode 26 disposed on the second wafer surface 10b.
[0006] FIG. 1b shows the doping in the channel region 18. The doping or charge density LD in the channel region 18 is typically uniform in the vertical direction, that is, constant in the depth direction. This, in combination with the uniform FB width of the fins in the channel region 18, results in a uniform local threshold voltage Uth across the entire channel region 18 (that is, for example, within regions 18.1, 18.2, and 18.3) as shown in FIG. 1d. The threshold voltage or Threshold voltage Uth means the voltage value at which current just begins to flow through the channel of the FET.
[0007] However, the fin width FB is typically not uniform or constant, and generally, in the case of a conventional FinFET based on FIG. 2a, it increases vertically from top to bottom. This is shown by the profile of the fin width FB of the fin shown in FIG. 2c. In this case, the uniform dopant profile (see FIG. 2b) within the channel region 18 of the expanding fin of the conventional FinFET results in a non-uniform local threshold voltage Uth in the vertical direction of the channel region 18 as recognizable in FIG. 2d. Along with the gradually increasing fin width FB of the fin, as shown in FIG. 2d, the threshold voltage Uth also locally increases in the vertical direction or at the depth D. Therefore, the increasing fin width FB of the fin causes a non-uniform, gradually upwardly increasing local threshold voltage Uth across the channel region 18 of the expanding fin. Summary of the Invention Problems to be Solved by the Invention
[0008] The present invention provides a vertical field effect transistor structure having the features of claim 1 and a method of manufacturing a vertical field effect transistor structure having the features of claim 11. Means for Solving the Problems
[0009] Based on a first aspect, the present invention relates to a substrate having a first substrate surface, a semiconductor layer on the first substrate surface, and from this semiconductor layer, on a side opposite to the first substrate surface of the semiconductor layer, a plurality of fin structures fixed to a silicon carbide layer are structured, and source regions are respectively formed at ends of the fin structures opposite to the substrate, and the semiconductor layer, a plurality of gate electrodes, each of the gate electrodes being between two adjacent fin structures, and the fin structures and the semiconductor layer being electrically insulated from the gate electrodes by at least one gate dielectric, a vertical field effect transistor structure comprising the gate electrodes. On the side of the source region of the fin structure facing the substrate, there are doped channel regions, and the doping of this channel region is adjusted to provide a predetermined local threshold voltage profile along the depth of each fin structure, providing a vertical field effect transistor structure.
[0010] Based on a further aspect, the present invention is a method of manufacturing a vertical field effect transistor structure, comprising: forming a semiconductor layer on a first substrate surface of a substrate; structuring a plurality of fin structures fixed to the semiconductor layer from the semiconductor layer on the side of the semiconductor layer facing away from the first substrate surface, wherein source regions are respectively formed at the ends of the fin structures facing away from the substrate; forming a plurality of gate electrodes, wherein one of the gate electrodes is respectively disposed between two adjacent fin structures, and the fin structures and the semiconductor layer are electrically insulated from the gate electrodes by at least one gate dielectric; adjusting the doping of the channel regions on the side of the source regions of the respective fin structures facing the substrate to provide a predetermined local threshold voltage profile along the depth of each fin structure.
[0011] Preferred variants are the subject of the respective cited claims. Advantages of the present invention The core idea of the present invention is to cancel or enhance the change in the local threshold voltage caused by the change in the fin width of the fin in order to obtain a defined local threshold voltage profile along the depth of each fin structure. To cancel or enhance, an appropriate doping profile of the doping concentration or charge density in the channel region is useful.
[0012] In a preferred embodiment, the dopant gradient of the doping in the channel region of the fin structure is generated by ion implantation. Thereby, the doping profile in the channel region can be precisely adjusted.
[0013] In a possible embodiment of the vertical field effect transistor structure, the fin width of the fin structure increases with increasing depth. This can occur due to manufacturing. In a possible embodiment of the vertical field effect transistor structure, the semiconductor layer has a silicon carbide layer.
[0014] In a possible embodiment of the vertical field effect transistor structure, the silicon carbide layer is epitaxially grown on the substrate surface of the substrate. In a possible embodiment of the vertical field effect transistor structure, the channel region is p-type doped.
[0015] In an alternative possible embodiment of the vertical field effect transistor structure, the channel region is n-type doped. In a possible embodiment of the vertical field effect transistor structure, a predetermined local threshold voltage profile along the depth of each fin structure has a constant threshold voltage.
[0016] In a possible embodiment of the vertical field effect transistor structure, a predetermined local threshold voltage profile along the depth of each fin structure has a gradually increasing threshold voltage. This can be advantageous in the switch-on or off process of the transistor for specific application cases.
[0017] In a possible embodiment of the vertical field effect transistor structure, a predetermined local threshold voltage profile along the depth of each fin structure has a gradually decreasing threshold voltage. This can be advantageous in the switch-on or off process of the transistor for specific application cases.
[0018] In one possible embodiment of a vertical field effect transistor structure, the vertical field effect transistor structure includes one source electrode on the side of the fin structure facing away from the substrate and one drain electrode on the second substrate surface of the substrate facing away from the first substrate surface.
[0019] Thus, the multiple fin structures of the embodiment of the vertical field effect transistor structure described herein are electrically contacted by this (only one) source electrode, which results in the minimum on-resistance or on-resistance of the vertical field effect transistor structure realized in this way.
[0020] Further features and advantages of the present invention will be described below with reference to the drawings.
Brief Description of the Drawings
[0021]
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Embodiments for Carrying Out the Invention
[0022] Figure 3a shows a schematic diagram of a possible embodiment of a vertical field effect transistor structure. The vertical field effect transistor structure schematically shown in Figure 3a has a substrate 30 having a first substrate surface 30a and a second substrate surface 30b facing opposite to the first substrate surface 30a. The substrate 30 is preferably an n-type doped substrate 30, particularly a substrate 30 doped with n-type at a high concentration. The substrate 30 is preferably a (n-type doped / highly n-type doped) silicon carbide substrate 30.
[0023] On the first substrate surface 30a, a semiconductor layer 32, particularly a silicon carbide layer, is epitaxially grown so that the semiconductor layer 32 contacts the first substrate surface 30a of the substrate 30. The first substrate surface 30a is the
[0024]
Number
[0025] It can be inclined by an angle between 2° and 7° with respect to the (0001) crystal plane of the silicon carbide substrate 30 along. This ensures a relatively small crystal defect structure in the semiconductor layer 32, especially the silicon carbide layer 32, epitaxially grown on the first substrate surface 30a.
[0026] The epitaxially grown silicon carbide layer 32 serves as the drift zone of the vertical field effect transistor structure. Therefore, the silicon carbide layer 32 is preferably n-type doped, especially doped with n-type at a low concentration. On the side of the silicon carbide layer 32 opposite to the first substrate surface 30a, a large number of recesses 34 can be structured in the silicon carbide layer 32, so that a large number of fin structures 36 fixed to the silicon carbide layer 32 are structured from the silicon carbide layer 32. The minimum width of the recess 34 oriented parallel to the first substrate surface 30a is at least twice, preferably at least five times larger than the maximum width of the fin structure 36 oriented parallel to the first substrate surface 30a. The formation of the fin structure 36 as a "narrow-width" fin structure results in a high channel density and a minimum on-resistance or on-resistance of the thus formed vertical field effect transistor structure. For each of the fin structures 36, it is preferably possible to define a longitudinal direction oriented parallel to the first substrate surface 30a, and in this longitudinal direction, the fin structure 36 has its maximum spread. Especially, the longitudinal direction of the fin structure 36 is that of the silicon carbide layer 32
[0027]
Number
[0028] It can be oriented perpendicular thereto. It is preferable that n-type doped source regions 38 are respectively formed at the ends of the fin structures 36 facing away from the substrate 30. In particular, each of the n-type doped source regions 38 of the fin structures 36 can be a strongly n-type doped source region 38. On the side of the n-type doped source regions 38 of the fin structures 36 facing towards the substrate 30, there are respectively p-type doped channel regions 40 in the exemplary embodiments shown in FIGS. 3a to 3d.
[0029] In the vertical field effect transistor structure of FIG. 3a, although only one gate electrode 42 is shown, there may also be a plurality of gate electrodes 42. Each of the gate electrodes 42 is between two adjacent fin structures 36. In the vertical field effect transistor structure, at least one gate dielectric 44 is formed and / or deposited such that the fin structures 36 and the silicon carbide layer 32 are electrically insulated from the gate electrode 42 by at least one gate dielectric 44. When present, in particular, the n-type doped source regions 38 and / or the p-type doped channel regions 40 can be electrically insulated from the adjacent gate electrodes 42 by at least one gate dielectric 44.
[0030] In the embodiment shown in FIG. 3a, the FinFET has one source electrode 46 on the side of the fin structures 36 facing away from the substrate 30 and / or one drain electrode 48 on the second substrate surface 30b of the substrate 30 facing away from the first substrate surface 30a.
[0031] In the FinFET according to the present invention, there are respectively doped channel regions 40 on the sides of the source regions 38 of the fin structures 36 facing towards the substrate 30. The doping of the channel regions 40 is adjusted to provide a predetermined local threshold voltage profile in the longitudinal direction along the depth D of each fin structure 36.
[0032] Figures 3a to 3d show a first exemplary embodiment of a FinFET according to the present invention together with a profile of attribution. In the exemplary embodiment shown in Figures 3a to 3d, the fin width FB of the fin increases with the increasing depth D (Depth) as shown in Figure 3c. The channel region 40 is p-type doped in the exemplary embodiment shown in Figure 3. The doping charge density LD is schematically shown in Figure 3b. In order to provide a local threshold voltage profile with a constant threshold voltage Uth in the longitudinal direction (see Figure 3d), the doping of the channel region 40 is carried out so as to gradually decrease as can be seen in Figure 3b. The channel region 40 is formed by a p-type doping that gradually decreases with the increasing depth D. As the fins within the channel region 40 become wider, the p-type doping within the channel region 40 of the fins also decreases. If the dopant profile is appropriately selected, both effects can partially or completely cancel each other out, thereby achieving a uniform or constant profile of the resulting threshold voltage Uth across the fin in the longitudinal direction or along the depth D, as can be recognized in Figure 3d. The charge density of the p-type charge carriers is varied in the exemplary embodiments shown in Figures 3a to 3d so as to cancel out the threshold voltage change caused by the varying fin width FB. The dopant gradient can be easily generated by ion implantation in one possible embodiment.
[0033] Not only a longitudinally uniform or non-varying local threshold voltage Uth, i.e., a constant threshold voltage Uth in the longitudinal direction (such as that shown in Figure 3d), but also a controlled change in the threshold voltage Uth along the height of the fin can be advantageous, for example, for the switch-on or switch-off process of a transistor. However, the controllability of the threshold voltage Uth due to fin width variations resulting from the fin manufacturing process is limited. By an appropriate selection of the doping gradient within the channel region 40, the threshold voltage Uth in the FinFET according to the present invention can be locally and precisely adjusted.
[0034] In the exemplary embodiment shown in FIG. 4 of the FinFET, a higher variation of the threshold voltage Uth along the fin height or depth D, as shown in FIG. 4d, is achieved. In this case, in order to further enhance or strengthen the effect of the local threshold voltage increase due to the increase in the fin width FB (see FIG. 4c) (see FIG. 4d), the p-type charge density LD is selected to gradually increase in the vertical direction along with the increasing depth D (as shown in FIG. 4b).
[0035] Not only a gradually increasing or decreasing or constant local threshold voltage Uth, but also combining an increasing / decreasing threshold voltage Uth and a constant threshold voltage Uth within one fin is also possible by an appropriate selection of the dopant profile or the charge density LD of the dopant.
[0036] The same mechanism can also be utilized in a FinFET without p-type doping in the channel region. A FinFET as shown in FIG. 5a with a uniform n-type doping profile with a constant charge density LD shown in FIG. 5b has a lower local threshold voltage Uth in a spatially deeper and wider region of the fin (see FIG. 5c), as shown in FIG. 5d.
[0037] In the case where there is no p-type doping in the channel region 40, in the case of an increasing fin width FB, in a possible embodiment of the FinFET according to the present invention shown in FIG. 6a, the n-type doping or the charge density LD can also be changed so that a vertically uniform or non-changing local threshold voltage Uth, as shown in FIG. 6d, is achieved (see FIG. 6b).
[0038] The procedure according to the present invention can be applied not only to silicon carbide (SiC), but also to other power semiconductors, especially similar components based on GaN, gallium oxide, aluminum nitride, or diamond.
[0039] FIG. 7 shows a flowchart for the manufacture of a vertical field effect transistor according to a further aspect of the present invention. The manufacturing method according to the present invention includes a plurality of main steps S as shown in FIG. 7.
[0040] In a first step S1, a semiconductor layer 32 is provided on a first substrate surface 30a of a substrate 30. In one possible embodiment, the semiconductor layer 32 has silicon carbide (SiC) epitaxially grown on the first substrate surface 30a of the substrate 30.
[0041] In a further step S2, a number of fin structures 36 fixed to the semiconductor layer 32 are structured from the semiconductor layer 32 on a side of the semiconductor layer 32 facing away from the first substrate surface 30a, wherein source regions 38 are respectively formed at ends of the fin structures 36 facing away from the substrate 30.
[0042] For example, a strip-shaped starting structure can be structured from the semiconductor layer 32 by an anisotropic trench process. Alternatively or in addition to this removal method, this can include at least a thermal oxidation treatment of the strip-shaped starting structure and a subsequent etching process for etching the oxidized semiconductor layer 32.
[0043] In a further step S3, a number of gate electrodes 42 are formed, wherein one of the gate electrodes 42 is respectively arranged between two adjacent fin structures 36. The fin structures 36 and the semiconductor layer 32 are electrically insulated from the gate electrodes 42 by at least one formed gate dielectric 44.
[0044] A number of gate electrodes 42 can be formed together with the shaping of the fin structures 36, wherein each of the gate electrodes 42 is arranged between two adjacent fin structures 36. Prior to the formation of the number of gate electrodes 42, at least one gate dielectric 44 is deposited and / or formed such that the fin structures 36 and the silicon carbide layer 32 are electrically insulated from the gate electrodes 42 by at least one formed gate dielectric 44.
[0045] In a further step S4, the doping of the channel region 40 on the side of the source region 38 of each fin structure 36 facing towards the substrate 30 is adjusted to provide a predetermined local threshold voltage profile along the depth D of each fin structure 36.
[0046] The dopant gradient of the doping of the channel region 40 is preferably generated by ion implantation in one preferred embodiment. Optionally further, one source electrode 46 may be formed on the side of the fin structure 36 facing away from the substrate 30 and / or one drain electrode 48 may be formed on the second substrate surface 30b of the substrate 30 facing away from the first substrate surface 30a.
[0047] Thus, these fin structures 36 can be electrically contacted by only one source electrode 46. It is preferable that the vertical field effect transistor structure also includes one drain electrode 48 fixed to the second substrate surface 30b. The vertical field effect transistor structure may further have a p-type doped shielding region in one possible embodiment, but is not shown in FIGS. 3 to 6 for clarity.
[0048] The vertical field effect transistor structures illustrated in FIGS. 3 to 6 may be used, for example, as traction inverters, particularly in the electric power train within an EV / HEV, or as inverters. This vertical field effect transistor structure can be utilized in a number of devices, for example, home appliances, especially washing machines. It should be noted that the usability of this vertical field effect transistor structure is not limited to special fields of use.
Description of the reference numerals
[0049] 30 Substrate 30a First substrate surface 30b Second substrate surface 32 Semiconductor layer 34 Recess 36 Fin structure 38 Source region 40-channel region 42 Gate electrode 44 Gate dielectric 46 Source electrode 48 Drain electrode D Depth FB Fin width LD Charge density Uth Threshold voltage
Claims
1. A substrate (30) having a first substrate surface (30a), a semiconductor layer (32) on the first substrate surface (30a), and a plurality of fin structures (36) fixed to the semiconductor layer (32) on a side of the semiconductor layer (32) opposite to the first substrate surface (30a) are structured, and source regions (38) are respectively formed at ends of the fin structures (36) opposite to the substrate (30), the semiconductor layer (32), a plurality of gate electrodes (42), each of the gate electrodes (42) being between two adjacent fin structures (36), and the fin structures (36) and the semiconductor layer (32) being electrically insulated from the gate electrodes (42) by at least one gate dielectric (44), in a vertical field effect transistor structure including the gate electrodes (42), doped channel regions (40) are respectively on a side of the source regions (38) of the fin structures (36) directed toward the substrate (30), and the doping of the channel regions (40) is adjusted to provide a predetermined local threshold voltage profile along the depth (D) of each of the fin structures (36). A vertical field effect transistor structure characterized by the above.
2. The vertical field effect transistor structure according to claim 1, wherein the fin width (FB) of the fin structures (36) increases with an increasing depth (D).
3. The vertical field effect transistor structure according to claim 1 or 2, wherein the semiconductor layer (32) has a silicon carbide layer.
4. The vertical field effect transistor structure according to claim 3, wherein the silicon carbide layer is epitaxially grown on the first substrate surface (30a) of the substrate (30).
5. The vertical field effect transistor structure according to any one of claims 1 to 4, wherein the channel region (40) is p-type doped.
6. The vertical field effect transistor structure according to any one of claims 1 to 4, wherein the channel region (40) is n-type doped.
7. The vertical field effect transistor structure according to any one of claims 1 to 6, wherein the predetermined local threshold voltage profile along the depth (D) of each of the fin structures (36) has a constant threshold voltage (Uth).
8. The vertical field effect transistor structure according to any one of claims 1 to 6, wherein the predetermined local threshold voltage profile along the depth (D) of each of the fin structures (36) has a threshold voltage (Uth) that gradually increases.
9. The vertical field effect transistor structure according to any one of claims 1 to 6, wherein the predetermined local threshold voltage profile along the depth (D) of each of the fin structures (36) has a threshold voltage (Uth) that gradually decreases.
10. The vertical field effect transistor structure according to any one of claims 1 to 9, wherein the vertical field effect transistor structure includes one source electrode (46) on a side of the fin structure (36) facing away from the substrate (30), and one drain electrode (48) on a second substrate surface (30b) of the substrate (30) facing away from the first substrate surface (30a).
11. A method for manufacturing a vertical field effect transistor structure, a step (S1) of applying a semiconductor layer (32) on a first substrate surface (30a) of a substrate (30); a step (S2) of structuring a plurality of fin structures (36) fixed to the semiconductor layer (32) from the semiconductor layer (32) on a side of the semiconductor layer (32) facing away from the first substrate surface (30a), wherein source regions (38) are formed at ends of the fin structures (36) facing away from the substrate (30), step (S2); a step (S3) of forming a plurality of gate electrodes (42), wherein one of the gate electrodes (42) is disposed between two adjacent fin structures (36), and the fin structures (36) and the semiconductor layer (32) are electrically insulated from the gate electrode (42) by at least one gate dielectric (44), step (S3); a step (S4) of adjusting the doping of a channel region (40) on a side of the source region (38) of each of the fin structures (36) facing the substrate (30) to provide a predetermined local threshold voltage profile along the depth (D) of each of the fin structures (36); A method having.
12. The method according to claim 11, wherein the dopant gradient of the doping of the channel region (40) is generated by ion implantation.
13. The method according to claim 11 or 12, wherein the semiconductor layer (32) has silicon carbide epitaxially grown on the first substrate surface (30a) of the substrate (30).
14. The method according to any one of claims 11 to 13, wherein the channel region (40) is p-type doped.
15. The method according to any one of claims 11 to 13, wherein the channel region (40) is n-type doped.