Semiconductor device

Abstract

To provide a semiconductor device in which the parasitic capacitance near a transistor is reduced, and a manufacturing method for the same.SOLUTION: A transistor 10 includes a first insulating layer 110, a first oxide semiconductor layer 121 thereon, a second oxide semiconductor layer 122 thereon, a source electrode layer 130 and a drain electrode layer 140 thereon, a second insulating layer 170 on the first insulating layer, the source electrode layer, and the drain electrode layer, a third insulating layer 175 thereon, a third oxide semiconductor layer 123 on the second oxide semiconductor layer, a gate insulating layer 150 thereon, and a gate electrode layer 160 thereon. The second insulating layer is an oxygen barrier layer and includes a region in contact with side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The third oxide semiconductor layer includes a region in contact with side surfaces of the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, and their driving methods, or their manufacturing methods. In particular, one aspect of the present invention relates to a semiconductor device or a method for manufacturing the same.

[0002] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a storage device, a display device, and an electronic device may have a semiconductor device.

Background Art

Background Art

[0003] Techniques for constructing a transistor using a semiconductor film formed on a substrate having an insulating surface have been attracting attention. Such a transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials. For example, Patent Document 1 discloses a transistor using an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor.

Prior Art Documents

Prior Art Documents

[0004] For example, a transistor using an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor is disclosed in Patent Document 1.

Patent Documents

Patent Documents

Patent Documents

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] As semiconductor elements become smaller, parasitic capacitance near transistors becomes a major problem.

[0007] In transistor operation, the area near the channel (for example, between the source electrode and the drain electrode) If parasitic capacitance is present, it takes time for the parasitic capacitance to charge, which slows down the transistor response. This reduces the performance and thus the response of the semiconductor device.

[0008] In addition, the various processes for forming transistors (especially film formation, processing, etc.) It is becoming increasingly difficult to control this, and variations in the manufacturing process can affect transistor characteristics, and even has a significant impact on reliability.

[0009] In addition, as miniaturization progresses, pattern formation becomes difficult due to the resolution limit of exposure equipment, and Problems have also arisen in the manufacturing of transistors, and the costs of capital investment are becoming enormous.

[0010] Therefore, one aspect of the present invention has an object to reduce parasitic capacitance in the vicinity of a transistor. Another object is to provide a semiconductor device having good electrical characteristics. Another object of the present invention is to provide a semiconductor device having high reliability. To provide a method for manufacturing a transistor or semiconductor device that allows for pattern formation below the resolution limit Alternatively, the present invention aims to prevent a problem that occurs during the manufacturing process of a transistor or a semiconductor device. One of the objectives is to reduce the variation in the resulting characteristics. Or, one of the objectives is to provide a semiconductor device having an oxide semiconductor layer with less oxygen deficiency. Or, one of the objectives is to provide a semiconductor device that can be formed in a simple process. Or, one of the objectives is to provide a semiconductor device having a configuration capable of reducing interface levels near the oxide semiconductor layer. Or, one of the objectives is to provide a semiconductor device with low power consumption. Also, one of the objectives is to provide a method for manufacturing a novel semiconductor device with reduced development costs. Or, one of the objectives is to provide a novel semiconductor device or the like. Or, one of the objectives is to provide a method for manufacturing the above semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will naturally become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011]

[0012] ​​​​​​​​​​​​, and the second insulating layer is an oxygen barrier layer, and has a region in contact with the side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and the third oxide semiconductor layer has a region in contact with the side surfaces of the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer, and is a semiconductor device characterized by the above.

[0013] Another aspect of the present invention is a first insulating layer, a first oxide semiconductor layer on the first insulating layer, and a first second oxide semiconductor layer on the first oxide semiconductor layer, a source electrode layer and a drain electrode layer on the second oxide semiconductor layer, a first conductive layer and a second conductive layer having a region in contact with the side surface of the second oxide semiconductor layer, a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer, a third insulating layer on the second insulating layer, a third oxide semiconductor layer on the second oxide semiconductor layer, a gate insulating layer on the third oxide semiconductor layer, and a gate electrode layer on the gate insulating layer, and the second insulating layer is an oxygen barrier layer, and the first electrode layer and the second electrode layer are in contact with the second insulating layer at the side portions, and the third oxide semiconductor layer has a region in contact with the side portions of the first insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer, and is a semiconductor device characterized by the above. Another aspect of the present invention is a first insulating layer, a first oxide semiconductor layer on the first insulating layer, and a first second oxide semiconductor layer on the first oxide semiconductor layer, a source electrode layer and a drain electrode layer on the second oxide semiconductor layer, a first insulating layer, the source electrode layer, and a second insulating layer on the drain electrode layer, and is a semiconductor device characterized by the above.

[0014] Another aspect of the present invention is a first insulating layer, a first oxide semiconductor layer on the first insulating layer, and a first second oxide semiconductor layer on the first oxide semiconductor layer, a source electrode layer and a drain electrode layer on the second oxide semiconductor layer, a first insulating layer, the source electrode layer, and a second The second insulating layer, the third insulating layer on the second insulating layer, on the source electrode layer and the drain electrode layer and a fourth insulating layer formed in contact with the side surfaces of the second insulating layer and the third insulating layer and a third oxide semiconductor layer on the second oxide semiconductor layer, and a gate insulating layer on the third oxide semiconductor layer, and a gate electrode layer on the gate insulating layer, and the second insulating layer is an oxygen barrier layer which has a region in contact with the side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and the third oxide semiconductor layer has a region in contact with the side surfaces of the first insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, and the fourth insulating layer, and is a semiconductor device characterized by this.

[0015] Also, it is preferable to use an aluminum oxide layer as the second insulating layer.

[0016] Another aspect of the present invention is a first conductive layer, a first insulating layer on the first conductive layer, and a first insulating layer, a first oxide semiconductor layer on the layer, a second oxide semiconductor layer on the first oxide semiconductor layer, and a second source electrode layer and a drain electrode layer on the oxide semiconductor layer, a first insulating layer, a source electrode layer, and a second insulating layer on the drain electrode layer, a third insulating layer on the second insulating layer, and a second third oxide semiconductor layer on the oxide semiconductor layer, a gate insulating layer on the third oxide semiconductor layer, a gate electrode layer on the gate insulating layer, a third insulating layer, a third oxide semiconductor layer, a gate insulating layer, and a fourth insulating layer on the gate electrode layer, and the second insulating layer is an oxygen barrier layer which is in contact with the side portions of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and the third oxide semiconductor layer is the first insulating layer, the first oxide semiconductor A tomographic layer, a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, a second insulating layer, and a third insulating layer having a region in contact with a side surface of a side surface, and the fourth insulating layer is an oxygen barrier layer, characterized in that it is a semiconductor device.

[0017] Also, it is preferable to use an aluminum oxide film as the second insulating layer and the fourth insulating layer.

[0018] Another aspect of the present invention is to form a first insulating layer, form a first oxide semiconductor film on the first insulating layer, form a second oxide semiconductor film on the first oxide semiconductor film, perform a first heat treatment, form a first conductive film on the second oxide semiconductor film, and etch a part of the first oxide semiconductor film and the second oxide semiconductor film using the first mask and the first conductive film, thereby forming the first oxide semiconductor layer and the second oxide semiconductor layer in an island shape, forming a second insulating layer on the first insulating layer and the first conductive film, forming a mixed layer of the first insulating layer and the second insulating film when forming the second insulating layer, and at the same time adding oxygen to the mixed layer or the first insulating layer, performing a second heat treatment, diffusing oxygen into the second oxide semiconductor layer, forming a third insulating film on the second insulating layer, performing a planarization treatment on the third insulating layer to form the third insulating layer, selectively etching the third insulating layer and the second insulating layer using a second mask, and selectively etching the first conductive film using the second mask and the second insulating layer, thereby forming a source electrode layer and a drain electrode layer, forming a third oxide semiconductor film on the third insulating layer and the second oxide semiconductor layer, forming a fourth insulating film on the third oxide semiconductor film, forming a second conductive film on the fourth insulating film, and the second conductive film, the third insulating film, and the third oxide semiconductor layer, forming a fourth insulating film on the third oxide semiconductor film, forming a second conductive film on the fourth insulating film, forming a fourth insulating film on the third oxide semiconductor film, forming a second conductive film on the fourth insulating film, forming a second conductive film, a third insulating film, and a ​By performing a chemical mechanical polishing process on the oxide semiconductor film of 3, a third oxide semiconductor layer, forming a gate insulating layer and a gate electrode layer, which is a method for manufacturing a semiconductor device. There is.

[0019] Another aspect of the present invention is to form a first insulating layer, and form a first oxide semiconductor film on the first insulating layer form a second oxide semiconductor film on the first oxide semiconductor film, and perform a first heat treatment form a first conductive film on the second oxide semiconductor film, and selectively etch the first oxide semiconductor film and the second oxide semiconductor film using the first mask and the first conductive film, thereby forming the first oxide semiconductor layer and the second oxide semiconductor layer in an island shape, and forming a second insulating film on the first insulating layer and the first conductive film, forming a mixed layer of the first insulating layer and the second insulating film when forming the second insulating film, adding oxygen to the mixed layer or the first insulating layer, performing a second heat treatment, diffusing oxygen into the second oxide semiconductor layer, reducing oxygen deficiency in the second oxide semiconductor layer, forming a third insulating film on the second insulating film, performing a planarization treatment on the third insulating film, and etching a part of the third insulating film and the second insulating film using the second mask to form a third insulating layer and a second insulating layer, forming a fourth insulating film on the first conductive layer and the third insulating layer, and forming a fourth insulating layer in contact with the side surfaces of the second insulating layer and the third insulating layer by anisotropic etching, and using the fourth insulating layer as a mask etching a part of the first conductive film to form source electrodes and drain electrodes forming a third oxide semiconductor film on the third insulating layer and the second oxide semiconductor layer, forming a fifth insulating film on the third oxide semiconductor film, and forming a second conductive film on the fifth insulating film forming a fourth insulating film on the first conductive layer and the third insulating layer, and forming a fourth insulating layer in contact with the side surfaces of the second insulating layer and the third insulating layer by anisotropic etching, and using the fourth insulating layer as a mask to form source electrodes and drain electrodes, forming a third oxide semiconductor film on the third insulating layer and the second oxide semiconductor layer, forming a fifth insulating film on the third oxide semiconductor film, and forming a second conductive film on the fifth insulating film etching a part of the first conductive film to form source electrodes and drain electrodes, forming a third oxide semiconductor film on the third insulating layer and the second oxide semiconductor layer, forming a fifth insulating film on the third oxide semiconductor film, and forming a second conductive film on the fifth insulating film forming a third oxide semiconductor film on the third insulating layer and the second oxide semiconductor layer, forming a fifth insulating film on the third oxide semiconductor film, and forming a second conductive film on the fifth insulating film forming a third oxide semiconductor film on the third insulating layer and the second oxide semiconductor layer, forming a fifth insulating film on the third oxide semiconductor film, and forming a second conductive film on the fifth insulating film Perform chemical mechanical polishing on the second conductive film, the third insulating film, and the third oxide semiconductor film to form a third oxide semiconductor layer, a gate insulating layer, and a gate electrode layer , which is a method for manufacturing a semiconductor device.

[0020] Also, it is preferable to form the second insulating film by a sputtering method using oxygen gas .

[0021] Also, the second insulating film is preferably formed on the silicon oxide film by a sputtering method using an aluminum oxide target under the condition of having 50% by volume or more of oxygen.

[0022] Also, it is preferable to perform the second heat treatment at 300°C or higher and 450°C or lower.

[0023] Also, a configuration using a semiconductor device, a microphone, a speaker, and a housing can be adopted.

Advantages of the Invention

[0024] By using one aspect of the present invention, the parasitic capacitance near the transistor can be reduced . Or, a semiconductor device with good electrical characteristics can be provided. Or, a highly reliable semiconductor device can be provided. Or, a transistor capable of forming a pattern below the resolution limit of an exposure apparatus, or a method for manufacturing a semiconductor device can be provided. Or, the variation in characteristics caused by the manufacturing process of a transistor or a semiconductor device can be reduced . Or, a semiconductor device having an oxide semiconductor layer with less oxygen deficiency can be provided . Or, a semiconductor device that can be formed by a simple process can be provided . Or, a semiconductor device configured to reduce the interface states near the oxide semiconductor layer can be provided . Or, a semiconductor device that can be formed by a simple process can be provided. Or, a semiconductor device having a configuration capable of reducing the interface states near the oxide semiconductor layer can be provided It can be used. Or, a semiconductor device with low power consumption can be provided. Also, A method for manufacturing a novel semiconductor device with reduced development costs can be provided. Or, a novel semi- conductor device or the like can be provided. Or, a method for manufacturing the above semiconductor device can be provided. It can be done.

[0025] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be obvious from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0026]

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Embodiments for Carrying Out the Invention

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and the repeated description thereof may be omitted. In addition, the matching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings.

[0028] ​​​​​​ For example, in this specification and the like, in the case where it is explicitly described that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in a figure or text, and those other than the connection relationship shown in the figure or text are also regarded as those described in the figure or text.

[0029] Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0030] As an example of the case where X and Y are directly connected, an element (for example, a switch, transistor, capacitor element, inductor, resistor element, diode, display element, light-emitting element, load, etc.) that enables an electrical connection between X and Y is not connected between X and Y, and X and Y are connected without passing through an element (for example, a switch, transistor, capacitor element, inductor, resistor element, diode, display element, light-emitting element, load, etc.) that enables an electrical connection between X and Y. As an example of the case where X and Y are electrically connected, one or more elements (for example, a switch, transistor, capacitor element, inductor, resistor element, diode, display element, light-emitting element, load, etc.) that enable an electrical connection between X and Y can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch becomes a conductive state (on state) or a non-conductive state (off state) to allow current to flow or not.

[0031] As an example of the case where X and Y are electrically connected, one or more elements (for example, a switch, transistor, capacitor element, inductor, resistor element, diode, display element, light-emitting element, load, etc.) that enable an electrical connection between X and Y can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch becomes a conductive state (on state) or a non-conductive state (off state) to allow current to flow or not. not, respectively.​​​​​​ It has a function of controlling whether current flows. Or, the switch has a function of selecting and switching the path through which current flows. When X and Y are electrically connected, it shall include the case where X and Y are directly connected.

[0032] As an example of the case where X and Y are functionally connected, a circuit that enables the functional connection between X and Y (for example, a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (such as a DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (such as a boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, such as an operational amplifier, differential amplification circuit, source follower circuit, buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) can be connected with one or more between X and Y. Even if there is another circuit between X and Y as an example, when the signal output from X is transmitted to Y, X and Y shall be regarded as functionally connected. When X and Y are functionally connected, it shall include the case where X and Y are directly connected and the case where X and Y are electrically connected.

[0033] When it is explicitly described that X and Y are electrically connected, the case where X and Y are electrically connected (that is, the case where they are connected with another element or another circuit sandwiched between X and Y), the case where X and Y are functionally connected (that is, the case where they are functionally connected with another circuit sandwiched between X and Y), and the case where X and Y are directly connected The case (i.e., the case where they are connected without another element or another circuit being interposed between X and Y) and shall be as disclosed in this specification and the like. That is, when it is explicitly described that they are electrically connected, it is merely described that they are connected when it is explicitly described in the same manner as in this specification and the like.

[0034] Note that, for example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X with (or without) passing through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y with (or without) passing through Z 2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows

[0035] For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and they are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." ​​​​​It can be expressed as "」. Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By using the same expression methods as these examples to define the connection order in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Or, as another expression method, for example, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first connection path, the first connection path does not have the second connection path, the second connection path is the path between the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor via the transistor, the first connection path is the path via Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third connection path, the third connection path does not have the second connection path, and the third connection path is the path via Z2." It can be expressed as such. Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via Z1 through at least the first connection path, the first connection path does not have the second connection path, the second connection path has the connection path via the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via Z2 through at least the third connection path."

[0036] ​​​​​​​​​​​​​​​​ is connected in terms of qi, and the third connection path does not have the second connection path.」 expression can be done. Or, 「The source of the transistor (or the first terminal, etc.) is at least electrically connected to X via Z1 by at least the first electrical path, and the first electrical path does not have a second electrical path, and the second electrical path is from the source of the transistor (or the first terminal, etc.) to the drain of the transistor (or the second terminal, etc.) electrical path, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y via Z2 by at least the third electrical path, and the third electrical path does not have a fourth electrical path, and the fourth electrical path is from the drain of the transistor (or the second terminal, etc.) to the source of the transistor (or the first terminal, etc.) electrical path.」 can be expressed. Using the same expression method as these examples, by defining the connection paths in the circuit configuration it is possible to distinguish between the source of the transistor (or the first terminal etc.) and the drain (or the second terminal, etc.) and determine the technical scope can be done.

[0037] Note that these expression methods are just examples and are not limited to these expression methods. Here, X , Y, Z1, Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0038] Note that even if components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of a plurality of components combined. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of the wiring and and​ It has the functions of both components of the electrode function. Therefore, the electrical connection in this specification also includes a case where one conductive film has the functions of a plurality of components. It is also included in that category.

[0039] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same part or parts having the same function, and the repeated description thereof will be omitted.

[0040] <Supplementary Note Regarding Description of Drawings> In this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0041] Also, the terms "above" and "below" do not limit that the positional relationship between components is directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be directly formed in contact with insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0042] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. refers to the state where it is. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially flat" "parallel" refers to the state where two straight lines are arranged at an angle of -30° or more and 30° or less. Also "perpendicular" refers to the state where two straight lines are arranged at an angle of 80° or more and 100° or less . Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" refers to two straight lines being arranged at an angle of 60° or more and 120° or less

[0043] Also, in this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system .

[0044] Also, in the drawings, the size, layer thickness, or area is shown in an arbitrary size for the convenience of explanation . Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity and are not limited to the shapes or values shown in the drawings

[0045] Also, in the drawings, in the top view (also called a plan view or layout view) or perspective view, etc., for the clarity of the drawings, the description of some components may be omitted

[0046] Also, "identical" may have the same area or the same shape. Also, due to the relationship of the manufacturing process , it is assumed that it may not be completely the same shape, so even if it is substantially the same it can be rephrased as being the same

[0047] <Supplementary Note Regarding Rephrasable Descriptions> In this specification, etc., when explaining the connection relationship of transistors, one of the source and drain is expressed as "one of the source or drain" (or the first electrode, or the first terminal), and the source and The other side with respect to the drain is referred to as "the other side of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of a transistor can change depending on the structure or operating conditions, etc., of the transistor. Regarding the naming of the source and drain of a transistor, it can be appropriately rephrased according to the situation, such as the source (drain) terminal, the source (drain) electrode, etc.

[0048] Also, in this specification, etc., the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0049] Also, in this specification, etc., a transistor is an element having at least three terminals including a gate, a drain, and a source. And there is a channel region between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current can flow through the drain, the channel region, and the source.

[0050] Here, since the source and drain can change depending on the structure or operating conditions, etc., of the transistor, it is difficult to limit which is the source or the drain. Therefore, instead of calling the part that functions as the source and the part that functions as the drain the source or the drain, one of the source and the drain may be denoted as the first electrode, and the other of the source and the drain may be denoted as the second electrode.

[0051] ​​​​​​​​​In addition, the ordinal numbers "first", "second", and "third" used in this specification are attached to avoid confusion of components, and it should be noted that they are not numerically limiting. It should be noted that they are not numerically limiting.

[0052] In addition, in this specification and the like, for a substrate of a display panel, for example, one with an FPC (Flexible Printed Circuits) or a TCP (Tape Carrier Package) attached, or one with an IC (integrated circuit) directly mounted by the COG (Chip On Glass) method may be referred to as a display device. nted Circuits) or a TCP (Tape Carrier Packa ge) attached, or one with an IC (integrated circuit) directly mounted on the substrate by the COG (Chip On Glass) method may be referred to as a display device.

[0053] In addition, the terms "film" and "layer" may be interchangeable depending on the case or situation. For example, the term "conductive layer" may be changed to the term "conductive film". For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0054] <Supplementary Note on Definition of Terms> Hereinafter, the definition of each term in this specification and the like will be described.

[0055] In this specification, when the terms "trench" or "groove" are used, they refer to a narrow strip-shaped depression. They refer to a narrow strip-shaped depression.

[0056] In addition, in this specification, when indicating silicon oxynitride as a film, it may be described as SiOxNy. At this time, x and y may be natural numbers or numbers with a decimal point. At this time, x and y may be natural numbers or numbers with a decimal point.

[0057] <Regarding Connection> In this specification, when it is stated that A and B are connected, it means that A and B are directly connected. In addition, it shall include those that are electrically connected. Here, when A and B are electrically connected, it means that when there is an object having some electrical effect between A and B, it enables the transfer of electrical signals between A and B. Here, when A and B are electrically connected, it means that when there is an object having some electrical effect between A and B, it enables the transfer of electrical signals between A and B. Here, when A and B are electrically connected, it means that when there is an object having some electrical effect between A and B, it enables the transfer of electrical signals between A and B.

[0058] Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0059] Note that the content described in one embodiment (even some of the content) can be applied, combined, or replaced with the content described in another part of that embodiment (even some of the content), and / or the content described in one or more other embodiments (even some of the content). Note that the content described in one embodiment (even some of the content) can be applied, combined, or replaced with the content described in another part of that embodiment (even some of the content), and / or the content described in one or more other embodiments (even some of the content). Note that the content described in one embodiment (even some of the content) can be applied, combined, or replaced with the content described in another part of that embodiment (even some of the content), and / or the content described in one or more other embodiments (even some of the content). Note that the content described in one embodiment (even some of the content) can be applied, combined, or replaced with the content described in another part of that embodiment (even some of the content), and / or the content described in one or more other embodiments (even some of the content).

[0060] Note that the content described in the embodiments refers to the content described using various figures in each embodiment, or the content described using the text described in the specification. Note that the content described in the embodiments refers to the content described using various figures in each embodiment, or the content described using the text described in the specification.

[0061] Note that the figure (even a part of it) described in one embodiment can be combined with another part of that figure, another figure (even a part of it) described in that embodiment, and / or the figure (even a part of it) described in one or more other embodiments to form more figures. Note that the figure (even a part of it) described in one embodiment can be combined with another part of that figure, another figure (even a part of it) described in that embodiment, and / or the figure (even a part of it) described in one or more other embodiments to form more figures. Note that the figure (even a part of it) described in one embodiment can be combined with another part of that figure, another figure (even a part of it) described in that embodiment, and / or the figure (even a part of it) described in one or more other embodiments to form more figures. Note that the figure (even a part of it) described in one embodiment can be combined with another part of that figure, another figure (even a part of it) described in that embodiment, and / or the figure (even a part of it) described in one or more other embodiments to form more figures.

[0062] (Embodiment 1) In this embodiment, a semiconductor device of one aspect of the present invention and its manufacturing method will be described with reference to the drawings. In this embodiment, a semiconductor device of one aspect of the present invention and its manufacturing method will be described with reference to the drawings.

[0063] Figures 1(A), 1(B), and 1(C) are top views and cross-sectional views of the transistor 10 according to one aspect of the present invention. Figure 1(A) is a top view, Figure 1(B) is a cross-sectional view taken along the dashed line A1-A2 shown in Figure 1(A), and Figure 1(C) is a cross-sectional view taken along A3-A4. In Figure 1(A), some elements are enlarged, reduced, or omitted for clarity of the drawing. Also, the direction of the dashed line A1-A2 is sometimes referred to as the channel length direction, and the direction of the dashed line A3-A4 is sometimes referred to as the channel width direction.

[0064] The transistor 10 includes a substrate 100, an insulating layer 110, an oxide semiconductor layer 121, an oxide semiconductor layer 122, an oxide semiconductor layer 123, a source electrode layer 130, a drain electrode layer 1 40, a gate insulating layer 150, a gate electrode layer 160, an insulating layer 170, and an insulating layer 175 . The insulating layer 110 is formed on the substrate 100. The oxide semiconductor layer 121 is formed on the insulating layer 110. The oxide semiconductor layer 122 is formed on the oxide semiconductor layer 121 . The source electrode layer 130 and the drain electrode layer 140 are formed on the oxide semiconductor layer 122 and are electrically connected to the oxide semiconductor layer 122. The insulating layer 170 is formed on the insulating layer 110 , the source electrode layer 130, and the drain electrode layer 140, and is in contact with the side surfaces of the oxide semiconductor layer 121 and the oxide semiconductor layer 122. The insulating layer 175 is formed on the insulating layer 170 and is in contact with the oxide semiconductor layer 123 at the side surface . The oxide semiconductor layer 123 is formed on the oxide semiconductor layer 1 22. Also, the oxide semiconductor layer 123 is in contact with the side surfaces of the insulating layer 170, the insulating layer 175 , the side surface of the source electrode layer 130, and the side surface of the drain electrode layer 140. The gate insulating layer 150 is formed on the oxide semiconductor layer 123. The gate electrode layer 160 is formed on the gate​​ It is formed on the gate insulating layer 150.

[0065] In FIG. 1(B), although a single-layer example of the gate electrode layer 160 is illustrated, it may be a stack of the gate electrode layer 161 and the gate electrode layer 162 described later. The ends of the oxide semiconductor layer 123 and the gate insulating layer 150 included in the transistor 10 are located outside the gate electrode layer 160. Further, in the structure described above, since the oxide semiconductor layer 122 and the oxide semiconductor layer 123 are in contact with the source electrode layer 130 and the drain electrode layer 140, it has a high heat dissipation effect against the heat generated in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 during the operation of the transistor 10. It may be a stack of the gate electrode layer 161 and the gate electrode layer 162. The ends of the oxide semiconductor layer 123 and the gate insulating layer 150 included in the transistor 10 are located outside the gate electrode layer 160. Further, in the structure described above, since the oxide semiconductor layer 122 and the oxide semiconductor layer 123 are in contact with the source electrode layer 130 and the drain electrode layer 140, it has a high heat dissipation effect against the heat generated in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 during the operation of the transistor 10. It is located outside the gate electrode layer 160. Further, in the structure described above, since the oxide semiconductor layer 122 and the oxide semiconductor layer 123 are in contact with the source electrode layer 130 and the drain electrode layer 140, it has a high heat dissipation effect against the heat generated in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 during the operation of the transistor 10. In addition, in the structure described above, since the oxide semiconductor layer 122 and the oxide semiconductor layer 123 are in contact with the source electrode layer 130 and the drain electrode layer 140, it has a high heat dissipation effect against the heat generated in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 during the operation of the transistor 10. Further, in the structure described above, since the oxide semiconductor layer 122 and the oxide semiconductor layer 123 are in contact with the source electrode layer 130 and the drain electrode layer 140, it has a high heat dissipation effect against the heat generated in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 during the operation of the transistor 10. During the operation of the transistor 10, it has a high heat dissipation effect against the heat generated in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123. It has the characteristic of high heat dissipation effect against the heat generated in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 during the operation of the transistor 10.

[0066] Also, when forming the second insulating film that becomes the insulating layer 170 of the transistor 10, a mixed layer having the material of the insulating layer 110 and the material of the second insulating film, and the gas used during the formation of the second insulating film is formed at the interface with the insulating layer 110, and oxygen (excess oxygen, referred to as exO) is added to the mixed layer or the insulating layer 110. Further, by performing a heat treatment, the oxygen diffuses to the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and the oxygen can fill the oxygen vacancies existing in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. Thereby, transistor characteristics (for example, threshold value, reliability, etc.) can be improved. A mixed layer having the material of the insulating layer 110 and the material of the second insulating film, and the gas used during the formation of the second insulating film is formed at the interface with the insulating layer 110, and oxygen (excess oxygen, referred to as exO) is added to the mixed layer or the insulating layer 110. Further, by performing a heat treatment, the oxygen diffuses to the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and the oxygen can fill the oxygen vacancies existing in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. Thereby, transistor characteristics (for example, threshold value, reliability, etc.) can be improved. A mixed layer having the material of the insulating layer 110 and the material of the second insulating film, and the gas used during the formation of the second insulating film is formed at the interface with the insulating layer 110, and oxygen (excess oxygen, referred to as exO) is added to the mixed layer or the insulating layer 110. Further, by performing a heat treatment, the oxygen diffuses to the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and the oxygen can fill the oxygen vacancies existing in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. Thereby, transistor characteristics (for example, threshold value, reliability, etc.) can be improved. A mixed layer having the material of the insulating layer 110 and the material of the second insulating film, and the gas used during the formation of the second insulating film is formed at the interface with the insulating layer 110, and oxygen (excess oxygen, referred to as exO) is added to the mixed layer or the insulating layer 110. Further, by performing a heat treatment, the oxygen diffuses to the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and the oxygen can fill the oxygen vacancies existing in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. Thereby, transistor characteristics (for example, threshold value, reliability, etc.) can be improved. By further performing a heat treatment, the oxygen diffuses to the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and the oxygen can fill the oxygen vacancies existing in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. Thereby, transistor characteristics (for example, threshold value, reliability, etc.) can be improved. By further performing a heat treatment, the oxygen diffuses to the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and the oxygen can fill the oxygen vacancies existing in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. Thereby, transistor characteristics (for example, threshold value, reliability, etc.) can be improved. Thereby, transistor characteristics (for example, threshold value, reliability, etc.) can be improved.

[0067] The excess oxygen added during the formation of the second insulating film exists in various states, such as oxygen radicals, oxygen ions, or oxygen atoms, due to the influence of factors such as the voltage, power, plasma, or substrate temperature applied during the film formation by, for example, sputtering method. At this time, the excess oxygen The excess oxygen added during the formation of the second insulating film exists in various states, such as oxygen radicals, oxygen ions, or oxygen atoms, due to the influence of factors such as the voltage, power, plasma, or substrate temperature applied during the film formation by, for example, sputtering method. At this time, the excess oxygen The excess oxygen added during the formation of the second insulating film exists in various states, such as oxygen radicals, oxygen ions, or oxygen atoms, due to the influence of factors such as the voltage, power, plasma, or substrate temperature applied during the film formation by, for example, sputtering method. At this time, the excess oxygen is a state having more energy than the stable state and can enter into the insulating layer 110. It can be done.

[0068] Note that the method of adding oxygen is not limited to the above method, and the insulating layer 110 may have the excess oxygen during film formation, or may use another method (for example, ion implantation method, ion plasma immersion method, etc.) after film formation. It may have excess oxygen during film formation, or may use another method (for example, ion implantation method, ion plasma immersion method, etc.) after film formation. It may be used.

[0069] As shown in the cross-sectional view of FIG. 1(C) A3 - A4, in the channel width direction, the gate electrode layer 160 faces the side surfaces of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 through the gate insulating layer 150. That is, when a gate voltage is applied to the gate electrode layer 160, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of the transistor in which the semiconductor layer is surrounded by the electric field of the gate electrode layer 160 is called a surrounded channel (s-channel) structure. Also, since the transistor 10 can form the gate electrode, the source electrode, and the drain electrode by using a groove in a cell array, it has excellent alignment accuracy and can easily fabricate a fine transistor. Such a structure is called a self-align s-channel FET (Self Align s-channel FET, SA s-channel FET) structure, or a trench gate s-channel FET (Trench gate s-channel FET), or a TGSA FET (Trench Gate Self Align) structure, or a GLSA FET (Gate Last Self Align FET). In the channel width direction, the gate electrode layer 160 faces the side surfaces of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 through the gate insulating layer 150. That is, when a gate voltage is applied to the gate electrode layer 160, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are surrounded by the electric field of the gate electrode layer 160 in the channel width direction. When a gate voltage is applied to the gate electrode layer 160, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are surrounded by the electric field of the gate electrode layer 160 in the channel width direction. 3 is surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of the transistor in which the semiconductor layer is surrounded by the electric field of the gate electrode layer 160 is called a surrounded channel (s-channel) structure. The structure of the transistor in which the semiconductor layer is surrounded by the electric field of the gate electrode layer 160 is called a surrounded channel (s-channel) structure. Also, since the transistor 10 can form the gate electrode, the source electrode, and the drain electrode by using a groove in a cell array, it has excellent alignment accuracy and can easily fabricate a fine transistor. It can form the gate electrode, the source electrode, and the drain electrode by using a groove in a cell array, so it has excellent alignment accuracy and can easily fabricate a fine transistor. It has excellent alignment accuracy and can easily fabricate a fine transistor. Note that such a structure is called a self-align s-channel FET (Self Align s-channel FET, SA s-channel FET) structure, or a trench gate s-channel FET (Trench gate s-channel FET), or a TGSA FET (Trench Gate Self Align) structure, or a GLSA FET (Gate Last Self Align FET). Such a structure is called a self-align s-channel FET (Self Align s-channel FET, SA s-channel FET) structure, or a trench gate s-channel FET (Trench gate s-channel FET), or a TGSA FET (Trench Gate Self Align) structure, or a GLSA FET (Gate Last Self Align FET). -channel FET, SA s-channel FET) structure, or a trench gate s-channel FET (Trench gate s-channel F ET), or a TGSA FET (Trench Gate Self Align) struct ure, or a GLSA FET (Gate Last Self Align FET) and Call.

[0070] Here, when the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are combined to form the oxide semiconductor layer 120, in a transistor with an SA s-channel structure in the on state, a channel is formed in the entire (bulk) of the oxide semiconductor layer 120, so the on-current increases. On the other hand, in the off state, since the entire channel region formed in the oxide semiconductor layer 120 is depleted, the off-current can be further reduced.

[0071] Thus, when forming the oxide semiconductor layer 123, the gate insulating layer 150, and the gate electrode layer 160 in the groove 174, the embedding property of each film can be improved, and the transistor 10 can be easily fabricated.

[0072] Also, since the transistor 10 has a TGSA structure, the parasitic capacitance generated between the gate electrode and the source electrode, or between the gate electrode and the drain electrode can be reduced, and the cutoff frequency characteristics of the transistor 10 can be improved, such as enabling the transistor 10 to respond at high speed.

[0073] Note that the position of the upper surface of the source electrode layer 130 or the drain electrode layer 140 may be lower, the same, or higher than the position of the bottom surface of the gate electrode layer 160.

[0074] Also, the groove 174 of the transistor 10 may have a linear shape as shown in Fig. 2(A). Also as shown in Fig. 2(B) of the transistor, the upper surface of the gate electrode layer 160 may be lower than the upper surface of the insulating layer 175. Also, the transistor 10 may be as shown in Fig. 2(C), with the insulating film 150a, And the third oxide semiconductor film 123a may not be flattened. Also, for the transistor 10, as shown in FIG. 3(A), the ends of the source electrode layer 130 and the drain electrode layer may have a shape shorter than that of the oxide semiconductor layer 122, or may have a longer shape.

[0075] <Regarding channel length> Note that the channel length is, for example, in a top view of the transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

[0076] <Regarding channel width> The channel width is, for example, the length of the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

[0077] ​​​​Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may differ from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. In some cases, the effective channel width (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, In a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, In a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, In a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, In a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, In a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view.

[0078] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0079] <Regarding SCW> Therefore, in this specification, in the top view of the transistor, the apparent channel width in the region where the semiconductor and the gate electrode overlap may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it refers to the surrounded channel width or the apparent channel width. Therefore, in this specification, in the top view of the transistor, the apparent channel width in the region where the semiconductor and the gate electrode overlap may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it refers to the surrounded channel width or the apparent channel width. Therefore, in this specification, in the top view of the transistor, the apparent channel width in the region where the semiconductor and the gate electrode overlap may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it refers to the surrounded channel width or the apparent channel width. Therefore, in this specification, in the top view of the transistor, the apparent channel width in the region where the semiconductor and the gate electrode overlap may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it refers to the surrounded channel width or the apparent channel width. This may be the case. Or, in this specification, when simply described as channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. In addition, when calculating the field-effect mobility of a transistor, the current value per channel width, etc., the enclosed channel width may be used for calculation. In that case, it may take a value different from the case of calculating using the effective channel width. For example, in the transistor of one aspect of the present invention shown in FIG. 1, as described above, the third oxide semiconductor layer 123 is formed so as to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel formation layer and the gate insulating layer are not in contact with each other. Therefore, carrier scattering occurring at the interface between the channel formation layer and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased. Also, in the transistor of one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as the channel, in addition to the gate electric field from the vertical direction to the oxide semiconductor layer 1223, a gate electric field from the side surface direction is applied.

[0080] Note that when calculating the field-effect mobility of a transistor, the current value per channel width, etc., the enclosed channel width may be used for calculation. In that case, it may take a value different from the case of calculating using the effective channel width. This may be the case. Or, in this specification, when simply described as channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. In addition, when calculating the field-effect mobility of a transistor, the current value per channel width, etc., the enclosed channel width may be used for calculation. In that case, it may take a value different from the case of calculating using the effective channel width.

[0081] <Characteristic improvement in miniaturization> To highly integrate a semiconductor device, miniaturization of transistors is essential. On the other hand, it is known that the electrical characteristics of transistors deteriorate due to miniaturization of transistors, and when the channel width is reduced, the on-current decreases. For example, in the transistor of one aspect of the present invention shown in FIG. 1, as described above, the third oxide semiconductor layer 123 is formed so as to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel formation layer and the gate insulating layer are not in contact with each other. Therefore, carrier scattering occurring at the interface between the channel formation layer and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased. Also, in the transistor of one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as the channel, in addition to the gate electric field from the vertical direction to the oxide semiconductor layer 1223, a gate electric field from the side surface direction is applied.

[0082] For example, in the transistor of one aspect of the present invention shown in FIG. 1, as described above, the third oxide semiconductor layer 123 is formed so as to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel formation layer and the gate insulating layer are not in contact with each other. Therefore, carrier scattering occurring at the interface between the channel formation layer and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased. Also, in the transistor of one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as the channel, in addition to the gate electric field from the vertical direction to the oxide semiconductor layer 1223, a gate electric field from the side surface direction is applied. For example, in the transistor of one aspect of the present invention shown in FIG. 1, as described above, the third oxide semiconductor layer 123 is formed so as to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel formation layer and the gate insulating layer are not in contact with each other. Therefore, carrier scattering occurring at the interface between the channel formation layer and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased. Also, in the transistor of one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as the channel, in addition to the gate electric field from the vertical direction to the oxide semiconductor layer 1223, a gate electric field from the side surface direction is applied. Therefore, carrier scattering occurring at the interface between the channel formation layer and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased.

[0083] Also, in the transistor of one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as the channel, in addition to the gate electric field from the vertical direction to the oxide semiconductor layer 1223, a gate electric field from the side surface direction is applied. For example, in the transistor of one aspect of the present invention shown in FIG. 1, as described above, the third oxide semiconductor layer 123 is formed so as to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel formation layer and the gate insulating layer are not in contact with each other. Therefore, carrier scattering occurring at the interface between the channel formation layer and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased. For example, in the transistor of one aspect of the present invention shown in FIG. 1, as described above, the third oxide semiconductor layer 123 is formed so as to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel formation layer and the gate insulating layer are not in contact with each other. Therefore, carrier scattering occurring at the interface between the channel formation layer and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased. An electric field is applied. That is, a gate electric field is applied to the entire oxide semiconductor layer, and thus current flows through the entire oxide semiconductor layer 122, further increasing the on-current.

[0084] Also, the transistor according to one aspect of the present invention has an effect of making it difficult to form interface levels by forming the oxide semiconductor layer 123 on the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and an effect of eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to improving the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. As a result, Icut (current when the gate voltage VG is 0 V) can be reduced, and power consumption can be reduced. Also, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved.

[0085] Note that, in this embodiment, an example in which the oxide semiconductor layer 120 or the like is used in a channel or the like has been shown, but one aspect of the embodiment of the present invention is not limited to this. For example, the channel, its vicinity, the source region, the drain region, etc. may be formed of a material having silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like, depending on the case or the situation.

[0086] <Configuration of Transistor> The configuration of the transistor according to this embodiment will be described below.

[0087] "Substrate 100" For the substrate 100, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. Also, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Semiconductor On Insulator) substrate, etc. can also be used, and those with semiconductor elements provided on these substrates may be used. The substrate 100 is not limited to a mere support material, and it may be a substrate on which other devices such as other transistors are formed. In this case, one of the gate electrode layer 160, the source electrode layer 13 0, and the drain electrode layer 140 of the transistor may be electrically connected to the above-mentioned other devices.

[0088] Also, a flexible substrate may be used as the substrate 100. As a method of providing a transistor on the flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to the substrate 100 which is a flexible substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. Note that as the substrate 100, a sheet, film or foil in which fibers are woven may be used. Also, the substrate 100 may have stretchability. Also, when the bending or pulling of the substrate 100 is stopped, it may have the property of returning to its original shape. Or it may have the property of not returning to its original shape. The thickness of the substrate 100 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. When the substrate 100 is made thinner, the semiconductor device In addition, by making the substrate 100 thinner, it is possible to reduce the weight of the substrate. It has the ability to stretch even when bent or pulled, and to return to its original shape when bending or pulling is stopped. Therefore, the semiconductor device on the substrate 100 may be subjected to a shock due to being dropped or the like. In other words, a robust semiconductor device can be provided.

[0089] The substrate 100, which is a flexible substrate, may be, for example, a metal, an alloy, a resin, or a glass. The substrate 100, which is a flexible substrate, has a linear expansion coefficient of The lower the temperature, the more preferable it is since deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 The resin may be, for example, polyester or polyolefin. Polyimide, polycarbonate, acrylic Aramid, in particular, has a linear expansion coefficient of Since the resistance is low, it is suitable for the substrate 100 which is a flexible substrate.

[0090] Insulating layer 110 The insulating layer 110 serves to prevent the diffusion of impurities from the substrate 100 and also serves to form an oxide semiconductor. The insulating layer 110 can supply oxygen to the conductor layer 120. It is preferable that the insulating film contains oxygen in an amount larger than the stoichiometric composition. For example, it is more preferable that the amount of oxygen released, calculated as oxygen atoms, is 1.0 ×10 19 atoms / cm 3Use the above-mentioned film. Note that the film during the above TDS analysis should preferably have a surface temperature in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower. Further, when the substrate 100 is a substrate on which other devices are formed as described above , the insulating layer 110 also functions as an interlayer insulating film. In that case, it is preferable to perform a planarization treatment by a method such as CMP (Chemical Mechanical Polishing) so that the surface becomes flat.

[0091] 《Oxide semiconductor layers 121, 122, 123》 The oxide semiconductor layer 122 is an oxide semiconductor film containing In or Zn, and typically, In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd ).

[0092] The oxide semiconductors that can be used as the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 preferably contain at least indium (In) or zinc (Zn). Or preferably contain both In and Zn. Further, in order to reduce the variation in the electrical characteristics of the transistors using the oxide semiconductor, it is preferable to include a stabilizer together with them.

[0093] Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr), etc. Further, as other stabilizers , there are lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. .

[0094] When the oxide semiconductor layer 123 is an In-M-Zn oxide, the atomic ratio of In and M is preferably such that In is 25 atomic% or more and M is less than 75 atomic%, and more preferably, In is 34 atomic% or more and M is less than 66 atomic%.

[0095] The content of indium, gallium, etc. in the oxide semiconductor layer 123 can be compared by time-of-flight secondary ion mass spectrometry (TOF-SIMS), X-ray photoelectron spectroscopy (XPS), ICP mass spectrometry (IC P-MS).

[0096] Since the oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more , more preferably 3 eV or more, the off-current of the transistor 10 can be reduced.

[0097] The thickness of the oxide semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0098] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are oxide semiconductor films composed of one or more of the elements constituting the oxide semiconductor layer 122. Therefore, at the interfaces between the oxide semiconductor layer 12 2 and the oxide semiconductor layer 122, and between the oxide semiconductor layer 124, interface scattering occurs. It is less likely to occur. Therefore, the movement of carriers is not hindered at the interface, so the field-effect mobility of the transistor 10 is increased.

[0099] The oxide semiconductor layers 121 and 123 are typically In-Ga oxide, In -Zn oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Z n oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), and the energy level of the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor layer 122. Typically, the difference between the energy of the lower end of the conduction band of the oxide semiconductor layers 121 and 123 and the energy of the lower end of the conduction band of the oxide semiconductor layer 122 is 0.05 eV or more, 0.0 7 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0 .5 eV or less, or 0.4 eV or less. That is, the difference in electron affinity between the oxide semiconductor layers 121 and 123 and the electron affinity of the oxide semiconductor layer 122 is 0.05 e V or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Note that the electron affinity indicates the difference between the vacuum level and the energy of the lower end of the conduction band.

[0100] When the oxide semiconductor layers 121 and 123 have Al, Ti, Ga, Y, Zr, S n, La, Ce, Mg, or Nd at an atomic ratio higher than that of In, the following effects may be obtained. (1) The energy gap of the oxide semiconductor layers 121, 122, and oxide semiconductor layer 124 is increased. (2) The acid oxide semiconductor layers 121, acid Reduce the electron affinity of the oxide semiconductor layer 123. (3) Shield impurities from the outside. (4) The insulating property becomes higher compared to the oxide semiconductor layer 122. (5) Al, Ti, Ga, Y , Zr, Sn, La, Ce, Mg, or Nd is a metal element with a strong binding force with oxygen Therefore, by having Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd at an atomic ratio higher than In , the occurrence of oxygen deficiency is less likely to occur.

[0101] Note that the oxide semiconductor layer 121 and the oxide semiconductor layer 123 have the same function as the gate insulating layer because they have a higher insulating property compared to the oxide semiconductor layer 122.

[0102] When the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are In-M-Zn oxides, the atomic ratio of In and M excluding Zn and O is preferably 50 atomic % or less for In and 50 atomic% or more for M, and more preferably 25 atomic% or less for In and 75 atomic% or more for M.

[0103] Also, when the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are In-M-Zn oxides (M is Al , Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), compared to the oxide semiconductor layer 122, the atomic ratio of M (Al , Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) contained in the oxide semiconductor layer 121 and the oxide semiconductor layer 123 is high, and typically, compared to the above atoms contained in the oxide semiconductor layer 123, it is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher atomic ratio. The elements represented by M above bind more strongly with oxygen than indium, so oxygen deficiency in the oxide semiconductor layer 121 and the oxide semiconductor layer It has a function of suppressing the occurrence in the conductor layer 123. That is, the oxide semiconductor layer 121, the oxide semiconductor layer 123 is an oxide semiconductor film in which oxygen deficiency is less likely to occur than the oxide semiconductor layer 122. There is.

[0104] Also, the oxide semiconductor layer 122 may have a higher indium content than the oxide semiconductor layer 121 and the oxide semiconductor layer 123. In an oxide semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction. By increasing the In content ratio, more s orbitals overlap. Therefore, an oxide having a composition with more In than M has a higher mobility compared to an oxide having a composition with In equal to or less than M. Therefore, by using an oxide with a high indium content in the oxide semiconductor layer 122, a transistor with high field-effect mobility can be realized.

[0105] Also, when the oxide semiconductor layer 122 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Z r, Sn, La, Ce, Mg, or Nd), in the target used to form the oxide semiconductor layer 122, if the atomic ratio of metal elements is In:M:Zn = x1:y1:z 1, then x1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, and z1 / y1 is preferably 1 / 3 or more and 6 or less, further 1 or more and 6 or less. Note that by setting z1 / y1 to 1 or more and 6 or less, a CAAC-OS (C A xis Aligned Crystalline Oxide Semiconduc tor) film is likely to be formed as the oxide semiconductor layer 122. Representative examples of the atomic ratio of metal elements in the target are In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, 2:1:1.5, 2: ​​​​​​There are 1:2.3, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, etc.

[0106] Further, when the oxide semiconductor layers 121 and 123 are In-M-Zn oxides (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), in the target used for forming the oxide semiconductor layers 121 and 123, if the atomic ratio of the metal elements is In:M:Zn = x2:y2:z2, then x2 / y2 < x1 / y1, and it is preferable that z2 / y2 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less. Note that by setting z2 / y2 to 1 or more and 6 or less, it becomes easier to form a CAAC-OS film as the oxide semiconductor layers 121 and 123. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, 1:3:4, 1:3:6, 1:3: 8, 1:4:4, 1:4:5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1: 5:6, 1:5:7, 1:5:8, 1:6:8, 1:6:4, 1:9:6, etc. Note that the atomic ratio of the oxide semiconductor layers 121 and 123 respectively includes fluctuations of plus or minus 40% of the above atomic ratio as an error. In addition, the oxide semiconductor layer 123 can be replaced with a metal oxide, for example, aluminum oxide (AlOx), gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), germanium oxide (GeOx), or zirconia (ZrOx), or the metal oxide can be provided on the oxide semiconductor layer 123.

[0107]

[0108]

[0109] ​​​​​​​​​Note that the atomic ratio is not limited to these, and an appropriate atomic ratio may be used according to the required semiconductor characteristics. It is sufficient to use the appropriate one.

[0110] Also, the oxide semiconductor layers 121 and 123 may have the same composition. For example, as the oxide semiconductor layers 121 and 123, a target with an atomic ratio of metal elements of In:Ga:Zn = 1:3:2, 1:3:4, or 1:4:5 of In-Ga-Zn oxide may be used.

[0111] Alternatively, the oxide semiconductor layers 121 and 123 may have different compositions. For example, as the oxide semiconductor layer 121, an In-Ga-Zn oxide with an atomic ratio of metal elements of In:Ga:Zn = 1:3:4 used in the sputtering method is used, and the oxide semiconductor layer 123 may use an In-Ga-Zn oxide with an atomic ratio of metal elements of In:Ga:Zn = 1:3:2 as the target. 123 may use an In-Ga-Zn oxide with an atomic ratio of metal elements of In:Ga:Zn = 1:3:2 as the target. Ga-Zn oxide may be used.

[0112] The thicknesses of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are preferably 3 nm or more and 100 nm or less, or 3 nm or more and 50 nm or less.

[0113] Here, the thickness of the oxide semiconductor layer 122 may be formed thinner, the same, or thicker than at least the oxide semiconductor layer 121. For example, when the oxide semiconductor layer 122 is thickened, the on-current of the transistor can be increased. Also, the oxide semiconductor layer 121 should have a thickness such that the effect of suppressing the generation of interface levels of the oxide semiconductor layer 122 is not lost. For example, the thickness of the oxide semiconductor layer 122 is the thickness of the oxide semiconductor layer 121, the same, or thicker than the oxide semiconductor layer 121. For example, when the oxide semiconductor layer 122 is thickened, the on-current of the transistor can be increased. Also, the oxide semiconductor layer 121 should have a thickness such that the effect of suppressing the generation of interface levels of the oxide semiconductor layer 122 is not lost. For example, the thickness of the oxide semiconductor layer 122 is the thickness of the oxide semiconductor layer With respect to the thickness of 121, it can be greater than 1 time, or 2 times or more, or 4 times or more, or 6 times or more. Also, when it is not necessary to increase the on-current of the transistor, the thickness of the oxide semiconductor layer 121 may be equal to or greater than the thickness of the oxide semiconductor layer 122. For example, when the insulating layer 110 or the insulating layer 175 has an excessive amount of oxygen, by heat treatment, the oxygen diffuses, and the amount of oxygen vacancies contained in the oxide semiconductor layer 122 can be reduced, and the electrical characteristics of the semiconductor device can be stabilized.

[0114] Also, similar to the oxide semiconductor layer 121, the oxide semiconductor layer 123 only needs to have a thickness such that the effect of suppressing the generation of interface levels with the oxide semiconductor layer 122 is not lost. For example, it may have a thickness equal to or less than that of the oxide semiconductor layer 121. If the oxide semiconductor layer 123 is thick, there is a possibility that the electric field by the gate electrode layer 160 (or the gate electrode layer 161, the gate electrode layer 162) will not easily reach the oxide semiconductor layer 122. Therefore, the oxide semiconductor layer 123 is preferably formed thin. For example, the oxide semiconductor layer 123 may be thinner than the thickness of the oxide semiconductor layer 122. Note that this is not limiting, and the thickness of the oxide semiconductor layer 123 may be appropriately set according to the voltage for driving the transistor in consideration of the breakdown voltage of the gate insulating layer 150.

[0115] When the compositions of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are different from each other, the interface may be observable using a scanning transmission electron microscope STEM (Scanning Tr ansmission Electron Microscope).

[0116] <Regarding hydrogen concentration> Included in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 Hydrogen reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies are formed in the lattice (or also the part where oxygen has desorbed) from which oxygen has desorbed. When hydrogen enters the oxygen vacancies, carriers electrons may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen is reduced as much as possible together with oxygen vacancies at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and

[0117] each of their interfaces. For example, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each of their interfaces is 1×10 16 atoms / cm 16 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less, preferably 1×10 16 atoms / cm 3 or more and 5×10 19 atoms / cm 3 or less, more preferably 1× 10 16 atoms / cm 3 or more and 1×10 19 atoms / cm 3 or less, even more preferably is 1×10 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3It is desirable to be as follows. As a result, the transistor 10 can have electrical characteristics (also referred to as normal-off characteristics) in which the threshold voltage is positive. (Also called the normal-off characteristic.)

[0118] <Regarding the carbon and silicon concentrations> Further, when silicon or carbon, which is one of the Group 14 elements, is contained at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and their respective interfaces, oxygen deficiency increases in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123, and an n-type region is formed. Therefore, it is desirable to reduce the silicon and carbon concentrations at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and their respective interfaces. For example, the concentrations of silicon and carbon obtained by SIMS at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, the oxide semiconductor layer 124, and their respective interfaces are 1×10 atoms / cm or more and 1 ×10 atoms / cm or less, preferably 1×10 16 atoms / cm 3 or more and 5 ×10 19 atoms / cm 3 or less, more preferably 1×10 16 atoms / cm 3 or more and 2×10 ×10 18 atoms / cm 3 or less. It is desirable to be as follows. 16 As a result, the transistor 10 has electrical characteristics (also referred to as normal-off characteristics) in which the threshold voltage is positive. 3 (Also called the normal-off characteristic.) 18 atoms / cm 3 (Also called the normal-off characteristic.) (Also called the normal-off characteristic.) has.

[0119] <Regarding the concentration of alkali metals> In addition, when an alkali metal and an alkaline earth metal combine with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface. For example, at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface, the concentration of the alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1×10 or less, preferably 2×10 or less. Thereby, the transistor 10 can have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. <Regarding nitrogen concentration> In addition, when nitrogen is contained in the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface, electrons as carriers are generated, the carrier density increases, and an n-type region is formed. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface. For example, at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface, the nitrogen concentration obtained by SIMS is 1×10 atoms / cm or less. 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. Thereby, the transistor 10 can have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

[0120] <Regarding nitrogen concentration> In addition, when nitrogen is contained in the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface, electrons as carriers are generated, the carrier density increases, and an n-type region is formed. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface. For example, at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface, the nitrogen concentration obtained by SIMS is 1×10 atoms / cm or less. Therefore, it is preferable that nitrogen is reduced as much as possible at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface. For example, at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface, the nitrogen concentration obtained by SIMS is 1×10 atoms / cm or less. For example, at the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each interface, the nitrogen concentration obtained by SIMS is 1×10 atoms / cm 15 or less.​3 5×10 or more 19 atoms / cm 3 below, Preferably 1 x 10 15 atoms / cm 3 5×10 or more 18 atoms / cm 3 below, More preferably, 1×10 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 Below or less, and more preferably 1×10 15 atoms / cm 3 5×10 or more 17 atoms / c m 3 It is preferable that the threshold voltage of the transistor 10 is set to 0.5 V or less. The device can have electrical characteristics (also called normally-off characteristics) that are suitable for use as a semiconductor device.

[0121] <About carrier density> Impurities in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are removed by By reducing the amount of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer Therefore, the carrier density in the oxide semiconductor layer 121 and the oxide semiconductor layer 123 can be reduced. The compound semiconductor layer 122 and the oxide semiconductor layer 123 have a carrier density of 1×10 15 pcs / c m 3 Less than or equal to 1×10 13 pieces / cm 3 Less than 8×10, more preferably 11 pieces / cm 3 less than 1×10 11 pieces / cm 3 less than 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 That is all.

[0122] As the oxide semiconductor layers 121, 122, and 123, an oxide semiconductor film with a low impurity concentration and a low density of defect levels is used, and a transistor with even more excellent electrical characteristics can be fabricated. Here, an oxide semiconductor film with a low impurity concentration and a low density of defect levels (with little oxygen deficiency) is called highly pure intrinsic or substantially highly pure intrinsic. Since a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor has few carrier generation sources, it may be possible to lower the carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film tends to have electrical characteristics (also called a normally-off characteristic) in which the threshold voltage is positive. Also, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the trap level density may also be low. Further, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has an extremely small off-current, and in the range where the voltage between the source electrode and the drain electrode (drain voltage) is from 1 V to 10 V, the off-current can be below the measurement limit of a semiconductor parameter analyzer, that is, 1× 10 A or less. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may become a transistor with small fluctuations in electrical characteristics and high reliability. Also, the off-current of a transistor using the oxide semiconductor film highly purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor 10 -13 A or less. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may become a transistor with small fluctuations in electrical characteristics and high reliability. Also, the off-current of a transistor using the oxide semiconductor film highly purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor

[0123] In addition, the off-current of a transistor using the oxide semiconductor film highly purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor V, or 10 V, the off-current normalized by the channel width of the transistor It is possible to reduce it to several yA / μm to several zA / μm.

[0124] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example may have a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS, polycrystalline structure , microcrystalline structure, or amorphous structure described later. In the non-single crystal structure, the amorphous structure has the highest defect level density, and CAAC-OS has the lowest defect level density.

[0125] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example may have a microcrystalline structure. The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 having a microcrystalline structure contain, for example, microcrystals with a size of 1 nm or more and less than 10 nm in the film . Or, the oxide film and the oxide semiconductor film having a microcrystalline structure are, for example, a mixed-phase structure having a crystal part of 1 n m or more and less than 10 nm in the amorphous phase.

[0126] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example may have an amorphous structure. The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 having an amorphous structure have, for example, a disordered atomic arrangement and no crystal component. Or, the oxide film having an amorphous structure is, for example, a complete amorphous structure and has no crystal part .

[0127] Note that the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 may be a mixed film having regions of two or more structures of CAAC-OS, microcrystalline structure, and amorphous structure . As the mixed film, for example, a region of an amorphous structure, a region of a microcrystalline structure, and CA There is a single-layer structure having an AC-OS region. Or, as a mixed film, for example, an amorphous There is a laminated structure including a region with an amorphous structure, a region with a microcrystalline structure, and a CAAC-OS region.

[0128] Note that the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 may have, for example, a single crystal structure.

[0129] By providing an oxide semiconductor film less likely to generate oxygen deficiency in contact with the upper and lower sides of the oxide semiconductor layer 122, the oxygen deficiency in the oxide semiconductor layer 122 can be reduced. In addition, since the oxide semiconductor layer 122 is in contact with the oxide semiconductor layer 121 and the oxide semiconductor layer 123 having one or more of the metal elements constituting the oxide semiconductor layer 122, the interface level density at the interface between the oxide semiconductor layer 121 and the oxide semiconductor layer 122 and at the interface between the oxide semiconductor layer 122 and the oxide semiconductor layer 123 is extremely low. For example, after adding oxygen to the insulating layer 110 and performing a heat treatment, the oxygen moves to the oxide semiconductor layer 122 via the oxide semiconductor layer 121. At this time, oxygen is less likely to be trapped at the interface level, and it is possible to efficiently move the oxygen contained in the oxide semiconductor layer 121 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. In addition, since oxygen is also added to the oxide semiconductor layer 121, it is possible to reduce the oxygen deficiency in the oxide semiconductor layer 121. That is, at least the local level density of the oxide semiconductor layer 122 can be reduced.

[0130] In addition, when the oxide semiconductor layer 122 is an insulating film having different constituent elements (for example, including a silicon oxide film) When in contact with a μ-gate insulating layer, interface levels are formed, and these interface levels may form a channel. In such a case, a second transistor with a different threshold voltage may appear, and the apparent threshold voltage of the transistor may vary. However, since the oxide semiconductor layer 121 and the oxide semiconductor layer 123 each contain one or more metal elements constituting the oxide semiconductor layer 122, it is difficult to form interface levels at the interface between the oxide semiconductor layer 121 and the oxide semiconductor layer 122 and at the interface between the oxide semiconductor layer 123 and the oxide semiconductor layer 122. However, since the oxide semiconductor layer 121 and the oxide semiconductor layer 123 each contain one or more metal elements constituting the oxide semiconductor layer 122, it is difficult to form interface levels at the interface between the oxide semiconductor layer 121 and the oxide semiconductor layer 122 and at the interface between the oxide semiconductor layer 123 and the oxide semiconductor layer 122. However, since the oxide semiconductor layer 121 and the oxide semiconductor layer 123 each contain one or more metal elements constituting the oxide semiconductor layer 122, it is difficult to form interface levels at the interface between the oxide semiconductor layer 121 and the oxide semiconductor layer 122 and at the interface between the oxide semiconductor layer 123 and the oxide semiconductor layer 122. Moreover, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 also function as barrier films for suppressing the constituent elements of the insulating layer 110 and the gate insulating layer 150 from mixing into the oxide semiconductor layer 122 and forming levels due to impurities. Moreover, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 also function as barrier films for suppressing the constituent elements of the insulating layer 110 and the gate insulating layer 150 from mixing into the oxide semiconductor layer 122 and forming levels due to impurities. Moreover, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 also function as barrier films for suppressing the constituent elements of the insulating layer 110 and the gate insulating layer 150 from mixing into the oxide semiconductor layer 122 and forming levels due to impurities.

[0131] Moreover, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 also function as barrier films for suppressing the constituent elements of the insulating layer 110 and the gate insulating layer 150 from mixing into the oxide semiconductor layer 122 and forming levels due to impurities. Moreover, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 also function as barrier films for suppressing the constituent elements of the insulating layer 110 and the gate insulating layer 150 from mixing into the oxide semiconductor layer 122 and forming levels due to impurities. Moreover, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 also function as barrier films for suppressing the constituent elements of the insulating layer 110 and the gate insulating layer 150 from mixing into the oxide semiconductor layer 122 and forming levels due to impurities.

[0132] For example, when an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150, silicon in the gate insulating layer 150 or carbon that may be mixed into the insulating layer 110 and the gate insulating layer 150 may be mixed into the oxide semiconductor layer 121 or the oxide semiconductor layer 123 by several nanometers from the interface. When impurities such as silicon and carbon enter the oxide semiconductor layer 122, impurity levels are formed, and the impurity levels may act as donors to generate electrons, resulting in n-type conversion. For example, when an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150, silicon in the gate insulating layer 150 or carbon that may be mixed into the insulating layer 110 and the gate insulating layer 150 may be mixed into the oxide semiconductor layer 121 or the oxide semiconductor layer 123 by several nanometers from the interface. When impurities such as silicon and carbon enter the oxide semiconductor layer 122, impurity levels are formed, and the impurity levels may act as donors to generate electrons, resulting in n-type conversion. For example, when an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150, silicon in the gate insulating layer 150 or carbon that may be mixed into the insulating layer 110 and the gate insulating layer 150 may be mixed into the oxide semiconductor layer 121 or the oxide semiconductor layer 123 by several nanometers from the interface. When impurities such as silicon and carbon enter the oxide semiconductor layer 122, impurity levels are formed, and the impurity levels may act as donors to generate electrons, resulting in n-type conversion. For example, when an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150, silicon in the gate insulating layer 150 or carbon that may be mixed into the insulating layer 110 and the gate insulating layer 150 may be mixed into the oxide semiconductor layer 121 or the oxide semiconductor layer 123 by several nanometers from the interface. When impurities such as silicon and carbon enter the oxide semiconductor layer 122, impurity levels are formed, and the impurity levels may act as donors to generate electrons, resulting in n-type conversion. For example, when an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150, silicon in the gate insulating layer 150 or carbon that may be mixed into the insulating layer 110 and the gate insulating layer 150 may be mixed into the oxide semiconductor layer 121 or the oxide semiconductor layer 123 by several nanometers from the interface. When impurities such as silicon and carbon enter the oxide semiconductor layer 122, impurity levels are formed, and the impurity levels may act as donors to generate electrons, resulting in n-type conversion. For example, when an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150, silicon in the gate insulating layer 150 or carbon that may be mixed into the insulating layer 110 and the gate insulating layer 150 may be mixed into the oxide semiconductor layer 121 or the oxide semiconductor layer 123 by several nanometers from the interface. When impurities such as silicon and carbon enter the oxide semiconductor layer 122, impurity levels are formed, and the impurity levels may act as donors to generate electrons, resulting in n-type conversion.

[0133] However, if the film thicknesses of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are thicker than several nanometers, the impurities such as silicon and carbon that have mixed in will not reach the oxide semiconductor layer 122, so the influence of the impurity levels is reduced. However, if the film thicknesses of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are thicker than several nanometers, the impurities such as silicon and carbon that have mixed in will not reach the oxide semiconductor layer 122, so the influence of the impurity levels is reduced. However, if the film thicknesses of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are thicker than several nanometers, the impurities such as silicon and carbon that have mixed in will not reach the oxide semiconductor layer 122, so the influence of the impurity levels is reduced.

[0134] Therefore, by providing the oxide semiconductor layer 121 and the oxide semiconductor layer 123, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0135] Further, when the gate insulating layer 150 is in contact with the oxide semiconductor layer 122 and a channel is formed at the interface, interface scattering occurs at the interface, and the field-effect mobility of the transistor decreases. However, since the oxide semiconductor layer 121 containing one or more metal elements constituting the oxide semiconductor layer 122 and the oxide semiconductor layer 123 are provided in contact with the oxide semiconductor layer 122, carrier scattering hardly occurs at the interfaces between the oxide semiconductor layer 122 and the oxide semiconductor layer 121 and between the oxide semiconductor layer 122 and the oxide semiconductor layer 123, and the field-effect mobility of the transistor can be increased.

[0136] In this embodiment, it is possible to reduce the oxygen deficiency amount of the oxide semiconductor layer 122 and further the oxygen deficiency amounts of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 in contact with the oxide semiconductor layer 122, and it is possible to reduce the density of localized levels of the oxide semiconductor layer 122. As a result, the transistor 10 shown in this embodiment can have characteristics with little variation in threshold voltage and high reliability. Further, the transistor 10 shown in this embodiment has excellent electrical characteristics.

[0137] Note that since an insulating film containing silicon is often used as the gate insulating layer of the transistor, for the above reasons, it can be said that a structure in which the region serving as the channel of the oxide semiconductor layer does not contact the gate insulating layer, like the transistor of one aspect of the present invention, is preferable. Further, when a channel is formed at the interface between the gate insulating layer and the oxide semiconductor layer, carrier scattering occurs at the interface. This may occur, and the field-effect mobility of the transistor may decrease. From this perspective as well, it can be said that the region serving as the channel of the oxide semiconductor layer is preferably separated from the gate insulating layer. .

[0138] Therefore, by forming the oxide semiconductor layer 120 into a stacked structure of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123, a channel can be formed in the oxide semiconductor layer 123, and a transistor having high field-effect mobility and stable electrical characteristics can be formed. .

[0139] Note that the oxide semiconductor does not necessarily have to be three layers, and it may have a single-layer, two-layer, four-layer, or even five-layer or more structure. In the case of a single layer, a layer corresponding to the oxide semiconductor layer 122 shown in this embodiment may be used. .

[0140] <Band diagram> Here, the band diagram will be described. The band diagram shows the energy (Ec) at the lower end of the conduction band of the insulating layer 110, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and the gate insulating layer 150 for easy understanding.

[0141] As shown in FIGS. 4(A) and 4(B), in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123, the energy at the lower end of the conduction band changes continuously. This is also understood from the fact that the elements constituting the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are common, and oxygen diffuses easily among them. Therefore, although the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are a stack of films with different compositions, it can also be said that they are physically continuous. .

[0142] The oxide semiconductor film, which is laminated with a common main component, is not simply laminated but is continuously joined. In this case, the energy of the conduction band edge changes continuously between layers. In other words, the interface between each layer is fabricated so that a U-shaped well structure is formed. There are no impurities that can form defect levels such as trap centers or recombination centers in the If impurities are present between the layers of the laminated multi-layer film, The continuity of the energy band is lost, and carriers disappear at the interface due to trapping or recombination. It ends up like this.

[0143] Note that in FIG. 4B, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 have the same Ec. Although certain cases are shown, they may be different.

[0144] As shown in FIG. 4B and FIG. 4C, the oxide semiconductor layer 122 serves as a well, and In the case of the gate electrode 10, it can be seen that a channel is formed in the oxide semiconductor layer 122. A U-shaped well in which the energy of the conduction band minimum changes continuously from the oxide semiconductor layer 122 at its bottom. The channel of the door structure may also be called a recessed channel.

[0145] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are formed of an insulating film such as a silicon oxide film. In the vicinity of the interface with the film, trap levels due to impurities or defects can be formed. The oxide semiconductor layer 122 and the oxide semiconductor layer 123 are formed on the oxide semiconductor layer 121 and the oxide semiconductor layer 123. However, the oxide semiconductor layer 121 or the oxide semiconductor When the energy difference between Ec of the oxide semiconductor layer 123 and Ec of the oxide semiconductor layer 122 is small, Electrons in the oxide semiconductor layer 122 may reach the trap level exceeding the energy difference. Ma When the electrons that become the charges of the minus are trapped in the trap level, a negative fixed charge is generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Furthermore, in the long-term storage test of the transistor, there is a concern that the trap is not fixed and causes fluctuations in characteristics. Therefore, in order to reduce the fluctuation of the threshold voltage of the transistor, an energy difference is required between the Ec of the oxide semiconductor layer 121 and the oxide semiconductor layer 123, and the oxide semiconductor layer 122. Each of the energy differences is preferably 0.1 eV or more,

[0146] and more preferably 0.2 eV or more. Note that the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 preferably include a crystal part. In particular, by using a crystal oriented along the c-axis, stable electrical characteristics can be imparted to the transistor. In addition, in the band diagram as shown in FIG. 4(B), the oxide semiconductor layer 123 may not be provided, and an In-Ga oxide (for example, an In-Ga oxide having an atomic ratio of

[0147] In:Ga = 7:93) may be provided between the oxide semiconductor layer 123 and the gate insulating layer 150, or gallium oxide may be provided. Alternatively, an In-Ga oxide may be provided between the oxide semiconductor layer 123 and the gate insulating layer 150 in a state where the oxide semiconductor layer 123 is provided, or gallium oxide may be provided. The oxide semiconductor layer 122 has a lower electric potential than the oxide semiconductor layer 121 and the oxide semiconductor layer 123.

[0148] In addition, in the band diagram as shown in FIG. 4(B), the oxide semiconductor layer 123 may not be provided, and an In-Ga oxide (for example, an In-Ga oxide having an atomic ratio of In:Ga = 7:93) may be provided between the oxide semiconductor layer 123 and the gate insulating layer 150, or gallium oxide may be provided. Alternatively, an In-Ga oxide may be provided between the oxide semiconductor layer 123 and the gate insulating layer 150 in a state where the oxide semiconductor layer 123 is provided, or gallium oxide may be provided. The oxide semiconductor layer 122 has a lower electric potential than the oxide semiconductor layer 121 and the oxide semiconductor layer 123. In addition, in the band diagram as shown in FIG. 4(B), the oxide semiconductor layer 123 may not be provided, and an In-Ga oxide (for example, an In-Ga oxide having an atomic ratio of In:Ga = 7:93) may be provided between the oxide semiconductor layer 123 and the gate insulating layer 150, or gallium oxide may be provided.

[0149] The oxide semiconductor layer 122 has a lower electric potential than the oxide semiconductor layer 121 and the oxide semiconductor layer 123. Use an oxide with a large electron affinity. For example, as the oxide semiconductor layer 122, an oxide semiconductor layer having an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.2 eV or more and 0.4 eV or less greater than that of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 can be used.

[0150] The transistor shown in this embodiment has an oxide semiconductor layer 121 and an oxide semiconductor layer 123 containing one or more metal elements constituting the oxide semiconductor layer 122. Therefore, it is difficult to form interface levels at the interface between the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and at the interface between the oxide semiconductor layer 123 and the oxide semiconductor layer 122. Thus, by providing the oxide semiconductor layer 121 and the oxide semiconductor layer 123, variations and fluctuations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0151] 《Source electrode layer 130, Drain electrode layer 140》 For the source electrode layer 130 and the drain electrode layer 140, a single substance, alloy, or a single layer or laminate of a conductive layer containing a compound such as oxygen, nitrogen, fluorine, silicon, etc., with these as the main components, made of materials such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) is preferred. For example, when laminating, the lower conductive layer (for example, the source electrode layer 131 and the drain electrode layer 141 shown in FIG. 15) in contact with the oxide semiconductor layer 122 is oxygen ​ It has a material that is easy to combine, and the upper conductive layer (for example, the source electrode layer 132 and the drain electrode layer 142 shown in FIG. 15) can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum or copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with the insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, so it is preferable.

[0152] Also, when a conductive material that easily combines with oxygen is brought into contact with the oxide semiconductor layer, a phenomenon occurs in which oxygen in the oxide semiconductor layer diffuses to the side of the conductive material that easily combines with oxygen. Oxygen deficiency occurs in the region near the contact with the source electrode layer or drain electrode layer of the oxide semiconductor layer, and hydrogen contained slightly in the film enters the oxygen deficiency, causing the region to be significantly n-type. Therefore, the n-type region can be made to act as the source or drain of the transistor.

[0153] For example, by using W as the lower conductive layer and Pt as the upper conductive layer to form a laminated structure, while making the contacted oxide semiconductor n-type, oxidation of the conductive layer due to contact with the insulating layer 170 can be suppressed.

[0154] 《Gate insulating layer 150》 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd). can have hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy) , silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide ( TaOx), an insulating film containing one or more of them can be used. Further, the gate insulating layer 150 may be a stack of the above-mentioned materials. Note that the gate insulating layer 150 may contain lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities.

[0155] Also, an example of the stacked structure of the gate insulating layer 150 will be described. The gate insulating layer 150 has, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it preferably contains hafnium oxide , and silicon oxide or silicon oxynitride.

[0156] Hafnium oxide has a higher relative dielectric constant than silicon oxide or silicon oxynitride. Therefore, since the physical film thickness can be increased for a given equivalent oxide thickness, even when the equivalent oxide thickness is 10 nm or less or 5 nm or less, the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it should have a crystal structure. It is preferable to use hafnium oxide. Examples of the crystal structure include monoclinic and cubic crystal systems. etc. However, one aspect of the present invention is not limited thereto.

[0157] By the way, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Thus, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, etc. can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Or, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Or, for the film having a buffering function, for example, a semiconductor or insulator having a larger ionization energy than the semiconductor that becomes the channel region is used. On the other hand, by trapping charges in the interface levels (trap centers) on the surface to be formed of hafnium oxide having the crystal structure described above, the threshold voltage of the transistor can be controlled. Or, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Or, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Or, for the film having a buffering function, for example, a semiconductor or insulator having a larger ionization energy than the semiconductor that becomes the channel region is used. A semiconductor or insulator is used.

[0158] On the other hand, by trapping charges in the interface levels (trap centers) on the surface to be formed of hafnium oxide having the crystal structure described above, the threshold voltage of the transistor can be controlled. center), the threshold voltage of the transistor can be controlled. In order to make the charge exist stably, for example, the channel region and hafnium oxide If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium Alternatively, if a semiconductor or insulator with a smaller electron affinity than hafnium oxide is placed, Alternatively, the film with a buffer function may have a higher ionization energy than hafnium oxide. By using such an insulator, the interface state This makes it difficult for the trapped charge to be released, and the charge can be retained for a long period of time. can.

[0159] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges at the interface state in the gate insulating layer 150, the gate potential must be increased from the oxide semiconductor film. Electrons can be moved toward the pole layer 160. As a specific example, a high temperature (e.g. 125°C to 450°C, typically 150°C to 300°C) The potential of the electrode layer 160 is set higher than the potential of the source electrode layer 130 and the drain electrode layer 140. It is sufficient to maintain the state for at least one second, typically at least one minute.

[0160] In this way, a transistor is formed in which a desired amount of electrons are trapped in the interface state of the gate insulating layer 150, etc. The threshold voltage of the gate electrode layer 160 and the voltage applied to the gate electrode layer 160 are shifted to the positive side. By adjusting the time for which the gate is turned on, the amount of electrons captured (the amount of change in the threshold voltage) can be controlled. If the charge can be trapped, it can be trapped in the gate insulating layer 150. A laminated film having a similar structure may be used for the other insulating layers.

[0161] <Gate electrode layer 160> The gate electrode layer 160 can use, for example, a conductive film such as aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), and tungsten (W). Further, the gate electrode layer 160 can be laminated. For example, as shown in FIG. 15, the gate electrode layer 162 may use the above materials, and the gate electrode layers 161 and 163 may use a conductive film containing nitrogen, such as a nitride of the above materials. r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta) and tungsten (W). The gate electrode layer 160 can be laminated. For example, as shown in FIG. 15, the gate electrode layer 16 2 may use the above materials, and the gate electrode layers 161 and 163 may use a conductive film containing nitrogen, such as a nitride of the above materials.

[0162] 《Insulating layer 170》 The insulating layer 170 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) can use an insulating film containing one or more of them. Further, the insulating layer 170 may be a laminate of the above materials. magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example , aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Ox), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaO x) can use an insulating film containing one or more of them. Further, the insulating layer 170 may be a laminate of the above materials. oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaO x), and an insulating film containing one or more of them can be used. Further, the insulating layer 170 may be a laminate of the above materials. oxide (HfOx), and tantalum oxide (TaOx) can use an insulating film containing one or more of them. Further, the insulating layer 170 may be a laminate of the above materials. oxide (TaOx) can use an insulating film containing one or more of them. Further, the insulating layer 170 may be a laminate of the above materials.

[0163] The insulating layer 170 preferably includes an aluminum oxide film. The aluminum oxide film is Has a barrier effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane Therefore, the aluminum oxide film can be used during and after the manufacturing process of the transistor. After manufacturing, the oxidation of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Preventing contamination of the oxide semiconductor layer 121 and the oxide semiconductor layer 122; Preventing emission from the semiconductor layer 121 and the oxide semiconductor layer 122, and eliminating the need for oxygen from the insulating layer 110 It is suitable for use as a protective film having an important emission prevention effect.

[0164] In addition, the insulating layer 170 is preferably a film having an oxygen supplying ability. When the second insulating film is formed, a mixed layer is formed, and the mixed layer or the insulating layer 110 is oxidized. The oxygen diffuses into the oxide semiconductor by the subsequent heat treatment, and the oxide semiconductor is formed. It can replenish oxygen to oxygen deficiencies in the body, improving transistor characteristics (e.g., threshold voltage). , reliability, etc.) can be improved.

[0165] In addition, another insulating layer may be provided above or below the insulating layer 170. For example, an oxide Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulating film containing one or more of neodymium oxide, hafnium oxide, and tantalum oxide may be used. Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), Yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (H f), tantalum (Ta), titanium (Ti), etc. can be included. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) can be used as an insulating film containing one or more. Further, the insulating layer 170 may be a laminate of the above materials. The insulating layer 170 preferably has more oxygen than the stoichiometric composition. Oxygen released from the insulating layer can diffuse through the gate insulating layer 150 to the channel formation region of the oxide semiconductor layer 120. Therefore, oxygen can fill the oxygen vacancies formed in the channel formation region. Thus, stable electrical characteristics of the transistor can be obtained.

[0166] 《Insulating layer 175》 The insulating layer 175 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example , magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (Si OxNx), silicon oxynitride (SiNxOx), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), oxide zirconium (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), acid hafnium (HfOx) and tantalum oxide (TaOx), aluminum oxide (AlO x) can be used as an insulating film containing one or more of them. Further, the insulating layer 175 may be a laminate of the above materials . It is preferable that the insulating layer has more oxygen than the stoichiometric composition .

[0167] Alternatively, the insulating layer 175 may be made of a low dielectric constant material (Low-k material). For example , silicon oxide (SiOF) into which a few percent of fluorine (F) is introduced, silicon oxide (SiOC) into which a few percent of carbon (C) is introduced , fluorinated silicate glass (FSG), organic silicate glass (OSG), hydrogenated silsesquioxane (HSQ), methylsilsesquioxane (M SQ), organic polymers, polyimide, fluororesins (such as polytetrafluoroethylene), fluorine -added amorphous carbon, etc. can be used to form it. By using a Low-k material for the insulating layer 175 , the capacitance related to the transistor 10 can be further reduced .

[0168] <Method for manufacturing a transistor> Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 5 to 13. Note that portions overlapping with those described in the configuration of the above transistor will be omitted . Also, the A1-A2 direction shown in FIGS. 7 to 13 may be referred to as the channel length direction shown in FIGS. 1(A) and 1(B). Further, the A3-A4 direction shown in FIGS. 7 to 13 is the same as the direction shown in FIG. 1(A length direction. ) and may be referred to as the channel width direction shown in Fig. 1(C).

[0169] In this embodiment, each layer (insulating layer, oxide semiconductor layer, conductive layer etc.) constituting the transistor can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method. Alternatively, it can be formed by a coating method or a printing method. As the film formation method, the sputtering method and the plasma chemical vapor deposition (PECVD ) method are representative, but a thermal CVD method may also be used. As an example of the thermal CVD method, MOCVD (organic metal chemical vapor deposition) method or ALD (atomic layer deposition) method may be used.

[0170] <Thermal CVD method> Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0171] Also, in the thermal CVD method, the source gas and the oxidant are simultaneously fed into the chamber, and the inside of the chamber is under atmospheric pressure or reduced pressure, and reacted near or on the substrate to deposit on the substrate to form a film.

[0172] Also, thermal CVD methods such as MOCVD and ALD can form various films such as the metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an In -Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In (CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3 . ​The chemical formula for dimethylzinc is Zn(CH3)2. Not limited to, triethylgallium (chemical formula Ga(C2H5 )3) can be used, and diethylzinc (chemical formula Zn(C2H5 )2) can also be used.

[0173] <ALD法> Conventional CVD deposition equipment requires a precursor gas for the reaction during deposition. One or more of the above are simultaneously supplied to the chamber. Precursors for the reaction are introduced into the chamber in sequence, and the sequence of gas introduction is repeated. For example, each switching valve (also called a high-speed valve) is turned on and off. Two or more precursors are supplied to the chamber in sequence by switching between them, and multiple precursors are mixed. To avoid dust, an inert gas (such as argon or nitrogen) is placed after the first precursor. In addition, instead of introducing an inert gas, the first precursor is introduced. Thus, after the first precursor is evacuated, the second precursor can be introduced.

[0174] 5(A), (B), (C), and (D) show the film formation process by the ALD method. 01 is adsorbed onto the surface of the substrate (see FIG. 5(A)), and a first monolayer is formed (FIG. 5(B)). In this case, metal atoms contained in the precursor bond with hydroxyl groups present on the substrate surface. Metal atoms can be bonded to alkyl groups such as methyl and ethyl groups. The first precursor 601 may be evacuated and then reacted with the second precursor 602 introduced. In response (see FIG. 5(C)), a second monolayer is deposited on the first monolayer to form a thin film. as shown in Fig. 5(D). For example, when an oxidizing agent is included as the second precursor, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent to form an oxide film. Further, if a gas containing hydrogen is used as the second precursor, a metal film can be formed by a reduction reaction.

[0175] The ALD method is a film-forming method based on surface chemical reactions. The precursor adsorbs on the surface of the film to be formed, and a single layer is formed by the action of the self-limiting mechanism. For example, a precursor such as trimethylaluminum reacts with the hydroxyl groups (OH groups) present on the surface of the film to be formed. At this time, since only the surface reaction by heat occurs, the precursor contacts the surface of the film to be formed, and metal atoms, etc. in the precursor can be adsorbed on the surface of the film to be formed through thermal energy. Further, the precursor has a high vapor pressure, is thermally stable and does not self-decompose at the stage before film formation, and has characteristics such as fast chemisorption to the substrate. Also, since the precursor is introduced as a gas, if there is sufficient time for the precursors introduced alternately to diffuse, even in a region having high aspect ratio irregularities, a film can be formed with good coverage.

[0176] Also, in the ALD method, by controlling the gas introduction order and repeating a plurality of times until the desired thickness is reached, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions, precise film thickness adjustment is possible. Also, by increasing the evacuation ability, the film formation speed can be increased, and further, the impurity concentration in the film can be reduced.

[0177] ​​​​​​​​​In addition, ALD methods include an ALD method using heat (thermal ALD method) and an ALD method using plasma ( plasma ALD method). In the thermal ALD method, the reaction of the precursor is carried out using thermal energy, whereas in the plasma ALD method, the reaction of the precursor is carried out in a radical state.

[0178] The ALD method can form an extremely thin film with high precision. Even for a surface with irregularities, the surface coverage rate is high and the film density is high.

[0179] <Plasma ALD> In addition, by forming a film using the plasma ALD method, film formation can be carried out at a lower temperature compared to the ALD method using heat (thermal ALD method). The plasma ALD method can form a film, for example, even at 100°C or lower without reducing the film formation rate. Also, in the plasma ALD method, N2 can be radicalized by plasma, so not only oxides but also nitrides can be formed.

[0180] In addition, in plasma ALD, the oxidizing power of the oxidant can be enhanced. As a result, when film formation is carried out by ALD, the precursor remaining in the film or the organic components desorbed from the precursor can be reduced, and also carbon, chlorine, hydrogen, etc. in the film can be reduced, and a film with a low impurity concentration can be obtained.

[0181] In addition, when performing plasma ALD, radical species can be generated and plasma can be generated in a state separated from the substrate, such as by inductively coupled plasma (ICP), and plasma damage to the substrate or the film on which the protective film is to be formed can be suppressed.

[0182] ​​​ As described above, by using the plasma ALD method, the process temperature can be lowered compared to other film-forming methods, and the surface coverage rate can be increased, enabling the formation of the film. This can suppress the intrusion of water and hydrogen from the outside. Therefore, the reliability of transistor characteristics can be improved.

[0183] <Description of the ALD apparatus> Fig. 6(A) shows an example of a film-forming apparatus using the ALD method. The film-forming apparatus using the ALD method includes a film-forming chamber (chamber 1701), a raw material supply unit 1711a, a raw material supply unit 1711b, high-speed valves 1712a and 1712b which are flow controllers, a raw material inlet 1713 a, a raw material inlet 1713b, a raw material outlet 1714, and an exhaust device 1715. The raw material inlets 1713a and 1713b installed inside the chamber are respectively connected to the raw material supply units 1711a and 1711b via supply pipes and valves, and the raw material outlet 1714 is connected to the exhaust device 1715 via a discharge pipe, a valve, and a pressure regulator.

[0184] Inside the chamber, there is a substrate holder 1716 equipped with a heater, and a film-forming substrate 1700 is placed on the substrate holder.

[0185] In the raw material supply units 1711a and 1711b, raw material gas is formed from solid raw materials or liquid raw materials by means of vaporizers and heating means. Alternatively, the raw material supply units 1711a and 1711b may be configured to supply gaseous raw material gas.

[0186] Also, an example of providing two raw material supply units 1711a and 1711b is shown, but It is not particularly limited, and three or more may be provided. Further, the high-speed valves 1712a and 1712b can be precisely controlled by time, and either the source gas or the inert gas is supplied. It is configured in such a way. The high-speed valves 1712a and 1712b are flow controllers for the source gas and can also be said to be flow controllers for the inert gas. In the film forming apparatus shown in FIG. 6(A), the film forming substrate 1700 is carried onto the substrate holder 1716. After sealing the chamber 1701, the film forming substrate 1700 is heated by the heater of the substrate holder 1716 to a desired temperature (for example, 100 °C or higher or 150 °C or higher), and the supply of the source gas, the evacuation by the evacuation device 1715, the supply of the inert gas, and the evacuation by the evacuation device 1715 are repeated to form a thin film on the substrate surface. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed.

[0187] In the film forming apparatus shown in FIG. 6(A), the film forming substrate 1700 is carried onto the substrate holder 1716, After sealing the chamber 1701, the film forming substrate 1700 is heated by the heater of the substrate holder 1716 to a desired temperature (for example, 100 °C or higher or 150 °C or higher), and the supply of the source gas, the evacuation by the evacuation device 1715, the supply of the inert gas, and the evacuation by the evacuation device 1715 are repeated to form a thin film on the substrate surface. In the film forming apparatus shown in FIG. 6(A), the film forming substrate 1700 is carried onto the substrate holder 1716. After sealing the chamber 1701, the film forming substrate 1700 is heated by the heater of the substrate holder 1716 to a desired temperature (for example, 100 °C or higher or 150 °C or higher), and the supply of the source gas, the evacuation by the evacuation device 1715, the supply of the inert gas, and the evacuation by the evacuation device 1715 are repeated to form a thin film on the substrate surface. In the film forming apparatus shown in FIG. 6(A), the film forming substrate 1700 is carried onto the substrate holder 1716. After sealing the chamber 1701, the film forming substrate 1700 is heated by the heater of the substrate holder 1716 to a desired temperature (for example, 100 °C or higher or 150 °C or higher), and the supply of the source gas, the evacuation by the evacuation device 1715, the supply of the inert gas, and the evacuation by the evacuation device 1715 are repeated to form a thin film on the substrate surface. In the film forming apparatus shown in FIG. 6(A), the film forming substrate 1700 is carried onto the substrate holder 1716. After sealing the chamber 1701, the film forming substrate 1700 is heated by the heater of the substrate holder 1716 to a desired temperature (for example, 100 °C or higher or 150 °C or higher), and the supply of the source gas, the evacuation by the evacuation device 1715, the supply of the inert gas, and the evacuation by the evacuation device 1715 are repeated to form a thin film on the substrate surface.

[0188] In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed. In the film forming apparatus shown in FIG. 6(A), by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, an insulating layer containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. (including composite oxides) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) prepared in the raw material supply parts 1711a and 1711b, thin films such as a tungsten layer, a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed.

[0189] For example, when forming a hafnium oxide layer using a film forming apparatus that utilizes the ALD method, a solvent and a liquid containing a hafnium precursor compound (hafnium alkoxide, hafnium amide such as tetrakis(dimethyl amide)hafnium (TDMAH), etc.) are vaporized to obtain a source gas, and two types of gases, ozone (O3) as an oxidizing agent, are used. In this case, the first source gas supplied from the source supply unit 1711a is TDMAH, and the second source gas supplied from the source supply unit 1711b is ozone. The chemical formula of tetrakis(dimethylamide)hafnium is Hf [N(CH3)2]4. As other materials, there are tetrakis(ethylmethylamide)hafnium, etc. Nitrogen has a function of eliminating charge trapping levels. Therefore, by including nitrogen in the source gas, hafnium oxide with a low charge trapping level density can be formed.

[0190] For example, when forming an aluminum oxide layer using a film forming apparatus that utilizes the ALD method, a solvent and a liquid containing an aluminum precursor compound (such as TMA) are vaporized to obtain a source gas, and two types of gases, H2O as an oxidizing agent, are used. In this case, the first source gas supplied from the source supply unit 1711a is TMA, and the second source gas supplied from the source supply unit 1711b is H 2O. The chemical formula of trimethylaluminum is Al(CH3)3. As other liquid materials, there are tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc.

[0191] For example, when forming a silicon oxide film using a film forming apparatus that utilizes ALD, hexachlorosilane is adsorbed onto the film forming surface, chlorine contained in the adsorbed material is removed, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed material. For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF6 gas and H2 gas are simultaneously introduced to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0192] For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF6 gas and H2 gas are simultaneously introduced to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas. For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF6 gas and H2 gas are simultaneously introduced to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0193] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, and then Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer, and then Zn(CH3)2 and O3 gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed by mixing these gases. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(CH3)2 gas may be used. For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, and then Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer, and then Zn(CH3)2 and O3 gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed by mixing these gases. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(CH3)2 gas may be used. For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, and then Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer, and then Zn(CH3)2 and O3 gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed by mixing these gases. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(CH3)2 gas may be used. For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, and then Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer, and then Zn(CH3)2 and O3 gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed by mixing these gases. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(CH3)2 gas may be used. For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, and then Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer, and then Zn(CH3)2 and O3 gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed by mixing these gases. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(CH3)2 gas may be used.

[0194] 《Multi-chamber Film Forming Apparatus》 Also, an example of a multi-chamber manufacturing apparatus having at least one film-forming apparatus shown in Fig. 6(A) is shown in Fig. 6(B). An example is shown in Fig. 6(B).

[0195] The manufacturing apparatus shown in Fig. 6(B) can continuously form a laminated film without exposing it to the atmosphere, aiming to prevent the incorporation of impurities and improve throughput.

[0196] The manufacturing apparatus shown in Fig. 6(B) has at least a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, a chamber 1701 which is a film-forming chamber, and an unload chamber 1706. Note that the chambers of the manufacturing apparatus (including the load chamber, processing chamber, transfer chamber, film-forming chamber, unload chamber, etc.) are preferably filled with an inert gas (such as nitrogen gas) with a controlled dew point in order to prevent the adhesion of moisture, etc., and preferably maintained under reduced pressure. Also, chambers 1704 and 1705 may be film-forming apparatuses using the same ALD method as chamber 1701,

[0197] or may be film-forming apparatuses using the plasma CVD method, or may be film-forming apparatuses using the sputtering method, or may be film-forming apparatuses using the metalorganic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition) method. For example, as chamber 1704, a film-forming apparatus using the plasma CVD method, and as chamber 1705, a film-forming apparatus using the MOCVD method, an example of forming a laminated film is shown below.

[0198]

[0199]

[0199] In Fig. 6(B), an example of the top view of the transfer chamber 1720 is shown as a hexagon, but depending on the number of layers of the laminated film, Next, it may also be a manufacturing apparatus connected to more chambers as more polygons. . In addition, in FIG. 6(B), the upper surface shape of the substrate is shown as a rectangle, but it is not particularly limited. Also , in FIG. 6(B), an example of a single-wafer type is shown, but it may also be a batch-type film-forming apparatus for forming films on a plurality of substrates at once.

[0200] <Formation of Insulating Layer 110> First, an insulating layer 110 is formed on the substrate 100. The insulating layer 110 can be formed by plasma CVD method, thermal CVD method (MOCVD method, ALD method), or sputtering method, etc. For example, aluminum oxide , magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide , yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide and other oxide insulating films, silicon nitride, silicon oxynitride, aluminum nitride , aluminum oxynitride and other nitride insulating films, or a mixed material thereof can be used for formation. Also, a laminate of the above materials may be used, and at least the upper layer of the laminate in contact with the first oxide semiconductor film that will become the oxide semiconductor layer 121 is preferably formed of a material containing excessive oxygen that can be a source of oxygen for the oxide semiconductor layer 1 22. For example, a silicon oxynitride film with a thickness of 100 nm can be used as the insulating layer 110 by plasma CVD method.

[0201] Next, a heat treatment may be performed to desorb water, hydrogen, etc. contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110, and by the heat treatment , the diffusion amount of water, hydrogen, etc. into the first oxide semiconductor film formed later can be reduced.

[0202] ​

[0203] <Formation of the first oxide semiconductor film and the second oxide semiconductor film> Subsequently, a first oxide semiconductor film that will later become the oxide semiconductor layer 121 and a second oxide semiconductor film that will later become the oxide semiconductor layer 122 are formed on the insulating layer 110. The first oxide semiconductor film, the second oxide semiconductor film can be formed by a sputtering method, an MOCVD method, a PLD method, etc., and it is more preferable to form them using the sputtering method. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, etc. can be used. Also, in the sputtering method, it can be formed by a facing target method (also called a facing electrode method, a gas phase sputtering method, a VDSP (Vapor Deposition Spattering) method), and by this, plasma damage during film formation can be reduced. For example, when the first oxide semiconductor film is formed by the sputtering method, each chamber in the sputtering apparatus should remove water and the like that are impurities for the oxide semiconductor as much as possible, and use an adsorption type vacuum exhaust pump such as a cryopump to achieve a high vacuum (from 5×10 Pa to 1 ×10 Pa or so), and it is preferable that the substrate to be formed can be heated to 100°C or higher, preferably 400°C or higher. Or, it is preferable to combine a turbomolecular pump and a cold trap so that gases containing carbon components, moisture, etc. do not flow back into the chamber from the exhaust system. Also, an exhaust system combining a turbomolecular pump and a cryopump

[0204] -7 Pa to 1 ×10 -4 Pa or so), and it is preferable that the substrate to be formed can be heated to 100°C or higher, preferably 400°C or higher. Or, it is preferable to combine a turbomolecular pump and a cold trap so that gases containing carbon components, moisture, etc. do not flow back into the chamber from the exhaust system. Also, an exhaust system combining a turbomolecular pump and a cryopump can be used so that gases containing carbon components, moisture, etc. do not flow back into the chamber from the exhaust system. Also, an exhaust system combining a turbomolecular pump and a cryopump can be used so that gases containing carbon components, moisture, etc. do not flow back into the chamber from the exhaust system. Also, an exhaust system combining a turbomolecular pump and a cryopump can be used.

[0205] To obtain a high-purity intrinsic oxide semiconductor, not only the chamber should be evacuated to a high vacuum, but also the sputtering Purification of the sputtering gas is also necessary. The oxygen gas and argon gas used as the sputtering gas should have a dew point of -40°C or lower, preferably -80°C or lower, and more preferably -100°C or lower. By using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor film as much as possible.

[0206] As the sputtering gas, noble gas (typically argon), oxygen, or a mixed gas of noble gas and oxygen is appropriately used. In the case of a mixed gas of noble gas and oxygen, it is preferable to increase the gas ratio of oxygen with respect to the noble gas.

[0207] When forming the oxide semiconductor film, for example, when using the sputtering method, the substrate temperature is set to 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, and more preferably 200°C or higher and 420°C or lower. By forming the oxide semiconductor film, a CAAC-OS film can be formed.

[0208] The material of the first oxide semiconductor film can be selected so that its electron affinity is smaller than that of the second oxide semiconductor film.

[0209] In addition, the second oxide semiconductor film may have a higher indium content than the first oxide semiconductor film and the third oxide semiconductor film. In oxide semiconductors, mainly the s orbitals of heavy metals contribute to carrier conduction. By increasing the indium content rate, more s orbitals overlap. Therefore, an oxide having a composition with more indium than gallium has a higher mobility than an oxide having a composition with indium equal to or less than that of gallium. Therefore, by using an oxide with a high indium content for the oxide semiconductor layer 122, a transistor with high mobility can be realized. ​​​​​​​​​​​​ It is.

[0210] Also, in the first oxide semiconductor film and the second oxide semiconductor film, for example, by the sputtering method When forming a film, by using a sputtering apparatus of a multi-chamber system, the first oxide semiconductor film and the second oxide semiconductor film can be continuously formed without being exposed to the atmosphere. In that case It is possible to suppress the entry of unnecessary impurities and the like into the interface between the first oxide semiconductor film and the second oxide semiconductor film and reduce the interface level. As a result, the electrical characteristics of the transistor, especially the characteristics can be stabilized in a reliability test.

[0211] Also, when there is damage in the first oxide semiconductor film to which oxygen is added during oxygen addition, due to the presence of the oxide semiconductor layer 122 the oxide semiconductor layer 123 that becomes the main conduction path can be separated from the damaged part, and as a result, the electrical characteristics of the transistor, especially the characteristics can be stabilized in a reliability test.

[0212] For example, as the first oxide semiconductor film, an oxide semiconductor film formed to a thickness of 20 nm using a target of In:Ga:Zn = 1 :3:4 (atomic ratio) by the sputtering method can be used. Also, as the second oxide semiconductor film, an oxide formed to a thickness of 15 nm using a target of In: Ga:Zn = 1:1:1 (atomic ratio) by the sputtering method semiconductor film can be used.

[0213] Also, by heat treatment after forming the first oxide semiconductor film and the second oxide semiconductor film, the oxygen deficiency amount of the second oxide semiconductor film can be reduced.

[0214] Next, first heat treatment is performed to move part of oxygen to the second oxide semiconductor film. The oxygen vacancies in the oxide semiconductor film can be reduced. The oxide semiconductor film is referred to as a second oxide semiconductor film. In addition, the first heat treatment can reduce oxygen vacancies. Hydrogen, water, and the like contained in the oxide semiconductor film and the second oxide semiconductor film can be released. As a result, the first oxide semiconductor film and the second oxide semiconductor film to which oxygen is added can be formed. The amount of impurities contained in the steel can be reduced.

[0215] The temperature of the first heat treatment is 250° C. or higher and lower than the substrate distortion point, preferably 300° C. or higher and 650° C. or higher. °C or less, and more preferably 350°C to 550°C.

[0216] The first heat treatment is performed using a rare gas such as helium, neon, argon, xenon, krypton, or the like. or in an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, Atmosphere or dry air (dew point below -80°C, preferably below -100°C, preferably below - Heating may be performed in an air atmosphere at 120°C or less, or under reduced pressure. In addition to the dry air, it is preferable that the inert gas and oxygen gas do not contain hydrogen, water, etc. Typically, the dew point is -80°C or less, preferably -100°C or less. Treatment times range from 3 minutes to 24 hours.

[0217] In the first heat treatment, a heat transfer heater such as a resistance heater is used instead of an electric furnace. A device that heats the workpiece by induction or thermal radiation may be used. For example, the GRTA ( Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Ra pid Thermal Anneal) equipment, etc., RTA (Rapid Thermal Anneal) equipment can be used. The LRTA equipment is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps , high-pressure mercury lamps, etc. The GRTA equipment is a device that performs a first heat treatment using a high-temperature gas. For the high-temperature gas, an inert gas such as a noble gas like argon or nitrogen is used. .

[0218] Note that the first heat treatment may be performed after the etching for forming the oxide semiconductor layer 121 and the oxide semiconductor layer 122 described later.

[0219] For example, in a nitrogen atmosphere, after performing a heat treatment at 450°C for 1 hour, in an oxygen atmosphere, a heat treatment at 450°C for 1 hour can be performed.

[0220] Through the above steps, the oxygen deficiency of the oxide semiconductor film can be reduced, and impurities such as hydrogen and water can be reduced. Also, an oxide semiconductor film with a reduced localized level density can be formed.

[0221] <Formation of the First Conductive Film> Next, a first conductive film that will become the source electrode layer 130 and the drain electrode layer 140 is formed on the oxide semiconductor layer 123. The first conductive film is formed by a sputtering method, a chemical vapor deposition (CVD) method ( metalorganic chemical vapor deposition (MOCVD) method, metal chemical vapor deposition method, atomic layer deposition (ALD) method, ​Alternatively, it includes a plasma chemical vapor deposition (PECVD) method, etc., and can be formed by using a vapor deposition method, a pulsed laser deposition (PLD) method, etc.

[0222] The material of the first conductive film is a single substance, alloy, or compound mainly composed of these, including copper (Cu), tungsten (W), molybdenum (Mo), gold (A u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S r). It is preferably a single layer or a laminate of a conductive film. For example, when laminating, the lower conductive layer in contact with the oxide semiconductor layer 1 22 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W ) or molybdenum (Mo) that combines heat resistance and conductivity. Further, it is preferably formed of a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu -Mn alloy, a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, so it is preferable.

[0223] For example, a tungsten film with a thickness of 20 to 100 nm can be formed as the first conductive film by sputtering.

[0224] Note that the conductive layer 130b formed by processing the first conductive film in a later process has a function as a hard mask and functions as a source electrode layer and a drain electrode layer in a later process. It is possible to reduce the semiconductor manufacturing process because additional film formation steps are not required. .

[0225] <Formation of Oxide Semiconductor Layers 121 and 122> Next, a resist mask is formed by a lithography process, and using this resist mask, the first conductive film is selectively etched to form a conductive layer 130b. Subsequently, after removing the resist on the conductive layer 13 0b, using the conductive layer 130b as a hard mask, the second oxide semiconductor film and the first oxide semiconductor film are selectively etched respectively, and the oxide semiconductor layers 122 and oxide semiconductor layer 121 can be formed in an island shape (see Fig. 7). Note that as the etching method , a dry etching method can be used. Note that by using the conductive layer 130b as a hard mask to etch the oxide semiconductor layer, the edge roughness of the oxide semiconductor layer after etching can be reduced compared with a resist mask.

[0226] For example, as the etching gas, methane gas and argon gas are used, and by selectively etching the first oxide semiconductor film and the second oxide semiconductor film using the resist mask and hard mask, the oxide semiconductor layers 121 and 122 can be formed.

[0227] <Deposition of Second Insulating Film> Next, a second insulating film is deposited on the insulating layer 110 and the conductive layer 130b.

[0228] The second insulating film and the third insulating film can be formed by plasma CVD method, thermal CVD method (MOCVD method, ALD method), or sputtering method, etc. For example, aluminum oxide (SiOx), magnesium oxide Magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx ), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdO x), hafnium oxide (HfOx), and tantalum oxide (TaOx), etc., oxide insulating films , silicon nitride (SiNx), silicon oxynitride (SiNxOy), aluminum nitride ( AlNx), aluminum oxynitride (AlNxOy), etc., nitride insulating films, or these mixed materials can be used to form. Also, a laminate of the above materials may be used.

[0229] Note that as the second insulating film, it is desirable to form an aluminum oxide film by sputtering. Also, as the sputtering target, it is desirable to use aluminum oxide. Also, as the gas used during film formation, it is desirable to have oxygen gas.

[0230] When forming the aluminum oxide film, a mixed layer 171 is formed at the interface with the insulating layer 110.

[0231] For example, the oxygen gas used during the formation of the second insulating film exists in various states such as oxygen radicals, oxygen ions, oxygen atoms, etc., due to the influence of the voltage, power, plasma, substrate temperature, etc. applied during film formation by sputtering, and has a state with higher energy compared to the stable state. At this time, oxygen (excess oxygen, referred to as exO) 172 is added to the insulating layer 110 or the mixed layer 171 (see Fig. 8).

[0232] Next, a second heat treatment may be performed. The second heat treatment is typically 150 °C or higher based ​​Less than the board warping point, preferably 250 ° C or higher and 500 ° C or lower, more preferably 300 ° C or higher and 45 0 ° C or lower. By the heat treatment, oxygen 172 added to the insulating layer 110 and the mixed layer diffuses and moves to the oxide semiconductor layer 122, and oxygen can be supplied to oxygen vacancies existing in the oxide semiconductor layer 122 (see Fig. 9).

[0233] For example, by a sputtering method, using an aluminum oxide (AlOx) target, A second insulating film can be formed by containing 50% by volume of oxygen gas as a gas during sputtering. The thickness can be 20 nm to 40 nm. Also, as the second heat treatment, It can be treated at 400 ° C for 1 hour in an oxygen atmosphere.

[0234] <Addition of oxygen> In addition, when manufacturing the transistor 10, the process is not limited to the above method, and a process of adding oxygen may be performed separately. The process of adding oxygen may be performed on the insulating layer 110, or on the first oxide semiconductor film, and the third oxide semiconductor film 123a described later. As the oxygen to be added, any one or more of oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. are used. As a method of adding oxygen, there are ion doping method, ion implantation method, plasma immersion ion implantation method, etc.

[0235] When the ion implantation method is used as the method of adding oxygen, oxygen atomic ions may be used or oxygen molecular ions may be used. When oxygen molecular ions are used, damage to the film to which they are added can be reduced. Oxygen molecular ions are separated on the surface of the film to which the oxygen is added and added as oxygen atomic ions. In order to separate oxygen molecules into oxygen atoms ​ When oxygen molecular ions are added to the film to which the oxygen is added because energy is used the energy per oxygen atomic ion in is lower than when oxygen atomic ions are added to the film to which the oxygen is added This can reduce the damage to the film to which the oxygen is added to a low level

[0236] Also, when injecting oxygen molecular ions, the energy per oxygen atomic ion is lower than when injecting oxygen atomic ions Therefore, by using oxygen molecular ions for injection it is possible to increase the acceleration voltage and increase the throughput. Also by using oxygen molecular ions for injection, it is possible to halve the dose amount for adding the same amount of oxygen atomic ions compared to the case of using oxygen atomic ions As a result, the throughput of the manufacturing process can be increased to a high level

[0237] Also, when adding oxygen to the film to which the oxygen is added, it is preferable to add oxygen to the film to which the oxygen is added under conditions such that the peak of the concentration profile of oxygen atomic ions is located in the film to which the oxygen is added. As a result compared to the case of injecting oxygen atomic ions it is possible to lower the acceleration voltage during injection and reduce the damage to the film to which the oxygen is added That is, it is possible to reduce the amount of defects in the film to which the oxygen is added and suppress fluctuations in the electrical characteristics of the transistor. As a result it is possible to reduce the damage to the film to which the oxygen is added and suppress fluctuations in the electrical characteristics of the transistor to a low level

[0238] Also, the film to which the oxygen is added is exposed to the plasma generated in an atmosphere containing oxygen, and oxygen is added to the film to which the oxygen is added by plasma treatment (plasma immersion ion implantation method). This is also possible. As the atmosphere containing oxygen, there is an atmosphere containing oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. In addition, by exposing the film to which the oxygen is added to the plasma generated while a bias is applied to the substrate 100 side, it is possible and preferable to increase the amount of oxygen added to the film to which the oxygen is added. As an example of an apparatus for performing such plasma treatment, there is an ashing apparatus.

[0239]

[0240] 16 / cm 2 For example, oxygen molecular ions with an acceleration voltage of 5 kV and a dose amount of 1×10 can be added to the first oxide semiconductor film by ion implantation method.

[0240] By combining the above steps and subsequent heat treatment, the oxygen deficiency amount of the oxide semiconductor layer 122 can be reduced. Note that the film to which oxygen is added has a lower film density compared to the film before oxygen addition.

[0241] <Formation of the third insulating film> Next, a third insulating film is formed on the second insulating film. The third insulating film is formed by plasma CVD method, thermal CVD method (MOCVD method, ALD method), sputtering method, or spin coating method, etc. For example, aluminum oxide (SiOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (Zr oxide (ZrOx), hafnium oxide (HfOx), tantalum oxide (TaOx), titanium oxide (TiO2), Ox), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (Hf Ox) and oxide insulating films such as tantalum oxide (TaOx), silicon nitride (SiNx) , silicon oxynitride (SiNxOy), aluminum nitride (AlNx), aluminum oxynitride (AlNxOy) and other nitride insulating films, or formed using a mixture of these materials can be. Also, a laminate of the above materials may be used.

[0242] Alternatively, the third insulating film may be made of a low dielectric constant material (Low-k material). For example , silicon oxyfluoride (SiOF) with a few percent of fluorine (F) introduced, silicon oxycarbide (SiOC) with a few percent of carbon (C) introduced , fluorinated silicate glass (FSG), organosilicate glass (OSG), hydrogenated silsesquioxane (HSQ), methylsilsesquioxane (M SQ), organic polymers, fluororesins (polytetrafluoroethylene), polyimides, fluorine added amorphous carbon, etc. can be used to form it.

[0243] Note that the second heat treatment may be performed after forming the third insulating film.

[0244] <Planarization of the Third Insulating Film> Next, a planarization process of the third insulating film is performed to form the insulating layer 175b. The planarization process can be performed using C MP (Chemical Mechanical Polishing) method, dry etching method, reflow method, etc. Also, when planarizing using the CMP method a film having a different composition from the third insulating film is introduced onto the third insulating film, so that C the film thickness of the insulating layer 175 in the substrate plane after CMP treatment can be made uniform.

[0245] Note that the second heat treatment may be performed after the third insulating film is planarized.

[0246] <Formation of Groove, Source Electrode Layer 130, and Gate Insulating Layer 150> Next, a resist mask 176 is formed on the insulating layer 175b by a lithography process (FIG. 10). Note that after applying an organic film onto the insulating layer 175b, or after applying a resist The lithography process may be performed after applying an organic film. It contains cholesteryl monomethyl ether, ethyl lactate, etc., and acts as an anti-reflective coating (BA) during exposure. RC (Bottom Anti Reflective Coating) function In addition, it is known to have the effect of improving the adhesion between the resist and the film and improving the resolution. can.

[0247] In addition, when forming a transistor with an extremely short channel length, at least the source electrode layer 130, in the region dividing the conductive layer 130b which becomes the drain electrode layer 140, an electron beam is Resist mask processing using methods suitable for fine line processing such as nanoimprint exposure, immersion exposure, and EUV exposure. Then, the region is etched by the etching process. When forming a resist mask by light, a positive resist is used as the resist mask. If such a device is used, the exposure area can be minimized and throughput can be improved. Using this method, it is possible to reduce the channel length to 100 nm or less, or even to 30 nm or less. A transistor can be formed. Or, light with a very short wavelength (e.g., extreme ultraviolet light) (EUV: Extreme Ultraviolet) and X-ray exposure technology Fine processing may be performed by techniques.

[0248] Using the resist mask, groove processing is performed on the insulating layer 175b by a dry etching method. By selectively proceeding with the etching process, a groove portion 174 is formed in the insulating layer 175.

[0249] Subsequently, the exposed conductive layer 130b is selectively etched in a form that divides it, and the source electrode layer 1 30 and the drain electrode layer 140 can be formed (see FIG. 11).

[0250] Note that after forming the source electrode layer 130 and the drain electrode layer 140, a cleaning process may be performed to remove etching residues. By performing this cleaning process, short - circuiting between the source electrode layer 130 and the drain electrode layer 140 can be suppressed. The cleaning process can be performed using an alkaline solution such as a TMAH (Tetramethylammonium Hydroxide) solution, or an acidic solution such as diluted hydrofluoric acid, oxalic acid, or phosphoric acid. Note that due to the cleaning process, a part of the oxide semiconductor layer 122 is etched, and a concave portion is formed in the oxide semiconductor layer 1 22. 22.

[0251] Note that the formation order of the oxide semiconductor layer 121, the oxide semiconductor layer 122, the source electrode layer 130, and the drain electrode layer 140 can be changed. For example, the groove portion 174 for forming the source electrode layer 130 and the drain electrode may be provided first, and then the oxide semiconductor layer 121 and the oxide semiconductor layer 122 may be formed.

[0252] For example, after planarizing the silicon oxynitride film formed as the second insulating film, a resist mask is formed on the silicon oxynitride film, and the resist mask and a gas having carbon and fluorine ​​​​​Dry etching is performed using the above to perform an opening process on the silicon oxynitride, and chlorine, The conductive layer 130b is dry-etched using a fluorine-based gas, whereby the source electrode layer 130 and the drain electrode layer 140 can be formed.

[0253] <Formation of the third oxide semiconductor film 123a> Next, a third oxide semiconductor film 123a used as the oxide semiconductor layer 123 is formed on the oxide semiconductor layer 122 and the insulating layer 175. The third oxide semiconductor film 123a can be formed in the same manner as the first oxide semiconductor film, and the material of the third oxide semiconductor film 123a can be selected so that its electron affinity is smaller than that of the second oxide semiconductor film.

[0254] For example, as the third oxide semiconductor film 123a, an oxide semiconductor film formed by sputtering with a target of In:Ga: Zn = 1:3:2 (atomic ratio) and having a thickness of 5 nm can be used.

[0255] <Formation of the insulating film 150a> Next, a fourth insulating film 150a that becomes the gate insulating layer 150 is formed on the oxide semiconductor film 123a. For the fourth insulating film 150a, for example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy) nitrided silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide and the like can be used. Note that the fourth insulating film 150a may be a laminate of the above materials. The fourth insulating film 150a can be formed by sputtering, CVD method (plasma CVD method, MOCV It can be formed using, for example, the D method, the ALD method, the MBE method, etc. Also, the fourth insulating film 150a can be formed by appropriately using the same method as the insulating layer 110 to form an insulating film. .

[0256] For example, as the fourth insulating film 150a, silicon oxynitride can be formed to a thickness of 10 nm by plasma CVD.

[0257] <Formation of the conductive film 160a> Next, a second conductive film 160a that becomes the gate electrode layer 160 is formed on the fourth insulating film 150a. (See FIG. 12). As the second conductive film 160a, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), or an alloy material mainly composed of these can be used. The second conductive film 160a can be formed by sputtering, CVD (such as plasma CVD, MOCVD, ALD), MBE, evaporation, plating, etc. Also, as the second conductive film 160a, a conductive film containing nitrogen may be used, or a laminate of the above conductive film and a conductive film containing nitrogen may be used. Also, the second conductive film 160a may be a single layer or a laminate. For example, as the conductive film 160a, a laminated structure of 10 nm of titanium nitride by ALD and 150 nm of tungsten by metal-organic CVD can be formed.

[0258]

[0259] <Planarization treatment> Next, a planarization process is performed. The planarization process can be carried out using a CMP method, a dry etching method, or the like. The planarization process may end when the third insulating film 150a is exposed. It may also end when the third oxide semiconductor film 123a is exposed, or when the insulating layer 175 is exposed. Thereby, the gate electrode layer 160, the gate insulating layer 150 , and the oxide semiconductor layer 123 can be formed (see FIG. 13).

[0260] In addition, when the oxide semiconductor film 123a or the insulating film 150a is provided on the planarized insulating layer 175, processing may be performed using a new resist mask. A resist mask is formed on the oxide semiconductor film 1 23a or the insulating film 150a by a lithography process. The mask has an area wider than the upper surface portion of the gate electrode layer 160, and by using the mask, the insulating film 150a and the oxide semiconductor film 123a are selectively etched, and the gate insulating layer 150 and the oxide semiconductor layer 123 can be formed.

[0261] In the transistor 10, by providing the oxide semiconductor layer 123 in which oxygen deficiency is less likely to occur, desorption of oxygen from the side surface of the oxide semiconductor layer 123 in the channel width direction is suppressed, and generation of oxygen deficiency can be suppressed. As a result, electrical characteristics are improved, and a highly reliable transistor can be realized.

[0262] Next, a third heat treatment may be performed. The heat treatment is typically performed at a temperature of 150°C or higher and below the substrate distortion point, preferably 250°C or higher and 500°C or lower, more preferably 300°C or higher and 450 °C or lower. By the heat treatment, additives are added to the insulating layer (for example, the insulating layer 175). The supplied oxygen diffuses and moves to the oxide semiconductor layer 122, and can supply oxygen to the oxygen vacancies present in the oxide semiconductor layer 122.

[0263] For example, heat treatment can be performed at 400 °C for 1 hour in an oxygen atmosphere.

[0264] Through the above steps, the density of localized levels in the oxide semiconductor film is reduced, and a transistor having excellent electrical characteristics can be fabricated. In addition, a highly reliable transistor with little variation in electrical characteristics due to changes over time and stress tests can be fabricated.

[0265] <Modification Example 1 of Transistor 10: Transistor 11> For a transistor 11 having a shape different from that of the transistor 10 shown in FIG. 1, it will be described with reference to FIG. 14.

[0266] FIGS. 14(A), 14(B), and 14(C) are top views and cross-sectional views of the transistor 11. FIG. 14(A) is a top view of the transistor 11, and FIG. 14(B) is a cross-sectional view taken between the dashed line A1 - A2 in FIG. 14(A ), and FIG. 14(C) is a cross-sectional view taken between A3 - A4.

[0267] The transistor 11 is different from the transistor 10 in that it has a conductive layer 135 in contact with the side surfaces (excluding the channel region) of the oxide semiconductor layer 121 and the oxide semiconductor layer 122, the side surfaces of the source electrode layer 130 and the drain electrode layer 140, the side surfaces and the top surface of the insulating layer 110, and the bottom surface of the insulating layer 170. The conductive layer 135 has a sidewall shape as shown in FIG. 14(B).

[0268] 《Conductive Layer 135》 The conductive layer 135 contains copper (Cu), tungsten (W), molybdenum (Mo), gold (Au) , aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co ), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) made of a single substance, alloy, or a single layer or laminate of a conductive layer containing compounds such as oxygen, nitrogen, fluorine, silicon, etc., mainly composed of these is preferred. For example , when laminating, the lower conductive layer in contact with the oxide semiconductor layer 122 has a material that easily binds to oxygen and the upper conductive layer can have a material with strong oxidation resistance. Also, high melting point materials such as tungsten and molybdenum that combine heat resistance and conductivity are preferably used . Also, it is preferably formed of a low-resistance conductive material such as aluminum or copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, so it is preferable.

[0269] By having the conductive layer 135, the area of the conductive layer in contact with the oxide semiconductor layer 121 and the oxide semiconductor layer 122 can be increased, and the on-current can be increased.

[0270] <Transistor 10 Modification Example 2: Transistor 12> For a transistor 12 having a different shape from the transistor 10 shown in FIG. 1, it will be described with reference to FIGS. 15 and 1 6.

[0271] FIGS. 15(A), 15(B), and 15(C) are top views and cross-sectional views of the transistor 12. FIG. 15(A) is a top view of the transistor 12, and FIG. 15(B) is a view taken along the line of FIG. 15(A Between the dashed lines A1 - A2 of (), Fig. 15(C) is a cross-sectional view between A3 - A4.

[0272] Transistor 12 has a conductive layer 165 on the lower side of the insulating layer 110, an insulating layer 175, an oxide semiconductor layer 123, a gate insulating layer 150, and an insulating layer 177 on the upper surface of the gate electrode layer 160, which is different from transistor 10 in this regard.

[0273] 《Conductive layer 165》 The conductive layer 165 can function as a bottom gate. The conductive layer 165 can be given the same potential as the gate electrode layer 160 or a different potential. The conductive layer 165 can be made of, for example, a single substance, alloy, or a single layer or laminate of a conductive layer containing compounds such as oxygen, nitrogen, fluorine, silicon, etc. with these as the main components, made of materials such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta ), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium For example, the conductive layer 166 can have a material with strong oxidation resistance. Also, for the conductive layer 1 67, it is preferable to use high melting point materials such as tungsten and molybdenum that can achieve both heat resistance and conductivity. Also, it is preferably formed of a low resistance conductive material such as aluminum or copper.

[0274] 《Insulating layer 177》 The insulating layer 177 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), indium​​​​​ Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (Hf) For example, the metals may include hafnium (Hf), tantalum (Ta), titanium (Ti), etc. , Aluminum oxide (AlOx), Magnesium oxide (MgOx), Silicon oxide (Si Ox), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), nitride Silicon (SiNx), Gallium oxide (GaOx), Germanium oxide (GeOx), Acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaO The insulating layer 177 can be a laminate of the above materials. may be also possible.

[0275] The insulating layer 177 preferably includes an aluminum oxide film. The aluminum oxide film is Has a barrier effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane Therefore, the aluminum oxide film can be used during and after the manufacturing process of the transistor. After manufacturing, the oxidation of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Preventing contamination of the oxide semiconductor layer 121 and the oxide semiconductor layer 122; Preventing emission from the semiconductor layer 121 and the oxide semiconductor layer 122, and eliminating the need for oxygen from the insulating layer 175 It is suitable for use as a protective film having an important emission prevention effect.

[0276] The insulating layer 177 is preferably a film having an oxygen supplying ability. It is preferable to form the insulating layer 177 by a sputtering method. A mixed layer is formed at the interface with the insulating layer 175, and oxygen-17 can be added to the mixed layer or the insulating layer 175. 2 can be added.

[0277] After forming the insulating layer 177, the transistor 12 can be subjected to a third heat treatment. The third heat treatment can typically be performed at a temperature of 150°C or higher and lower than the substrate distortion point, preferably 250°C or higher and 500°C or lower, more preferably 300°C or higher and 450°C or lower. By the third heat treatment, although it diffuses after being added to the insulating layer 175, it moves to the oxide semiconductor layer 121 and the oxide semiconductor layer 122, and oxygen can be supplied to the oxygen vacancies existing in the oxide semiconductor layer 122.

[0278] Also, the third heat treatment can also serve as the second heat treatment. As a result, oxygen-17 added to the insulating layer 1 10 and the insulating layer 175 moves to the oxide semiconductor layer 122 through the gate insulating layer 150, the oxide semiconductor layer 1 23, the oxide semiconductor layer 121, etc., and oxygen can be supplied to the oxygen vacancies existing in the oxide semiconductor layer 122 (see Fig. 16). .

[0279] Thereby, the transistor characteristics (e.g., threshold value, reliability, etc.) of the transistor 12 can be improved.

[0280] Note that as shown in Fig. 17, the transistor 12 can have a structure in which transistors are arranged in parallel (transistor 13) (see Fig. 17). Furthermore, as shown in Fig. 18, the transistor 13 has an insulating layer 180 on the insulating layer 170 and a conductive layer 1 90 (conductive layer 191, conductive layer 192) on the gate electrode layer 160, and the gate electrode layer 160 and the conductive layer 190 are electrically ​​​It can have a structure connected in a spiritual manner.

[0281] Also, the insulating layer 180 can be formed of the same material as the insulating layer 175. Also, the conductive layer 190 can be formed of the same material as the gate electrode layer 160.

[0282] The transistor 13 can increase the on-current while showing good transistor characteristics.

[0283] Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0284] (Embodiment 2) In this embodiment, a transistor 14 having a structure different from that of the transistor 10 described in Embodiment 1, and a method for manufacturing the transistor 14 will be described.

[0285] <Transistor 14> FIGS. 19(A), 19(B), and 19(C) are top views and cross-sectional views of a transistor 14 according to an aspect of the present invention. FIG. 19(A) is a top view, FIG. 19(B) is a cross-sectional view taken between the dashed line A1 - A2 in FIG. 19(A), and FIG. 19(C) is a cross-sectional view taken between the dashed line A3 - A4 in FIG. 19(A). Also, in FIG. 19(A), some elements are enlarged, reduced, or omitted for clarity of the drawing. Also, the direction of the dashed line A1 - A2 may be referred to as the channel length direction, and the direction of the dashed line A3 - A4 may be referred to as the channel width direction. As shown in FIGS. 19(A), 19(B), and 19(C), in the groove 17 4, the transistor 14 has an insulating layer 185 on the upper surfaces of the source electrode layer 130 and the drain electrode layer 140.

[0286] ​​​​​​The point where it is located is different from that of transistor 10. The insulating layer 185 is in contact with the side surface of the insulating layer 170 and the insulating layer 175 and has an oxide semiconductor layer 123 on the upper side of the insulating layer 185.

[0287] 《Insulating layer 185》 The insulating layer 185 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNx), silicon nitride oxide (SiNxOx), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum oxide (AlOx) can be used as an insulating film containing one or more of them. Also, the insulating layer 185 may be a laminate of the above materials. It is preferable that the insulating layer has more oxygen than the stoichiometric composition.

[0288] Alternatively, the insulating layer 185 may be made of a low dielectric constant material (Low-k material). For example, silicon oxide with a few percent of fluorine (F) introduced (SiOF), silicon oxide with a few percent of carbon (C) introduced (SiOC), fluorinated silicate glass (FSG), organic silicate glass (OSG), hydrogenated silsesquioxane (HSQ), methylsilsesquioxane (M) SQ), organic polymers, polyimides, fluororesins (polytetrafluoroethylene), fluorine-added amorphous carbon, etc. It can be formed using, for example. By using a Low-k material for the insulating layer 185, the capacitance related to the transistor 14 can be further reduced. It can be further reduced.

[0289] Since the transistor 14 has the insulating layer 185, processing below the resolution limit of the device can be performed, enabling finer processing, and thus development costs such as the introduction of new equipment can be suppressed.

[0290] <Fabrication method of transistor 14> The fabrication method of the transistor 14 will be described below. For the same processes as the transistor 10 described in Embodiment 1, the description thereof will be incorporated herein by reference.

[0291] As shown in FIGS. 20(A) and 20(B), after forming the insulating layer 170 and the insulating layer 175b, a resist mask 176 for forming a groove portion is formed. The resist mask 176 can have a wider groove dimension (looser design rule) compared to the fabrication of the transistor 10.

[0292] Next, the insulating layer 175b is selectively etched using the resist mask 176 to form the insulating layer 175.

[0293] Next, a fourth insulating film that will become the insulating layer 185 is formed. The fourth insulating film can be formed by, for example, plasma CVD method, thermal CVD method (MOCVD method, ALD method), sputtering method, or spin coating method.

[0294] Next, an etch-back process is performed using a dry etching method to form the insulating layer 185. ​

[0295] Next, the insulating layer 185 is used as a hard mask until the oxide semiconductor layer 122 is exposed. The conductive layer 130b is selectively etched to form the source electrode layer 130 and the drain electrode layer 140. (See FIG. 21).

[0296] Next, the third oxide semiconductor film 123a, the third insulating film 150a, and the conductive film 160a are sequentially formed (see FIG. 22), and the transistor 14 is fabricated by performing a planarization process (see FIG. 23). (See FIG. 23). In addition, this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0297] It can be done.

[0298] (Embodiment 3) (Structure of Oxide Semiconductor) In this embodiment, the structure of the oxide semiconductor will be described.

[0299] Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline Oxide Semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous like Oxide Semiconductor), and amorphous oxide semiconductors.

[0300] From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystalline oxide semiconductors, CAAC-O There are S, polycrystalline oxides, nc-OS, etc.

[0301] Generally, the definition of an amorphous structure is that it is not fixed in a metastable state, is isotropic, and has no heterogeneous structure. Also, it can be rephrased as a structure with flexible bond angles, having short-range order but no long-range order. In the case of an oxide semiconductor that is essentially stable, it cannot be called a completely amorphous oxide semiconductor. Also, an anisotropic (for example, having a periodic structure in a microscopic region) oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although a-like OS has a periodic structure in a microscopic region, it has voids and is an unstable structure. Therefore, it can be said that its physical properties are close to those of an amorphous oxide semiconductor.

[0302] Conversely, (e.g., having a periodic structure in a microscopic region)

[0303] <caac-os> First, CAAC-OS will be described.

[0304] CAAC-OS is one of the oxide semiconductors having a plurality of c-axis oriented crystal parts (also referred to as pellets). conductors.

[0305] Using a transmission electron microscope (TEM: Transmission Electron Micro scope), when observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of CAAC-OS, a plurality of pellets can be confirmed. On the other hand In a high-resolution TEM image, the boundaries between pellets, that is, grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries.

[0306] Hereinafter, CAAC-OS observed by TEM will be described. FIG. 24(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function was used. A high-resolution TEM image using a spherical aberration correction function is specifically referred to as a Cs-corrected high-resolution TEM image. The acquisition of a Cs-corrected high-resolution TEM image can be performed, for example, by an atomic-resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

[0307] A Cs-corrected high-resolution TEM image obtained by enlarging the region (1) in FIG. 24(A) is shown in FIG. 24(B). From FIG. 24(B), it can be confirmed that in the pellet, metal atoms are arranged in layers. ​​​​​​​。The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface on which the CAAC-OS film is formed, and is parallel to the surface to be formed or the upper surface of the CAAC-OS. That is, it is parallel to the surface to be formed or the upper surface of the CAAC-OS, reflecting the unevenness of the surface to be formed or the upper surface.

[0308] As shown in FIG. 24(B), CAAC-OS has a characteristic atomic arrangement. FIG. 24(C) shows the characteristic atomic arrangement indicated by auxiliary lines. From FIGS. 24(B) and 24(C) it can be seen that the size of one pellet is 1 nm or more or 3 nm or more, and the size of the gap generated by the inclination between the pellets is about 0.8 nm. Therefore, the pellet can also be called a nanocrystal (nc). Also, CAAC-OS can also be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). 。 。

[0309] Here, based on the Cs-corrected high-resolution TEM image, when schematically showing the arrangement of the pellets 5100 of CAAC-OS on the substrate 5120, it has a structure like bricks or blocks stacked (see FIG. 24(D)). The location where the inclination occurs between the pellets observed in FIG. 24(C) corresponds to the region 5161 shown in FIG. 24(D). 。 。

[0310] Also, FIG. 25(A) shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The enlarged Cs-corrected high-resolution TEM images of the regions (1), (2), and (3) in FIG. 25(A) are shown in FIGS. 25(B), 25(C), and FIG. 25(D), respectively. From FIGS. 25(B), 25(C), and 25(D), it can be confirmed that the metal atoms in the pellets are arranged in a triangular, square, or hexagonal shape. However, 。 。 。 However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0311] Next, CA analyzed by X-ray diffraction (XRD) AC-OS will be described. For example, for CAAC-OS having a crystal of InGaZnO4 when performing a structural analysis by the out-of-plane method, as shown in Fig. 26(A) a peak may appear at around a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZ nO4 crystal, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0312] In the structural analysis of CAAC-OS by the out-of-plane method, in addition to the peak around 2θ of 31° a peak may also appear at around 2θ of 36°. The peak around 2θ of 36° indicates that a part of CAAC-OS contains crystals without c-axis orientation. More preferable CAAC-OS shows a peak at around 2θ of 31° and does not show a peak at around 2θ of 36° in the structural analysis by the out-of-plane method.

[0313] On the other hand, when performing a structural analysis of CAAC-OS by the in-plan e method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears at around 2θ of 56°. This peak is attributed to the (110) plane of the In GaZnO4 crystal. In the case of CAAC-OS, even when the analysis ( φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56° as shown in Fig. 26(B), no distinct peak appears. In contrast When the single-crystalline oxide semiconductor is InGaZnO4 and 2θ is fixed near 56° and φ is scanned, six peaks attributed to crystal planes equivalent to the (110) plane are observed as shown in Fig. 26(C). Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular orientations of the a-axis and b-axis. Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface on a CAAC-OS having a crystal of InGaZnO4, a diffraction pattern (also referred to as a limited-field transmission electron diffraction pattern) as shown in Fig. 27(A) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it can also be seen by electron diffraction that the pellets included in the CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, Fig. 27(B) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface on the same sample. From Fig. 27(B), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen by electron diffraction that the a-axis and b-axis of the pellets included in the CAAC-OS do not have orientation. Note that the first ring in Fig. 27(B) is considered to be due to the (010) plane and the (100) plane, etc. of the InGaZnO4 crystal. Also, the second ring in Fig. 27(B) is considered to be due to the (110) plane, etc. As described above, the CAAC-OS is a highly crystalline oxide semiconductor.

[0314] As described above, the CAAC-OS is a highly crystalline oxide semiconductor. When the single-crystalline oxide semiconductor is InGaZnO4 and 2θ is fixed near 56° and φ is scanned, six peaks attributed to crystal planes equivalent to the (110) plane are observed as shown in Fig. 26(C). Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular orientations of the a-axis and b-axis. Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface on a CAAC-OS having a crystal of InGaZnO4, a diffraction pattern (also referred to as a limited-field transmission electron diffraction pattern) as shown in Fig. 27(A) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it can also be seen by electron diffraction that the pellets included in the CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, Fig. 27(B) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface on the same sample. From Fig. 27(B), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen by electron diffraction that the a-axis and b-axis of the pellets included in the CAAC-OS do not have orientation. Note that the first ring in Fig. 27(B) is considered to be due to the (010) plane and the (100) plane, etc. of the InGaZnO4 crystal. Also, the second ring in Fig. 27(B) is considered to be due to the (110) plane, etc. As described above, the CAAC-OS is a highly crystalline oxide semiconductor. When the single-crystalline oxide semiconductor is InGaZnO4 and 2θ is fixed near 56° and φ is scanned, six peaks attributed to crystal planes equivalent to the (110) plane are observed as shown in Fig. 26(C). Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular orientations of the a-axis and b-axis. Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface on a CAAC-OS having a crystal of InGaZnO4, a diffraction pattern (also referred to as a limited-field transmission electron diffraction pattern) as shown in Fig. 27(A) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it can also be seen by electron diffraction that the pellets included in the CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, Fig. 27(B) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface on the same sample. From Fig. 27(B), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen by electron diffraction that the a-axis and b-axis of the pellets included in the CAAC-OS do not have orientation. Note that the first ring in Fig. 27(B) is considered to be due to the (010) plane and the (100) plane, etc. of the InGaZnO4 crystal. Also, the second ring in Fig. 27(B) is considered to be due to the (110) plane, etc. As described above, the CAAC-OS is a highly crystalline oxide semiconductor. When the single-crystalline oxide semiconductor is InGaZnO4 and 2θ is fixed near 56° and φ is scanned, six peaks attributed to crystal planes equivalent to the (110) plane are observed as shown in Fig. 26(C). Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular orientations of the a-axis and b-axis. Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface on a CAAC-OS having a crystal of InGaZnO4, a diffraction pattern (also referred to as a limited-field transmission electron diffraction pattern) as shown in Fig. 27(A) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it can also be seen by electron diffraction that the pellets included in the CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, Fig. 27(B) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface on the same sample. From Fig. 27(B), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen by electron diffraction that the a-axis and b-axis of the pellets included in the CAAC-OS do not have orientation. Note that the first ring in Fig. 27(B) is considered to be due to the (010) plane and the (100) plane, etc. of the InGaZnO4 crystal. Also, the second ring in Fig. 27(B) is considered to be due to the (110) plane, etc. As described above, the CAAC-OS is a highly crystalline oxide semiconductor.

[0315] As described above, the CAAC-OS is a highly crystalline oxide semiconductor. Crystallinity may decrease due to contamination by impurities or generation of defects, so the opposite view is taken. CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0316] Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. Elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, can deprive the oxide semiconductor of oxygen, disrupting the atomic arrangement of the oxide semiconductor and becoming a factor in reducing crystallinity. Also, heavy metals such as iron and nickel, argon, and carbon dioxide, etc., have a large atomic radius (or molecular radius), so they disrupt the atomic arrangement of the oxide semiconductor and become a factor in reducing crystallinity.

[0317] When the oxide semiconductor has impurities or defects, its characteristics may vary due to light, heat, etc. For example, impurities contained in the oxide semiconductor may become carrier traps or carrier generation sources. Also, oxygen vacancies in the oxide semiconductor may become carrier traps or carrier generation sources by capturing hydrogen.

[0318] CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with a low carrier density. Specifically, it is less than 8×10 / cm 11 3 Preferably less than 1×10 11 / cm 3 Even more preferably less than 1×10 10 / cm 3 And it can be an oxide semiconductor with a carrier density of 1×10 -9 / cm 3 or more. Such an oxide semiconductor can be a high-purity intrinsic or ​​​​​​​​​​It is substantially called a highly pure and genuine oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect energy levels. That is, it can be said that it is an oxide semiconductor having stable characteristics.

[0319] <nc-os> Next, nc-OS will be described.

[0320] nc-OS has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed in a high-resolution TEM image. The crystal parts included in nc-OS often have a size of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. Note that an oxide semiconductor with crystal parts larger than 10 nm and 100 nm or less may be called a microcrystalline oxide semiconductor. nc-OS, for example, may not clearly show grain boundaries in a high-resolution TEM image. Note that nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, the crystal parts of nc-OS may be referred to as pellets below.

[0321] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS has no regularity in the crystal orientation between different pellets. Therefore, no orientation is seen in the whole film. Thus, nc-OS may not be distinguishable from a-like OS or amorphous oxide semiconductor depending on the analysis method. For example, when using an X-ray with a diameter larger than that of the pellet for nc-OS, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron diffraction using an electron beam with a probe diameter larger than that of the pellet (for example, 50 nm or more) for nc-OS, a diffraction pattern like a halo pattern is measured. On the other hand, for nc-OS, when using a probe with a size close to or smaller than that of the pellet When performing nanobeam electron diffraction using an electron beam with a diameter of ーブ, spots are observed. Also, n When performing nanobeam electron diffraction on c-OS, regions with high brightness may be observed that draw a circle (ring-shaped). Furthermore, multiple spots may be observed within the ring-shaped region. There are cases.

[0322] Thus, since the crystal orientations among the pellets (nanocrystals) do not have regularity, nc- OS can also be called an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide semiconductor having NANC (Non-Aligned nanocrystals ).

[0323] nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. Therefore, nc-OS has a lower density of defect levels than a-like OS or an amorphous oxide semiconductor. . However, nc-OS does not show regularity in crystal orientation among different pellets. Therefore , nc-OS has a higher density of defect levels than CAAC-OS.

[0324] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. conductor.

[0325] In a high-resolution TEM image, looseness may be observed for a-like OS. Also, in a high resolution TEM image, there are regions where the crystal part can be clearly confirmed and regions where the crystal part cannot be confirmed. .

[0326] Due to having looseness, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0327] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0328] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0329] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0330] Figure 28 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 28, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also referred to as the initial nucleus) with a size of has grown to a size of about 2.6 nm at a cumulative irradiation dose of 4.2×10 8 e - / nm 2 . On the other hand, for nc-OS and CAAC-OS, it can be seen that there is no change in the size of the crystal part within the range where the cumulative irradiation dose of electrons is up to 4.2×10 8 e - / nm 2 . Specifically, as shown in (2) and (3) of Fig. 28, regardless of the cumulative irradiation dose of electrons, the sizes of the crystal parts of nc-OS and CAAC-OS are about 1.4 nm and about 2.1 nm, respectively .

[0331] Thus, a-like OS may show crystal part growth due to electron irradiation . On the other hand, it can be seen that nc-OS and CAAC-OS hardly show crystal part growth due to electron irradiation . That is, it can be seen that a-like OS has an unstable structure compared to nc-OS and CAAC-O S

[0332] . Also, because it has looseness, a-like OS has a lower density structure compared to nc-OS and CAAC-OS . Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal with the same composition . Also, the density of nc-OS and the density of CAAC -OS are 92.3% or more and less than 100% of the density of a single crystal with the same composition . An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself

[0333] . For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], rhombic The density of a single crystal InGaZnO4 having a hexahedral crystal structure is 6.357 g / cm 3 becomes. Therefore, in an oxide semiconductor satisfying, for example, In:Ga:Zn = 1:1:1 [atomic ratio], the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 becomes. Also, in an oxide semiconductor satisfying, for example, In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 becomes.

[0334] Note that there may be cases where single crystals of the same composition do not exist. In that case, by combining single crystals with different compositions in an arbitrary ratio, the density corresponding to the single crystal in the desired composition can be estimated. The density corresponding to the single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor has various structures, each having various characteristics. Also,

[0335] the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0336] (Embodiment 4) In this embodiment, an example of a circuit using the transistor of one aspect of the present invention will be described with reference to the drawings.

[0337] <Cross-sectional structure> <Cross-sectional structure> FIG. 29A is a cross-sectional view of a semiconductor device of one embodiment of the present invention. In FIG. The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The semiconductor device shown in FIG. 2 has a transistor 2200 using a first semiconductor material in the lower part and In FIG. 29A, a transistor 2100 using a second semiconductor material is provided in the first region. As the transistor 2100 using the second semiconductor material, the transistor 2100 shown in the above embodiment may be used. The left side of the dashed line is the channel of the transistor. The left side is a cross section in the longitudinal direction, and the right side is a cross section in the channel width direction.

[0338] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide) The second semiconductor is a The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0339] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors may be used, and an appropriate transistor may be used depending on the circuit. Except for using the transistor of one aspect of the present invention using a compound semiconductor, there is no need to limit the materials and structures used, nor the specific configuration of the semiconductor device shown here.

[0340] In the configuration shown in FIG. 29(A), a transistor 2100 is provided above the transistor 2200 via an insulator 2201 and an insulator 2207. A plurality of wirings 2202 are provided between the transistor 2200 and the transistor 2100. Also, a plurality of plugs 2203 embedded in various insulators electrically connect the wirings and electrodes provided in the upper and lower layers, respectively. Further, an insulator 2204 covering the transistor 2100 and a wiring 2205 are provided on the insulator 2204.

[0341] In this way, by stacking two types of transistors, the occupied area of the circuit is reduced, and a plurality of circuits can be arranged at higher density.

[0342] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, hydrogen in the insulator provided near the semiconductor film of the transistor 2200 terminates the dangling bonds of silicon and has the effect of improving the reliability of the transistor 2200. On the other hand, when an oxide semiconductor is used for the transistor 2100 provided in the upper layer, hydrogen in the insulator provided near the semiconductor film of the transistor 21 00 becomes one of the factors for generating carriers in the oxide semiconductor, and thus may be a factor for reducing the reliability of the transistor 2100 in some cases. Therefore, when the transistor 2100 using an oxide semiconductor is stacked and provided above the transistor 2200 using a silicon-based semiconductor material, hydrogen diffusion occurs between them ​​It is particularly effective to provide an insulator 2207 having a function of preventing [something]. The insulator 220 7 improves the reliability of the transistor 2200 by confining hydrogen in the lower layer, and in addition, suppresses the diffusion of hydrogen from the lower layer to the upper layer, thereby simultaneously improving the reliability of the transistor 2100.

[0343] As the insulator 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0344] Also, it is preferable to form a block film having a function of preventing the diffusion of hydrogen on the transistor 2100 so as to cover the transistor 2100 which is composed of an oxide semiconductor film. As the block film, the same materials as those of the insulator 2207 can be used, and in particular, it is preferable to apply aluminum oxide. The aluminum oxide film has a high blocking effect that does not allow the film to permeate both impurities such as hydrogen and moisture and oxygen. Therefore, by using an aluminum oxide film as the block film covering the transistor 2100, it is possible to prevent the desorption of oxygen from the oxide semiconductor film contained in the transistor 2100 and at the same time, prevent the incorporation of water and hydrogen into the oxide semiconductor film. Note that the block film may be used by laminating the insulator 2204, or may be provided below the insulator 2204.

[0345] Note that the transistor 2200 is not only a planar type transistor but also various types of It can be a transistor. For example, it can be a transistor such as a FIN (fin) type, a TRI-GATE (tri-gate) type, etc. An example of a cross-sectional view in that case is shown in FIG. 29(D). An insulator 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at the tip. Note that an insulator may be provided on the convex portion. The insulator functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the convex portion does not have to have a thin tip. For example, it may be a convex portion having a substantially rectangular parallelepiped shape, or a convex portion having a thick tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. The convex portion does not have to have a thin tip. For example, it may be a convex portion having a substantially rectangular parallelepiped shape, or a convex portion having a thick tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. is not limited thereto. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0346] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistors 2100 and 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0347] <CMOS inverter circuit> The circuit diagram shown in FIG. 29(B) is a so-called CMO in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their gates are connected. ​​​​4 shows the configuration of an S inverter.

[0348] <CMOSアナログスイッチ> In addition, the circuit diagram shown in FIG. 29C shows the transistors 2100 and 2200. In FIG. 29(A), the source and drain of each of the transistors are connected. The X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. This allows it to function as a so-called CMOS analog switch.

[0349] <Example of storage device> By using a transistor according to one embodiment of the present invention, it is possible to preserve memory contents even in a state where power is not supplied. FIG. 30 shows an example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written. As shown in.

[0350] The semiconductor device shown in FIG. 30A includes a transistor 3200 using a first semiconductor material and a The semiconductor device includes a transistor 3300 using the semiconductor material of the second embodiment, and a capacitor element 3400 . Note that the transistor described in Embodiments 1 and 2 is used as the transistor 3300. There can be.

[0351] 30B is a cross-sectional view of the semiconductor device shown in FIG. In the example shown, a back gate is provided in the transistor 3300. It is also possible to adopt a configuration in which no.

[0352] FIG. 30(A) shows a configuration in which the intermediate layer 2210 has electrical conductivity. In the case where 2210 is insulating, the transistor is connected to the wiring 3005 as shown in FIG. 2200 and transistor 2100 are connected.

[0353] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 3300 has a small off-current, it is possible to retain the stored content over a long period of time by using this transistor. That is, it is possible to configure a semiconductor memory device that does not require a refresh operation or requires a very low-frequency refresh operation, and thus the power consumption can be significantly reduced.

[0354] In FIG. 30(A), the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. Also, the third wiring 3003 is electrically connected to one of the source electrode or the drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the other of the source electrode or the drain electrode of the transistor 3300 and one of the electrodes of the capacitor element 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor element 3400.

[0355] In the semiconductor device shown in FIG. 30(A), by taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be retained, writing, holding, and reading of information can be performed as follows.

[0356] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, and the transistor 3300 is turned on. ​​​​​​​​​​​As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and also to the capacitor element 3400. That is, a predetermined amount of charge is applied to the gate of the transistor 3200 (writing). Here, it is assumed that either one of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. Thereafter, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is in the off state, and by turning off the transistor 3300, the charge applied to the gate of the transistor 3200 is held (holding).

[0357] Since the off - current of the transistor 3300 is extremely small, the charge on the gate of the transistor 3200 is held for a long time.

[0358] Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 while a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 takes on different potentials according to the amount of charge held on the gate of the transistor 3200. Generally, when the transistor 3200 is an n - channel type, the apparent threshold value V is lower than the apparent threshold value V when a High level charge is applied to the gate electrode of the transistor 3200 than when a Low level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage means the potential of the fifth wiring 3005 required to turn the transistor 3200 into the "on state". th_H Therefore, when the potential of the fifth wiring 3005 is between V and V th_L (assuming this), the potential of the fifth wiring 3005 is between V and V th_H and V th_L By setting it as V0, the charge applied to the gate of the transistor 3200 can be discriminated. For example, in writing, when a High-level charge is applied, if the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in the "on state" . When a Low-level charge is applied, even if the potential of the fifth wiring 3005 is V0 (< V th_L ), the transistor 3200 remains in the "off state". Therefore, by discriminating the potential of the second wiring 3002, the stored information can be read out.

[0359] Note that when the memory cells are arranged and used in an array, it is necessary to be able to read out only the information of the desired memory cell. If the information is not read out in this way, a potential such that the transistor 3200 is in the "off state" regardless of the state of the gate, that is, a potential smaller than V may be applied to the fifth wiring 3005. Or, a potential such that the transistor 3200 is in the "on state" regardless of the state of the gate, that is, a potential larger than V may be applied to the fifth wiring 3005. th_H may be applied to the fifth wiring 3005. th_L

[0360] The semiconductor device shown in Fig. 30(C) is different from Fig. 30(A ) in that the transistor 3200 is not provided. Also in this case, the writing and holding operations of information are possible by the same operation as described above.

[0361] Next, the reading of information will be described. When the transistor 3300 is turned on, the floating third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected, and the third wiring 3003 and Charge is redistributed among the capacitance elements 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 takes different values depending on the potential of the first terminal of the capacitance element 3400 ( or the charge stored in the capacitance element 3400). For example, if the potential of the first terminal of the capacitance element 3400 is V, the capacitance of the capacitance element 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge redistribution is VB0, then the potential of the third wiring 3003 after charge redistribution is (CB ×

[0362] VB0 + C × V) / (CB + C). Therefore, assuming that the potential of the first terminal of the capacitance element 3400 takes two states of V1 and V0 (V1 > V0) as the state of the memory cell, the potential of the third wiring 3003 when holding the potential V1 (=(CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the third wiring 3003 when holding the potential V0 (=(CB × VB0 + C × V0) / (CB + C)). And information can be read by comparing the potential of the third wiring 3003 with a predetermined potential. In this case, a transistor to which the first semiconductor material is applied in a drive circuit for driving the memory cell may be used, and a transistor to which the second semiconductor material is applied as the transistor 3300 may be stacked and provided on the drive circuit. In the semiconductor device shown in this embodiment, by applying a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, the stored content can be retained for an extremely long period of time.

[0363]

[0364]

[0365] ​​​​​​​​​​This is possible. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. In addition, even when there is no power supply (however, it is desirable that the potential is fixed), it is possible to retain the stored content over a long period of time. Also, in the semiconductor device according to the present embodiment, a high voltage is not required for writing information, and there is no problem of electron degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which has been a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized. In the present specification and the like, for all terminals of active elements (such as transistors and diodes), passive elements (such as capacitive elements and resistive elements), etc., even if the connection destination is not specified, a person skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destination. And when the content of the specified connection destination is described in the present specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destination is described in the present specification and the like. In particular, when multiple cases are conceivable as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location.

[0366] In addition, in the semiconductor device shown in the present embodiment, a high voltage is not required for writing information, and there is no problem of electron degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate. Therefore, problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which has been a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which has been a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized.

[0367] In the present specification and the like, for all terminals of active elements (such as transistors and diodes), passive elements (such as capacitive elements and resistive elements), etc., even if the connection destination is not specified, a person skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destination. And when the content of the specified connection destination is described in the present specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destination is described in the present specification and the like. In particular, when multiple cases are conceivable as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. That is, it can be said that an aspect of the invention is clear even without specifying the connection destination. And when the content of the specified connection destination is described in the present specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destination is described in the present specification and the like. In particular, when multiple cases are conceivable as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. . Therefore, for some terminals of active elements (such as transistors and diodes), passive elements (such as capacitive elements and resistive elements), etc., it may be possible to constitute an aspect of the invention by specifying their connection destinations. There may be cases where an aspect of the invention can be configured.

[0368] In this specification, etc., for a certain circuit, if at least the connection destination is specified, a person skilled in the art may be able to specify the invention. Or, for a certain circuit, if at least the function is specified, a person skilled in the art may be able to specify the invention. In other words, it can be said that if the function is specified, an aspect of the invention is clear. And, when an aspect of the invention with the function specified can be determined to be described in this specification, etc., then. Therefore, for a certain circuit, even if the function is not specified, if the connection destination is specified, it is disclosed as an aspect of the invention and can constitute an aspect of the invention. Or, for a certain circuit, even if the connection destination is not specified, if the function is specified, it is disclosed as an aspect of the invention and can constitute an aspect of the invention. In addition, in this specification, etc., in a certain embodiment, in the figure or text described, it is possible to take out a part of it to constitute an aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content obtained by taking out a part of the figure or text of that part is also disclosed as an aspect of the invention and can be considered to be able to

[0369] constitute an aspect of the invention. Therefore, for example, active elements (such as transistors and diodes etc.), wirings, passive elements (such as capacitive elements and resistive elements), conductive layers, insulating layers, semiconductor layers, organic layers, etc. a part of the figure or text of that part is also disclosed as an aspect of the invention and can be considered to be able to constitute an aspect of the invention. Therefore, for example, active elements (such as transistors and diodes etc.), wirings, passive elements (such as capacitive elements and resistive elements), conductive layers, insulating layers, semiconductor layers, organic layers, etc. Drawings depicting one or more materials, inorganic materials, components, devices, operating methods, manufacturing methods, etc. In the drawings or the text, it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer, M < N) circuit elements (transistors, capacitor elements, etc.) to constitute an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer, M < N) layers to constitute an aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer, M < N) elements to constitute an aspect of the invention.

[0370] <Imaging device> Hereinafter, an imaging device according to an aspect of the present invention will be described.

[0371] FIG. 31(A) is a plan view showing an example of an imaging device 200 according to an aspect of the present invention. The imaging device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and peripheral circuits 270, 280, and 290. The pixel section 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuits 260, 270, 280, and 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. In this specification, etc., all of the peripheral circuits 260, 270, 280, and 290 may be referred to as "peripheral circuits" or "driving circuits". ​ For example, the peripheral circuit 260 can be regarded as a part of the peripheral circuits.

[0372] In addition, the imaging device 200 preferably has a light source 291. The light source 291 can emit detection light P1.

[0373] In addition, the peripheral circuit has at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. The peripheral circuit may be arranged on the substrate forming the pixel section 210. In addition, part or all of the peripheral circuit may be implemented by a semiconductor device such as an IC. Further, the peripheral circuit may omit any one or more of the peripheral circuits 260, 270, 280, and 290.

[0374] In addition, as shown in FIG. 31(B), in the pixel section 210 included in the imaging device 200, the pixel 211 may be arranged obliquely. By arranging the pixel 211 obliquely, the pixel pitch in the row direction and the column direction can be shortened. As a result, the imaging quality of the imaging device 200 can be further improved.

[0375] <Example configuration of a pixel 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and filters (color filters) that transmit light in specific wavelength bands are combined with the respective sub-pixels 212, whereby information for realizing color image display can be obtained.

[0376] FIG. 32(A) is a plan view showing an example of the pixel 211 for obtaining a color image. The pixel 211 shown in FIG. 32(A) is provided with a color filter that transmits light in the red (R) wavelength band. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") that has passed through, the sub-pixel 212 provided with a color filter that transmits the green (G) wavelength band (hereinafter also referred to as "sub-pixel 212G"), and the sub-pixel 212 provided with a color filter that transmits the blue (B) wavelength band (hereinafter also referred to as "sub-pixel 212B"). The sub-pixel 212 can function as a photosensor. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits the green (G) wavelength band, and the sub-pixel 212 provided with a color filter that transmits the blue (B) wavelength band (hereinafter also referred to as "sub-pixel 212B"). And the sub-pixel 212 (hereinafter also referred to as "sub-pixel 212B") provided with a color filter that transmits the blue (B) wavelength band. It has. The sub-pixel 212 can function as a photosensor. It can be done.

[0377] The sub-pixels 212 (sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B) are electrically connected to the wiring 231, wiring 247, wiring 248, wiring 249, and wiring 250. Also, the sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row are respectively referred to as wiring 248[n] and wiring 249[n]. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is referred to as wiring 253[m]. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. And the sub-pixel 212 (sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B) are electrically connected to the wiring 231, wiring 247, wiring 248, wiring 249, and wiring 250. Also, the sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row are respectively referred to as wiring 248[n] and wiring 249[n]. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is referred to as wiring 253[m]. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. The sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row are respectively referred to as wiring 248[n] and wiring 249[n]. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is referred to as wiring 253[m]. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row are respectively referred to as wiring 248[n] and wiring 249[n]. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is referred to as wiring 253[m]. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. For example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row are respectively referred to as wiring 248[n] and wiring 249[n]. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is referred to as wiring 253[m]. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is referred to as wiring 253[m]. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. In FIG. 32(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring.

[0378] Also, the imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. In FIG. 32(B), it is arranged in n rows (n is an integer from 1 to p) and m columns (m is an integer from 1 to q). Also, the imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. In FIG. 32(B), it is arranged in n rows (n is an integer from 1 to p) and m columns (m is an integer from 1 to q). In FIG. 32(B), it is arranged in n rows (n is an integer from 1 to p) and m columns (m is an integer from 1 to q). The sub-pixels 212 of the pixel 211 and the sub-pixels 212 are arranged in n + 1 rows and m columns adjacent to the pixel 211 An example of the connection of the sub-pixels 212 of the pixel 211 is shown. In FIG. 32(B), the sub-pixel 212R arranged in n rows and m columns and the sub-pixel 212R arranged in n + 1 rows and m columns are connected via the switch 201. Also, the sub-pixel 212G arranged in n rows and m columns and the sub-pixel 212G arranged in n + 1 rows and m columns are connected via the switch 202. Also, the sub-pixel 212B arranged in n rows and m columns and the sub-pixel 212B arranged in n + 1 rows and m columns are switched connected via the switch 203.

[0379] Note that the color filters used for the sub-pixels 212 are not limited to red (R), green (G), and blue (B), and color filters that transmit cyan (C), yellow (Y), and magenta (M) light respectively may be used. By providing sub-pixels 212 that detect light in three different wavelength bands for one pixel 211, a full-color image can be obtained.

[0380] Alternatively, in addition to the sub-pixels 212 provided with color filters that transmit red (R), green (G), and blue (B) light respectively, sub-pixels 212 provided with color filters that transmit yellow (Y) light may be used. Alternatively, in addition to the sub-pixels 212 provided with color filters that transmit cyan (C), yellow (Y ) and magenta (M) light respectively, pixels 21 1 having sub-pixels 212 provided with color filters that transmit blue (B) light may be used. By providing sub-pixels 2 12 that detect light in four different wavelength bands for one pixel 211, the color reproducibility of the obtained image can be further improved.

[0381] Also, for example, in FIG. 32(A), the pixel numbers ( or light-receiving area ratios) of the sub-pixels 212 that detect the red wavelength band, the sub-pixels 212 that detect the green wavelength band, and the sub-pixels 212 that detect the blue wavelength band do not have to be 1:1:1. For example, the pixel number ratio (light-receiving area ratio ) may be a Bayer array with red:green:blue = 1:2:1. Or, the pixel number ratio (light -receiving area ratio) may be red:green:blue = 1:6:1.

[0382] Note that there may be one sub-pixel 212 provided in the pixel 211, but two or more are preferred. For example , by providing two or more sub-pixels 212 that detect the same wavelength band, redundancy can be increased and the reliability of the imaging device 200 can be enhanced.

[0383] Also, by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light, an imaging device 200 that detects infrared light can be realized.

[0384] Also, by using an ND (ND: Neutral Density) filter (attenuating filter), it is possible to prevent output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light-receiving element). By combining ND filters with different light attenuation amounts, the dynamic range of the imaging device can be increased.

[0385] Also, in addition to the filters described above, a lens may be provided in the pixel 211. Here, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described using the cross-sectional view of FIG. 33. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically , as shown in FIG. 33(A), the lens 255 formed on the pixel 211, the filter 25 4, 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0386] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in Figure 33(B), A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0387] As the photoelectric conversion element 220 shown in FIG. 33, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0388] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0389] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0390] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0391] <Example configuration of pixels 2> Hereinafter, an example of configuring a pixel using a transistor using silicon and a transistor using an oxide semiconductor will be described. will be described.

[0392] FIGS. 34(A) and 34(B) are cross-sectional views of elements constituting an imaging device.

[0393] The imaging device shown in FIG. 34(A) includes a transistor 351 using silicon provided on a silicon substrate 300, a transistor 352 and a transistor 353 using an oxide semiconductor stacked and disposed on the transistor 351, and an anode 361 and a cathode 362 provided on the silicon substrate 300. A photodiode 360 having. Each transistor and the photodiode 360 have electrical connections with various plugs 370 and wirings 371. Further, the anode 361 of the photodiode 360 has an electrical connection with the plug 370 via a low resistance region 363. and a transistor 352 and a transistor 353 using an oxide semiconductor stacked and disposed on the transistor 351, and an anode 361 provided on the silicon substrate 300. and a cathode 362, and a photodiode 360 having the same. Each transistor and the photodiode 360 have electrical connections with various plugs 370 and wirings 371. Further, the anode 361 of the photodiode 360 has an electrical connection with the plug 370 via a low resistance region 363. and a photodiode 360 having a cathode 362. Each transistor and the photodiode 360 have electrical connections with various plugs 370 and wirings 371. Further, the anode 361 of the photodiode 360 has an electrical connection with the plug 370 via a low resistance region 363. connections. Also, the anode 361 of the photodiode 360 has an electrical connection with the plug 370 via a low resistance region 363. connections. Also, the anode 361 of the photodiode 360 has an electrical connection with the plug 370 via a low resistance region 363. connections. Also, the anode 361 of the photodiode 360 has an electrical connection with the plug 370 via a low resistance region 363.

[0394] The imaging device also includes a layer 310 having a transistor 351 and a photodiode 360 provided on the silicon substrate 300, a layer 320 provided in contact with the layer 310 and having a wiring 371, and a layer 320 provided in contact with the layer 320 and having a transistor 352 and a transistor 353. A layer 330 having the same, and a layer 340 provided in contact with the layer 330 and having wirings 372 and 373. and a layer 320 provided in contact with the layer 310 and having a wiring 371, and a layer 330 provided in contact with the layer 320 and having a transistor 352 and a transistor 353. and a layer 330 provided in contact with the layer 320 and having a transistor 352 and a transistor 353. and a layer 340 provided in contact with the layer 330 and having wirings 372 and 373. is provided.

[0395] In an example of the cross-sectional view of FIG. 34(A), on the silicon substrate 300, the light receiving surface of the photodiode 360 is formed on the surface opposite to the surface on which the transistor 351 is formed. configured to have By adopting such a configuration, an optical path can be secured without being affected by various transistors, wirings, etc. Therefore, pixels with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 360 can also be made the same as the surface on which the transistor 351 is formed.

[0396] When forming a pixel using a transistor, layer 310 may be a layer having a transistor. Or layer 310 may be omitted and the pixel may be composed of only transistors.

[0397] Also, in the cross-sectional view of FIG. 34(A), the photodiode 360 provided in layer 310 and the transistor provided in layer 330 can be formed so as to overlap. Then, the integration degree of the pixel can be increased. That is, the resolution of the imaging device can be increased.

[0398] Also, FIG. 34(B) shows that the imaging device can have a structure in which the photodiode 365 is disposed on the transistor on the layer 340 side. In FIG. 34(B), for example, layer 310 has a transistor 351 using silicon and a transistor 352, layer 320 has a wiring 371, layer 330 has a transistor 352 using an oxide semiconductor layer and a transistor 353, layer 340 has a photodiode 365, and the photodiode 365 is composed of a semiconductor layer 63, a semiconductor layer 64, and a semiconductor layer 65, and is electrically connected to a wiring 373 and a wiring 374 via a plug 370.

[0399] By adopting the element configuration shown in FIG. 34(B), the aperture ratio can be widened.

[0400] In addition, for the photodiode 365, an amorphous silicon film, a microcrystalline silicon film, or the like may be used, and a pin-type diode element or the like may be used. The photodiode 365 has a structure in which an n-type semiconductor layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are stacked in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. Also, for the p-type semiconductor layer 366 and the n-type semiconductor layer 368, amorphous silicon or microcrystalline silicon containing dopants for imparting their respective conductivity types can be used. The photodiode 365 having an amorphous silicon photoelectric conversion layer has high sensitivity in the visible light wavelength region and is easy to detect weak visible light.

[0401] Note that this embodiment can be appropriately combined with other embodiments and examples described in this specification.

[0402] (Embodiment 5) <RF Tag> In this embodiment, the RF tag including the transistor or the memory device described in the previous embodiment will be described with reference to FIG. 35.

[0403] The RF tag in this embodiment has a memory circuit inside, stores information necessary for the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Due to such characteristics, the RF tag can be used in an individual authentication system or the like for identifying an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications.

[0404] The configuration of the RF tag will be described with reference to FIG. 35. FIG. 35 is a block FIG.

[0405] As shown in FIG. 35, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 804. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectification effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of being used for the insulating lay...

Claims

【Claim 1】 a first insulating layer; a first oxide semiconductor layer on the first insulating layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer on the second oxide semiconductor layer; a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer; a third insulating layer on the second insulating layer; a third oxide semiconductor layer on the second oxide semiconductor layer; a gate insulating layer on the third oxide semiconductor layer; a gate electrode layer on the gate insulating layer; comprising the second insulating layer is an oxygen barrier layer and has a region in contact with side surfaces of the first oxide semiconductor layer, side surfaces of the second oxide semiconductor layer, side surfaces of the source electrode layer, and side surfaces of the drain electrode layer; the third oxide semiconductor layer has a region in contact with side surfaces of the second oxide semiconductor layer, side surfaces of the source electrode layer, side surfaces of the drain electrode layer, side surfaces of the second insulating layer, and side surfaces of the third insulating layer; a semiconductor device, characterized by the above.

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