Imaging unit and imaging apparatus

Abstract

To provide an imaging device suitable for obtaining information of focus detection.SOLUTION: An imaging device comprises a pixel part including unit groups 167 and 168 consisting of a plurality of pixels. The imaging device comprises the pixel part and a driving part. In the pixel part, first and second photoelectric conversion parts are arranged along a row direction. The first photoelectric conversion part (disparity pixels Lt1, Rt1, Lt2, Rt2) is a photoelectric conversion part for converting light from an optical system to an electric charge and is used for focus detection of the optical system. The second photoelectric conversion part (B pixels B1, B2, B5, B6) is a photoelectric conversion part for converting light from the optical system to an electric charge and is used for image generation of an imaged subject. The driving part performs control such that an accumulation time for accumulating the electric charges converted by the first photoelectric conversion part and an accumulation time for accumulating the electric charges converted by the second photoelectric conversion part are different.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to an imaging unit and an imaging device.

Background Art

[0002] There is known an imaging unit in which a back-illuminated imaging chip and a signal processing chip are connected via microbumps for each cell unit formed by grouping a plurality of pixels. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-49361

Summary of the Invention

Problems to be Solved by the Invention

[0003] In the above imaging unit, control of the charge accumulation time and control of the readout of the pixel signal are performed for each cell. However, since the above cells are groups of pixels that are two-dimensionally adjacent, it has not been possible to finely control the charge accumulation time and the readout of the pixel signal within or between cells.

Means for Solving the Problems

[0004] According to one aspect of the present invention, there is provided an imaging unit including: a pixel unit in which a first photoelectric conversion unit that converts light from an optical system into charge and is used for focus detection of the optical system and a second photoelectric conversion unit that converts light from the optical system into charge and is used for generating an image of a subject to be imaged are arranged along a row direction; a driving unit that controls the accumulation time for accumulating the charge converted by the first photoelectric conversion unit and the accumulation time for accumulating the charge converted by the second photoelectric conversion unit to be different accumulation times.

[0005] Note that the above summary of the invention does not list all of the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0006]

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0008] FIG. 1 is a cross-sectional view of a back-illuminated image sensor 100 according to the present embodiment. The image sensor 100 includes an imaging chip 113 that outputs a pixel signal corresponding to incident light, a signal processing chip 111 that processes the pixel signal, and a memory chip 112 that stores the pixel signal. These imaging chip 113, signal processing chip 111, and memory chip 112 are stacked and electrically connected to each other by bumps 109 having conductivity such as Cu.

[0009] As shown in the figure, incident light mainly enters in the +Z-axis direction indicated by the white arrow. In the present embodiment, in the imaging chip 113, the surface on the side where the incident light enters is referred to as the back surface. Also, as shown in the coordinate axes, the right direction of the paper surface orthogonal to the Z-axis is the +X-axis direction, and the front direction of the paper surface orthogonal to the Z-axis and the X-axis is the +Y-axis direction. In some of the following figures, the coordinate axes are displayed based on the coordinate axes of FIG. 1 so that the orientation of each figure can be understood.

[0010] An example of the imaging chip 113 is a back-illuminated MOS image sensor. The PD layer is arranged on the back surface side of the wiring layer 108. The PD layer 106 has a plurality of PDs (photodiodes) 104 arranged two-dimensionally and transistors 105 provided corresponding to the PDs 104.

[0011] A color filter 102 is provided on the incident side of the incident light in the PD layer 106 via a passivation film 103. The color filter 102 has a plurality of types that transmit different wavelength regions and has a specific arrangement corresponding to each of the PDs 104. The arrangement of the color filter 102 will be described later. A combination of the color filter 102, PD 104, and transistor 105 forms one pixel.

[0012] On the incident side of the incident light in the color filter 102, a microlens 101 is provided corresponding to each pixel. The microlens 101 condenses the incident light toward the corresponding PD104.

[0013] The wiring layer 108 has a wiring 107 for transmitting the pixel signal from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multilayered, and passive elements and active elements may be provided.

[0014] A plurality of bumps 109 are arranged on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the opposing surface of the signal processing chip 111, and by pressing the imaging chip 113 and the signal processing chip 111, etc., the aligned bumps 109 are joined to each other and electrically connected.

[0015] Similarly, a plurality of bumps 109 are arranged on the opposing surfaces of the signal processing chip 111 and the memory chip 112. These bumps 109 are aligned with each other, and by pressing the signal processing chip 111 and the memory chip 112, etc., the aligned bumps 109 are joined to each other and electrically connected.

[0016] Note that the joining between the bumps 109 is not limited to Cu bump joining by solid-phase diffusion, and microbump bonding by solder melting may also be employed. Also, for example, about one bump 109 may be provided for one output wiring described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD104. Also, in the peripheral region outside the pixel region where the pixels are arranged, bumps larger than the bumps 109 corresponding to the pixel region may be provided together.

[0017] The signal processing chip 111 has TSVs (through-silicon vias) 110 that connect the circuits provided on the front and back surfaces to each other. The TSVs 110 are preferably provided in the peripheral region. Also, the TSVs 110 may be provided in the peripheral region of the imaging chip 113 and the memory chip 112 as well.

[0018] FIG. 2 is a diagram for explaining the pixel array of the imaging chip 113 and the unit group 131. In particular, it shows how the imaging chip 113 is observed from the back side. In the pixel region, more than 20 million pixels are arranged in a matrix. In the present embodiment, 16 adjacent 4×4 pixels form one group. The grid lines in the figure indicate the concept that adjacent pixels are grouped to form the unit group 131.

[0019] As shown in the partial enlarged view of the pixel region, the unit group 131 includes four so-called Bayer arrays each consisting of 4 pixels, namely green pixels Gb, Gr, blue pixel B, and red pixel R, enclosed vertically and horizontally. The green pixels Gb, Gr have a green filter as the color filter 102 and receive light in the green wavelength band of the incident light. Similarly, the blue pixel B has a blue filter as the color filter 102 and receives light in the blue wavelength band, and the red pixel R has a red filter as the color filter 102 and receives light in the red wavelength band.

[0020] FIG. 3 shows an equivalent circuit diagram of the pixel 150. Each of the plurality of pixels 150 has the above-mentioned PD104, transfer transistor 152, reset transistor 154, amplification transistor 156, and selection transistor 158. At least some of these transistors correspond to the transistor 105 in FIG. 1. Further, a reset wiring 300 to which an on signal of the reset transistor 154 is supplied, a transfer wiring 302 to which an on signal of the transfer transistor 152 is supplied, a power supply wiring 304 that receives power supply from the power supply Vdd, a selection wiring 306 to which an on signal of the selection transistor 158 is supplied, and an output wiring 308 that outputs a pixel signal are arranged in the pixel 150. Hereinafter, an example in which each transistor is an n-channel type FET will be described, but the type of transistor is not limited thereto.

[0021] The source, gate, and drain of transfer transistor 152 are connected to one end of PD104, transfer wiring 302, and the gate of amplification transistor 156, respectively. Also, the drain of reset transistor 154 is connected to power supply wiring 304, and the source is connected to the gate of amplification transistor 156. The drain of amplification transistor 156 is connected to power supply wiring 304, and the source is connected to the drain of selection transistor 158. The gate of selection transistor 158 is connected to selection wiring 306, and the source is connected to output wiring 308. Load current source 309 supplies current to output wiring 308. That is, output wiring 308 for selection transistor 158 is formed by a source follower. Note that load current source 309 may be provided on the side of imaging chip 113 or on the side of signal processing chip 111.

[0022] FIG. 4 is a circuit diagram showing the connection relationship of pixel 150 in unit group 131. For the purpose of making the drawing easy to view, the reference numbers of each transistor are omitted, but each transistor of each pixel in FIG. 4 has the same configuration and function as each transistor arranged at the corresponding position in pixel 150 of FIG. 3.

[0023] Within unit group 131 shown in FIG. 4, pixels 150 having color filters 102 of the same color form a pixel group. Corresponding to the fact that there are three types of color filters 102, i.e., RGB as shown in FIG. 2, eight pixels, namely pixels Gb1, Gb2, Gb3, Gb4, Gr1, Gr2, Gr3, Gr4, form a G pixel group. Similarly, four pixels, namely pixels R1, R2, R3, R4, form an R pixel group, and four pixels, namely pixels B1, B2, B3, B4, form a B pixel group. That is, a pixel group is formed for each wavelength region that passes through color filter 102.

[0024] Here, the gates of the transfer transistors are commonly connected among the plurality of pixels included in each pixel group. Thereby, the gates of the transfer transistors are controlled simultaneously for the pixels belonging to the pixel group and independently between pixel groups.

[0025] In the example shown in FIG. 4, the gates of the transfer transistors of pixels Gb1, Gb2, Gb3, Gb4, Gr1, Gr2, Gr3, and Gr4 included in the G pixel group are connected to a common G transfer wiring 310. Similarly, the gates of the transfer transistors of pixels R1, R2, R3, and R4 in the R pixel group are connected to a common R transfer wiring 312, and the gates of the transfer transistors of pixels B1, B2, B3, and B4 in the B pixel group are connected to a common B transfer wiring 314.

[0026] Also, the sources of the selection transistors are commonly connected among a plurality of pixels included in each pixel group. The sources of the selection transistors of pixels Gb1, Gb2, Gb3, Gb4, Gr1, Gr2, Gr3, and Gr4 in the G pixel group are connected to a common G output wiring 320. Similarly, the sources of the selection transistors of pixels R1, R2, R3, and R4 in the R pixel group are connected to a common R output wiring 322, and the sources of the selection transistors of pixels B1, B2, B3, and B4 in the B pixel group are connected to a common B output wiring 324.

[0027] A load current source 311 is connected to the G output wiring 320. Similarly, a load current source 313 is connected to the R output wiring 322, and a load current source 315 is connected to the B output wiring 324. Note that the reset wiring 326 and the power supply wiring 316 are common in the unit group 131. Also, 16 selection wirings are arranged one-to-one for each pixel and are connected to the gates of the corresponding selection transistors.

[0028] In this way, a plurality of output wirings are provided for one unit group 131. However, since the imaging chip 113 is a back-illuminated type, without reducing the amount of light incident on the PD104, the number of layers of the wiring 107 of the imaging chip 113 can be increased and the wiring can be routed without increasing the size in the plane direction.

[0029] FIG. 5 is a block diagram showing the configuration of the imaging device according to the present embodiment. The imaging device 500 includes a photographing lens 520 as a photographing optical system, and the photographing lens 520 guides a subject light beam incident along the optical axis OA to the imaging element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. The imaging device 500 mainly includes an imaging element 100, a system control unit 501, a driving unit 502, a photometric unit 503, a work memory 504, a recording unit 505, and a display unit 506.

[0030] The photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of a subject light beam from a scene near its focal plane. Note that in FIG. 5, it is represented by a virtual single lens disposed near the pupil. The driving unit 502 is a control circuit that executes charge accumulation control such as timing control and area control of the imaging element 100 according to an instruction from the system control unit 501. In this sense, it can be said that the driving unit 502 assumes the function of an imaging element control unit that causes the imaging element 100 to perform charge accumulation and output a pixel signal. The driving unit 502 is combined with the imaging element 100 to form an imaging unit. The control circuit forming the driving unit 502 may be chip-sized and stacked on the imaging element 100.

[0031] The imaging element 100 delivers a pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 performs various image processes using the work memory 504 as a work space to generate image data. For example, when generating image data in the JPEG file format, compression processing is executed after performing white balance processing, gamma processing, etc. The generated image data is recorded in the recording unit 505 and is also converted into a display signal and displayed on the display unit 506 for a preset time.

[0032] Before a series of shooting sequences for generating image data, the photometric unit 503 detects the luminance distribution of the scene. The photometric unit 503 includes, for example, an AE sensor of about 1 million pixels. The arithmetic unit 512 of the system control unit 501 receives the output of the photometric unit 503 and calculates the luminance for each region of the scene. The arithmetic unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. Note that the pixels used for the AE sensor may be provided in the imaging device 100. In this case, it is not necessary to provide a photometric unit 503 separate from the imaging device 100.

[0033] FIG. 6 is a block diagram showing the functional configuration of the imaging device 100. The analog multiplexer 411 sequentially selects eight pixels Gb1 etc. of the G pixel group of the unit group 131 and outputs the respective pixel signals to the G output wiring 320 etc.

[0034] The pixel signal output via the multiplexer 411 is subjected to correlated double sampling (CDS) and analog / digital (A / D) conversion by the signal processing circuit 412 that performs CDS and A / D conversion via the G output wiring 320. The A / D converted pixel signal is delivered to the demultiplexer 413 via the G output wiring 321 and stored in the pixel memory 414 corresponding to each pixel.

[0035] Similarly, the multiplexer 421 sequentially selects four pixels R1 etc. of the R pixel group of the unit group 131 and outputs the respective pixel signals to the R output wiring 322. The signal processing circuit 422 performs CDS and A / D conversion on the pixel signal output to the R output wiring 322. The A / D converted pixel signal is delivered to the demultiplexer 423 via the R output wiring 323 and stored in the pixel memory 414 corresponding to each pixel.

[0036] Similarly, the multiplexer 431 sequentially selects four pixels B1 etc. of the B pixel group of the unit group 131, and outputs their respective pixel signals to the B output wiring 324. The signal processing circuit 432 performs CDS and A / D conversion on the pixel signals output to the B output wiring 324. The A / D converted pixel signals are delivered to the demultiplexer 433 via the B output wiring 325, and stored in the pixel memory 414 corresponding to each pixel.

[0037] The multiplexers 411, 421, 431 are respectively formed on the imaging chip 113 by the selection transistor 158 and the selection wiring 306 of FIG. 3. The signal processing circuits 412, 422, 432 are formed on the signal processing chip 111. In the example of FIG. 6, three signal processing circuits 412, 422, 432 are provided corresponding to the G pixel group, the R pixel group, and the B pixel group. The demultiplexer 413 and the pixel memory 414 are formed on the memory chip 112.

[0038] G output wirings 320, 321, R output wirings 322, 323, and B output wirings 324, 325 are provided corresponding to the G pixel group, the R pixel group, and the B pixel group in the unit group 131. Since the imaging device 100 stacks the imaging chip 113, the signal processing chip 111, and the memory chip 112, these wirings can be routed by making electrical connections between chips using the bumps 109, without increasing the size of each chip in the plane direction.

[0039] The arithmetic circuit 415 processes the pixel signals stored in the pixel memory 414 and delivers them to the subsequent image processing unit. The arithmetic circuit 415 may be provided on the signal processing chip 111, or may be provided on the memory chip 112. Note that the figure shows the connection for one group, but in reality, these exist for each group and operate in parallel. However, the arithmetic circuit 415 does not have to exist for each group. For example, one arithmetic circuit 415 may sequentially process while referring to the values of the pixel memories 414 corresponding to each group in order.

[0040] FIG. 7 shows a timing chart of the operations of each pixel group in FIG. 4. The driving unit 502 turns on the reset transistors of each pixel Gb1 etc. of the unit group 131 via the reset wiring 326 at time t0. Thereby, the charge at the gate of the amplification transistor of each pixel Gb1 etc. is discarded, and the potential of the gate is reset. Further, the driving unit 502 keeps the reset transistors of each pixel Gb1 etc. in the on state, and turns on the transfer transistors of each pixel Gb1 etc. belonging to the G pixel group via the G transfer wiring 310 from time t1 to t2. Thereby, the charge accumulated in the PD of each pixel Gb1 etc. belonging to the G pixel group is discarded.

[0041] Similarly, the driving unit 502 turns on the transfer transistors of each pixel R1 etc. of the R pixel group and the transistors of each pixel B1 etc. of the B pixel group via the R transfer wiring 312 and the B transfer wiring 314 from time t1 to t2. Thereby, the charge accumulated in the PD of each pixel R1 etc. of the R pixel group and each pixel B1 etc. of the B pixel group is discarded. Thereafter, the driving unit 502 turns off the reset transistors of each pixel Gb1 etc. of the unit group 131 via the reset wiring 326 at time t3.

[0042] At time t4 after a predetermined accumulation time from the above time t2, the driving unit 502 turns on the transfer transistors of each pixel Gb1 etc. belonging to the G pixel group via the G transfer wiring 310, and turns them off at time t6 thereafter. Thereby, the charge accumulated in the PD of each pixel Gb1 etc. belonging to the G pixel group during the period from time t2 to t4 is simultaneously transferred to the gate of the amplification transistor via the transfer transistor. Thereby, the driving unit 502 can collectively control the charge accumulation time of each pixel Gb1 belonging to the G pixel group. Note that the accumulation time is, for example, the same as the exposure time.

[0043] In the example shown in FIG. 7, similar to the G pixel group, from time t4 to t6, the driving unit 502 turns on the transfer transistors of each pixel R1, etc. of the R pixel group via the R transfer wiring 312. As a result, the charges accumulated in the PD from time t2 to t4 in each pixel R1, etc. of the R pixel group are simultaneously transferred to the gates of the amplification transistors via the transfer transistors.

[0044] Also, in the example shown in FIG. 7, from time t5 after time t4 to time t7 after a predetermined time, the driving unit 502 turns on the transfer transistors of each pixel B1, etc. of the B pixel group via the B transfer wiring 314. As a result, the charges accumulated in the PD from time t2 to t5 in each pixel B1, etc. of the B pixel group are simultaneously transferred to the gates of the amplification transistors via the transfer transistors.

[0045] Thereby, the driving unit 502 can collectively control the charge storage time of each pixel B1, etc. of the B pixel group to be different from the charge storage time of each pixel Gr1, etc. of the G pixel group. Also, it is possible to accumulate charges with a charge storage time different from the exposure time for a specific image group. Which charge storage time to set for which pixel group may be determined from the output for each piece of image information corresponding to the pixel group when a preliminary shooting is performed before this shooting. For example, when the system control unit 501 determines that an image based on one piece of image information is darker than an image based on other image information, the system control unit 501 may cause the driving unit 502 to make the charge storage time longer for the pixel group corresponding to the one piece of image information than for other pixel groups.

[0046] At time t8 after the above-mentioned time t7, the driving unit 502 turns on the selection transistor of pixel Gr1 in the G pixel group via the selection wiring Gr1. As a result, a pixel signal corresponding to the charge transferred by the transfer transistor is generated by the amplification transistor, and the pixel signal is output to the G output wiring 320 via the selection transistor. At time t9 after time t8, the driving unit 502 turns on the selection transistor of pixel Gr2 in the G pixel group via the selection wiring Gr2, and similarly, the pixel signal of pixel Gr2 is output to the G output wiring 320 via the selection transistor. In this way, the driving unit 502 sequentially turns on the selection transistors of each pixel Gr1 etc. in the G pixel group via the selection wirings Gr1 etc. of each pixel Gr1 etc., and sequentially outputs the pixel signals of each pixel Gr1 etc. in the G pixel group to one G output wiring 320.

[0047] Synchronously with the above-mentioned times t8, t9, etc., the driving unit 502 sequentially turns on the selection transistors of pixels R1 etc. in the R pixel group via the selection wirings R1 etc., and sequentially outputs the pixel signals of each pixel R1 etc. in the R pixel group to one R output wiring 322. Similarly, synchronously with the above-mentioned times t8, t9, etc., the driving unit 502 sequentially turns on the selection transistors of pixels B1 etc. in the B pixel group via the selection wirings B1 etc., and sequentially outputs the pixel signals of each pixel B1 etc. in the B pixel group to one B output wiring 324.

[0048] As described above, the pixel signals of each pixel included in the unit group 131 are output from the output wirings of each pixel group. Note that the order of the pixels that output pixel signals within the pixel group is preferably determined in advance and incorporated into the driving unit 502 as hardware or stored as software.

[0049] As described above, according to the present embodiment, it is possible to collectively control the charge accumulation time of each pixel belonging to each pixel group corresponding to each image information. Therefore, it is possible to accumulate charges with an accumulation time suitable for each image information. For example, when imaging a subject biased toward any of RGB, by varying the accumulation time between the pixel group corresponding to the strong color and the pixel group corresponding to the weak color, it is possible to widen the dynamic range for each color. Also, the pixel signals of each pixel can be read out independently between pixel groups.

[0050] FIG. 8 shows an example of another unit group 132 and the connection relationship of each pixel. In FIG. 8, for the purpose of easy viewing of the figure, the transfer wiring and the output wiring are shown, but other configurations of each pixel are omitted and shown by squares.

[0051] In the example shown in FIG. 8, in the pixel array of the image sensor 100, instead of the green pixel Gb in FIG. 2, a white pixel W is arranged. The white pixel W is not provided with a corresponding color filter 102, or is provided with a colorless filter that transmits red, green, and blue. As a result, incident light corresponding to color information, which is an example of different image information, is incident on the green pixel Gb, the blue pixel B, the red pixel R, and the white pixel W.

[0052] Each unit group 132 has 16 pixels of 4×4. Note that the number of pixels included in each unit group 132 is not limited to this, as in the example of FIG. 4.

[0053] Within the unit group 132, pixels 150 having the same color color filter 102 form a pixel group. Corresponding to the four types of RGBW color filters 102, four pixels of pixels G1, G2, G3, and G4 form a G pixel group. Similarly, four pixels of pixels R1, R2, R3, and R4 form an R pixel group, and four pixels of pixels B1, B2, B3, and B4 form a B pixel group. Further, four pixels of pixels W1, W2, W3, and W4 form a W pixel group. That is, a pixel group is formed for each wavelength region that passes through the color filter 102.

[0054] Here, the gates of the transfer transistors are commonly connected among a plurality of pixels included in each pixel group. Thereby, the driving unit 502 controls the gates of the transfer transistors all at once within a pixel group and independently among pixel groups.

[0055] The gates of the transfer transistors of pixels G1, G2, G3, and G4 included in the G pixel group are connected to a common G transfer wiring 330. Similarly, the gates of the transfer transistors of pixels R1, R2, R3, and R4 in the R pixel group are connected to a common R transfer wiring 332, and the gates of the transfer transistors of pixels B1, B2, B3, and B4 in the B pixel group are connected to a common B transfer wiring 334. Further, the gates of the transfer transistors of pixels W1, W2, W3, and W4 in the W pixel group are connected to a common W transfer wiring 336.

[0056] Also, the output sides of the selection transistors are commonly connected among a plurality of pixels included in each pixel group. The output sides of the selection transistors of pixels G1, G2, G3, and G4 in the G pixel group are connected to a common G output wiring 340. Similarly, the output sides of the selection transistors of pixels R1, R2, R3, and R4 in the R pixel group are connected to a common R output wiring 342, and the sources of the selection transistors of pixels B1, B2, B3, and B4 in the B pixel group are connected to a common B output wiring 344. Further, the output sides of the selection transistors of pixels W1, W2, W3, and W4 in the W pixel group are connected to a common W output wiring 346.

[0057] Note that, similar to the example in FIG. 4, the reset wiring and the power supply wiring are common in the unit group 132. Also, 16 selection wirings are arranged one-to-one for each pixel and are connected to the gates of the corresponding selection transistors. Further, load current sources are connected to the output wirings, similar to the example in FIG. 4.

[0058] As a result, the driving unit 502 can collectively control the charge storage time of each pixel belonging to each pixel group. Also, for a specific image group, charges can be stored with a storage time different from that of other pixel groups. For example, since the color filter of the W pixel group is colorless, there are cases where the amount of light is larger than that of the G pixel group or the like. Therefore, by making the charge storage time of each pixel in the W pixel group shorter than the charge storage time of each pixel in the G pixel group or the like, appropriate exposure can be obtained for the W pixel group and the G pixel group or the like, respectively.

[0059] FIG. 9 is a cross-sectional view of another image sensor 160 of the back-illumination type. In the image sensor 160, the same components as those of the image sensor 100 in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

[0060] The image sensor 160 in FIG. 9 has an aperture mask 162 between the passivation film 103 and the color filter 102. The aperture mask 162 is formed of, for example, an aluminum film.

[0061] The aperture mask 162 has apertures 164, 165, and 166 corresponding to each PD104, and blocks incident light except for the aperture portions. As a result, the aperture mask 162 transmits a part of the light beam in the imaging optical system according to the aperture position. In the example shown in FIG. 9, the aperture 164 corresponding to the pixel arranged on the most -X side among the four pixels shown is displaced to the -X side with respect to the PD104. On the other hand, the aperture 166 corresponding to the third pixel from the most -X side among the four pixels is displaced to the +X side with respect to the PD104. By making the light beams displaced to -X and +X of the exit pupil in the imaging optical system incident, information on the phase difference AF can be obtained.

[0062] Pixels in which these apertures are displaced with respect to the PD104 may be referred to as parallax pixels. On the other hand, the aperture 165 is not displaced with respect to the PD104. A white color filter 102 is arranged for the parallax pixels. This pixel may be referred to as a non-parallax pixel. An RGB color filter 102 is arranged for the non-parallax pixel.

[0063] FIG. 10 shows an example of unit groups 167 and 168 corresponding to the imaging device 160 and the connection relationship of each pixel. In FIG. 10, for the purpose of making the figure easier to view, like FIG. 8, the transfer wiring and the output wiring are shown, but other configurations of each pixel are omitted and shown by squares.

[0064] In the example shown in FIG. 10, in the pixel array of the imaging device 160, for the 4×4 pixels, instead of the green pixels Gr1 and Gr2 in FIG. 4, the parallax pixels Lt1 and Rt1 are arranged. The parallax pixel Lt1 corresponds to the pixel provided with the aperture 164 in FIG. 9, and the parallax pixel Rt1 corresponds to the pixel provided with the aperture 166 in FIG. 9. Also, the 16 pixels of the 4×4 form a unit group 167.

[0065] Within the unit group 167, pixels 150 having the same color color filter 102 form a pixel group. Corresponding to the three types of RGB color filters 102, a G pixel group, an R pixel group, and a B pixel group are formed in the same manner as in FIG. 4. Since the configurations and operations of the G pixel group, the R pixel group, and the B pixel group are the same as those in FIG. 4, the description is omitted. However, in the unit group 167, corresponding to the arrangement of the parallax pixels Lt1 and Rt1 instead of the green pixels Gr1 and Gr2 in FIG. 4, the G pixel group is formed by 6 pixels. Regarding the unit group 168, separate G transfer wiring 370, R transfer wiring 372, B transfer wiring 374, G output wiring 380, R output wiring 382, and B output wiring 384 are provided, but the connection relationship is the same as that of the unit group 167.

[0066] Furthermore, a pixel group is also formed for each aperture position. In this case, a pixel group is formed across a plurality of unit groups 167 and 168. In the example of FIG. 10, the four pixels of the parallax pixels Lt1, Lt2, Rt1, and Rt2 with displaced aperture positions form a parallax pixel group.

[0067] The gates of the transfer transistors of the parallax pixels Lt1, Lt2, Rt1, and Rt2 included in the parallax pixel group are connected to a common parallax transfer wiring 356. Also, the output sides of the selection transistors of the pixels Lt1, Lt2, Rt1, and Rt2 in the parallax pixel group are connected to a common parallax output wiring 366.

[0068] As a result, the driving unit 502 can collectively control the charge accumulation time of each pixel belonging to each pixel group. Also, it is possible to accumulate charges with an accumulation time different from that of other pixel groups for a specific image group. Further, load current sources are connected to the output wirings in the same manner as in the example of FIG. 4.

[0069] For example, when the release button of the imaging device 500 is half-pressed, each pixel Lt1, etc. of the parallax pixel group is driven to acquire phase difference AF information, and at this time, each pixel Gr1, etc. of other pixel groups is not driven. On the other hand, when the release button of the imaging device 500 is fully pressed, each pixel Gr1, etc. of the G pixel group, R pixel group, and B pixel group is driven to acquire RGB image information, and each pixel Lt1, etc. of the parallax pixel group is not driven. As a result, when the release button is in the half-pressed state, charges can be accumulated with an accumulation time suitable for phase difference AF information, and the phase difference AF information can be obtained in a short time by performing image processing with a small number of pixels. On the other hand, when the release button is in the fully pressed state, charges can be accumulated with an accumulation time suitable for RGB image information while maintaining high resolution.

[0070] In FIG. 10, a parallax pixel group is formed across two unit groups 167 and 168, but a parallax pixel group may be formed by the parallax pixels within a unit group or across three or more unit groups. Further, a parallax pixel group may be formed for each displacement direction of the aperture position. That is, a parallax pixel group composed of a plurality of pixels Lt1, Lt2, etc. with the aperture displaced to the -X side and a parallax pixel group composed of a plurality of pixels Rt1, Rt2, etc. with the aperture displaced to the +X side may be formed.

[0071] Also, in the arrangement of FIG. 4 or FIG. 8, each pixel may have a displaced aperture. In this case, pixel groups may be formed for each color and for each displacement direction of the aperture position. Further, instead of or in addition to the parallax pixels of FIG. 10, pixels having non-displaced apertures and not provided with the color filter 102 or pixels of the colorless color filter 102 may be arranged as AE pixels in the unit groups 167, 168. Also in this case, by forming a plurality of AE pixels into an AE pixel group, the drive unit 502 collectively controls the charge accumulation time of each pixel belonging to the AE pixel group. Thereby, an accumulation time suitable for obtaining exposure information as image information is set, and pixel information can be read independently of other image groups, for example, when the release button is half-pressed.

[0072] FIG. 11 shows an equivalent circuit of another pixel 170. The same components as those of the pixel 150 in FIG. 3 in FIG. 11 are denoted by the same reference numerals and the description thereof is omitted. Note that a load current source is connected to the output wiring 308 in the same manner as in the example of FIG. 4, but the illustration thereof is omitted.

[0073] In the pixel 170, a row selection transistor 171 and a column selection transistor 172 are provided between the transfer wiring 302 and the gate of the transfer transistor 152. The gate of the row selection transistor 171 is connected to the row selection wiring 391, and the gate of the column selection transistor 172 is connected to the column selection wiring 392. For example, the gates of the row selection transistors of the pixels arranged in the X direction (i.e., the row direction) with the pixel 170 in at least the unit group 131 are commonly arranged on the row selection wiring 391. Similarly, for example, the gates of the column selection transistors of the pixels arranged in the Y direction (i.e., the column direction) with the pixel 170 in at least the unit group 131 are commonly arranged on the column selection wiring 392.

[0074] According to the above configuration, when an on signal is applied to the row selection wiring 391 and the column selection wiring 392, the transfer transistor 152 of the pixel 170 specified by the wiring can be turned on. Thereby, the on / off of the transfer transistor can be controlled in pixel units.

[0075] Furthermore, instead of the single selection transistor 158 of the pixel 150, the pixel 170 is provided with a row selection transistor 174 and a column selection transistor 175. The gate of the row selection transistor 174 is connected to the row selection wiring 394, and the gate of the column selection transistor 175 is connected to the column selection wiring 395. For example, the gates of the row selection transistors of the pixels arranged in the X direction (i.e., the row direction) with the pixel 170 within at least the unit group 131 are commonly arranged on the row selection wiring 394. Similarly, for example, the gates of the column selection transistors of the pixels arranged in the Y direction (i.e., the column direction) with the pixel 170 within at least the unit group 131 are commonly arranged on the column selection wiring 395.

[0076] According to the above configuration, when an on signal is added to the row selection wiring 394 and the column selection wiring 395, the pixel signal of the pixel 170 specified by the wiring can be output to the output wiring 308. As a result, the number of wirings can be reduced compared to the selection wiring 318 that corresponds one-to-one with the selection transistor 158 like the pixel 150.

[0077] Note that the row selection wiring 391 and the column selection wiring 392 for the transfer transistor 152 and the row selection wiring 394 and the column selection wiring 395 for the output wiring 308 do not have to be used in pairs. The configuration of the pixel 150 may be used for either one. Also, when transfer and output are not performed simultaneously, the row selection wirings 391 and 394 may be combined into one and commonly used for transfer and output, and the column selection wirings 392 and 395 may also be combined into one and commonly used for transfer and output.

[0078] In all of the above embodiments, the reset wiring 326 and the power supply wiring 316 are common in the unit group 131. In addition to this, the reset wiring 326 and the power supply wiring 316 may be common among a plurality of unit groups 131. Alternatively, the reset wiring 326 may be common for each pixel group and may be separate wiring between pixel groups. Further, the reset wiring 326 may be separate wiring for each pixel, and the reset transistor 154 may be controlled in the same manner as the control of the transfer transistor 152 in the pixel 170.

[0079] As described above, according to the present embodiment, a plurality of pixels corresponding to the same image information are controlled for charge accumulation time and reading as a pixel group within the unit group 131 or between unit groups 131. Therefore, it is possible to set a charge accumulation time and a read timing suitable for each image information.

[0080] FIG. 12 schematically shows a unit group 602 of another imaging device 600. FIG. 13 shows a circuit diagram of a pixel unit 603 within the unit group 602.

[0081] In the unit group 602 of the imaging device 600, pixels are two-dimensionally arranged in a Bayer array in the same manner as in FIG. 2. Row selection lines are provided one by one for every two rows of pixels, and pixels for two rows are commonly connected to each row selection line. Output wirings 604 are provided one by one for every two columns of pixels, and pixels for two columns are commonly connected to each output wiring 604. Each of the output wirings 604 is connected one-to-one to a CDS circuit 608 via a bump 606 that electrically connects the imaging chip 113 and the signal processing chip 111.

[0082] Outputs of a plurality of CDS circuits 608 connected one-to-one to each of the plurality of output wirings 604 included in the unit group 602 are input to a multiplexer 610. Further, the output from the multiplexer 610 is input to an A / D conversion circuit 612, and the output of the A / D conversion circuit 612 is connected to a pixel memory 414.

[0083] Also, one unit in the Bayer array forms the pixel unit 603. That is, the pixel unit 603 has four pixels Gb, Gr, B, and R.

[0084] The power supply wiring Vdd and the reset wiring are commonly connected to all the pixels included in the unit group 131. Also, the Gb transfer wiring is commonly connected to the pixels Gb in the unit group 131. Similarly, the Gr transfer wiring is commonly connected to the pixels Gr in the unit group 131, the B transfer wiring is commonly connected to the pixels B in the unit group 131, and the R transfer wiring is commonly connected to the pixels R in the unit group 131. Further, the reset wiring and each transfer wiring are provided separately between the plurality of unit groups 131.

[0085] The pixels Gb, Gr, B, and R of the pixel unit 603 share the reset transistor 620, the amplification transistor 622, and the selection transistor 624. Also, the pixel Gb1 has transfer transistors 626 and 628. Similarly, the pixel Gr has transfer transistors 630 and 632, the pixel B has transfer transistors 634 and 636, and the pixel R has transfer transistors 638 and 640.

[0086] When focusing on each pixel, the connection relationship between the pixel and the reset transistor 620, the amplification transistor 622, and the selection transistor 624 is the same as that in FIG. 3. On the other hand, the connection relationship of the transfer transistors 626, etc. is different from that in FIG. 3. The gate, drain, and source of the transfer transistor 626 of the pixel Gb are connected to the Gb transfer wiring, the row selection line 1, and the gate of the transfer transistor 628, respectively. Also, the source and drain of the transfer transistor 628 are connected to one end of the PD of the pixel Gb and the gate of the amplification transistor 622, respectively. The connection relationships of the pixels Gr, B, and R are the same.

[0087] In the forms shown in FIGS. 12 and 13, the image signals of each pixel are read out as follows. For the sake of simplicity, the description of the reset operation is omitted.

[0088] Any one of the row selection lines, for example, row selection line 1 is turned on. In this state, any one of the transfer wirings, for example, the Gb transfer wiring is turned on. As a result, both of the transfer transistors 626 and 628 of pixel Gb are turned on, and the charge of pixel Gb is transferred to the gate of the amplification transistor 622. Here, since the row selection line 1 is in the on state, the selection transistor 624 is also turned on, and a pixel signal amplified according to the charge transferred to the gate of the amplification transistor 622 is output from the output wiring 604.

[0089] The row selection line 1 is common to two rows of pixels within the unit group 602, and the Gb transfer wiring is common to the pixels Gb within the unit group 602. Therefore, the pixel signals of the pixels Gb for one row of the unit group 602 are simultaneously output to the corresponding output wirings 604. Here, since the CDS circuits 608 are arranged one-to-one on the output wiring 604, each pixel signal is temporarily held in the individual CDS circuits 608 in a state where noise is removed.

[0090] The multiplexer 610 sequentially reads out the pixel signals held in the CDS circuits 608 and delivers them to the A / D conversion circuit 612. The A / D conversion circuit 612 sequentially digitizes the pixel signals and writes them into the pixel memory 414. As a result, each of the pixel signals of the pixels Gb for one row of the unit group 602 is stored in the pixel memory 414 without being affected by other pixel signals.

[0091] Next, with the row selection line 1 turned on, by turning on the Gr transfer wiring, each of the pixel signals of the pixels Gr for one row of the unit group 602 is sequentially read out without being affected by other pixel signals. Similarly, with the row selection line 1 turned on, by turning on the B transfer wiring, each of the pixel signals of the pixels B for one row of the unit group 602 is read out and stored in the pixel memory 414. With the row selection line 1 turned on, by turning on the R transfer wiring, each of the pixel signals of the pixels R for one row of the unit group 602 is read out and stored in the pixel memory 414. As described above, the pixel signals of the pixels for two rows of the unit group 602 are read out.

[0092] Next, by turning on the row selection line 2 and repeating the above procedure, pixel signals of the next two rows of pixels in the unit group 602 are read out. By repeating the above procedure for all the row selection lines, pixel signals of all the pixels in the unit group 602 are read out.

[0093] According to the forms shown in FIGS. 12 and 13, for each unit group 602, one row selection line may be provided for every two rows of pixels, so that the routing of the wiring becomes easy. Also, for each unit group 602, one output wiring may be provided for every two columns of pixels, so that the routing of the wiring becomes easy.

[0094] FIG. 14 schematically shows a unit group 652 of still another image sensor 650. FIG. 15 shows a circuit diagram of a pixel unit 653 in the unit group 652. In FIGS. 14 and 15, the same components and functions as those in FIGS. 12 and 13 are denoted by the same reference numerals and the description thereof is omitted.

[0095] In the unit group 652, column selection lines are provided one by one for every two columns of pixels, and two columns of pixels are commonly connected to each column selection line. The column selection lines are connected to the drains of the transfer transistors 626, 630, 634, 638 of the pixel unit 653.

[0096] Each output wiring 604 is arranged to the signal processing chip 111 via a bump 606 and input to a multiplexer 610 provided corresponding to the unit group 652. The output of the multiplexer 610 is input to an A / D conversion circuit 614. The A / D conversion circuit 614 has a circuit for digitally executing CDS in addition to a circuit for digitizing the pixel signal. The output digitized by the A / D conversion circuit 614 and for which CDS is executed is stored in the pixel memory 414.

[0097] In the forms of FIGS. 14 and 15, the image signal of each pixel is read out as follows. For simplicity of explanation, the description of the reset operation is omitted.

[0098] Any one of the row selection lines, for example, row selection line 1 is turned on. In this state, any one of the transfer lines, for example, the Gb transfer wiring is turned on. In this state, further, any one of the column selection lines, for example, column selection line 1 is turned on. As a result, the transfer transistors 626 and 628 of pixel Gb of one pixel unit 653 within the unit group 652 are both turned on, and the charge of pixel Gb is transferred to the gate of the amplification transistor 622. Here, since row selection line 1 is in the on state, the selection transistor 624 is also on, and the pixel signal amplified according to the charge transferred to the gate of the amplification transistor 622 is output from the output wiring 604 corresponding to the pixel unit 653. Further, by keeping row selection line 1 and the Gb transfer wiring in the on state and sequentially switching the on state of the column selection lines, the pixel signals of pixel Gb for one row are sequentially output from the respective output wirings 604.

[0099] In synchronization with the switching of the column selection lines, the multiplexer 610 switches the input from each output wiring 604, so that the pixel signals from pixel Gb are input to the A / D conversion circuit 614 one pixel at a time. Each of the pixel signals of pixel Gb for one row of the unit group 652 is read out without being affected by other pixel signals and stored in the pixel memory 414.

[0100] Next, with row selection line 1 and the Gr transfer wiring turned on, by sequentially switching the on state of the column selection lines, the pixel signals of pixel Gr for one row are sequentially output from the respective output wirings 604. Similarly, with row selection line 1 and the B transfer wiring turned on, by sequentially switching the on state of the column selection lines, the pixel signals of pixel B for one row are sequentially output from the respective output wirings 604, and with row selection line 1 and the R transfer wiring turned on, by sequentially switching the on state of the column selection lines, the pixel signals of pixel R for one row are sequentially output from the respective output wirings 604. Thus, the pixel signals of pixels for two rows of the unit group 652 are read out.

[0101] Next, by turning on the row selection line 2 and repeating the above procedure, pixel signals of the next two rows of pixels in the unit group 652 are read out. By repeating the above procedure for all row selection lines, pixel signals of all pixels in the unit group 652 are read out.

[0102] Also in the forms shown in FIGS. 14 and 15, for each unit group 652, one row selection line may be provided for every two rows of pixels, which facilitates the routing of the wiring. Also, for each unit group 652, one output wiring may be provided for every two columns of pixels, which facilitates the routing of the wiring. Further, the CDS circuit can be provided on the side of the signal processing chip 111.

[0103] FIG. 16 schematically shows a unit group 655 of another imaging device 654. FIG. 17 shows a circuit diagram of a pixel unit 656 in the unit group 655. In FIGS. 16 and 17, the same components and functions as those in FIGS. 14 and 15 are denoted by the same reference numerals and the description thereof is omitted.

[0104] In the unit group 655, a plurality of output wirings 604 are commonly connected to a bump 606 provided corresponding to the unit group 652. The bump 606 is connected to the input side of the A / D conversion circuit 614. Also, a selection transistor 642 having a column selection line and a gate connected thereto is provided in the output wiring 604 of the pixel unit 656.

[0105] In the forms of FIGS. 16 and 17, the image signal of each pixel is read out as follows. For simplicity of explanation, the description of the reset operation is omitted.

[0106] Any one of the row selection lines, for example, row selection line 1 is turned on. In this state, any one of the transfer lines, for example, the Gb transfer wiring is turned on. In this state, further, any one of the column selection lines, for example, column selection line 1 is turned on. As a result, both the transfer transistors 626 and 628 of pixel Gb in one pixel unit 656 within the unit group 655 are turned on, and the charge of pixel Gb is transferred to the gate of the amplification transistor 622. Here, since row selection line 1 is in the on state, the selection transistor 624 is also on, and the pixel signal amplified according to the charge transferred to the gate of the amplification transistor 622 is output from the output wiring 604 corresponding to the pixel unit 653.

[0107] Furthermore, by keeping row selection line 1 and the Gb transfer wiring in the on state and sequentially switching the on state of the column selection lines, the pixel signals of pixel Gb for one row are sequentially output from the respective output wirings 604. Therefore, the pixel signals from pixel Gb are input one pixel at a time to the A / D conversion circuit 614 via the bumps 606. In this case, since the selection transistor 642 is arranged in each pixel unit 656, the output from pixel Gb of the pixel unit 656 not selected by the column selection line is blocked. Therefore, the pixel signals of pixel Gb for one row in the unit group 655 are each read out without being affected by other pixel signals and stored in the pixel memory 414.

[0108] Next, by sequentially switching the on state of the column selection lines with row selection line 1 and the Gr transfer wiring turned on, the pixel signals of pixel Gr for one row are sequentially output from the respective output wirings 604. Similarly, by sequentially switching the on state of the column selection lines with row selection line 1 and the B transfer wiring turned on, the pixel signals of pixel B for one row are sequentially output from the respective output wirings 604, and by sequentially switching the on state of the column selection lines with row selection line 1 and the R transfer wiring turned on, the pixel signals of pixel R for one row are sequentially output from the respective output wirings 604.

[0109] As described above, pixel signals of two rows of pixels in the unit group 655 are read out. Next, by turning on the row selection line 2 and repeating the above procedure, pixel signals of the next two rows of pixels in the unit group 655 are read out. By repeating the above procedure for all row selection lines, pixel signals of all pixels in the unit group 655 are read out.

[0110] Also, in the forms shown in FIGS. 16 and 17, for each unit group 655, one row selection line may be provided for every two rows of pixels, which facilitates the routing of the wiring. Also, for each unit group 655, one output wiring may be provided for every two columns of pixels, which facilitates the routing of the wiring. Also, the CDS circuit can be provided on the side of the signal processing chip 111. Further, since it is not necessary to provide a multiplexer, the wiring on the side of the signal processing chip 111 can be simplified.

[0111] In the forms shown in FIGS. 12 to 17, the A / D conversion circuits 612 and 614 are provided one-to-one for the unit groups 602, 652, and 655, but the number of the A / D conversion circuits 612 and 614 is not limited to this. A plurality of A / D conversion circuits 612 and 614 may be provided for each unit group 602, 652, and 655. In this case, a plurality of output wirings 604 of each unit group 602, 652, and 655 are wired and input so as to be distributed to any of the plurality of A / D conversion circuits 612 and 614.

[0112] Also, the pixel unit consists of 4 pixels, the row selection wiring is arranged for every two rows of pixels, and the output wiring is arranged for every three columns of pixels, but it is not limited to this. For example, when the pixel unit consists of m rows and n columns, for the unit group, one row selection wiring may be provided for every m rows, one output wiring may be provided for every n columns, and m×n separate transfer wirings may be provided. Note that each transfer wiring may be common within the pixel group.

[0113] The imaging device 500 according to the above embodiment may be used to capture still images or may be used to capture moving images. When capturing moving images, the accumulation time for each pixel group may be changed temporally. For example, the accumulation time for each pixel group may be dynamically changed before and after the scene is switched. In this case, the accumulation time may be changed in the same manner as in the case of still images based on the immediately previous image. Also, based on the images of the immediately previous few seconds, for example, based on their time average, the accumulation time may be changed. Also, using a database in which the relationship between the shooting flow and the accumulation time is registered in advance, the accumulation time may be changed according to the shooting flow.

[0114] Also, in the above embodiment, the imaging chip 113, the signal processing chip 111, and the memory chip 112 are stacked, but they may not be stacked. That is, these functions may be provided on a single chip.

[0115] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0116] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly indicated as "earlier" or "preceding" etc., and unless the output of the previous process is used in the subsequent process, it can be realized in any order. Regarding the operation flows in the claims, the specification, and the drawings, even if "first," "next," etc. are used for convenience of explanation, it does not mean that it is essential to be implemented in this order.

Explanation of Reference Numerals

[0117] 100, 600, 650, 654 imaging elements, 101 microlenses, 102 color filters, 103 passivation films, 104 PDs, 105 transistors, 106 PD layers, 107 wirings, 108 wiring layers, 109, 606 bumps, 110 TSVs, 111 signal processing chips, 112 memory chips, 113 imaging chips, 131, 132, 167, 168, 602, 652, 655 unit groups, 150 pixels, 152, 626, 628, 630, 632, 634, 636, 638, 640 transfer transistors, 154, 620 reset transistors, 156, 622 amplification transistors, 158, 624, 642 selection transistors, 160 imaging elements, 162 aperture masks, 164 apertures, 165 apertures, 166 apertures, 170 pixels, 171, 174 row selection transistors, 172, 175 column selection transistors, 300, 326 reset wirings, 302 transfer wirings, 304 power supply wirings, 306 selection wirings, 308, 604 output wirings, 309 load current sources, 310, 330, 370 G transfer wirings, 311 load current sources, 312, 332, 372 R transfer wirings, 313 load current sources, 314, 334, 374 B transfer wirings, 315 load current sources, 316 power supply wirings, 318 selection wirings, 320, 321, 340, 380 G output wirings, 322, 323, 342, 382 R output wirings, 324, 325, 344, 384 B output wirings, 336 W transfer wirings, 346 W output wirings, 356 parallax transfer wirings, 366 parallax output wirings, 391, 394 row selection wirings, 392, 395 column selection wirings, 411, 421, 431, 610 multiplexers, 412, 422, 432 signal processing circuits, 413, 423, 433 demultiplexers, 414 pixel memories, 415 arithmetic circuits, 500 imaging devices, 520 photographing lenses, 501 system control units, 502 drive units, 503 photometry units, 504 work memories, 505 recording units, 506 display units, 511 image processing units, 512 arithmetic units, 603, 653, 656 pixel units, 608 CDS circuits, 612, 614 A / D conversion circuits

Claims

1. A pixel unit in which a first photoelectric conversion unit that converts light from an optical system into electric charges and is used for focus detection of the optical system and a second photoelectric conversion unit that converts light from the optical system into electric charges and is used for generating an image of a subject to be imaged are arranged along the row direction, and a driving unit that controls the accumulation times of the electric charges converted by the first photoelectric conversion unit and the electric charges converted by the second photoelectric conversion unit to be different accumulation times. An imaging unit comprising the same.

2. In the imaging unit according to Claim 1, a member having a first aperture portion having a first aperture and a second aperture portion having a second aperture larger than the first aperture is provided, the first photoelectric conversion unit converts the light that has passed through the first aperture among the light from the optical system into electric charges, and the second photoelectric conversion unit converts the light that has passed through the second aperture among the light from the optical system into electric charges. An imaging unit.

3. In the imaging unit according to Claim 1 or Claim 2, the driving unit controls the timing at which the accumulation of the electric charges converted by the first photoelectric conversion unit ends and the timing at which the accumulation of the electric charges converted by the second photoelectric conversion unit ends to be different timings. An imaging unit.

4. In the imaging unit according to Claim 3, the driving unit controls the timing at which the accumulation of the electric charges converted by the first photoelectric conversion unit starts and the timing at which the accumulation of the electric charges converted by the second photoelectric conversion unit starts to be different timings. An imaging unit.

5. In the imaging unit according to Claim 1 or Claim 2, the driving unit controls the timing at which the accumulation of the electric charges converted by the first photoelectric conversion unit starts and the timing at which the accumulation of the electric charges converted by the second photoelectric conversion unit starts to be different timings. An imaging unit.

6. In the imaging unit according to Claim 1 or Claim 2, the pixel unit includes a first transfer unit that transfers the electric charges converted by the first photoelectric conversion unit and a second transfer unit that transfers the electric charges converted by the second photoelectric conversion unit, and the driving unit controls the timing at which the electric charges converted by the first photoelectric conversion unit are transferred by the first transfer unit and the timing at which the electric charges converted by the second photoelectric conversion unit are transferred by the second transfer unit to be different timings. An imaging unit.

7. In the imaging unit according to Claim 6, The drive unit is an imaging unit that controls so that the timing at which the first transfer unit starts transferring the charge converted by the first photoelectric conversion unit and the timing at which the second transfer unit starts transferring the charge converted by the second photoelectric conversion unit are different timings.

8. In the imaging unit according to claim 6 or claim 7, The pixel unit includes a first discharging unit that discharges the charge converted by the first photoelectric conversion unit and a second discharging unit that discharges the charge converted by the second photoelectric conversion unit. The drive unit is an imaging unit that controls so that the timing at which the charge converted by the first photoelectric conversion unit is discharged by the first discharging unit and the timing at which the charge converted by the second photoelectric conversion unit is discharged by the second discharging unit are different timings.

9. In the imaging unit according to claim 8, The drive unit is an imaging unit that controls so that the timing at which the first discharging unit starts discharging the charge converted by the first photoelectric conversion unit and the timing at which the second discharging unit starts discharging the charge converted by the second photoelectric conversion unit are different timings.

10. In the imaging unit according to claim 1 or claim 2, The pixel unit includes a first discharging unit that discharges the charge converted by the first photoelectric conversion unit and a second discharging unit that discharges the charge converted by the second photoelectric conversion unit. The drive unit is an imaging unit that controls so that the timing at which the charge converted by the first photoelectric conversion unit is discharged by the first discharging unit and the timing at which the charge converted by the second photoelectric conversion unit is discharged by the second discharging unit are different timings.

11. In the imaging unit according to claim 10, The drive unit is an imaging unit that controls so that the timing at which the first discharging unit starts discharging the charge converted by the first photoelectric conversion unit and the timing at which the second discharging unit starts discharging the charge converted by the second photoelectric conversion unit are different timings.

12. In the imaging unit according to any one of claims 1 to 11, a first signal processing unit that performs first signal processing on a first signal based on the charge converted by the first photoelectric conversion unit; a second signal processing unit that performs second signal processing on a second signal based on the charge converted by the second photoelectric conversion unit An imaging unit comprising.

13. In the imaging unit according to claim 12, The first signal processing unit performs signal processing for amplifying the first signal at a first amplification factor as the first signal processing. The second signal processing unit is an imaging unit that performs signal processing for amplifying the second signal at a second amplification factor as the second signal processing.

14. In the imaging unit according to claim 13, the first signal processing unit performs signal processing for converting the first signal into a digital signal as the first signal processing, and the second signal processing unit is an imaging unit that performs signal processing for converting the second signal into a digital signal as the second signal processing.

15. In the imaging unit according to claim 12, the first signal processing unit performs signal processing for converting the first signal into a digital signal as the first signal processing, and the second signal processing unit is an imaging unit that performs signal processing for converting the second signal into a digital signal as the second signal processing.

16. In the imaging unit according to any one of claims 12 to 15, the first photoelectric conversion unit and the second photoelectric conversion unit are disposed on a first semiconductor substrate, and the first signal processing unit and the second signal processing unit are disposed on a second semiconductor substrate laminated with the first semiconductor substrate.

17. In the imaging unit according to any one of claims 12 to 15, a first storage unit that stores the signal on which the first signal processing has been performed, and a second storage unit that stores the signal on which the second signal processing has been performed are provided.

18. In the imaging unit according to claim 17, the first photoelectric conversion unit and the second photoelectric conversion unit are disposed on a first semiconductor substrate, the first signal processing unit and the second signal processing unit are disposed on a second semiconductor substrate laminated with the first semiconductor substrate, and the first storage unit and the second storage unit are disposed on a third semiconductor substrate laminated with the first semiconductor substrate.

19. An imaging device including the imaging unit according to any one of claims 1 to 18.

20. In the imaging device according to claim 19, an imaging device including an image processing unit that is electrically connected to the imaging unit and generates image data.

21. In the imaging device according to claim 19 or claim 20, a control unit is provided that causes the driving unit to execute control of an accumulation time for accumulating charges converted by the first photoelectric conversion unit and control of an accumulation time for accumulating charges converted by the second photoelectric conversion unit.

Images