Semiconductor device and power conversion device

Abstract

To suppress current concentration in an end part of an active region while suppressing the increase in chip area, and increase the cutoff tolerance.SOLUTION: In a semiconductor device 30, a diode 33 in an active region 31 includes a second electrode 12, a drift layer 5 of a first conductivity type, and a second semiconductor layer 2 of a second conductivity type provided in contact with the drift layer 5 and electrically connected to the second electrode 12. The active region 31 includes, between the diode 33 and a termination region 32, a third semiconductor layer 3 of the second conductivity type disposed in contact with the drift layer 5 and on the second semiconductor layer 2 side relative to the drift layer 5, and a fourth semiconductor layer 4 disposed between the second semiconductor layer 2 and the third semiconductor layer 3. The third semiconductor layer 3 and the fourth semiconductor layer 4 are not directly connected to the second electrode 12. The third semiconductor layer 3 has higher impurity concentration than the second semiconductor layer 2. The fourth semiconductor layer 4 has the second conductivity type or the first conductivity type, and has lower impurity concentration than the second semiconductor layer 2.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a power conversion device.

Background Art

[0002] Due to the global trend towards a decarbonized society, the markets for electric vehicles (EVs), power grids, and railways are growing steadily. For applications in these markets, a power conversion device that converts DC power supplied from a DC power source into an alternating current to control an inductive load such as an electric motor is used. As key components of the power conversion device, there are a semiconductor device and a gate drive circuit for driving the semiconductor device.

[0003] For semiconductor devices, in addition to low power loss, a high withstand capacity is required to block a large current flowing through the semiconductor device without destroying the semiconductor elements inside the semiconductor device. In an inverter device, which is a type of power conversion device, a freewheel diode is used as a semiconductor device for refluxing the current flowing through the inductive load. In order to achieve a high breakdown withstand capacity for such a diode, it has been reported that it is necessary to suppress current concentration at the end portion of the anode, and an element structure for realizing this is disclosed in, for example, Patent Document 1.

[0004] Patent Document 1 describes a diode element structure that reduces the carrier concentration injected from the end portion in the planar direction of the anode layer into the n-drift layer within the termination region by ensuring a certain distance or more between the end portion in the planar direction of the contact region between the anode layer and the anode electrode and the end portion in the planar direction of the junction between the anode layer and the n-drift layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In Patent Document 1, by ensuring that the distance (L) between the end of the contact region between the anode layer (p+-conductive semiconductor layer (11)) and the anode electrode (16) in the planar direction and the end of the junction (J1) between the anode layer and the n-drift layer (n-conductive semiconductor region (14)) in the planar direction is a certain value or more, the concentration of carriers injected from the end of the anode layer in the planar direction into the n-drift layer in the termination region can be reduced, and a technique is described in which the di / dt (critical di / dt) when destruction occurs during the recovery of the diode can be increased.

[0007] However, as the withstand voltage of the semiconductor device increases, the length of the distance (L) required to suppress the concentration of hole current during recovery becomes longer, resulting in a problem that the chip area increases.

[0008] The problem to be solved by the present invention is to provide a semiconductor device with a high breakdown withstand and a power conversion device using the same, which can suppress the increase in chip area while suppressing current concentration at the end of the active region.

Means for Solving the Problems

[0009] To solve the above problems, a semiconductor device according to the present invention is a semiconductor device having an active region with a diode and a termination region surrounding the active region, wherein the diode includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type electrically connected to the first electrode, a drift layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, and a second semiconductor layer of a second conductivity type in contact with the drift layer and electrically connected to the second electrode. The active region has, between the diode and the termination region, a third semiconductor layer of the second conductivity type in contact with the drift layer and disposed on the side of the second semiconductor layer with respect to the drift layer, and a fourth semiconductor layer disposed between the second semiconductor layer and the third semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are not directly connected to the second electrode. The third semiconductor layer has an impurity concentration higher than that of the second semiconductor layer, and the fourth semiconductor layer is of the second conductivity type or the first conductivity type and has an impurity concentration lower than that of the second semiconductor layer.

[0010] Further, a power conversion device according to the present invention is characterized by having a reflux diode using the above-described semiconductor device.

Advantages of the Invention

[0011] According to the present invention, it is possible to suppress an increase in chip area, suppress current concentration at the end of the active region, and realize a semiconductor device with a high breakdown withstand voltage and a power conversion device using the same.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant explanations are omitted.

Examples

[0014] FIG. 1 is a diagram showing the overall configuration of a motor control system using the power conversion device of Example 1.

[0015] The power conversion device 130 is a device that converts power using a power semiconductor device. Here, an example in which an inverter device is used as the power conversion device 130 will be described.

[0016] The motor control system 100 includes a DC power supply 110, a power conversion device 130, and a motor 120.

[0017] The power conversion device 130 includes a smoothing capacitor 131, an inverter unit 135 for three phases of the UVW phase (U-phase inverter unit 135U, V-phase inverter unit 135V, W-phase inverter unit 135W), and a command logic unit 132. The power conversion device 130 converts the DC power supplied from the DC power source 110 into AC power and outputs it to drive the motor 120. A smoothing capacitor 131 is provided between the DC power source 110 (power supply voltage = Vcc) and the positive connection line 133 and the negative connection line 134 of the power conversion device 130.

[0018] In each phase, the inverter unit 135 includes an upper arm, a lower arm, and a gate drive device 139. The upper arm and the lower arm each include a semiconductor switching element 136 and a freewheeling diode 137. The semiconductor switching element 136 of the upper arm and the semiconductor switching element 136 of the lower arm are connected in series. The semiconductor switching element 136 is composed of an IGBT (Insulated Gate Bipolar Transistor) in this embodiment. Gate signals (G1, G2) are transmitted from the gate drive device 139 to the gate of the semiconductor switching element 136. The high-potential side terminal of the semiconductor switching element 136 of the upper arm is connected to the first end side of the smoothing capacitor 131 via the positive connection line 133. The high-potential side terminal of the semiconductor switching element 136 of the lower arm is connected to the low-potential side terminal of the semiconductor switching element 136 of the upper arm. The low-potential side terminal of the semiconductor switching element 136 of the lower arm is connected to the second end side of the smoothing capacitor 131 via the negative connection line 134.

[0019] In each phase, the connection point 138 between the low-potential side terminal of the semiconductor switching element 136 of the upper arm and the high-potential side terminal of the semiconductor switching element 136 of the lower arm is connected to one end of the winding of the corresponding phase of the motor 120. The other end of the winding of each phase of the motor 120 is connected to the neutral point of the motor 120. The motor 120 is, for example, an induction motor.

[0020] A freewheeling diode 137 is connected in anti-parallel to each semiconductor switching element 136. As the freewheeling diode 137, various diodes such as a pn junction diode, a diode using both a pn junction and a Schottky junction, and a MOS controlled diode can be used.

[0021] The command logic unit 132 outputs, as drive command signals (P1, P2) for the semiconductor switching element 136, an on command instructing an on state or an off command instructing an off state to the gate drive device 139. The command logic unit 132 controls the semiconductor switching element 136 of the upper arm and the semiconductor switching element 136 of the lower arm in each phase to be alternately in an on state in order to control the control amount of the electric motor 120 to its command value. The control amount of the electric motor 120 is, for example, the torque of the electric motor.

[0022] The gate drive device 139 is provided corresponding to each semiconductor switching element 136, acquires the drive command signals (P1, P2) from the command logic unit 132, and outputs gate signals (G1, G2) based on the acquired drive command signals (P1, P2) to turn the semiconductor switching element 136 on or off.

[0023] Next, a configuration and operation of an example of the semiconductor device 30 used for the freewheeling diode 137 of the upper arm of the U phase in the power conversion device 130 shown in FIG. 1 will be described. The freewheeling diodes 137 of the lower arm of the U phase, the upper arms and the lower arms of the V phase and the W phase can also use the same semiconductor device 30 and have the same configuration and operation.

[0024] FIG. 2 is a plan view of the semiconductor device of Example 1. FIG. 3 is a cross-sectional view of the semiconductor device of Example 1. Note that FIG. 3 is a cross-sectional view taken along A-B of FIG. 2. Also, in FIG. 2, some of the components shown in FIG. 3 are omitted from illustration.

[0025] In this embodiment, an example in which the first conductivity type is n-type and the second conductivity type is p-type will be described. Note that the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the anode and the cathode are reversed, and the holes and electrons of the carriers are reversed.

[0026] The semiconductor device 30 of this embodiment has an active region 31 having a diode 33 and a termination region 32 surrounding the active region 31.

[0027] FIG. 2 shows a plan view of one main surface side (the side where the anode is formed) of the semiconductor substrate. A cathode is formed on the other main surface side of the semiconductor substrate. In order to ensure the breakdown voltage of the diode 33 in a state where a high voltage is applied to the cathode with respect to the anode, a termination region 32 is provided. The active region 31 surrounded by the termination region 32 is a current conduction region.

[0028] As shown in FIG. 3, the diode 33 in the active region 31 of the semiconductor device 30 of this embodiment includes a first electrode 11 (cathode electrode), a second electrode 12 (anode electrode), a first semiconductor layer 1 of the first conductivity type (cathode layer) electrically connected to the first electrode 11, a drift layer 5 of the first conductivity type having a lower impurity concentration than the first semiconductor layer 1, and a second semiconductor layer 2 of the second conductivity type (anode layer) in contact with the drift layer 5 and electrically connected to the second electrode 12.

[0029] The drift layer 5 is formed of, for example, a low-concentration n-type semiconductor substrate. A second semiconductor layer 2 serving as an anode layer is formed on one main surface side of the drift layer 5. At least a part of the second semiconductor layer 2 is in contact with the second electrode 12 serving as an anode electrode. A first semiconductor layer 1 serving as a cathode layer is formed on the other main surface side of the drift layer 5. The first semiconductor layer 1 is, for example, an n+-type high-concentration region. The first electrode 11 serving as a cathode electrode is in contact with the first semiconductor layer 1.

[0030] In the semiconductor device 30 of this embodiment, the active region 31 has a third semiconductor layer 3 of the second conductivity type, which is in contact with the drift layer 5 and is disposed on the side of the second semiconductor layer 2 with respect to the drift layer 5, between the diode 33 and the termination region 32, and a fourth semiconductor layer 4 disposed between the second semiconductor layer 2 and the third semiconductor layer 3.

[0031] The third semiconductor layer 3 and the fourth semiconductor layer 4 are not directly connected to the second electrode 12. Therefore, it is desirable that the active region 31 of the semiconductor device 30 has a first insulating film 13 that covers the third semiconductor layer 3 and the fourth semiconductor layer 4. The first insulating film 13 is, for example, an oxide film. The first insulating film 13 also covers a part of the second semiconductor layer 2 by the distance Δ in FIG. 3, and the second semiconductor layer 2 and the second electrode 12 are connected at the opening of the first insulating film 13.

[0032] The third semiconductor layer 3 is set to have a higher impurity concentration than the second semiconductor layer 2. The third semiconductor layer 3 is, for example, a p+-type high-concentration region. It is desirable that the third semiconductor layer 3 is formed at the end of the active region 31.

[0033] The fourth semiconductor layer 4 has the second conductivity type or the first conductivity type and is set to have a lower impurity concentration than the second semiconductor layer 2. The fourth semiconductor layer 4 is, for example, a p−-type or n−-type low-concentration region. When the fourth semiconductor layer 4 has the first conductivity type, for example, by forming the second semiconductor layer 2 and the third semiconductor layer 3 while separating them on the surface of the drift layer 5, a part of the drift layer 5 is left between the second semiconductor layer 2 and the third semiconductor layer 3, and a part of the drift layer 5 may also serve as the fourth semiconductor layer 4.

[0034] FIG. 4 is a diagram showing the relationship of the impurity concentration along C-D in FIG. 3. In FIG. 4, the horizontal axis is the horizontal distance x, and the vertical axis is the impurity concentration IC.

[0035] The impurity concentration of the fourth semiconductor layer 4 is designed to be lower than the impurity concentration of the second semiconductor layer 2. The impurity concentration of the second semiconductor layer 2 is, for example, 1×10 14 / cm 3 ~1×1016 / cm 3 is. The impurity concentration of the fourth semiconductor layer 4 is, for example, 1×10 12 / cm 3 ~1×10 14 / cm 3 . The impurity concentration of the third semiconductor layer 3 is designed to be higher than that of the second semiconductor layer 2. The impurity concentration of the third semiconductor layer 3 is, for example, 1×10 16 / cm 3 ~1×10 18 / cm 3 .

[0036] The ratio of the impurity concentration is preferably 10 -1 ~10 -2 times that of the impurity concentration of the second semiconductor layer 2 for the fourth semiconductor layer 4, and preferably 10 1 ~10 2 times that of the impurity concentration of the second semiconductor layer 2 for the third semiconductor layer 3.

[0037] Note that the effects of the third semiconductor layer 3 and the fourth semiconductor layer 4 will be described in detail in the following description of the operation.

[0038] As shown in FIG. 3, the termination region 32 of the semiconductor device 30 of this embodiment includes, for example, a drift layer 5, a first electrode 11, a first semiconductor layer 1, a second-conductivity-type breakdown voltage holding layer 21, a first-conductivity-type channel stopper 22, a second insulating film 23, and a termination portion field plate 24.

[0039] In the termination region 32, a plurality of breakdown voltage holding layers 21 are formed so as to surround the active region 31. The breakdown voltage holding layer 21 is, for example, a p+-type guard ring.

[0040] As a structure for ensuring the breakdown voltage of the diode 33 in addition to the breakdown voltage holding layer 21, a termination field plate 24 that is electrically connected to the breakdown voltage holding layer 21 and adjusts the electric field distribution, and a channel stopper 22 that is provided at the outermost periphery of the termination region 32 and terminates the electric field are formed. The channel stopper 22 is, for example, of n+ type. Also, a termination field plate 24 electrically connected to the channel stopper 22 is provided. A second insulating film 23 is formed between the termination field plate 24 and the breakdown voltage holding layer 21, or between the termination field plate 24 and the channel stopper 22. The second insulating film 23 is, for example, an oxide film. At the opening of the second insulating film 23, an electrical connection is made between the termination field plate 24 and the breakdown voltage holding layer 21, or between the termination field plate 24 and the channel stopper 22.

[0041] In FIG. 3, a plurality of breakdown voltage holding layers 21 are separated from each other. However, as long as the breakdown voltage of the diode 33 can be ensured, not all of the breakdown voltage holding layers 21 necessarily have to be separated from each other, and some of them may be adjacent to each other.

[0042] Next, the operation of the semiconductor device 30 of this embodiment will be described separately for the forward conduction state and the reverse recovery state.

[0043] FIG. 5 is a schematic diagram showing the flow of holes during forward conduction in the semiconductor device of Embodiment 1.

[0044] In FIG. 5, as shown with (+) on the anode side and (-) on the cathode side, when the potential of the anode side becomes higher than that of the cathode side and a forward voltage is applied in the forward conduction direction between the anode and the cathode, a large number of carriers are accumulated in the drift layer 5. The carriers (holes) injected from the anode side are not only injected into the drift layer 5 of the active region 31 from the second electrode 12 via the second semiconductor layer 2 as shown by arrow E, but also diffuse and are injected into the drift layer 5 of the termination region 32 from the second electrode 12 via the second semiconductor layer 2, the fourth semiconductor layer 4, and the third semiconductor layer 3 as shown by arrow F and are accumulated.

[0045] In this embodiment, since the third semiconductor layer 3 and the fourth semiconductor layer 4 are not directly connected to the second electrode 12, carriers (holes) are injected into the drift layer 5 of the termination region 32 via the second semiconductor layer 2, the fourth semiconductor layer 4, and the third semiconductor layer 3. And since the fourth semiconductor layer 4 is set to have a lower impurity concentration than the second semiconductor layer 2, it functions as a high-resistance layer with a large sheet resistance (R). As a result, since the hole current injected into the termination region 32 passes through the fourth semiconductor layer 4 with a large sheet resistance (R) as shown by arrow F, even if the distance L from the end of the region where the second electrode 12 and the second semiconductor layer 2 are in direct contact to the termination region 32 is short, the injection amount of holes into the termination region 32 can be suppressed. Note that although the third semiconductor layer 3 has a lower resistance because it has a higher impurity concentration than the second semiconductor layer 2, if the sheet resistance (R) of the fourth semiconductor layer 4 is sufficiently large, the influence on the required distance L is small.

[0046] Therefore, compared with the case where the second semiconductor layer 2, the third semiconductor layer 3, and the fourth semiconductor layer 4 all have the same impurity concentration, even if the distance L is short, the accumulation amount of carriers (holes) in the drift layer 5 of the termination region 32 can be reduced, so that an increase in the chip area of the semiconductor device 30 can be suppressed.

[0047] FIG. 6 is a schematic diagram showing the flow of holes during reverse recovery in the semiconductor device of Example 1.

[0048] In FIG. 6, as shown with (-) on the anode side and (+) on the cathode side, during the off state (reverse recovery state) where the anode side has a lower potential than the cathode side and a high reverse voltage is applied between the anode and the cathode, the carriers accumulated in the drift layer 5 are discharged. Since the cathode is at a higher potential than the anode, holes accumulated in the drift layer 5 flow toward the second electrode 12 and are discharged as indicated by arrow G. At this time, not only the holes accumulated in the drift layer 5 of the active region 31 but also the holes accumulated in the drift layer 5 of the termination region 32 flow into the second semiconductor layer 2 as indicated by arrow H. Therefore, at the end portion of the second semiconductor layer 2, there is a concern that current and electric field concentrate to cause dynamic avalanche, resulting in an increase in temperature and destruction of the diode 33.

[0049] In this embodiment, as described above, the accumulation amount of carriers (holes) injected and accumulated in the drift layer 5 of the termination region 32 during forward conduction is reduced. Therefore, it is possible to suppress the concentration of current and electric field during hole discharge during reverse recovery. Furthermore, since the impurity concentration of the third semiconductor layer 3 is set higher than that of the second semiconductor layer 2, the third semiconductor layer 3 functions as a low-resistance layer, and holes are more likely to gather in the third semiconductor layer 3 compared to the case where the impurity concentration of the third semiconductor layer 3 is the same as that of the second semiconductor layer 2. As a result, most of the holes accumulated in the drift layer 5 of the termination region 32 during forward conduction pass through the fourth semiconductor layer 4 via the third semiconductor layer 3 and flow into the second electrode 12 via the second semiconductor layer 2 as indicated by arrow H during reverse recovery. At this time, since it passes through the fourth semiconductor layer 4 with a large sheet resistance (R), the current does not flow all at once, and the current is dispersed in time and the current density decreases, so that the current concentration at the end portion of the second semiconductor layer 2 during reverse recovery can be suppressed. As a result, the electric field at the end portion of the second semiconductor layer 2 is suppressed and dynamic avalanche is less likely to occur. Even if the distance L is short, the breakdown tolerance of the diode 33 can be increased, and high breakdown tolerance can be achieved.

[0050] Thus, according to this embodiment, it is possible to suppress the current concentration at the end of the active region 31 while suppressing the increase in chip area, and to realize the semiconductor device 30 having a high breakdown withstand voltage and the power conversion device 130 using the same.

[0051] (Modification Example of Example 1) FIG. 7 is a cross-sectional view of a semiconductor device according to a modification example of Example 1.

[0052] In this modification example, the fourth semiconductor layer 4 has a second conductivity type and a configuration in which the depth of the bottom is shallower than the depths of the bottoms of the second semiconductor layer 2 and the fourth semiconductor layer 4. Such a fourth semiconductor layer 4 can be formed, for example, by forming the second semiconductor layer 2 and the third semiconductor layer 3 and then connecting them by lateral diffusion of impurities.

[0053] In this modification example, compared with Example 1, the impurity concentration of the fourth semiconductor layer 4 can be made lower (the sheet resistance can be made higher). This is because, instead of additionally introducing impurities by a method such as ion implantation, the fourth semiconductor layer 4 is formed only by the lateral diffusion of impurities in the second semiconductor layer 2 and the third semiconductor layer 3. Therefore, the impurity concentration of the fourth semiconductor layer 4 is relatively lower and the sheet resistance is higher than in the case of ion implantation.

[0054] According to this modification example, since the sheet resistance of the fourth semiconductor layer 4 can be made even higher than in Example 1, current concentration can be suppressed more effectively, and the breakdown withstand voltage of the semiconductor device 30 can be increased. Alternatively, if the same breakdown withstand voltage is provided, the distance L can be shortened more, and the chip area can be reduced.

Example

[0055] FIG. 8 is a cross-sectional view of a semiconductor device according to Example 2.

[0056] Example 2 is a modification example of Example 1. The semiconductor device 30 has a first insulating film 13 that covers at least the fourth semiconductor layer 4, and a part of the second electrode 12 is formed on the first insulating film 13 and covers at least the fourth semiconductor layer 4 via the first insulating film 13.

[0057] According to this embodiment, since the second electrode 12 projects so as to cover at least the fourth semiconductor layer 4, the projecting portion (the portion of the distance L1 in FIG. 8) is formed on the fourth semiconductor layer 4 via the first insulating film 13 as a field plate connected to the second electrode 12. Therefore, when forward conduction occurs with the anode potential higher than that of the cathode, a depletion layer easily extends on the surface of the fourth semiconductor layer 4, and the sheet resistance of the fourth semiconductor layer 4 further increases compared to the first embodiment. As a result, the amount of holes injected into the termination region 32 can be suppressed more than in the first embodiment. Therefore, even if the distance L is short, the accumulation amount of carriers (holes) in the drift layer 5 of the termination region 32 can be reduced.

[0058] Also, during reverse recovery when the cathode potential is higher than that of the anode, due to the field plate effect of the projecting portion, the interval between equipotential lines in the fourth semiconductor layer 4 widens. As a result, since the potential difference (ΔV in FIG. 8) on the current path from the fourth semiconductor layer 4 to the second semiconductor layer 2 is reduced compared to the first embodiment, current concentration can be effectively suppressed. Therefore, the electric field in this region is suppressed, and dynamic avalanche is less likely to occur, resulting in an increase in the breakdown withstand of the semiconductor device 30.

[0059] (Modification of Embodiment 2) FIG. 9 is a cross-sectional view of a semiconductor device according to a modification of Embodiment 2.

[0060] The semiconductor device 30 of this modification has a direct connection region where the second electrode 12 and the second semiconductor layer 2 are in direct contact at least partially, and it is desirable that the planar distance (Δ in FIG. 8) between the end of the direct connection region (I in FIG. 8) and the boundary between the second semiconductor layer 2 and the third semiconductor layer 3 (J in FIG. 8) is 5 μm or less.

[0061] FIG. 9 shows the case where Δ = 0 and I and J are the same. However, it may be ensured until the depletion layer on the surface of the fourth semiconductor layer 4 does not reach the second semiconductor layer 2 (for example, until Δ is about 5 μm). Therefore, it is desirable that Δ ≤ 5 μm.

[0062] In the second embodiment, during reverse recovery, when holes accumulated in the drift layer 5 of the termination region 32 flow toward the second electrode 12 as indicated by the arrow H in FIG. 9, the potential of the fourth semiconductor layer 4 increases by an amount equal to the product of the sum of the sheet resistances of the second semiconductor layer 2 and the fourth semiconductor layer 4 and the current flowing laterally through the second semiconductor layer 2 and the fourth semiconductor layer 4 during reverse recovery. As a result, the maximum electric field strength applied to the first insulating film 13 between the fourth semiconductor layer 4 and the second electrode 12 increases, raising concerns about shortening the life of the insulating film.

[0063] In this modification, by setting Δ ≤ 5 μm, the contribution of the sheet resistance of the second semiconductor layer 2 becomes small, so the potential of the fourth semiconductor layer 4 decreases and the maximum electric field strength applied to the first insulating film 13 is reduced, which acts in the direction of ensuring the life of the insulating film.

Embodiment

[0064] FIG. 10 is a cross-sectional view of the semiconductor device of the third embodiment.

[0065] The third embodiment is a modification of the second embodiment. The semiconductor device 30 has a first insulating film 13 that covers at least the fourth semiconductor layer 4 and a field plate 14 formed inside the first insulating film 13. The field plate 14 is electrically connected to the second electrode 12 and covers at least the fourth semiconductor layer 4 via the first insulating film 13.

[0066] According to this embodiment, due to the field plate 14 electrically connected to the second electrode 12, the distance between the second electrode 12 and the fourth semiconductor layer 4 becomes closer than in Example 2. When forward conduction occurs with the potential of the anode higher than that of the cathode, the depletion layer on the surface of the fourth semiconductor layer 4 extends more easily than in Example 2, and the sheet resistance of the fourth semiconductor layer 4 further increases. As a result, the injection amount of holes into the termination region 32 can be more effectively suppressed. Therefore, even when the distance L is short, the accumulation amount of carriers (holes) in the drift layer 5 of the termination region 32 can be reduced.

[0067] Also, due to the field plate 14 electrically connected to the second electrode 12, the distance between the second electrode 12 and the fourth semiconductor layer 4 becomes closer than in Example 2. During reverse recovery when the potential of the cathode is higher than that of the anode, the field plate effect by the field plate 14 is further enhanced, and the interval between the equipotential lines in the fourth semiconductor layer 4 further expands. As a result, since the potential difference (ΔV in FIG. 10) on the current path from the fourth semiconductor layer 4 to the second semiconductor layer 2 is further reduced, current concentration can be more effectively suppressed. Therefore, the electric field in this region is suppressed, and dynamic avalanche is less likely to occur, resulting in an increase in the breakdown withstand of the semiconductor device 30.

Example

[0068] FIG. 11 is a cross-sectional view of the semiconductor device of Example 4.

[0069] Example 4 is a modification of Example 3. The semiconductor device 30 includes at least a first insulating film 13 covering the fourth semiconductor layer 4, a field plate 14 formed inside the first insulating film 13, and a bias application electrode 15 for applying a voltage biased with respect to the second electrode 12. The field plate 14 is electrically connected to the bias application electrode 15 and covers at least the fourth semiconductor layer 4 via the first insulating film 13.

[0070] According to this embodiment, when the bias application electrode 15 is positively biased with respect to the second electrode 12, the positively biased field plate 14 makes it easier for the depletion layer to extend on the surface of the fourth semiconductor layer 4 than in the third embodiment, and the sheet resistance of the fourth semiconductor layer 4 further increases. As a result, the amount of holes injected into the termination region 32 can be more effectively suppressed. Therefore, even if the distance L is short, the accumulation amount of carriers (holes) in the drift layer 5 of the termination region 32 can be reduced.

[0071] Also, when the bias application electrode 15 is positively biased with respect to the second electrode 12, the positively biased field plate 14 makes it easier for the depletion layer to extend on the surface of the fourth semiconductor layer 4 than in the third embodiment. Also, during reverse recovery when the potential of the cathode becomes higher than that of the anode, since the sheet resistance increases on the path of the hole current from the fourth semiconductor layer 4 to the second semiconductor layer 2, current concentration can be effectively suppressed. Therefore, the electric field in this region is suppressed, and dynamic avalanche is less likely to occur, resulting in an increase in the breakdown withstand of the semiconductor device 30.

[0072] (Modification of Example 4) In the modification of Example 4, in Example 4, as the diode 33, a MOS controlled diode 41 is used.

[0073] FIG. 12 is a cross-sectional view for explaining the structure of the MOS controlled diode used in the semiconductor device of the modification of Example 4.

[0074] The semiconductor device 30 of this modification has an n-type first conductivity type and a p-type second conductivity type. The diode 33 has the first electrode 11, the second electrode 12, the first semiconductor layer 1, the second semiconductor layer 2, and the drift layer 5 as in Example 4, and further has a gate electrode 42 to which a voltage biased with respect to the second electrode 12 is applied, and a gate insulating film 43 provided between the gate electrode 42 and the second semiconductor layer 2, and the bias application electrode 15 and the gate electrode 42 are electrically connected.

[0075] In addition, in FIG. 12, a low-concentration p-type is used for the second semiconductor layer 2, but it is not limited to this. Even when a low-concentration p-type is used for the second semiconductor layer 2, the point of making the impurity concentration of the third semiconductor layer 3 higher than that of the second semiconductor layer 2 and making the impurity concentration of the fourth semiconductor layer 4 lower than that of the second semiconductor layer 2 is the same as in other embodiments.

[0076] Also, in FIG. 12, a so-called side gate type gate electrode 42 in which the gate electrode 42 is formed on the side wall of the wide trench 47 is used, but it is not limited to this. For example, the gate electrode 42 may be formed inside a normal trench that is not wide. In the case of a normal trench, the interlayer insulating film 48 provided inside the wide trench 47 does not need to be provided inside the normal trench.

[0077] Also, in FIG. 12, the second electrode 12 and the second semiconductor layer 2 are electrically connected via the P+ layer 45, or via the P+ layer 45 and the P layer 44, or via the n+ layer 46 and the P layer 44, but it is not limited to this.

[0078] FIG. 13 is a timing chart for explaining a semiconductor device and a control method of a power conversion device in a modified example of Example 4.

[0079] Note that the power conversion device 130 of this modified example has a driving device (not shown) that applies drive signals (DG1, DG2) to the gate electrode 42 and the bias application electrode 15 of the semiconductor device 30 of this modified example used as the freewheeling diode 137. Similarly, also in Example 4, the power conversion device 130 has a driving device (not shown) that applies a bias voltage to the bias application electrode 15 of the semiconductor device 30 of Example 4 used as the freewheeling diode 137. These driving devices are controlled by a driving command signal (not shown) from the command logic unit 132.

[0080] As shown in FIG. 13, at time t1, when the drive command signal P2 from the command logic unit 132 switches from the H level to the L level, the gate drive device 139 switches the gate signal G2 applied to the gate of the semiconductor switching element 136 of the lower arm from +15V to -15V, turning off the semiconductor switching element 136 of the lower arm. As a result, the forward conduction period T1 during which the freewheeling diode 137 of the upper arm conducts in the forward direction starts. At this time, the drive signal DG1 applied to the gate electrode 42 and the bias application electrode 15 of the freewheeling diode 137 of the upper arm is -15V, which is a negative bias.

[0081] At time t2, which is after the dead time DT from time t1, the drive command signal P1 from the command logic unit 132 switches from the L level to the H level, and the gate drive device 139 switches the gate signal G1 applied to the gate of the semiconductor switching element 136 of the upper arm from -15V to +15V, turning on the semiconductor switching element 136 of the upper arm. As a result, the reverse recovery period td_rr2 of the freewheeling diode 137 of the lower arm starts.

[0082] At time t3, the reverse recovery period td_rr2 of the freewheeling diode 137 of the lower arm ends.

[0083] Time t4 is a time that is a predetermined period before time t6. At time t4, the drive signal DG1 is switched from -15V, which is a negative bias, to +15V, which is a positive bias. As a result, the MOS gate of the MOS control diode 41 turns on, and the charge extraction period td_rr1 during which charge is extracted from the MOS control diode 41 starts.

[0084] At time t5, the drive command signal P1 switches from the H level to the L level, and the gate signal G1 is switched from +15V to -15V. As a result, the semiconductor switching element 136 of the upper arm is turned off.

[0085] At time t6 after the dead time DT from time t5, the drive command signal P2 switches from the L level to the H level, and the gate signal G2 is switched from -15V to +15V. As a result, the semiconductor switching element 136 of the lower arm is turned on. Consequently, the freewheeling diode 137 of the upper arm transitions to reverse recovery, and the forward conduction period T1 and the charge extraction period td_rr1 of the freewheeling diode 137 of the upper arm end, and the reverse recovery period td_rr2 of the freewheeling diode 137 of the upper arm starts.

[0086] Then, at time t7, the reverse recovery period td_rr2 of the freewheeling diode 137 of the upper arm ends. At this time, the drive signal DG1 is switched from -15V, which is a positive bias, to -15V, which is a negative bias.

[0087] By the operation of this modified example, when the semiconductor switching element 136 of the lower arm turns off at time t1 and the current flowing through the motor 120, which is a load, commutes to the freewheeling diode 137 of the upper arm and the freewheeling diode 137 of the upper arm conducts in the forward direction, the drive signal DG1 applied to the gate electrode 42 and the bias application electrode 15 of the freewheeling diode 137 of the upper arm is set to a negative bias (for example, the potential of the gate electrode 42 with respect to the potential of the second electrode 12 is -15V). As a result, the MOS gate of the MOS controlled diode 41 turns off and operates as a normal diode.

[0088] Then, at time t4, which is a timing a predetermined period (charge extraction period td_rr1) before the timing when the semiconductor switching element 136 of the lower arm turns on at time t6 and the freewheeling diode 137 of the upper arm transitions to reverse recovery, the gate electrode 42 of the freewheeling diode 137 of the upper arm is set to a positive bias (for example, the potential of the gate electrode with respect to the potential of the second electrode 12 is +15V). As a result, the MOS gate of the MOS controlled diode 41 turns on and a channel is formed, so carriers are extracted from the anode side and the carriers accumulated in the active region 31 are extracted.

[0089] Thereafter, until the reverse recovery of the upper arm's freewheeling diode 137 is completed at time t7 (reverse recovery period td_rr2), after holding the gate electrode 42 at a positive bias, it is returned to a negative bias. Therefore, the positive bias application period T2 during which the gate electrode 42 is at a positive bias may be a period obtained by combining the charge extraction period td_rr1 and the reverse recovery period td_rr2.

[0090] Summarizing the above operations, in this modified example, the gate electrode 42 and the bias application electrode 15 are applied with a negative bias voltage when the diode 33 (MOS controlled diode 41 in this modified example) is forward conducting, during a predetermined period (charge extraction period td_rr1) before the diode 33 transitions to reverse recovery, and during the period from when the diode 33 transitions to reverse recovery until it is completed (reverse recovery period td_rr2), a positive bias voltage is applied.

[0091] According to this modified example, during the charge extraction period td_rr1, due to the field plate 14 being positively biased with respect to the second electrode 12, the depletion layer on the surface of the fourth semiconductor layer 4 becomes even more likely to extend as in Example 4, and the sheet resistance of the fourth semiconductor layer 4 further increases. As a result, the amount of hole injection into the termination region 32 can be more effectively suppressed.

[0092] Furthermore, during the charge extraction period td_rr1, when the MOS gate of the MOS controlled diode 41 turns on, the carriers accumulated in the active region 31 are extracted, so the amount of hole accumulation diffusing into the termination region 32 can be reduced compared to Example 4.

[0093] Therefore, even when the distance L is short, the amount of carrier (hole) accumulation in the drift layer 5 of the termination region 32 can be reduced.

[0094] Also, during the reverse recovery period td_rr2, due to the field plate 14 being positively biased with respect to the second electrode 12, the depletion layer on the surface of the fourth semiconductor layer 4 becomes even more likely to extend as in Example 4. Also during reverse recovery when the potential of the cathode becomes higher than that of the anode, the sheet resistance on the path of the hole current from the fourth semiconductor layer 4 to the second semiconductor layer 2 increases.

[0095] Furthermore, due to the effect of charge extraction by turning on the MOS gate of the MOS control diode 41 during the charge extraction period td_rr1, the amount of hole accumulation diffused to the termination region 32 is sufficiently reduced compared to Example 4 immediately before reverse recovery.

[0096] Therefore, current concentration can be effectively suppressed. As a result, the electric field in the region is suppressed and dynamic avalanche is less likely to occur, so the breakdown withstand voltage of the semiconductor device 30 can be increased.

[0097] Also, since reverse recovery occurs with the carriers accumulated in the active region 31 sufficiently extracted, the reverse recovery charge is reduced, and the recovery loss of the diode 33 of the semiconductor device 30 is reduced.

[0098] Also, as the voltage applied to the bias application electrode 15, the voltage applied to the gate electrode 42 of the MOS control diode 41 can be used.

Example

[0099] Example 5 is a modified example of the power conversion devices of Examples 1 to 4.

[0100] The semiconductor switching element 136 used in the power conversion device 130 is not limited to an IGBT. The semiconductor material can also be changed to Si, SiC, GaN, gallium oxide, etc. and applied. Also, it can be used not only for power conversion devices for hybrid vehicles, electric vehicles, and railway applications, but for power conversion devices in general.

[0101] The above describes the embodiments of the present invention. However, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical idea of the present invention. Also, a part or all of the configurations described in each embodiment may be combined and applied.

[0102] Also, regarding the impurity concentration, it is just an example and can be appropriately changed within the range where the intended operations in the embodiments can be realized.

Description of Reference Numerals

[0103] 1: First semiconductor layer (cathode layer) 2: Second semiconductor layer (anode layer) 3: Third semiconductor layer 4: Fourth semiconductor layer 5: Drift layer 11: First electrode (cathode electrode) 12: Second electrode (anode electrode) 13: First insulating film 14: Field plate 15: Bias application electrode 21: Breakdown voltage holding layer 22: Channel stopper 23: Second insulating film 24: Termination region field plate 30: Semiconductor device 31: Active region 32: Termination region 33: Diode 41: MOS controlled diode 42: Gate electrode 43: Gate insulating film 44: P layer 45: P+ layer 46: n+ layer 47: Trench 48: Interlayer insulating film 100: Motor control system 110: DC power supply 120: Motor 130: Power conversion device 131: Smoothing capacitor 132: Command logic unit 133: Positive electrode connection wire 134: Negative electrode connection wire 135: Inverter unit 136: Semiconductor switching element 137: Freewheeling diode 138: Connection point 139: Gate drive device x: Horizontal distance IC: Impurity concentration DT: Dead time td_rr1: Charge extraction period td_rr2: Reverse recovery period

Claims

1. A semiconductor device having an active region with a diode and a termination region surrounding the active region, wherein the diode includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type electrically connected to the first electrode, a drift layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, and a second semiconductor layer of a second conductivity type in contact with the drift layer and electrically connected to the second electrode, the active region having, between the diode and the termination region, a third semiconductor layer of the second conductivity type in contact with the drift layer and disposed on the side of the second semiconductor layer with respect to the drift layer, and a fourth semiconductor layer disposed between the second semiconductor layer and the third semiconductor layer, the third semiconductor layer and the fourth semiconductor layer not being directly connected to the second electrode, the third semiconductor layer having an impurity concentration higher than that of the second semiconductor layer, and the fourth semiconductor layer being of the second conductivity type or the first conductivity type and having an impurity concentration lower than that of the second semiconductor layer. A semiconductor device characterized by this.

2. In Claim 1, a semiconductor device characterized in that the fourth semiconductor layer is of the second conductivity type.

3. In Claim 1, a semiconductor device characterized in that the fourth semiconductor layer is of the second conductivity type and has a bottom depth shallower than the bottom depths of the second semiconductor layer and the fourth semiconductor layer.

4. In Claim 1, having a first insulating film covering at least the fourth semiconductor layer, wherein the second electrode is partially formed on the first insulating film and covers at least the fourth semiconductor layer via the first insulating film. A semiconductor device characterized by this.

5. In Claim 1, having a direct connection region where the second electrode and the second semiconductor layer are at least partially in direct contact, and a semiconductor device characterized in that the planar distance between the end of the direct connection region and the boundary between the second semiconductor layer and the third semiconductor layer is 5 μm or less.

6. In Claim 1, having a first insulating film covering at least the fourth semiconductor layer, and a field plate formed inside the first insulating film, wherein the field plate is electrically connected to the second electrode and covers at least the fourth semiconductor layer via the first insulating film. A semiconductor device characterized by this.

7. In Claim 1, having a first insulating film covering at least the fourth semiconductor layer, A field plate formed inside the first insulating film, and a bias application electrode for applying a voltage biased with respect to the second electrode, wherein the field plate is electrically connected to the bias application electrode and covers at least the fourth semiconductor layer via the first insulating film. A semiconductor device characterized by this.

8. In claim 7, wherein the first conductivity type is n-type and the second conductivity type is p-type, the diode has a gate electrode to which a voltage biased with respect to the second electrode is applied, and a gate insulating film provided between the gate electrode and the second semiconductor layer, A semiconductor device characterized in that the bias application electrode and the gate electrode are electrically connected.

9. In claim 8, when the diode is forward-conducting, a negative bias voltage is applied to the gate electrode and the bias application electrode, and a positive bias voltage is applied during a predetermined period before the diode transitions to reverse recovery and during the period from when the diode transitions to reverse recovery until completion. A semiconductor device characterized by this.

10. In claim 1, The impurity concentration of the second semiconductor layer is 1×10 １４ / cm ３ ~1×10 １６ / cm ３ and The impurity concentration of the third semiconductor layer is 1×10 １６ / cm ３ to 1×10 １８ / cm ３ and The impurity concentration of the fourth semiconductor layer is 1×10 １２ / cm ３ to 1×10 １４ / cm ３ A semiconductor device characterized by this.

11. In claim 1, The impurity concentration of the third semiconductor layer is 10 １ to 10 ２ times that of the second semiconductor layer, The impurity concentration of the fourth semiconductor layer is 10 －１ to 10 －２ times that of the second semiconductor layer, characterized by a semiconductor device.

12. In claim 1, A semiconductor device characterized in that the first conductivity type is n-type and the second conductivity type is p-type.

13. A power conversion device that converts DC power into AC power, characterized by having a reflux diode using the semiconductor device according to any one of claims 1 to 12.

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