Device with piezoelectric element, laminated substrate and method for manufacturing device

Abstract

To provide a device comprising a semiconductor element and a piezoelectric element having a piezoelectric film composed of an alkali niobium oxide containing potassium, sodium, niobium, and oxygen, formed on the same substrate.SOLUTION: A device has a semiconductor element and a piezoelectric element having a piezoelectric film composed of an alkali niobium oxide containing potassium, sodium, niobium, and oxygen, and the semiconductor element and the piezoelectric element are formed on the same substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to an apparatus including a piezoelectric element, a laminated substrate, and a method for manufacturing the apparatus.

Background Art

[0002] Piezoelectrics are widely used in functional electronic components such as sensors and actuators. As piezoelectric materials, lead-based materials, particularly, perovskite-type ferroelectrics represented by the composition formula Pb(Zr 1-x Ti x )O3 are widely used. Since PZT-based piezoelectrics contain lead, they are not preferable from the viewpoint of pollution prevention. Therefore, as lead-free piezoelectric materials, piezoelectric materials containing potassium, sodium, niobium, and oxygen have been proposed, and piezoelectric elements having a piezoelectric film (hereinafter referred to as a KNN film) formed using such a piezoelectric material have been proposed (see, for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, it may be required to form a piezoelectric element having the above-described KNN film on a substrate on which a semiconductor element is formed. At this time, it may be required to reduce the thermal history with respect to the semiconductor element. For this reason, when forming a KNN film on a substrate on which a semiconductor element is formed, it may be required to form the KNN film at a low temperature. However, when the KNN film is formed at a low temperature, the piezoelectric characteristics may deteriorate. Therefore, it has been difficult to form a piezoelectric element having a KNN film on a substrate on which a semiconductor element is formed.

[0005] The present disclosure aims to provide an apparatus in which a semiconductor element and a piezoelectric element having a KNN film are formed on the same substrate.

Means for Solving the Problems

[0006] According to one aspect of the present disclosure, a semiconductor element, and a piezoelectric element having a piezoelectric film composed of an alkali niobate oxide containing potassium, sodium, niobium, and oxygen, wherein the semiconductor element and the piezoelectric element are formed on the same substrate, an apparatus or a laminated substrate is provided.

[0007] According to another aspect of the present disclosure, a step of preparing a substrate on which a semiconductor element is formed, and a step of forming a piezoelectric element on the substrate, wherein the step of forming the piezoelectric element includes a step of forming a piezoelectric film composed of an alkali niobate oxide containing potassium, sodium, niobium, and oxygen on the substrate under the conditions that the film formation temperature is 400 °C or higher and lower than 500 °C, the oxygen partial pressure is 0.0025 Pa or higher and lower than 0.01 Pa, and the atmospheric pressure is 0.03 Pa or higher and lower than 0.1 Pa, a method for manufacturing an apparatus is provided.

Advantages of the Invention

[0008] According to the present disclosure, an apparatus in which a semiconductor element and a piezoelectric element having a KNN film are formed on the same substrate can be provided.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Mode for Carrying Out the Invention

[0010] <One Aspect of the Present Disclosure> Hereinafter, one aspect of the present disclosure will be described with reference to the drawings.

[0011] (1) Configuration of an Apparatus Having a Piezoelectric Element FIG. 1 shows a schematic configuration diagram of an apparatus 100 having a piezoelectric element according to this aspect. The apparatus 100 includes a semiconductor element 30 and a piezoelectric element (an element having a piezoelectric film) 20. In the apparatus 100, the semiconductor element 30 and the piezoelectric element 20 are formed on the same substrate 1.

[0012] The apparatus 100 is obtained by processing a laminated substrate having a piezoelectric film (a laminate having a piezoelectric film (piezoelectric laminate)) 10 (hereinafter also referred to as the laminate 10). FIG. 2 shows a schematic configuration diagram of the laminate 10 according to this aspect. As shown in FIG. 2, the laminate 10 includes a substrate 1, a lower electrode film 2 formed on the substrate 1, a piezoelectric film (piezoelectric thin film) 3 formed on the lower electrode film 2, and an upper electrode film 4 formed on the piezoelectric film 3. Note that the film obtained by "film formation" in the present disclosure is a film directly deposited on the substrate 1 and does not include a film bonded (joined) to the substrate 1.

[0013] As the substrate 1, for example, a p-type single crystal silicon (Si) substrate 1a can be used. The thickness of the substrate 1 can be, for example, 300 μm or more and 1000 μm or less.

[0014] On either one of the two main surfaces (upper surface) of the substrate 1, a semiconductor element 30 is formed. The semiconductor element 30 includes, for example, a p-type MOSFET 31 and an n-type MOSFET 32, and has a CMOS (Complementary Metal Oxide Semiconductor) structure in which these function complementarily. The p-type MOSFET 31 includes an n-well 311 formed in the substrate 1, a p-type source region 312 and a p-type drain region 313 provided apart from each other in the n-well 311, a gate insulating film 314, a gate electrode 315 formed on the gate insulating film 314, a source electrode 316 electrically connected to the p-type source region 312, and a drain electrode 317 electrically connected to the p-type drain region 313. The n-type MOSFET 32 includes an n-type source region 321 and an n-type drain region 322 provided apart from each other on the substrate 1, a gate insulating film 323, a gate electrode 324 formed on the gate insulating film 323, a source electrode 325 electrically connected to the n-type source region 321, and a drain electrode 326 electrically connected to the n-type drain region 322. The n-well 311, the n-type source region 321, and the n-type drain region 322 are regions formed on either one of the two main surfaces of the substrate 1 by thermal diffusion of an n-type dopant or the like. The p-type source region 312 and the p-type drain region 313 are regions formed on the surface of the n-well 311 by thermal diffusion of a p-type dopant or the like.

[0015] A protective film 33 such as an oxide film or a nitride film for protecting the semiconductor element 30 may be further formed on the substrate 1. The protective film 33 may be considered to be included in the semiconductor element 30.

[0016] Of the surface of the substrate 1 on which the semiconductor element 30 is formed (hereinafter, also referred to as the "upper surface of the substrate 1"), a surface oxide film (SiO2 film) 1b such as a thermal oxide film or a CVD (Chemical Vapor Deposition) oxide film may be formed on the portion other than the formation location of the semiconductor element 30. That is, the substrate 1 may be a p-type single crystal Si substrate 1a having the surface oxide film 1b. The thickness of the surface oxide film 1b can be, for example, 1 nm or more and 4000 nm or less. Instead of the surface oxide film 1b, the substrate 1 may have an insulating film formed of an insulating material other than SiO2. Further, the substrate 1 may not have the surface oxide film 1b or the insulating film.

[0017] The lower electrode film 2 is formed at a position on the upper surface of the substrate 1 different from the formation location of the semiconductor element 30 (on the surface oxide film 1b or the insulating film when the substrate 1 has a surface oxide film 1b or an insulating film, etc.). The lower electrode film 2 can be formed using, for example, platinum (Pt). The lower electrode film 2 is a polycrystalline film. Hereinafter, the polycrystalline film formed using Pt is also referred to as a Pt film. It is preferable that the (111) plane of the Pt film is parallel to the main plane of the substrate 1 (including the case where the (111) plane is inclined at an angle within ±5° with respect to the main plane of the substrate 1), that is, the Pt film is oriented in the (111) plane orientation. That the Pt film is oriented in the (111) plane orientation means that no peaks other than the peak caused by the (111) plane are observed in the X-ray diffraction pattern obtained by X-ray diffraction (XRD) measured on the surface of the piezoelectric film 3. Thus, it is preferable that the main plane of the lower electrode film 2 (the plane serving as the base of the piezoelectric film 3) is composed of the Pt(111) plane. The lower electrode film 2 can be formed by a method such as sputtering or vapor deposition. As materials for the lower electrode film 2, in addition to Pt, various metals such as gold (Au), ruthenium (Ru), or iridium (Ir), alloys having these as main components, metal oxides such as strontium ruthenate (SrRuO3, abbreviation: SRO) or lanthanum nickelate (LaNiO3, abbreviation: LNO), etc. can also be used. When forming the lower electrode film 2 using a metal oxide, it is preferable that the crystal constituting the lower electrode film 2 is preferentially oriented in the (001) plane orientation with respect to the surface of the substrate 1. The lower electrode film 2 can be a single-layer film formed using the above various metals, alloys having the above various metals as main components, or metal oxides, etc. The lower electrode film 2 may be a laminate of a Pt film and a film mainly composed of SRO provided on the Pt film, a laminate of a Pt film and a film mainly composed of LNO provided on the Pt film, etc. The thickness of the lower electrode film 2 (when the lower electrode film 2 is a laminate, the total thickness of each layer) can be, for example, 100 nm or more and 400 nm or less.

[0018] A adhesion layer 6 may be provided between the substrate 1 and the lower electrode film 2 to enhance their adhesion. The adhesion layer 6 can be, for example, a layer mainly composed of zinc (Zn) and oxygen (O) (hereinafter also referred to as "ZnO layer"). The ZnO layer can be formed using, for example, zinc oxide. The composition ratio of Zn and O constituting the ZnO layer preferably satisfies the relationship of Zn:O = 1:1, but is not limited thereto, and there may be some variations. The ZnO layer is a polycrystalline layer. The (0001) plane of the ZnO layer is preferably parallel to the main surface of the substrate 1 (including the case where the (0001) plane is inclined at an angle within ±5° with respect to the main surface of the substrate 1), that is, the ZnO layer is preferably oriented in the (0001) plane direction. That the ZnO layer is oriented in the (0001) plane direction means that in the X-ray diffraction pattern obtained by XRD measured on the surface of the piezoelectric film 3, the intensity of the peak caused by the (0002) plane is high. Thus, the main surface of the ZnO layer (the surface serving as the base for the lower electrode film 2) is preferably composed of the ZnO (0001) plane. The ZnO layer can be formed by a method such as sputtering or vapor deposition. The thickness of the ZnO layer can be, for example, 1 nm or more and 200 nm or less, preferably 10 nm or more and 50 nm or less. As the adhesion layer 6, for example, a layer mainly composed of titanium (Ti), tantalum (Ta), titanium oxide (TiO2), nickel (Ni), ruthenium oxide (RuO2), iridium oxide (IrO2), etc. may be provided. Such an adhesion layer 6 can also be formed by a method such as sputtering or vapor deposition, and the thickness of the adhesion layer 6 can be, for example, 1 nm or more and 200 nm or less, preferably 10 nm or more and 50 nm or less. In this specification, the adhesion layer 6 provided between the substrate 1 and the lower electrode film 2 may also be referred to as the lower adhesion layer 6.

[0019] The piezoelectric film 3 is, for example, a film formed from an alkali niobate oxide containing potassium (K), sodium (Na), niobium (Nb), and oxygen (O). That is, the piezoelectric film 3 is a film mainly composed of an alkali niobate oxide containing K, Na, Nb, and O. The piezoelectric film 3 has the composition formula (K 1-x Na x)It can be formed using an alkali niobium oxide represented by NbO3, that is, potassium sodium niobate (KNN). The coefficient x [=Na / (K+Na)] in the above composition formula can be in the range of 0 < x < 1, preferably 0.4 ≤ x ≤ 0.8. The piezoelectric film 3 is a polycrystalline film of KNN (hereinafter also referred to as the KNN film 3). Also, the crystal structure of KNN is a perovskite structure. That is, the KNN film 3 has a perovskite structure. Also, it is preferable that more than half of the crystals constituting the KNN film 3 have a columnar structure. In this specification, the crystal system of KNN is regarded as a tetragonal system. The KNN film 3 can be formed by a sputtering method. The thickness of the KNN film 3 can be, for example, 0.5 μm or more and 5 μm or less, preferably 1 μm or more and 3 μm or less.

[0020] The crystals constituting the KNN film 3 are preferentially oriented in the (001) plane orientation with respect to the main surface of the substrate 1 (when the substrate 1 is, for example, a Si substrate 1a having a surface oxide film 1b or an insulating film or the like, it is the Si substrate 1a). That is, the main surface of the KNN film 3 (the surface that becomes the base of the upper electrode film 4) is mainly composed of the KNN (001) plane. For example, by directly forming the KNN film 3 on a Pt film (lower electrode film 2) whose main surface is mainly composed of the Pt (111) plane, a KNN film 3 whose main surface is mainly composed of the KNN (001) plane can be obtained. In this specification, that the crystals constituting the KNN film 3 are oriented in the (001) plane orientation means that the (001) plane of the crystals constituting the KNN film 3 is parallel or substantially parallel to the main surface of the substrate 1. Also, that the crystals constituting the KNN film 3 are preferentially oriented in the (001) plane orientation means that there are many crystals whose (001) plane is parallel or substantially parallel to the main surface of the substrate 1.

[0021] In addition, the alkali niobium oxide constituting the KNN film 3 may further contain at least one element (dopant) selected from the group consisting of lithium (Li), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), bismuth (Bi), antimony (Sb), vanadium (V), indium (In), tantalum (Ta), molybdenum (Mo), tungsten (W), chromium (Cr), Ti, zirconium (Zr), hafnium (Hf), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), copper (Cu), zinc (Zn), silver (Ag), manganese (Mn), iron (Fe), cobalt (Co), Ni, aluminum (Al), Si, germanium (Ge), tin (Sn), and gallium (Ga). The concentration of these elements in the alkali niobium oxide can be, for example, 5 at% or less (when a plurality of the above elements are contained, the total concentration is 5 at% or less).

[0022] The upper electrode film 4 is mainly composed of various metals such as Pt, Au, Al, Cu, or alloys thereof. The upper electrode film 4 can be formed by methods such as sputtering, vapor deposition, plating, and metal paste method. The upper electrode film 4 does not significantly affect the crystal structure of the KNN film 3 like the lower electrode film 2. Therefore, the material, crystal structure, and film formation method of the upper electrode film 4 are not particularly limited. Note that an adhesion layer 7 mainly composed of, for example, RuO2, IrO2, Ti, Ta, TiO2, Ni, etc. may be provided between the KNN film 3 and the upper electrode film 4 to enhance their adhesion. The thickness of the upper electrode film 4 is, for example, 50 nm or more and 5000 nm or less, preferably 50 nm or more and 300 nm or less. When the adhesion layer 7 is provided, the thickness of the adhesion layer 7 can be, for example, 1 nm or more and 200 nm or less, preferably 5 nm or more and 50 nm or less. In this specification, the adhesion layer 7 provided between the KNN film 3 and the upper electrode film 4 may also be referred to as the upper adhesion layer 7.

[0023] As described above, the device 100 including the semiconductor element 30 and the piezoelectric element 20 is obtained by processing the laminate 10. As shown in FIG. 1, the piezoelectric element 20 includes a lower electrode film 2, a KNN film 3, and an upper electrode film 4. Note that the substrate 1 may be considered to be included in the piezoelectric element 20. Also, as described above, the lower electrode film 2 is formed at a position different from the formation location of the semiconductor element 30 on the surface of the substrate 1 where the semiconductor element 30 is formed. As a result, the piezoelectric element 20 is formed at a position different from the formation position of the semiconductor element 30 on the surface of the substrate 1 where the semiconductor element 30 is formed.

[0024] Further, the piezoelectric element 20 further includes an insulating film 8 and metal wirings 9a, 9b.

[0025] The metal wiring 9a is provided so as to be connected to (in contact with) the lower electrode film 2 and not to be connected to (not in contact with) the upper electrode film 4. Also, the metal wiring 9b is provided so as to be connected to the upper electrode film 4 and not to be connected to the lower electrode film 2. The metal wirings 9a and 9b can each be formed using various metals such as Au, Al, Ti, Cr, etc., or alloys mainly composed of these various metals. The metal wirings 9a and 9b may be single-layer films or may be laminates in which a plurality of layers are laminated. The metal wirings 9a and 9b can be formed into films by methods such as sputtering, vapor deposition, plating, and the metal paste method.

[0026] The insulating film 8 is provided so as to insulate between the metal wiring 9b and the lower electrode film 2. The insulating film 8 is provided, for example, from the upper electrode film 4 to the substrate 1 so as to cover a part of the side surface of the KNN film 3. The insulating film 8 can be formed using oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), etc. The insulating film 8 may be a single-layer film or may be a laminate in which a plurality of layers are laminated. The insulating film 8 can be formed into a film by methods such as CVD and sputtering.

[0027] In the device 100, the piezoelectric element 20 and the semiconductor element 30 are electrically connected via the metal wirings 9a and 9b, and the piezoelectric element 20 is controlled by the semiconductor element 30.

[0028] For example, when the piezoelectric element 20 functions as an actuator, the (deformation) operation of the piezoelectric element 20 is controlled by the semiconductor element 30. Specifically, a voltage is applied between the lower electrode film 2 and the upper electrode film 4 by the semiconductor element 30, and the KNN film 3 included in the piezoelectric element 20 can be deformed. By the deformation operation of the piezoelectric element 20 (KNN film 3), various members connected to the device 100 can be operated. In this case, examples of the uses of the device 100 include a head for an inkjet printer, a MEMS mirror for a scanner, a vibrator for an ultrasonic generator, etc.

[0029] For example, when the piezoelectric element 20 functions as a sensor, the signal detected by the piezoelectric element 20 is processed by the semiconductor element 30. For example, when the KNN film 3 provided in the piezoelectric element 20 deforms in accordance with a change in some physical quantity, a voltage is generated between the lower electrode film 2 and the upper electrode film 4 due to the deformation. The piezoelectric element 20 detects this voltage as a signal, and by processing the signal detected by the piezoelectric element 20 with the semiconductor element 30, the magnitude of the physical quantity applied to the KNN film 3 can be measured. In this case, examples of the applications of the apparatus 100 include an angular velocity sensor, an ultrasonic sensor, a pressure sensor, an acceleration sensor, and the like.

[0030] For example, when the piezoelectric element 20 functions as a harvester, the semiconductor element 30 is operated by the electrical energy generated by the piezoelectric element 20.

[0031] Although details will be described later, in this embodiment, the KNN film 3 is formed under the conditions of low temperature, high oxygen partial pressure, and low ambient pressure in the manufacturing process of the apparatus 100 (the laminate 10). As a result, the laminate 10 and thus the apparatus 100 in this embodiment may have at least any one of the following features 1, 2, and 3. Hereinafter, various features that the laminate 10 and thus the apparatus 100 in this embodiment may have will be described.

[0032] (Feature 1) When the KNN film 3 is formed, an alkali metal (potassium atom, sodium atom) may diffuse to the substrate 1 through the lower electrode film 2 (and the lower adhesion layer 6). When the alkali metal diffuses to the substrate 1, the adhesion between the substrate 1 and the lower electrode film 2 (the lower adhesion layer 6 when it has the lower adhesion layer 6) may decrease. As a result, when an excessive external force is repeatedly applied to the periphery (member) of the lower electrode film 2 due to the KNN film 3 repeatedly deforming greatly during the driving of the apparatus 100 (the piezoelectric element 20), the lower electrode film 2 and thus the KNN film 3 may peel off from the substrate 1.

[0033] In response to such problems, in this embodiment, during the manufacturing process of the device 100, the KNN film 3 is formed at a low temperature. As a result, it has been successful in suppressing the diffusion of alkali metals into the substrate 1. Specifically, when the surface layer region of the substrate 1 in the device 100 of this embodiment is analyzed by Secondary Ion Mass Spectrometry (SIMS), the potassium concentration (K concentration) is 5E15 cm -3 or less, and the sodium concentration (Na concentration) is 5E15 cm -3 or less, having the feature (Feature 1).

[0034] Thus, by forming the KNN film 3 at a low temperature, it is possible to suppress the diffusion of alkali metals into the substrate 1, and obtaining a device 100 with low K concentration and Na concentration in the surface layer region of the substrate 1 is a new finding discovered for the first time as a result of the intensive studies by the inventors of the present invention.

[0035] Note that the "surface layer region of the substrate 1" in this embodiment refers to the region ranging from the interface between the piezoelectric element 20 and the substrate 1 (when the substrate 1 has the surface oxide film 1b, from the interface between the piezoelectric element 20 and the surface oxide film 1b) to a depth of 1 μm toward the back surface of the substrate 1. Note that the "back surface of the substrate 1" in this specification means the surface of the substrate 1 on the side opposite to the surface (the upper surface of the substrate 1) on which the semiconductor element 30 is formed.

[0036] When the K concentration and the Na concentration in the surface layer region of the substrate 1 are each 5E15 cm -3 or less, the adhesion between the substrate 1 and the lower electrode film 2 (or the lower adhesion layer 6) can be improved. As a result, even if an excessive external force is repeatedly applied to the periphery of the lower electrode film 2 during the driving of the device 100 (piezoelectric element 20), peeling of the lower electrode film 2 and thus the KNN film 3 from the substrate 1 can be avoided. As a result, it becomes possible to improve the reliability of the device 100 (piezoelectric element 20).

[0037] The lower the K concentration and the Na concentration in the surface layer region of the substrate 1, the more the adhesion between the substrate 1 and the lower electrode film 2 (or the lower adhesion layer 6) can be improved. The K concentration and the Na concentration in the surface layer region of the substrate 1 are each preferably 3E14 cm -3 or less, and this makes it possible to further improve the above adhesion. Also, the K concentration in the surface layer region of the substrate 1 is, for example, preferably 1E14 cm -3 or less, and this makes it possible to further improve the above adhesion.

[0038] The lower limit values of the K concentration and the Na concentration in the surface layer region of the substrate 1 are not particularly limited. Note that the detection limit of the K concentration by SIMS analysis at present is about 1E14 cm -3 or so, and the detection limit of the Na concentration is about 3E14 cm -3 or so.

[0039] (Feature 2) When the KNN film 3 is formed at a low temperature, although the diffusion of the alkali metal into the substrate 1 can be suppressed, the (001) orientation ratio of the KNN film 3 may decrease. As a result, the performance of the piezoelectric element 20 may decrease.

[0040] In response to such a problem, in this aspect, in the manufacturing process of the device 100, the KNN film 3 is formed under the conditions of low temperature, high oxygen partial pressure, and low ambient pressure. That is, not only is the film formation condition of the KNN film 3 set to a low temperature, but also the oxygen partial pressure is high and the ambient pressure is low. As a result, even when the film is formed at a low temperature, a KNN film 3 with a high (001) orientation ratio (high crystal orientation) has been successfully obtained. This is a new finding first discovered as a result of the inventors' intensive studies.

[0041] Specifically, the device 100 (the laminate 10) may have a feature (Feature 2) that the (001) orientation ratio of the KNN film 3 is, for example, 96% or more, preferably 98% or more.

[0042] When the (001) orientation ratio of the KNN film 3 is 96% or more, the piezoelectric element 20 can have high performance. When the (001) orientation ratio of the KNN film 3 is 98% or more, the piezoelectric element 20 can have even higher performance.

[0043] Note that the (001) orientation ratio of the KNN film 3 is the orientation ratio of the (001) plane orientation of the crystals constituting the KNN film 3. "The (001) orientation ratio of the KNN film 3 is 96% or more" means that, for example, 96% or more of the crystals constituting the KNN film 3 are oriented in the (001) plane orientation with respect to the main surface of the substrate 1. Note that the "orientation ratio" in this specification is a value calculated by the following formula (1) based on the peak intensity of the X-ray diffraction pattern (2θ / θ) obtained by performing XRD measurement on the KNN film 3.

[0044] Orientation ratio (%) = {(001) peak intensity / ((001) peak intensity + (110) peak intensity)} × 100 ··· (1)

[0045] The "(001) peak intensity" in the above formula (1) is the intensity of the diffraction peak caused by the crystals oriented in the (001) plane orientation among the crystals constituting the KNN film 3 (that is, the crystals whose (001) plane is parallel to the main surface of the substrate 1) in the X-ray diffraction pattern obtained by performing XRD measurement on the KNN film 3, and is the intensity of the peak that appears within the range of 2θ of 20° to 23°. When a plurality of peaks appear within the range of 2θ of 20° to 23°, it is the intensity of the highest peak. Also, the "(110) peak intensity" in the above formula (1) is the intensity of the diffraction peak caused by the crystals oriented in the (110) plane orientation among the crystals constituting the KNN film 3 (that is, the crystals whose (110) plane is parallel to the main surface of the substrate 1) in the X-ray diffraction pattern obtained by performing XRD measurement on the KNN film 3, and is the intensity of the peak that appears within the range of 2θ of 30° to 33°. Note that when a plurality of peaks appear within the range of 2θ of 30° to 33°, it is the intensity of the highest peak.

[0046] In addition, in order to exhibit this characteristic, the KNN film 3 needs to have a perovskite structure. If the KNN film 3 does not have a perovskite structure, in the X-ray diffraction pattern obtained by performing XRD measurement, peaks cannot be observed within at least the range of 2θ from 20° to 23°, and as a result, the (001) orientation ratio cannot be calculated.

[0047] (Characteristic 3) In this aspect, in the manufacturing process of the device 100, the KNN film 3 is formed under the conditions of low temperature, high oxygen partial pressure, and low ambient pressure. As a result, even when the film is formed at a low temperature, the KNN film 3 with a high (001) orientation ratio has been successfully obtained. As a result, it is also possible to obtain the KNN film 3 with a high piezoelectric constant.

[0048] Specifically, the device 100 (laminated body 10) has a characteristic (Characteristic 3) that the absolute value of the piezoelectric constant e of the KNN film 3 is, for example, 7 C / m 31 or more, preferably 10 C / m 2 or more. 2

[0049] When the absolute value of the piezoelectric constant e of the KNN film 3 is 7 C / m 31 or more, the piezoelectric element 20 can have higher performance. When the absolute value of the piezoelectric constant e of the KNN film 3 is 10 C / m 2 or more, the piezoelectric element 20 can have even higher performance. 31 2

[0050] (2) Manufacturing method of a piezoelectric laminated body and a device having a piezoelectric element The manufacturing methods of the above-described laminated body 10 and device 100 will be described.

[0051] (Preparation of substrate) ​​​First, as the substrate 1, a p-type Si substrate is prepared. On either one of the two main surfaces of the substrate 1, a semiconductor element 30 having, for example, a CMOS structure is pre-formed. Also, on the surface of the substrate 1 where the semiconductor element 30 is formed (the upper surface of the substrate 1), a surface oxide film 1b is formed except for the formation site of the semiconductor element 30. Note that various known techniques can be used to form the semiconductor element 30. Further, for the formation of the n-type regions (n-well 311, n-type source region 321, n-type drain region 322) and p-type regions (p-type source region 312, p-type drain region 313) of the semiconductor element 30, techniques such as a technique of thermally diffusing a dopant and a technique of activating ions by ion implantation and annealing can be used. The CMOS structure formed using these techniques is vulnerable to heat. For example, when the n-type region or p-type region is heated, the dopant may migrate and the dopant concentration may change.

[0052] (Film formation of the lower adhesion layer and the lower electrode film) On the upper surface (the surface oxide film 1b) of the substrate 1, a lower adhesion layer 6 (for example, a ZnO layer) and a lower electrode film 2 (for example, a Pt film) are formed in this order by, for example, a sputtering method. Note that a substrate 1 on which the lower adhesion layer 6 and the lower electrode film 2 are pre-formed may be prepared on the upper surface of the substrate 1.

[0053] As conditions for forming the ZnO layer as the lower adhesion layer 6, the following conditions are exemplified. The film formation time of the lower adhesion layer 6 is appropriately adjusted according to the target thickness of the lower adhesion layer 6. Target: ZnO sintered body Temperature (substrate temperature): 200 °C or higher and lower than 500 °C, preferably 300 °C or higher and 450 °C or lower, more preferably 400 °C or higher and 450 °C or lower Discharge power density: 2 W / cm 2 Up to 6 W / cm 2 Below, preferably 3 W / cm 2 Up to 5 W / cm 2 Below Atmosphere: Atmosphere of a mixed gas of argon (Ar) gas and oxygen (O2) gas (hereinafter, also referred to as "Ar / O2 mixed gas atmosphere") Ratio of partial pressure of Ar gas to O2 gas (Ar gas partial pressure / O2 gas partial pressure): 5 / 1 to 30 / 1, preferably 7 / 1 to 20 / 1, more preferably 10 / 1 to 15 / 1 Atmospheric pressure: 0.1 Pa or more and 0.5 Pa or less, preferably 0.2 Pa or more and 0.4 Pa or less Thickness: 1 nm or more and 200 nm or less, preferably 10 nm or more and 50 nm or less

[0054] The notation of a numerical range such as "5 / 1 to 30 / 1" in this specification means that the lower limit value and the upper limit value are included in the range. The same applies to other numerical ranges. Also, the "substrate temperature" in this specification means the surface temperature of the substrate during the film formation of each film (each layer).

[0055] In addition, the following conditions are exemplified as the conditions for forming a Ti layer or the like as the lower adhesion layer 6. Target: Ti plate or the like Temperature (substrate temperature): 100 °C or more and less than 500 °C, preferably 200 °C or more and 400 °C or less Atmosphere: Ar gas atmosphere Atmospheric pressure: 0.1 Pa or more and 0.5 Pa or less, preferably 0.2 Pa or more and 0.4 Pa or less Other conditions can be the same as the conditions for forming the ZnO layer.

[0056] The following conditions are exemplified as the conditions for forming the Pt film as the lower electrode film 2. The film formation time of the lower electrode film 2 is appropriately adjusted according to the target thickness of the lower electrode film 2. Target: Pt plate Temperature (substrate temperature): 200 °C or more and less than 500 °C, preferably 300 °C or more and 450 °C or less Discharge power density: 1 W / cm 2 To 5 W / cm 2 Or less, preferably 2 W / cm 2 Or more and 4 W / cm 2 Or less Atmosphere: Ar gas atmosphere Atmospheric pressure: 0.1 Pa or more and 0.5 Pa or less, preferably 0.2 Pa or more and 0.4 Pa or less Thickness: 100 nm or more and 400 nm or less

[0057] By forming the lower adhesion layer 6 and the lower electrode film 2 under the above conditions, particularly by forming the lower adhesion layer 6 and the lower electrode film 2 with the film formation temperature within the range of the above predetermined conditions, the thermal history of the semiconductor element 30 can be reduced. Thereby, shortening of the life and performance deterioration of the semiconductor element 30 can be suppressed.

[0058] (Film formation of KNN film) When the film formation of the lower adhesion layer 6 and the lower electrode film 2 is completed, subsequently, a KNN film 3 is formed on the lower electrode film 2 by a sputtering method such as an RF magnetron sputtering method. The composition of the KNN film 3 can be adjusted, for example, by controlling the composition of the target used during sputter film formation. The target can be produced by mixing powders such as K2CO3 powder, Na2CO3 powder, and Nb2O5 powder and firing them. The composition of the target can be controlled by adjusting the mixing ratio of powders such as K2CO3 powder, Na2CO3 powder, and Nb2O5 powder. When forming a KNN film 3 containing the above elements such as Cu and Mn, a target obtained by mixing Cu powder (or CuO powder), Mn powder (or MnO powder), etc. in a predetermined ratio may be used in addition to the above-mentioned respective powders.

[0059] In this embodiment, the film formation conditions of the KNN film 3 are set to be at a low temperature, the oxygen partial pressure is increased, and further, the atmospheric pressure is decreased. Specifically, the following conditions are exemplified as the conditions for forming the KNN film 3. The film formation time of the KNN film 3 is appropriately adjusted according to the target thickness of the KNN film 3. Temperature (substrate temperature): 400 °C or more and less than 500 °C, more preferably 400 °C or more and 450 °C or less Atmosphere: Ar / O2 mixed gas atmosphere Oxygen partial pressure in the atmosphere (O2 gas partial pressure): 0.0025 Pa or more and less than 0.01 Pa, preferably 0.003 Pa or more and less than 0.01 Pa Atmospheric pressure (chamber pressure): 0.03 Pa or more and less than 0.1 Pa, preferably 0.03 Pa or more and 0.08 Pa or less Discharge power density: 2.7 W / cm 2 Above 4.1 W / cm 2 Below, preferably above 2.8 W / cm 2 Above 3.8 W / cm 2 Below Film formation rate: 0.5 μm / hr or more and 4 μm / hr or less, preferably 0.5 μm / hr or more and 2 μm / hr or less Thickness: 0.5 μm or more and 5 μm or less, preferably 1 μm or more and 3 μm or less

[0060] By forming the KNN film 3 under the above conditions, in particular, by forming the KNN film 3 with the film formation temperature within the range of the above predetermined conditions, the thermal history of the semiconductor element 30 can be reduced. As a result, for example, the migration of dopants in the n-type region and p-type region of the semiconductor element 30 can be suppressed. As a result, shortening of the life and deterioration of the performance of the semiconductor element 30 can be suppressed. In addition, the manufacturing yield of the apparatus 100 can be increased.

[0061] Also, by forming the KNN film 3 under the above conditions, in particular, by forming the KNN film 3 with the film formation temperature within the range of the above predetermined conditions, it becomes possible to suppress the diffusion of alkali metals into the substrate 1. As a result, the K concentration and Na concentration in the surface layer region of the substrate 1 can each be made 5E15 cm -3 Below. That is, the laminate 10 having the above-described feature 1 and thus the apparatus 100 can be obtained.

[0062] Also, by forming the KNN film 3 under the above conditions, in particular, by forming the KNN film 3 with the film formation temperature, oxygen partial pressure, and atmospheric pressure within the range of the above predetermined conditions, it becomes possible to make the (001) orientation ratio of the KNN film 3 96% or more. That is, the laminate 10 having the above-described feature 2 and thus the apparatus 100 can be obtained.

[0063] Also, since it becomes possible to make the (001) orientation ratio of the KNN film 3 96% or more, the absolute value of the piezoelectric constant e of the KNN film 3 31 Is 7 C / m 2It is also possible to achieve the above. That is, by forming the KNN film 3 under the above-mentioned conditions, particularly by forming the KNN film 3 with the film formation temperature, oxygen partial pressure, and atmospheric pressure within the range of the above-mentioned predetermined conditions, the piezoelectric constant e 31 of the KNN film 3 can also be made 7 C / m 2 or more. As a result, it is also possible to obtain the laminate 10 and thus the device 100 having the above-mentioned feature 3.

[0064] When the film formation temperature of the KNN film 3 is 500°C or higher, the thermal history on the semiconductor element 30 cannot be reduced, and as a result, the shortening of the life and the deterioration of the performance of the semiconductor element 30 may not be suppressed. Further, when the film formation temperature of the KNN film 3 is 500°C or higher, the diffusion of the alkali metal into the substrate 1 may not be suppressed.

[0065] By making the film formation temperature of the KNN film 3 less than 500°C, the thermal history on the semiconductor element 30 can be reduced. Thereby, for example, the migration of dopants in the n-type region and p-type region of the semiconductor element 30 can be suppressed. As a result, the shortening of the life and the deterioration of the performance of the semiconductor element 30 can be suppressed. Further, the manufacturing yield of the device 100 can also be increased. Further, by making the film formation temperature of the KNN film 3 less than 500°C, the diffusion of the alkali metal can be suppressed, and the K concentration and Na concentration in the surface layer region of the substrate 1 can be reduced respectively. As a result, the K concentration and Na concentration in the surface layer region of the substrate 1 can be made 5E15 cm -3 or less.

[0066] Further, by making the film formation temperature of the KNN film 3, for example, 450°C or lower, the thermal history on the semiconductor element 30 can be further reduced. Further, the diffusion of the alkali metal can be surely suppressed, and the K concentration and Na concentration in the surface layer region of the substrate 1 can be further reduced respectively. For example, the K concentration and Na concentration in the surface layer region of the substrate 1 can be made 3E14 cm -3 or less, and further, the K concentration in the surface layer region of the substrate 1 can be made 1E14 cm -3 or less.

[0067] When the film formation temperature of the KNN film 3 is less than, for example, 400°C, the effect of suppressing the diffusion of alkali metals into the substrate 1 reaches its peak, while the (001) orientation ratio of the KNN film 3 may decrease. As a result, even if the oxygen partial pressure and the atmospheric pressure during the film formation of the KNN film 3 are within the range of predetermined conditions, the (001) orientation ratio of the KNN film 3 may not be able to reach 96% or more. For this reason, the absolute value of the piezoelectric constant e 31 may not be able to reach 7 C / m 2 or more. Due to these results, the performance of the piezoelectric element 20 may decrease.

[0068] When the film formation temperature of the KNN film 3 is, for example, 400°C or higher, while suppressing the diffusion of alkali metals into the substrate 1, the (001) orientation ratio of the KNN film 3 can be made 96% or more, or the absolute value of the piezoelectric constant e 31 can be made 7 C / m 2 or more. As a result, it becomes possible to obtain the laminate 10 in which the semiconductor element 30 and the high-performance piezoelectric element 20 are formed on the same substrate 1, and thus the device 100.

[0069] Also, when the oxygen partial pressure during the film formation of the KNN film 3 is less than 0.0025 Pa, the (001) orientation ratio of the KNN film 3 may not be able to be increased sufficiently. That is, when the film formation temperature of the KNN film 3 is 400°C or higher and less than 500°C and the oxygen partial pressure is less than 0.0025 Pa, the (001) orientation ratio of the KNN film 3 may not be able to reach 96% or more. For this reason, the absolute value of the piezoelectric constant e 31 may not be able to reach 7 C / m 2 or more. Due to these results, the performance of the piezoelectric element 20 may decrease.

[0070] By the oxygen partial pressure being 0.0025 Pa or more, the (001) orientation ratio of the KNN film 3 can be increased sufficiently. Even when the film formation temperature of the KNN film 3 is 400°C or higher and less than 500°C, the (001) orientation ratio of the KNN film 3 can be made 96% or more, or the absolute value of the piezoelectric constant e 31 can be made 7 C / m 2It becomes possible to achieve the above. As a result, it becomes possible to obtain a laminate 10 in which the semiconductor element 30 and the high-performance piezoelectric element 20 are formed on the same substrate 1, and thus the device 100. By having an oxygen partial pressure of 0.003 Pa or more, the (001) orientation ratio of the KNN film 3 can be further increased, and the (001) orientation ratio of the KNN film 3 can be made 98% or more, or the piezoelectric constant e of the KNN film 3 31 The absolute value of is 10 C / m 2 or more. As a result, it becomes possible to obtain a laminate 10 in which the semiconductor element 30 and an even higher-performance piezoelectric element 20 are formed on the same substrate 1, and thus the device 100.

[0071] When the oxygen partial pressure is 0.01 Pa or more, the sputtering energy required for the crystallization of the KNN film 3 is taken away by the ionization of oxygen, so the (001) orientation ratio of the KNN film 3 tends to decrease. Therefore, when the film formation temperature is 400 °C or more and less than 500 °C and the oxygen partial pressure is 0.01 Pa or more, the (001) orientation ratio of the KNN film 3 may not be able to reach 96% or more. For this reason, the absolute value of the piezoelectric constant e 31 May not be 7 C / m or more 2 or more. As a result, the performance of the piezoelectric element 20 may deteriorate.

[0072] By having an oxygen partial pressure of less than 0.01 Pa, a decrease in the (001) orientation ratio of the KNN film 3 can be suppressed. Even when the film formation temperature of the KNN film 3 is 400 °C or more and less than 500 °C, the (001) orientation ratio of the KNN film 3 can be made 96% or more, or the piezoelectric constant e of the KNN film 3 31 The absolute value of is 7 C / m 2 or more. As a result, it becomes possible to obtain a laminate 10 in which the semiconductor element 30 and the high-performance piezoelectric element 20 are formed on the same substrate 1, and thus the device 100.

[0073] In addition, when the atmospheric pressure during the formation of the KNN film 3 is 0.1 Pa or higher, the (001) orientation ratio of the KNN film 3 may not be sufficiently increased. Therefore, when the film formation temperature of the KNN film 3 is 400 °C or higher and less than 500 °C and the atmospheric pressure is 0.1 Pa or higher, the (001) orientation ratio of the KNN film 3 may not reach 96% or higher. For this reason, the absolute value of the piezoelectric constant e 31 may not be able to reach 7 C / m 2 or higher. As a result, the performance of the piezoelectric element 20 may be degraded.

[0074] When the atmospheric pressure is less than 0.1 Pa, the (001) orientation ratio of the KNN film 3 can be sufficiently increased. Even when the film formation temperature of the KNN film 3 is 400 °C or higher and less than 500 °C, the (001) orientation ratio of the KNN film 3 can be made 96% or higher, or the absolute value of the piezoelectric constant e 31 of the KNN film 3 can be made 7 C / m 2 or higher. As a result, it becomes possible to obtain the laminate 10 in which the semiconductor element 30 and the high-performance piezoelectric element 20 are formed on the same substrate 1, and thus the device 100. Further, when the atmospheric pressure is 0.08 Pa or less, the (001) orientation ratio of the KNN film 3 can be further increased, and the (001) orientation ratio of the KNN film 3 can be made 98% or higher, or the absolute value of the piezoelectric constant e 31 of the KNN film 3 can be made 10 C / m 2 or higher. As a result, it becomes possible to obtain the laminate 10 in which the semiconductor element 30 and the even higher-performance piezoelectric element 20 are formed on the same substrate 1, and thus the device 100.

[0075] In addition, when the atmospheric pressure is less than 0.03 Pa, the (001) orientation ratio of the KNN film 3 may not be sufficiently increased. Therefore, when the film formation temperature of the KNN film 3 is 400 °C or higher and less than 500 °C and the atmospheric pressure is less than 0.03 Pa, the (001) orientation ratio of the KNN film 3 may not reach 96% or higher. For this reason, the absolute value of the piezoelectric constant e 31 may not be able to reach 7 C / m 2 or higher. As a result, the performance of the piezoelectric element 20 may be degraded.

[0076] When the atmospheric pressure is 0.03 Pa or more, the (001) orientation ratio of the KNN film 3 can be sufficiently increased. Even when the film formation temperature of the KNN film 3 is 400 °C or more and less than 500 °C, the (001) orientation ratio of the KNN film 3 can be made 96% or more, or the absolute value of the piezoelectric constant e 31 of the KNN film 3 can be made 7 C / m 2 or more. As a result, it becomes possible to obtain a laminate 10 in which the semiconductor element 30 and the high-performance piezoelectric element 20 are formed on the same substrate 1, and thus the device 100.

[0077] As described above, only by forming the KNN film 3 with all of the film formation temperature, oxygen partial pressure, and atmospheric pressure within the range of the above-described predetermined conditions, it is possible to obtain the device 100 (laminate 10) in which the semiconductor element 30 and the piezoelectric element 20 are formed on the same substrate 1 while reducing the thermal history of the semiconductor element 30. Further, while reducing the thermal history of the semiconductor element 30, it is possible to obtain the device 100 (laminate 10) having at least any one of the above-described features 1, 2, and 3, preferably all of the above-described features 1, 2, and 3. That is, it becomes possible to obtain the laminate 10 and thus the device 100 in which the semiconductor element 30 and the high-performance piezoelectric element 20 are formed on the same substrate 1. If at least any one of the conditions of the film formation temperature, oxygen partial pressure, and atmospheric pressure is outside the range of the above conditions, it may not be possible to suppress the shortening of the life and performance deterioration of the semiconductor element 30, or the performance of the piezoelectric element 20 may deteriorate. As a result, the laminate 10 and thus the device 100 in which the semiconductor element 30 and the piezoelectric element 20 are formed on the same substrate 1 may not be obtained.

[0078] (Film formation of upper adhesion layer and upper electrode film) After the film formation of the KNN film 3 is completed, an upper adhesion layer 7 (for example, RuO2 layer) and an upper electrode film 4 (for example, Pt film) are formed in this order on the KNN film 3, for example, by sputtering.

[0079] As conditions for forming a RuO₂ layer or the like as the upper contact layer 7, the following conditions are exemplified. The film formation time of the upper contact layer 7 is appropriately adjusted according to the target thickness of the upper contact layer 7. Target: Ru plate or the like Temperature (substrate temperature): Room temperature (25 °C) or higher and lower than 500 °C, preferably room temperature (25 °C) or higher and lower than 450 °C Discharge power density: 0.3 W / cm 2 Up to 2 W / cm 2 Preferably 0.5 W / cm or more 2 Up to 1 W / cm 2 Or less Atmosphere: Ar / O₂ mixed gas atmosphere Ratio of partial pressure of Ar gas to O₂ gas (Ar gas partial pressure / O₂ gas partial pressure): 3 / 5 to 1 / 1, preferably 3 / 4 to 1 / 1 Atmospheric pressure: 0.1 Pa or more and 1.0 Pa or less, preferably 0.2 Pa or more and 0.7 Pa or less Thickness: 1 nm or more and 200 nm or less, preferably 5 nm or more and 50 nm or less

[0080] As conditions for forming a Pt film or the like as the upper electrode film 4, the following conditions are exemplified. The film formation time of the upper electrode film 4 is appropriately adjusted according to the target thickness of the upper electrode film 4. Target: Pt plate or the like Temperature (substrate temperature): Room temperature (25 °C) or higher and lower than 500 °C, preferably room temperature (25 °C) or higher and lower than 450 °C Discharge power density: 1 W / cm 2 Up to 5 W / cm 2 Preferably 2 W / cm or more 2 Up to 4 W / cm 2 Or less Atmosphere: Ar gas atmosphere Atmospheric pressure: 0.1 Pa or more and 0.5 Pa or less, preferably 0.2 Pa or more and 0.4 Pa or less Thickness: 50 nm or more and 5000 nm or less, preferably 50 nm or more and 300 nm or less

[0081] By forming the upper adhesion layer 7 and the upper electrode film 4 under the above conditions, particularly by forming the upper adhesion layer 7 and the upper electrode film 4 with the film formation temperature within the range of the above-mentioned predetermined conditions, it is possible to more reliably suppress the diffusion of alkali metals into the substrate 1 while reducing the thermal history of the semiconductor element 30. As a result, while reducing the thermal history of the semiconductor element 30, it is possible to more reliably obtain the device 100 (laminated body 10) having at least any one of the above-mentioned features 1, 2, and 3, preferably all of the above-mentioned features 1, 2, and 3.

[0082] As described above, by sequentially forming the lower adhesion layer 6, the lower electrode film 2, the KNN film 3, the upper adhesion layer 7, and the upper electrode film 4, a laminated body 10 as shown in FIG. 2 is obtained.

[0083] (Formation of piezoelectric element) After producing a laminated body 10 as shown in FIG. 2, the laminated body 10 is processed to form a piezoelectric element 20 on the substrate 1.

[0084] Specifically, first, for example, dry etching using Ar gas or a reactive gas is used to perform pattern processing on the upper electrode film 4 (including the upper adhesion layer 7) and the KNN film 3 individually. In the pattern processing, the upper electrode film 4 (including the upper adhesion layer 7) and the KNN film 3 are each formed into a predetermined shape, and a part of the lower electrode film 2 is exposed. Also, in the pattern processing, a photoresist can be used as an etching mask.

[0085] After the pattern processing of the upper electrode film 4 (including the upper adhesion layer 7) and the KNN film 3 is completed, for example, dry etching using Ar gas or a reactive gas is used to perform pattern processing on the lower electrode film 2 and the lower adhesion layer 6 respectively, and the lower electrode film 2 and the lower adhesion layer 6 are each formed into a predetermined shape. In this pattern processing, a photoresist can be used as an etching mask.

[0086] When the patterning of the lower electrode film 2 and the lower adhesion layer 6 is completed, the insulating film 8 and the metal wirings 9a and 9b are provided. Specifically, first, a layer made of an insulating material (i.e., the insulating film 8) is provided from the upper electrode film 4 to the substrate 1 so as to cover the side surface of the KNN film 3 by a method such as CVD method or sputtering method. Then, dry etching using a reactive gas such as Ar gas or CF4 gas, or wet etching is performed on the insulating film 8 to pattern the insulating film 8 into a predetermined shape.

[0087] After providing the insulating film 8, a layer made of a material containing metal (metal wiring layer) is provided by a method such as sputtering method, vapor deposition method, plating method, or metal paste method. Then, dry etching using Ar gas or a reactive gas, or wet etching is performed on the metal wiring layer to pattern the metal wiring layer and form the metal wirings 9a and 9b. The metal wiring 9a is formed (patterned) so as to be connected to the lower electrode film 2 and not to be connected to the upper electrode film 4, and the metal wiring 9b is formed so as to be connected to the upper electrode film 4 and not to be connected to the lower electrode film 2.

[0088] Note that the etching conditions in the patterning during the formation of the insulating film 8 and the metal wirings 9a and 9b, and the etching conditions of the substrate 1 when the piezoelectric laminate 10 is processed into the piezoelectric element 20 can be general etching conditions used in the semiconductor device manufacturing process as long as the insulation property of the KNN film 3 is not deteriorated.

[0089] Also, a part of the substrate 1 is removed from the back side of the substrate 1 by Deep - RIE or wet etching. Thereby, the piezoelectric element 20 is formed on the substrate 1. As a result, the device 100 in which the piezoelectric element 20 and the semiconductor element 30 as shown in FIG. 1 are formed on the same substrate 1 is obtained.

[0090] (3) Effects According to this aspect, one or more of the following effects can be obtained.

[0091] (a) In this aspect, in the manufacturing process of the device 100, the KNN film 3 is formed under the temperature condition of 400 °C or higher and less than 500 °C. Thereby, while reducing the thermal history on the semiconductor element 30, the device 100 in which the semiconductor element 30 and the piezoelectric element 20 are formed on the same substrate 1 can be obtained. Further, by reducing the thermal history on the semiconductor element 30, shortening of the life and deterioration of the performance of the semiconductor element 30 can be suppressed. Also, the manufacturing yield of the device 100 can be increased.

[0092] (b) Further, by forming the KNN film 3 under the temperature condition of 400 °C or higher and less than 500 °C, the laminate 10 and thus the device 100 can have the feature (Feature 1) that "the K concentration in the surface layer region of the substrate 1 is 5E15 cm -3 or less, and the Na concentration is 5E15 cm -3 or less". By the device 100 (laminate 10) having the above Feature 1, it becomes possible to improve the adhesion between the substrate 1 and the lower electrode film 2 (lower adhesion layer 6). Thereby, when the device 100 (piezoelectric element 20) is driven, even if an excessive external force is repeatedly applied to the periphery (member) of the lower electrode film 2 due to the KNN film 3 being repeatedly deformed greatly, peeling of the lower electrode film 2 and thus the KNN film 3 from the substrate 1 can be avoided. As a result, the reliability of the device 100 can be improved.

[0093] (c) Further, in this aspect, in the manufacturing process of the device 100, the KNN film 3 is formed under the conditions that the film formation temperature is 400 °C or higher and less than 500 °C, the oxygen partial pressure is 0.0025 Pa or higher and less than 0.01 Pa, and the atmospheric pressure is 0.03 Pa or higher and less than 0.1 Pa. Thereby, while forming the KNN film 3 at a low temperature of 400 °C or higher and less than 500 °C, the (001) orientation ratio of the KNN film 3 formed on the substrate 1 on which the semiconductor element 30 is formed can be made 96% or higher, or the absolute value of the piezoelectric constant e 31 can be made 7 C / m 2 or higher. That is, the laminate 10 and thus the device 100 can have the feature (Feature 2) that "the (001) orientation ratio of the KNN film 3 is 96% or higher". As a result, the laminate 10 and thus the device 100 have "the piezoelectric constant e of the KNN film 3 31The absolute value of which is 7 C / m 2 It is also possible to have the feature (feature 3) that "it is 7 C / m or more". By the device 100 (the laminate 10) having at least one of the above-mentioned feature 2 and feature 3, the piezoelectric element 20 can have high performance. Thus, in this aspect, while reducing the thermal history with respect to the semiconductor element 30 (while suppressing the performance degradation of the semiconductor element 30), it is possible to form a high-performance piezoelectric element 20 on the substrate 1 on which the semiconductor element 30 is formed.

[0094] (d) By forming the KNN film 3 with all of the film formation temperature, the oxygen partial pressure, and the atmospheric pressure within the range of the above-mentioned predetermined conditions, it is possible to obtain the laminate 10 and thus the device 100 having all of the above-mentioned features 1 to 3 while reducing the thermal history with respect to the semiconductor element 30.

[0095] It has also been proposed to fabricate a piezoelectric laminate using a bonding (joining) method. That is, a method has been proposed in which a first electrode film, a KNN film, and a second electrode film are formed on a first substrate in this order, and a second substrate on which a semiconductor element 30 is pre-formed is bonded to the upper surface of the second electrode film, and then the first substrate is removed to fabricate a piezoelectric laminate. In a piezoelectric laminate fabricated using a bonding method, the thermal history with respect to the semiconductor element 30 is small, and it is considered that the alkali metal has not diffused into the second substrate. In addition, in a piezoelectric laminate fabricated using this method, the second electrode film functions as a lower electrode film, and the first electrode film functions as an upper electrode film. However, a piezoelectric laminate fabricated using such a bonding method has a problem that the adhesion between the substrate (second substrate) and the lower electrode film (second electrode film) is very low. Further, in the method using bonding, since the number of manufacturing steps of the piezoelectric laminate increases, there are also concerns such as complication of the manufacturing process, reduction in productivity, and cost increase. On the other hand, in this aspect, a laminate 10 in which the semiconductor element 30 and the piezoelectric element 20 are formed on the same substrate 1 is fabricated without using a bonding method. Further, in the manufacturing process thereof, while reducing the thermal history with respect to the semiconductor element 30, the diffusion of the alkali metal into the substrate 1 is suppressed. As a result, while reducing the thermal history with respect to the semiconductor element 30, the adhesion between the substrate 1 and the lower electrode film 2 (lower adhesion layer 6) has been successfully improved. In addition, since the laminate 10 is fabricated without using a bonding method, the laminate 10 (and thus the piezoelectric element 20) according to this aspect has no trace derived from bonding. That is, in the laminate 10 (and thus the piezoelectric element 20) according to this aspect, there is no trace derived from bonding at the interface between the substrate 1 and the KNN film 3, the interface between the substrate 1 and the lower electrode film 2 (lower adhesion layer 6 if there is a lower adhesion layer 6), or the interface between the lower electrode film 2 and the KNN film 3. Here, examples of the "trace derived from bonding" include the presence (distribution) of an inclusion (e.g., an adhesive) used for bonding and the presence (distribution) of impurities not derived from the film formation process (e.g., impurities derived from the adhesive).

[0096] (4) Modification Example This aspect can be modified as follows. In the description of the following modification examples, the same components as those in the above aspect are denoted by the same reference numerals, and the description thereof is omitted. Further, the above aspect and the following modification examples can be arbitrarily combined.

[0097] (Modification Example 1) In the above aspect, an example in which the piezoelectric element 20 is formed at a position different from the formation position of the semiconductor element 30 on the upper surface of the substrate 1 has been described, but the present invention is not limited thereto. For example, as shown in FIG. 3, the piezoelectric element 20 may be formed on the semiconductor element 30. In this case, the “surface layer region of the substrate 1” is a region extending from the interface between the piezoelectric element 20 and the semiconductor element 30 (when the protective film 33 is provided, the protective film 33) to a depth of 1 μm toward the back surface of the substrate 1. Further, for example, the piezoelectric element 20 may be formed on the upper surface of the substrate 1 such that a part of the piezoelectric element 20 is located on the semiconductor element 30. In this case, the “surface layer region of the substrate 1” is a region extending from the interface between the piezoelectric element 20 and the semiconductor element 30 (protective film 31) or the substrate 1 to a depth of 1 μm toward the back surface of the substrate 1.

[0098] Also in this modification example, in the manufacturing process of the device 100, by forming the KNN film 3 with all of the film formation temperature, oxygen partial pressure, and atmospheric pressure within the range of the above-described predetermined conditions, the thermal history with respect to the semiconductor element 30 can be reduced. As a result, also in this modification example, the laminate 10 in which the semiconductor element 30 and the piezoelectric element 20 are formed on the same substrate 1 and thus the device 100 can be obtained. Further, also in this modification example, the laminate 10 and thus the device 100 may have at least any one of the above-described features 1, 2, and 3. Thus, the same effects as those of the above aspect can be obtained also in this modification example.

[0099] (Modification Example 2) In the above aspect, the case where the substrate 1 is a p-type single crystal Si substrate 1a, that is, the case where the substrate 1 is a p-type semiconductor substrate, has been described as an example. However, the present invention is not limited to this. The substrate 1 may be an n-type semiconductor substrate. In this case, the p-type MOSFET 31 does not include an n-well 311, and the p-type source region 312 and the p-type drain region 313 are provided on the upper surface of the substrate 1 so as to be separated from each other. Further, the n-type source region 321 and the n-type drain region 322 of the n-type MOSFET 32 are provided in a p-well formed on the upper surface of the substrate 1 so as to be separated from each other. Also in this modified example, in the manufacturing process of the device 100, by forming the KNN film 3 with all of the film formation temperature, oxygen partial pressure, and atmospheric pressure within the range of the above-described predetermined conditions, the thermal history of the semiconductor element 30 can be reduced. As a result, also in this modified example, the laminate 10 in which the semiconductor element 30 and the piezoelectric element 20 are formed on the same substrate 1 and thus the device 100 can be obtained. Also in this modified example, the laminate 10 and thus the device 100 may have at least any one of the above-described features 1, 2, and 3. Thus, the same effects as those of the above aspect can be obtained also in this modified example.

[0100] (Modified Example 3) In the above aspect and modified examples, an example in which the semiconductor element 30 has a CMOS structure has been described. However, the semiconductor element 30 is not limited to CMOS as long as it has an element structure that is vulnerable to heat. Elements formed by using techniques such as thermal diffusion or ion implantation of dopants for the formation of n-type regions or p-type regions are vulnerable to heat. Therefore, when the semiconductor element 30 is formed by using these techniques, that is, when the semiconductor element 30 has either a region in which a p-type or n-type dopant is thermally diffused or a region in which the dopant is ion implanted, this aspect can be preferably applied, and the same effects as those of the above aspect and modified examples can be obtained.

[0101] (Modified Example 4) In the above aspect and modified examples, an example in which the substrate on which the semiconductor element 30 is formed is used as the substrate 1 has been described. However, the present invention is not limited to this.

[0102] As described above, since the KNN film 3 is formed at a low temperature of 400°C or higher and less than 500°C, it is also possible to use other substrates that require less thermal history as the substrate 1. For example, it is also possible to use a substrate on which a CMUT (Capacitive Micro-machined Ultrasound Transducer) structure is formed as the substrate 1. Further, as the substrate 1, it is also possible to use either a resin substrate or a glass substrate that is vulnerable to heat. Even when such a substrate is used as the substrate 1, in the manufacturing process of the device 100, by forming the KNN film 3 with all of the film formation temperature, oxygen partial pressure, and atmospheric pressure within the range of the above-described predetermined conditions, a high-performance piezoelectric element 20 can be formed on the substrate 1 that requires less thermal history or the substrate 1 that is vulnerable to heat. Also, in this modified example, the laminate 10 and thus the device 100 may have at least any one of the above-described features 1, 2, and 3.

[0103] Further, as the substrate 1, an SOI (Silicon On Insulator) substrate or a quartz glass (SiO2) substrate can also be used. Even in this case, the laminate 10 and thus the device 100 may have at least any one of the above-described features 1, 2, and 3.

[0104] (Modified Example 5) In the above-described embodiments and modified examples, the example of providing the lower adhesion layer 6 and the lower electrode film 2 has been described, but the present invention is not limited thereto. The lower adhesion layer 6 and the lower electrode film 2 may not be provided. That is, the KNN film 3 may be directly formed on the substrate 1. In this modified example, the piezoelectric element 20 is configured to include at least the KNN film 3 and the upper electrode film 4 (including the upper adhesion layer 7). Also, in this modified example, since the KNN film 3 is formed at a low temperature of 400°C or higher and less than 500°C, as the substrate 1, the substrates described in any one of the above-described modified examples 1 to 4 can be used.

[0105] Also in this modification example, in the manufacturing process of the device 100, by forming the KNN film 3 with all of the film formation temperature, oxygen partial pressure, and atmospheric pressure within the range of the predetermined conditions described above, the semiconductor element 30 and the piezoelectric element 20 can be formed on the same substrate 1. Further, also in this modification example, the laminate 10, and thus the device 100, may have at least any one of the above-described feature 1, feature 2, and feature 3. Thus, also in this modification example, the same effects as those of the above-described aspect can be obtained.

[0106] <Other aspect> As described above, the aspects and modification examples of the present disclosure have been specifically described. However, the present disclosure is not limited to the above-described aspects and modification examples, and various changes can be made without departing from the gist thereof.

[0107] Further, in the above-described embodiment, the case where the lower adhesion layer 6 is provided between the substrate 1 and the lower electrode film 2 and the upper adhesion layer 7 is provided between the KNN film 3 and the upper electrode film 4 has been described, but the present disclosure is not limited thereto. If the necessary adhesion can be ensured, the lower adhesion layer 6 and the upper adhesion layer 7 may not be provided.

[0108] <Preferred aspect of the present disclosure> Hereinafter, preferred aspects of the present disclosure will be appended.

[0109] (Appendix 1) According to one aspect of the present disclosure, a semiconductor element, a piezoelectric element having a piezoelectric film composed of an alkali niobate oxide containing potassium, sodium, niobium, and oxygen, and the semiconductor element and the piezoelectric element are formed on the same substrate, a device is provided.

[0110] (Appendix 2) Preferably, when performing SIMS analysis on a region ranging from the interface between the piezoelectric element and the semiconductor element or the substrate to a depth of 1 μm toward the surface opposite to the surface of the substrate on which the piezoelectric element is formed, the concentration of potassium is 5E15 cm-3 is as follows, and the sodium concentration is 5E15 cm -3 or less.

[0111] (Appendix 3) Preferably, the orientation rate of the crystal constituting the piezoelectric film in the (001) plane direction is 96% or more.

[0112] (Appendix 4) Preferably, the piezoelectric constant e of the piezoelectric film 31 is 7 C / m 2 or more.

[0113] (Appendix 5) Preferably, the semiconductor element has a CMOS structure.

[0114] (Appendix 6) Preferably, the piezoelectric element is controlled by the semiconductor element.

[0115] (Appendix 7) Preferably, the piezoelectric element functions as an actuator, and the operation of the piezoelectric element is controlled by the semiconductor element.

[0116] (Appendix 8) Preferably, the piezoelectric element functions as a sensor, and the signal detected by the piezoelectric element is processed by the semiconductor element.

[0117] (Appendix 9) Preferably, the piezoelectric element functions as a sensor, and the operation of the piezoelectric element is controlled by the semiconductor element.

[0118] (Appendix 10) Preferably, the piezoelectric element functions as an energy harvester, and the semiconductor element is operated by the electrical energy generated by the piezoelectric element.

[0119] (Appendix 11) Preferably, the semiconductor element has either a region where a p-type or n-type dopant is thermally diffused or a region where the dopant is ion-implanted.

[0120] (Appendix 12) According to another aspect of the present disclosure, a semiconductor element, and a piezoelectric element having a piezoelectric film composed of an alkali niobate oxide containing potassium, sodium, niobium, and oxygen, are provided, wherein the semiconductor element and the piezoelectric element are formed on the same substrate. A laminated substrate is provided.

[0121] (Appendix 13) The device according to any one of Appendices 1 to 11, or the laminated substrate according to Appendix 12, preferably, there are no traces resulting from bonding at the interface between the substrate and the piezoelectric film, the interface between the substrate and the lower electrode film (including the lower adhesion layer if present), or the interface between the lower electrode film and the piezoelectric film. Note that the traces resulting from bonding mean the distribution of inclusions used for bonding and impurities not derived from the film formation process, etc.

[0122] (Appendix 14) According to still another aspect of the present disclosure, a step of preparing a substrate on which a semiconductor element is formed, and a step of forming a piezoelectric element on the substrate, are provided, wherein the step of forming the piezoelectric element includes a step of forming a piezoelectric film composed of an alkali niobate oxide containing potassium, sodium, niobium, and oxygen on the substrate under conditions where the film formation temperature is less than 500°C, the oxygen partial pressure is 0.0025 Pa or more and less than 0.01 Pa, and the atmospheric pressure is 0.03 Pa or more and less than 0.1 Pa. A method for manufacturing a device is provided.

Description of Reference Numerals

[0123] 1 Substrate 2 Lower electrode film 3 Piezoelectric film (KNN film) 4 Upper electrode film 6 Lower adhesion layer 7 Upper adhesion layer 8 Insulating film 9a, 9b Metal wiring 10 Laminate 20 Piezoelectric element 30 Semiconductor element 100 Device (having a piezoelectric film)

Claims

1. A semiconductor device, and a piezoelectric element having a piezoelectric film composed of an alkali niobate oxide containing potassium, sodium, niobium, and oxygen, wherein the semiconductor device and the piezoelectric element are formed on the same substrate. An apparatus.

2. When performing SIMS analysis on a region ranging from the interface between the piezoelectric element and the semiconductor element or the substrate to a depth of 1 μm toward the surface opposite to the surface of the substrate on which the piezoelectric element is formed, the potassium concentration is 5E15 cm －３ or less, and the sodium concentration is 5E15 cm －３ or less. The apparatus according to claim 1.

3. The apparatus according to claim 1 or 2, wherein the orientation rate of the crystal constituting the piezoelectric film in the (001) plane direction is 96% or more.

4. The piezoelectric constant e of the piezoelectric film ３１ is 7 C / m ２ or more. The device according to claim 1 or 2

5. The apparatus according to claim 1 or 2, wherein the semiconductor device has a CMOS structure.

6. The apparatus according to claim 1 or 2, wherein the piezoelectric element is controlled by the semiconductor device.

7. The piezoelectric element functions as an actuator, and the operation of the piezoelectric element is controlled by the semiconductor device. The apparatus according to claim 1 or 2.

8. The piezoelectric element functions as a sensor, and a signal detected by the piezoelectric element is processed by the semiconductor device. The apparatus according to claim 1 or 2.

9. The piezoelectric element functions as a sensor, and the operation of the piezoelectric element is controlled by the semiconductor device. The apparatus according to claim 1 or 2.

10. The piezoelectric element functions as an energy harvester, and the semiconductor device is operated by the electrical energy generated by the piezoelectric element. The apparatus according to claim 1 or 2.

11. The apparatus according to claim 1 or 2, wherein the semiconductor device has either a region where a p-type or n-type dopant is thermally diffused or a region where the dopant is ion-implanted.

12. A semiconductor device, and a piezoelectric element having a piezoelectric film composed of an alkali niobate oxide containing potassium, sodium, niobium, and oxygen, wherein the semiconductor device and the piezoelectric element are formed on the same substrate. A laminated substrate.

13. A step of preparing a substrate on which a semiconductor device is formed, and a step of forming a piezoelectric element on the substrate, wherein the step of forming the piezoelectric element includes a step of forming a piezoelectric film composed of an alkali niobate oxide containing potassium, sodium, niobium, and oxygen on the substrate under conditions that the film formation temperature is 400 °C or higher and lower than 500 °C, the oxygen partial pressure is 0.0025 Pa or higher and lower than 0.01 Pa, and the atmospheric pressure is 0.03 Pa or higher and lower than 0.1 Pa. A method for manufacturing an apparatus.

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