Method for manufacturing a semiconductor device having a germanium region disposed in a semiconductor substrate

Abstract

PURPOSE: To provide a semiconductor device having a germanium region disposed in a semiconductor substrate.SOLUTION: A single-photon avalanche detector (SPAD) device includes a silicon substrate including a recess in an upper surface thereof. A p-type region is arranged in the silicon substrate below a lower surface of the recess. An n-type avalanche region is arranged in the silicon substrate below the p-type region and meets the p-type region at a p-n junction. A germanium region is disposed within the recess over the p-n junction.SELECTED DRAWING: Figure 1

Description

Background Art

[0001] A single-photon avalanche diode (SPAD) is a solid-state photodetector of the same family as a photodiode and an avalanche photodiode (APD). Similar to photodiodes and APDs, SPADs are based on a semiconductor p-n junction that can be illuminated with ultraviolet (UV) through visible wavelengths to infrared (IR) along a wide portion of the electromagnetic spectrum, as well as ionizing radiation such as gamma, X-rays, beta, and / or alpha. During operation, photo-generated carriers are accelerated by the device's electric field to a kinetic energy sufficient to overcome the ionization energy of the bulk material, knocking electrons out of the atoms of the bulk material. The large avalanche of current carriers increases exponentially and can be triggered from just a single photon-initiated carrier. SPADs can detect a single photon that provides a countable short-duration trigger pulse. However, because of the high speed at which the avalanche occurs, they can also be used to obtain the arrival time of incident photons.

Summary of the Invention

Problems to be Solved by the Invention

[0002] A Germanium single-photon avalanche diode (Ge-SPAD) is a type of SPAD for operating in the eye-safe short-wave infrared (SWIR) region, but germanium itself, especially at room temperature or higher, At a temperature, it has high dark count rate (DCR) material characteristics. **Means for Solving the Problem**

[0003] In some embodiments, the present invention provides a single photon avalanche detector (SPAD) device including a silicon substrate, a p-type region, an n-type avalanche region, and a germanium region. The silicon substrate includes a recess in an upper surface of the silicon substrate. The p-type region is disposed in the silicon substrate under a lower surface of the recess. The n-type avalanche region is disposed in the silicon substrate under the p-type region and contacts the p-type region at a p-n junction. The ger manium region is disposed in the recess above the p-n junction. manium region is disposed in the recess above the p-n junction. The germanium region is disposed in the recess above the p-n junction.

[0004] In some embodiments, the present invention also provides a semiconductor structure including a semiconductor substrate, a silicon-based multiplication region, a ger manium-based absorption region, and an electron channel. The silicon-based multiplication region is provided in the semiconductor substrate. The germanium-based absorption region is provided in the semiconductor substrate and the germanium-based absorption region is installed above the silicon-based multiplication region. The electron ch annel is between the silicon-based multiplication region and the germanium-based absorption region. The electron channel is between the silicon-based multiplication region and the germanium-based absorption region.

[0005] In some embodiments, the present invention further provides a method. Receive a semiconductor substrate. Perform ion implantation to form a lateral connection region under an upper surface of the semiconductor substrate. Perform another ion implantation to form a vertical connection region, where the vertical connection region and the lateral connection region contact each other to form a guard ring. Form a recess in the upper surface of the semiconductor substrate, where the recess is laterally surrounded by the guard ring and the recessed upper surface of the semiconductor substrate and the semiconductor substrate's recessed upper surface and the semiconductor substrate's It is defined by an inner sidewall. A germanium region is formed in the recess.

Advantages of the Invention

[0006] Various embodiments of the present invention use a separate absorption and multiplication (SAM) structure embedded for commercial value use.

Brief Description of the Drawings

[0007] The accompanying drawings are included to further understand the principles of the present invention, incorporated herein and constituting a part thereof. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0008]

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[0009] The following disclosure provides a number of different embodiments or methods for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and configurations are provided below. These are of course merely examples and are not intended to be limiting. For example, The formation on a first feature or on a second feature in the description means that the first and second features Also included are embodiments in which the first and second features are formed in direct contact, and embodiments in which the first and second features are not in direct contact. In addition, embodiments may also include those in which an additional feature is formed between the first feature and the second feature. Additionally, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition is for the purposes of simplicity and clarity and, as such, It is not intended to dictate any relationship between different embodiments and / or configurations.

[0010] FIG. 1 is a diagram of a single-photon avalanche detector (SPAD) device according to some embodiments. 1 shows a SPAD device 100 having a recess 104 in an upper surface 102u. It includes a silicon substrate 102. The p-type region 106 is located below the bottom of the recess 104 in the silicon substrate. It is disposed within the silicon substrate. The n-type avalanche region 108 is disposed within the silicon substrate 102 and contacts the p-type region 106 at a p-n junction 110 corresponding to a photodiode within the silicon substrate 102. It is disposed within the silicon substrate 102 and contacts the p-type region 106 at a p-n junction 110 corresponding to a photodiode within the silicon substrate 102. The germanium region 112 is disposed within the recess 104. The upper surface of the germanium region 112 may be at a depth (d) below the upper surface 102u of the silicon substrate 102 (see 112ub), may be horizontal with the upper surface 102u of the substrate (see 112ul), or may be at a height (h) above the upper surface 102u of the substrate. The upper surface of the germanium region 112 may be at a depth (d) below the upper surface 102u of the silicon substrate 102 (see 112ub), may be horizontal with the upper surface 102u of the substrate (see 112ul), or may be at a height (h) above the upper surface 102u of the substrate. The upper surface of the germanium region 112 may be at a depth (d) below the upper surface 102u of the silicon substrate 102 (see 112ub), may be horizontal with the upper surface 102u of the substrate (see 112ul), or may be at a height (h) above the upper surface 102u of the substrate. The upper surface of the germanium region 112 may be at a depth (d) below the upper surface 102u of the silicon substrate 102 (see 112ub), may be horizontal with the upper surface 102u of the substrate (see 112ul), or may be at a height (h) above the upper surface 102u of the substrate. In some embodiments, a unique silicon region 118 may be disposed between the uppermost part of the p-type region 106 and the bottom surface of the germanium region 112. In some embodiments, a unique silicon region 118 may be disposed between the uppermost part of the p-type region 106 and the bottom surface of the germanium region 112. The unique silicon region 118 is configured to operate as an electron channel between the p-n junction 110 and the germanium region 112. The unique silicon region 118 is configured to operate as an electron channel between the p-n junction 110 and the germanium region 112. The bias circuit 150 is configured to apply a bias to the p-n junction 110 to apply a voltage greater than the avalanche breakdown voltage to the SPAD device 100, and is also configured to suppress the SPAD device 100 after an avalanche occurs. The bias circuit 150 is configured to apply a bias to the p-n junction 110 to apply a voltage greater than the avalanche breakdown voltage to the SPAD device 100, and is also configured to suppress the SPAD device 100 after an avalanche occurs. The bias circuit 150 can be implemented using transistors disposed on or within the silicon substrate 102, or within another substrate, and / or other active or passive elements. The bias circuit 150 can be implemented using transistors disposed on or within the silicon substrate 102, or within another substrate, and / or other active or passive elements. The bias circuit 150 can be implemented using transistors disposed on or within the silicon substrate 102, or within another substrate, and / or other active or passive elements.

[0011] In some cases, the germanium region 112 contacts the silicon substrate 102 at a Ge-Si interface region 117. The Ge-Si interface region 117 is where the outer wall and the lower surface of the germanium region 112 respectively contact the inner side wall and the recessed upper surface of the silicon substrate 102. The Ge-Si interface region 117 is where the outer wall and the lower surface of the germanium region 112 respectively contact the inner side wall and the recessed upper surface of the silicon substrate 102. is defined by the contact area. This Ge-Si interface region 117 is composed of a Ge-Si alloy having a lattice constant in the range of 56.6 nm to 54.3 nm. In some cases, the Ge-Si alloy can have a thickness in the range of 1 angstrom to 20 nm and can have a U-shaped cross-section.

[0012] The n-type lateral connection region 114 extends laterally from the outer edge of the p-n junction 110 through the outer wall of the germanium region 112. The n-type vertical connection region 116 extends upward from the outer edge of the n-type lateral connection region 114 to the upper surface 102u of the silicon substrate 102. In some cases, the n-type vertical connection region 116 surrounds the germanium region 112 laterally when viewed from above. Therefore, the n-type lateral connection region 114 and / or the n-type vertical connection region 116 are also referred to as a "guard ring". In some embodiments, the n-type avalanche region 108, the n-type lateral connection region 114, and the n-type vertical connection region 116 jointly form a U-shaped cross-sectional contour that generally encloses the p-type region 106 and the germanium region 112 when viewed in cross-section.

[0013] During operation, the bias circuit 150 applies a bias to the p-n junction 110 that exceeds the avalanche breakdown voltage. Under this bias condition, when incident photons 152 (e.g., from a laser pulse) are absorbed in the absorption region 113 corresponding to the germanium region 112, electron-hole pairs are generated, and electrons flow through the intrinsic silicon region 118 into the multiplication region 115 including the p-n junction 110. Then, the electrons are accelerated in the multiplication region 115. , obtain sufficient kinetic energy to be collisionally ionized and generate a second electron-hole pair. The second electron and the second electron-hole pair are similarly accelerated and collisionally ionized, in the multiplication region 115 to generate additional electron-hole pairs. Further collisional ionization of holes and electrons results in a large avalanche current being rapidly generated, so that the device can self-sustain when biased beyond the avalanche breakdown voltage. In these situations, as a result, a detectable electronic signal can be obtained that is time-aligned relative to the initial incident photon 152 (e.g., from the generation of a laser pulse). After detection, the bias circuit 150 biases the SPAD device 100 below the avalanche breakdown voltage for a very short instant to suppress the avalanche, after which the SPAD device 100 returns to its quiescent state and is ready to detect further incident photons. For example, from the generation of a laser pulse) and is time-aligned relative to the initial incident photon 152 and a detectable electronic signal can be obtained. After detection, the bias circuit 150 biases the SPAD device 100 below the avalanche breakdown voltage for a very short instant to suppress the avalanche, and then the SPAD device 100 returns to its quiescent state and is ready to detect further incident photons.

[0014] In particular, by disposing the germanium region 112 in the recess 104 within the upper surface 102u of the silicon substrate 102, on the one hand, the dark current rate (DCR) can be reduced compared to other methods. Further, the germanium region 112 also facilitates the absorption (detection) of short-wavelength infrared (SWIR) signals that do not occur in pure silicon-based SPADs. Thus, the SPAD device 100 is germanium (Ge) in a silicon (Si) SAM device. In this device, forming the germanium region 112 in the recess 104 of the silicon substrate 102 provides several advantages, rather than simply as a plateau on the upper surface of the substrate.

[0015] ​​​​​​​​Figure 2 shows another embodiment of the SPAD device 100 according to some embodiments. The SPAD device 100 also includes a silicon substrate 102 with a recess 104 in its upper surface 102u. The p-type region 106 is disposed within the silicon substrate beneath the bottom of the recess 104. The n-type avalanche region 108 is disposed within the silicon substrate 102 beneath the p-type region 106 and contacts the p-type region 106 at the p-n junction 110. The germanium region 112 is disposed in the recess 104.

[0016] The n-type lateral connection region 114 extends laterally from the outer edge of the p-n junction 110 and passes by the outer sidewall of the germanium region 112. The n-type vertical connection region 116 extends upward from the outer edge of the n-type lateral connection region 114 to the upper surface 102u of the silicon substrate 102. In some cases, the n-type vertical connection region 116, when viewed from above, laterally surrounds the germanium region 112. Thus, the n-type lateral connection region 114 and / or the n-type vertical connection region 116 are also referred to as a "guard ring". In some embodiments, the n-type avalanche region 108, the n-type lateral connection region 114, and the n-type vertical connection region 116 jointly form a U-shaped cross-sectional contour that generally encloses the p-type region 106 and the germanium region 112 when viewed in cross-section.

[0017] In some embodiments, the SPAD device further includes a p-type surface region 120 that is arranged in a row with the recess 104 and laterally surrounds a unique silicon region 118. The p-type surface region is made of silicon such as single-crystalline silicon. The p-type surface region 120 includes a base portion 120b having a central opening corresponding to the unique silicon region 118 and germanium ​ including sidewall portions 120s that extend upward along the outer wall of the germanium region 112 (and / or the inner sidewall of the recess 104 in the silicon substrate).

[0018] In some embodiments, the germanium region 112 further includes a corresponding bulk region in the absorption region 113, and the bulk region and the absorption region 113 are of intrinsic (undoped) germanium. The sidewall germanium region 126 extends continuously along the outer wall of the germanium region 112. The sidewall germanium region 126 is also p-type. The p-type surface region 1 20 and the sidewall germanium region can reduce the dark current caused by stress, misalignment, etc. generated at the Ge-Si interface region to help reduce leakage.

[0019] The cap 128, for example, a p-type silicon cap, is disposed on the upper surface of the germanium region 112 to limit / prevent oxidation of the top surface of the germanium region 112. In the illustrated example, the cap 128 has an upper surface that is coplanar or horizontal with the upper surface 102u of the silicon substrate, but in other cases, the upper surface of the cap 128 may be recessed below the upper surface of the silicon substrate, may be horizontal with the top surface of the silicon substrate, or may be lifted above the upper surface of the silicon substrate. Further, in the illustrated embodiment, the cap 128 has a lower surface that directly contacts and is coplanar or horizontal with the upper surfaces of the bulk germanium region and the sidewall germanium region 126. However, in another embodiment, the sidewall germanium region 126 is disposed within the outer edge of the recess 104 and extends upward along the outer wall of the cap 128 and the upper surface 10 of the silicon substrate 102 It becomes horizontal with 2u.

[0020] The dielectric structure 132 is made of, for example, a silicon diode or a low-k dielectric material, extends over the upper surface 102u of the substrate. The conductive contact 134, for example, a metal contact extends through the dielectric structure 132, and a metal wire or a conductive pad 136 is formed on the conductive contact. The metal wire or the conductive pad 13 is operably coupled to a bias circuit such as the bias circuit 150 of FIG. 1, and can include a semiconductor device formed on the silicon substrate 102 or another silicon substrate. For example, when the semiconductor device is formed on the silicon substrate 102, the semiconductor device can include a transistor including fins and / or gate electrodes disposed on the upper surface 102u of the substrate, or alternatively, can include a transistor including fins and / or gate electrodes disposed on the lower surface 102l of the substrate. In this case, a through silicon via can extend through the substrate to facilitate an operable connection.

[0021] Referring to FIG. 3A, in some embodiments, the germanium region 112 includes an upper germanium region 122 having a first p-type doping concentration, an intermediate germanium region 124 having a second p-type doping concentration, and a bottom germanium region 130 that is intrinsic (undoped) germanium. The second p-type doping concentration is lower than the first p-type doping concentration, and when there is a non-zero dopant level, the third p-type doping concentration is lower than the second p-type doping concentration. ​​​​​​​​​Yes. In some cases, the first, second, and / or third p-type doping concentrations are substantially uniform / constant over the respective depths in the upper germanium region 122, the middle germanium region 124, and the bottom germanium region 130, but in other cases, these doping concentrations exhibit distinct “kinks” or discontinuities at the upper and lower edges of each region shown in FIG. 3A. In another case, the change in doping concentration is more stepwise and / or continuous over the entire depth of the germanium region 112. In some embodiments, the sidewall germanium region 126 extends continuously along the outer wall of the germanium region 112 and crosses the upper germanium region 122, the middle germanium region 124, and the bottom germanium region 130. By using these doping regions shown in FIG. 3A, the lens function of the SPAD device is facilitated and the carrier flows more efficiently into the p- n junction 110, which helps to improve the jitter performance.

[0022] FIG. 3B shows an example of a band diagram that is consistent with some embodiments of the SPAD device of FIG. 3A. The band diagram includes a conduction band 350 and a valence band 352. The left side of the band diagram corresponds to an n-type material (e.g., the n-type avalanche region 108), and the right side of the band diagram corresponds to a p-type material (e.g., p+ germanium). The Fermi level of the device is indicated by line 354. As shown in the figure, at the interface between the absorption region 113 and the multiplication region 115, near the silicon / germanium heterojunction, there are interface states and ​​​​Shallow and / or deep traps are provided, and these traps cause discontinuities in the valence band and the conduction band. In particular, the valence band includes an S-shaped curve in the multiplication region 115 and shows a sharp (e.g., vertical) rise at the interface between the absorption region 113 and the multiplication region 115, and then has a "dip" within the absorption region before returning to the maximum valence band energy. The conduction band also includes an S-shaped curve in the multiplication region 115, but at this time, the top of the S-shaped curve corresponds to a peak or vertex and then corresponds to the "dip" within the absorption region before returning to the maximum conduction band energy.

[0023] Figures 4 and 5 show some embodiments in which the first and second SPAD devices are arranged side-by-side with the silicon substrate. In Figures 4 and 5, since the first SPAD device 100a and the second SPAD device 100b each have the features described in Figure 2, the features indicated by a and b have the same or similar structures and functions as those described in Figure 2 (e.g., 102a and 102b in Figures 4 and 5 correspond to 102 in Figure 2, and 106a, 106b in Figures 4 and 5 correspond to 106 in Figure 2). Therefore, in Figures 4 and 5, the first n-type vertical continuation region 11 6a laterally surrounds the germanium region 112a of the first SPAD device 100a, and the second n-type vertical continuation region 116b laterally surrounds the germanium region 112b of the second SPAD device 100b. A part of the silicon substrate 402 separates the first n-type vertical continuation region 11 6a from the second n-type vertical continuation region 116b. In the embodiment of Figure 4, this part of the silicon substrate may be intrinsic single-crystalline silicon. In Figure 5, the isolation structure 50 laterally surrounds the first n-type vertical continuation region 116a and the second n-type vertical continuation region 116b, and a part of the silicon substrate 402 is located between the first n-type vertical continuation region 116a and the second n-type vertical continuation region 116b. In the embodiment of Figure 5, this part of the silicon substrate 402 may be an insulating layer. laterally surrounds the first n-type vertical continuation region 116a and the second n-type vertical continuation region 116b, and a part of the silicon substrate 402 is located between the first n-type vertical continuation region 116a and the second n-type vertical continuation region 116b. In the embodiment of Figure 5, this part of the silicon substrate 402 may be an insulating layer.​​​​​ 2. For example, a deep trench isolation structure made of a dielectric material or including p-type silicon separates the first n-type vertical continuation region 116a from the second n-type vertical continuation region 116b. In the silicon substrate, any number of SPAD devices can be arranged. For example, it should be understood that these can be arranged in an array including several rows and columns. Also, FIGS. 4 and 5 show an example where the first SPAD device 100a and the second SPAD device 100b correspond to the SPAD device 100 in FIG. 2. However, in another embodiment, the first SPA D device 100a and the second SPAD device 100b may correspond to the SPA D device 100 in FIG. 1 or FIG. 3A, and / or other illustrated embodiments, and / or combinations thereof .

[0024] FIGS. 6 to 14 show manufacturing flows according to some embodiments. FIGS. 6 to 14 will be described with respect to the method. However, the structures disclosed in FIGS. 6 to 14 are not limited to these methods and may be independent as structures unrelated to the methods.

[0025] In FIG. 6, a base semiconductor substrate 600 is received, and a sacrificial oxide 602 is formed on the upper surface of the semiconductor substrate. In some embodiments, the base semiconductor substrate 600 is a single crystal si licon wafer. However, in another embodiment, the semiconductor substrate may have other shapes . For example, the base semiconductor substrate 600 may be silicon on an insulator substrate, a sapphire substrate, or a III-V base plate, etc. The sacrificial oxide 602 may be silicon dioxide or other oxidized silicon, for example, silicon oxynitride. The sacrificial oxide 602 may be formed by thermal oxidation, rapid thermal a It can be formed by Neil, plasma vapor deposition, chemical vapor deposition, spin-on, or other techniques. In some embodiments, the sacrificial oxide 602 is in the range between 30 angstroms and 30 0 angstroms or between 75 angstroms and 120 angstroms, or has a thickness of about 90 angstroms.

[0026] In FIG. 7, blanket p-type implantation, for example, boron, aluminum, or indium implantation is performed to form a p-type region 138 embedded in the semiconductor substrate. Then, with the first photo resist mask in a predetermined position, n-type implantation, for example, phosphorus, arsenic, or antimony implantation is performed to form an n-type avalanche region 108 and an n-type lateral connection region 114.

[0027] In FIG. 8, in some cases, the sacrificial oxide is removed, and an epitaxial single-crystal silicon region 900 is epitaxially formed on the upper surface of the base semiconductor substrate 600, thereby providing a single-crystal silicon substrate. In some embodiments, the removal of the sacrificial oxide and the epitaxial formation of the epitaxial single-crystal silicon region 900 are performed in situ. The in situ treatment helps to ensure that there is no oxide on the semiconductor substrate, and thus serves to promote high-quality crystal growth with few or no defects. Then, another sacrificial oxide layer 90 2 is formed on the epitaxial single-crystal silicon region 900. In some cases, the sacrificial oxide layer 902 is formed by an in-situ steam generation (ISSG) process, but thermal oxidation, physical vapor deposition (physical v apor deposition, PVD), chemical vapor deposition (CVD), or other processes can also be used. apor deposition, PVD), chemical vapor deposition (CVD), or other processes can also be used. apor deposition, PVD), chemical vapor deposition (CVD), or other processes can also be used. It may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like. In some embodiments, the sacrificial oxide layer 902 is between 30 angstroms and 300 angstroms or between 75 angstroms and 120 angstroms, or has a thickness of about 90 angstroms. Then, in FIG. 8, a second photoresist mask 1002 is formed on the sacrificial oxide layer 902. With the second photoresist mask in a predetermined position, n-type implantation, for example, phosphorus, arsenic, or antimony implantation, is performed to form the n-type vertical connection region 116. FIG. 8 shows a case where the outer edge of the n-type vertical connection region 116 is aligned with the outer edge of the n-type lateral connection region 114. However, in another embodiment, there may be a slight deviation between these outer edges, so the edge of the n-type lateral connection region 114 may be shifted left or right with respect to the outer edge of the n-type vertical connection region 116. In FIG. 9, for example, an undoped silicate glass (USG) region having a thickness in the range of 200 angstroms to 1200 angstroms is formed. Then, a third photoresist mask (not shown) is formed, and etching is performed with the third photomask in a predetermined position to form a recess 104 in the upper surface of the silicon substrate 102. In some cases, the recess 104 can have a depth d of about 1 μm. For example, by in-situ steam generation (ISSG), 500 angstroms to 1000 angstroms that are arranged in a row with the lower surface and side walls of the recess 104 and extend on the upper surface of the semiconductor substrate

[0028]

[0029] ​​​​​​​​​​​​​​​Another oxide layer 1102 having a thickness in the range of angstroms may be formed.

[0030] In FIG. 10, a fourth photomask 1202 is formed to form a p-type region 106. p The p-type region 106 is formed at a depth d under the recessed surface, leaving a unique silicon region between the p-type region and the recessed surface for spacing below the recessed surface.

[0031] In FIG. 11, a p-type surface region 120 is formed in the semiconductor substrate, leaving a unique silicon region 118 on the p-type region 106. Further, for example, a germanium region 112 is formed by epitaxial growth. The germanium region 112 is formed to have a recessed upper surface below the upper surface of the silicon substrate 102. However, in another embodiment, the germanium region 112 may be formed to have an upper surface that is horizontal with or lifted above the upper surface of the silicon substrate 102. In some cases as the germanium region 112 grows, the germanium region forms a thin alloy with the silicon substrate, so that the germanium region contacts the silicon substrate 10 2 at the Ge-Si interface region. The Ge-Si interface region is defined where the outer wall and the lower surface of the germanium region contact the inner side wall and the recessed upper surface of the silicon substrate, respectively.

[0032] In FIG. 12, a cap 128 is formed on the germanium region 112. The formation of the cap 128 can be performed by an epitaxial growth process and completed in situ (e.g., with the same tool as when forming the germanium region 112, in a vacuum or ​​​​​​​​in a controlled environment such as nitrogen, the oxidation of the germanium region 112 can be restricted . In certain cases, the cap 128 can be epitaxially grown p-type single crystal silicon and can have an upper surface lifted above the upper surface of the substrate, but the upper surface of the cap may be flush with the upper surface of the substrate or below it. And , for example, an oxide 1502 can be formed on the cap 128 via rapid thermal annealing or as a native oxide .

[0033] In FIG. 13, another ion implantation process is performed to form the p-type sidewall germanium region 126 . In certain cases, before this ion implantation, another photomask is formed and then , with the photomask in a predetermined position, this ion implantation is performed to form the p-type sidewall germanium region 126.

[0034] In FIG. 14, a dielectric structure 132 is formed on the upper surface of the silicon substrate 102. A contact opening is formed through the dielectric structure 132 and a conductive contact 134 such as a metal contact, and a metal wire or a conductive pad 136 is formed on the conductive contact. And , the metal wire or the conductive pad 136 may be operably coupled to a bias circuit, and the bias circuit can include a semiconductor device formed on the silicon substrate 102 or on another semiconductor substrate. For example, when the semiconductor device is formed on a semiconductor substrate, the semiconductor device can include a transistor including fins and / or gate electrodes disposed on the upper surface of the substrate, or alternatively can include a transistor including fins and / or gate electrodes disposed on the lower surface of the substrate. In this case, the silicon through electrodes extend through the substrate and can include a transistor including fins and / or gate electrodes disposed on the upper surface of the substrate, or alternatively can include a transistor including fins and / or gate electrodes disposed on the lower surface of the substrate. In this case, the silicon through electrodes extend through the substrate and can include a transistor including fins and / or gate electrodes disposed on the upper surface of the substrate, or alternatively can include a transistor including fins and / or gate electrodes disposed on the lower surface of the substrate. In this case, the silicon through electrodes extend through the substrate and can include a transistor including fins and / or gate electrodes disposed on the upper surface of the substrate, or alternatively can include a transistor including fins and / or gate electrodes disposed on the lower surface of the substrate. In this case, the silicon through electrodes extend through the substrate and in this case, the silicon through electrodes extend through the substrate It is possible to facilitate operable coupling.

[0035] Figures 15 to 21 show another manufacturing flow according to some embodiments. Contrary to Figures 6 to 14 showing the formation of a single SPAD device, Figures 15 to 21 show first and second SPAD devices formed directly adjacent to each other. The structures disclosed in Figures 15 to 21 are not limited to these methods and may be independent as structures unrelated to the methods.

[0036] In Figure 15 (in some aspects, corresponding to Figures 6 to 8), a base semiconductor substrate 600 is received, and a p-type region 138 buried in the semiconductor substrate is formed using a blanket p-type implant. For example, by forming a photomask and performing ion implantation, an n-type lateral connection region 114 is also formed. An epitaxial single crystal silicon region 900 is formed on the upper surface of the base semiconductor substrate 600, and an n-type vertical connection region 116 is formed. In this example, the first and second n-type vertical connection regions 116a, 116b are laterally spaced apart by an isolation region of the semiconductor substrate. A sacrificial oxide 1802 is formed on the upper surface of the epitaxial single crystal silicon region 900.

[0037] In Figure 16 (in some aspects, corresponding to Figure 9), for example, an undoped silicate glass (USG ) region having a thickness in the range between 200 angstroms and 1200 angstroms is formed. Then, a third photoresist mask 1902 is formed, and etching is performed with the third photomask in a predetermined position to form a recess 1 04 in the upper surface of the silicon substrate. In some cases, the recess can have a depth d of about 1 μm.​​​​​ For example, by in-situ steam generation (ISSG), another oxide layer 1102 may be formed in alignment with the lower surface and sidewalls of the recess.

[0038] In FIG. 17 (which corresponds to FIG. 11 in one aspect), p-type regions 106a, 106b, p-type sidewall portions 120a, and p-type base portions 120b are formed within the semiconductor substrate. The p-type regions 106a, 106b are formed at a depth d below the recessed surface, thereby leaving distinct silicon regions 118a, 118b between the p-type regions and the recessed surface.

[0039] In FIG. 18 (which corresponds to FIG. 11 again in one aspect), germanium regions 112a, 112b are formed, for example, by epitaxial growth. The germanium regions are formed to have a recessed upper surface below the upper surface of the silicon substrate. However, in another embodiment, the germanium regions may be formed to have an upper surface that is horizontal with or raised above the upper surface of the silicon substrate. In certain cases, as the germanium regions 112a, 112b grow, they form a thin alloy with the silicon substrate, such that the germanium regions contact the silicon substrate 102 at the Ge-Si interface region. The Ge-Si interface region is defined where the outer sidewalls and lower surface of the germanium regions contact the inner sidewalls and recessed upper surface of the silicon substrate, respectively.

[0040] In FIG. 19 (which corresponds to FIG. 12 in one aspect), silicon caps 128a, 128b are formed over the germanium regions 112a, 112b, respectively. The formation of the silicon caps can be performed by an epitaxial growth process and can be in-situ. ​​​​​​​​​​​​​​ After completion (e.g., in a controlled environment such as vacuum or nitrogen, in the same manner as when forming the germanium region), the oxidation of the germanium region can be restricted. In certain cases , the epitaxially grown silicon cap is p-type. And, for example, an oxide can be formed on the silicon cap via rapid thermal annealing or as a native oxide.

[0041] In FIG. 20 (which in one aspect corresponds to FIG. 13), another ion implantation process is performed to form p-type germanium regions 126a, 126b. In certain cases, before this ion implantation, another photomask is formed and then this ion implantation is performed with the photomask in a predetermined position.

[0042] In FIG. 21 (which in one aspect corresponds to FIG. 14), a dielectric is formed on the upper surface of the substrate. Contact openings are formed through the dielectric and conductive contacts 134, e.g., metal contacts, and a metal wire or conductive pad 136 is formed on the conductive contacts. Then, the metal wire or conductive pad may be operably coupled to a bias circuit and a quench circuit, which may include semiconductor devices formed on a silicon substrate or other semiconductor substrates. For example, if the semiconductor device is formed on a semiconductor substrate, the semiconductor device can include transistors having fins and / or gate electrodes disposed on the upper surface of the substrate, or transistors having fins and / or gate electrodes disposed on the lower surface of the substrate. In this case, silicon through electrodes extend through the substrate and can facilitate an operable connection. Thus, in FIG. 21, the first and second ​​​​​​​​​​​​ and the outer walls of the 2n-th type vertical connection regions 116a and 116b (for example, guard rings) are separated from each other by an isolation region corresponding to a part of the semiconductor substrate. In the case of FIG. 21, they can be separated by single crystal silicon.

[0043] FIGS. 22 to 29 show another manufacturing flow according to some embodiments. FIGS. 22 to 29 will be described with respect to the method, but the structures disclosed in FIGS. 22 to 29 are not limited to these methods and may be independent as structures unrelated to the method.

[0044] FIGS. 22 to 28 are approximately the same as FIGS. 15 to 21 described above and show adjacent SPAD devices. However, in FIG. 29 (continuing from FIG. 28), an isolation structure 502 is formed from the lower surface of the semiconductor substrate to isolate adjacent SPAD devices from each other. In some cases, the isolation structure 502 can be formed by forming a photomask on the lower surface of the semiconductor substrate, then performing etching to form a trench on the lower surface of the semiconductor substrate, and then filling the trench with a dielectric material. In other cases, the isolation structure 502 can be formed by implanting ions (for example, p-type dopants) into the lower surface of the substrate.

[0045] FIG. 30 is a flowchart of a manufacturing flow according to some embodiments. Method 330 0 is shown and described as a series of operations and events, but it should be understood that these operations and events are not limited by the order thereof. For example, some operations may be performed in a different order than shown and / or described in this specification, and / or in combination with other It may occur simultaneously with any action or event. It is also possible that one or more aspects of the present specification may be combined. Not all illustrated acts are necessarily required to implement any particular embodiment. Furthermore, one or more of the acts described herein may be combined with one or more The above may be performed in separate operations and / or steps.

[0046] In act 3302, a semiconductor substrate is received.

[0047] In operation 3304, ion implantation is performed to form a lateral connection region below an upper surface of the semiconductor substrate. Form.

[0048] In operation 3306, ion implantation is performed to form a vertical connection region. The lateral connection regions contact each other to form a guard ring.

[0049] In operation 3308, a recess is formed in the upper surface of the semiconductor substrate, the recess being configured to include a guard ring. and a recessed upper surface of the semiconductor substrate and an inner sidewall of the semiconductor substrate. It is defined by:

[0050] In an operation 3310, a germanium region is formed in the recess.

[0051] As such, some embodiments may employ single photon avalanche detector (SPAD) devices. The device includes a silicon substrate including a recess in an upper surface. The p-type region is disposed in the recess. The n-type avalanche region is located in the silicon substrate below the lower surface of the p-type A gate electrode is disposed in the underlying silicon substrate and contacts the p-type region at the pn junction. The ruthenium region is disposed in a recess above the pn junction.

[0052] Another embodiment provides a semiconductor structure. The semiconductor structure includes a silicon substrate and a silicon-based multiplication region embedded in the semiconductor substrate. A germanium-based absorption region is embedded in the semiconductor substrate and is disposed above the silicon-based multiplication region. An electron channel is disposed between the silicon-based multiplication region and the germanium-based absorption region.

[0053] Yet another embodiment provides a method. A semiconductor substrate is received. Ion implantation is performed to form a lateral connection region beneath the upper surface of the semiconductor substrate. Ion implantation is performed to form a vertical connection region. The vertical connection region and the lateral connection region contact each other to form a guard ring in the upper surface of the semiconductor substrate. A recess is formed within the upper surface of the semiconductor substrate, and the recess is laterally surrounded by the guard ring and is defined by the recessed upper surface and the inner sidewalls of the semiconductor substrate of the semiconductor substrate. A germanium region is formed in the recess.

[0054] Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or other orientations), and the spatially relative descriptions used herein may be interpreted accordingly similarly.

Industrial Applicability

[0055] The semiconductor structure and method of the present invention are applicable to single photon avalanche diode (SPAD) devices​​​​​​ It can be applied to

Description of Signs

[0056] 100 SPAD device 100a First SPAD device 100b Second SPAD device 102 Silicon structure 102l Lower surface 102u Upper surface 104 Recess 106, 106a, 106b p-type regions 108, 108a, 108b n-type avalanche regions 110, 110a, 110b p-n junctions 112, 112a, 112b Germanium regions 112ua, 112ub, 112ul Upper surface 113 Absorption region 114, 114a, 114b n-type lateral connection regions 115 Multiplication region 116 n-type vertical connection region 116a First n-type vertical connection region 116b Second n-type vertical connection region 117 Ge-S interface region 118, 118a, 118b Intrinsic silicon regions 120 p-type surface region 120a p-type sidewall portion 120b p-type base portion 120s Sidewall portion 122 Upper germanium region 124 Intermediate germanium region 126 p-type sidewall germanium region 126a, 126b p-type germanium regions 128 Cap 128a, 128b Silicon caps 130 Bottom germanium region 132 Dielectric structure 134 Conductive contact 136 Metal wire or conductive pad 138 Embedded p-type region 150 Bias circuit 152 Incident photons 350 Conduction band 352 Valence band 354 Fermi level 402 Silicon structure 502 Isolation structure 600 Semiconductor structure 602, 1802 Sacrificial oxide 900 Epitaxial single-crystal silicon region 902 Sacrificial oxide layer 1002 Second photoresist mask 1102 Oxide layer 1202 Fourth photomask 1502 Oxide 1902 Third photoresist mask 3300 Method 3302, 3304, 3306, 3308, 3310 Operations d Depth h Height

Claims

1. receiving a semiconductor substrate; performing ion implantation to form a lateral connection region below an upper surface of the semiconductor substrate; performing ion implantation to form a vertical connection region, the vertical connection region and the lateral connection region contacting each other to form a guard ring; forming a recess in the upper surface of the semiconductor substrate, the recess being laterally surrounded by the guard ring and defined by a recessed upper surface of the semiconductor substrate and an interior sidewall of the semiconductor substrate; forming a germanium region in the recess; A method comprising:

2. after forming the lateral connection region, growing an epitaxial silicon region on an upper region of the semiconductor substrate; 2. The method of claim 1, wherein the vertical connection region is formed within the epitaxial silicon region.

3. the lateral connection region is an n-type semiconductor material; and 3. The method of claim 2, further comprising forming a p-type region contacting the n-type semiconductor material at a pn junction prior to growing the epitaxial silicon region.

4. 4. The method of claim 3, wherein the germanium region has an outer wall that extends laterally past the outer edge of the pn junction.

5. 4. The method of claim 3, wherein the p-type region is formed below a lower surface of the recess, such that an intrinsic region of silicon separates the lower surface of the germanium region from an uppermost portion of the p-type region.

6. forming a silicon cap on the upper surface of the germanium region, the silicon cap directly contacting the upper surface of the germanium region without an oxide separating the germanium region from the silicon cap; The method of claim 1 , wherein the silicon cap is grown in situ in the same tool or chamber as the germanium region.

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