Semiconductor device

Abstract

To provide a highly reliable semiconductor device whose yield can be prevented from decreasing due to electrostatic discharge damage.SOLUTION: There is provided a semiconductor device including: a gate electrode layer; a first gate insulating layer over the gate electrode layer; a second gate insulating layer provided over the first gate insulating layer and having a smaller thickness than the first gate insulating layer; an oxide semiconductor layer over the second gate insulating layer; and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The first gate insulating layer includes a silicon film containing nitrogen and has a spin density of 1×1017 spins / cm3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. The second insulating layer includes a silicon film containing nitrogen and has a lower hydrogen-containing concentration than the first gate insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification and the like relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices, all of which are semiconductor devices. be. [Background technology]

[0003] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is used in integrated circuits (ICs) and image display devices (also known simply as display devices). These are widely used in electronic devices such as semiconductors that can be used in transistors. Silicon-based semiconductor materials are widely known as thin semiconductor films, but other materials include oxide semiconductors. Conductors are in the spotlight.

[0004] For example, a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor can be used. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] When mass-producing semiconductor devices using oxide semiconductors (hereinafter abbreviated as mass production), , considering development costs and development speed, a transistor configuration, process conditions, or the use of production equipment, etc., using silicon-based semiconductor materials such as amorphous silicon or polycrystalline silicon, which are mass production technologies that have been put into practical use, is desired.

[0007] However, the carrier generation mechanism of oxide semiconductors is significantly different from that of silicon-based semiconductor materials, and the physical properties of oxide semiconductors greatly affect the characteristics or reliability of transistors.

[0008] In particular, the gate insulating layer used for silicon-based semiconductor materials is not a configuration that sufficiently satisfies the interface characteristics with the oxide semiconductor for application to the oxide semiconductor. Therefore, the development of a gate insulating layer suitable for semiconductor devices using oxide semiconductors is desired.

[0009] Also, semiconductor devices composed of transistors using silicon-based semiconductor materials such as amorphous silicon or polycrystalline silicon have the advantages of high productivity and low cost because they can support glass substrates of the 8th generation (2160 mm horizontal × 2460 mm vertical) or larger. On the other hand, when using a glass substrate, due to its high insulation and large area, the problem of electrostatic breakdown (ESD: Electro-Static Discharge) becomes particularly prominent. This is an issue that should naturally be considered even when using oxide semiconductor materials.

[0010] Based on the technical background as described above, one aspect of the present invention involves few changes to the transistor configuration, process conditions, or production equipment, etc., from mass production technologies that have been put into practical use, and is stable for semiconductor devices. One of the problems is to provide a semiconductor device with improved electrical characteristics and high reliability.

[0011] Another aspect of the present invention is a semiconductor device capable of preventing a reduction in yield due to electrostatic breakdown. One of the problems is to provide such a semiconductor device.

Means for Solving the Problems

[0012] One aspect of the disclosed invention is a semiconductor device including, between a gate electrode layer and an oxide semiconductor layer, a stacked structure of a silicon film containing nitrogen with reduced defects in the film and a silicon film containing nitrogen with reduced hydrogen concentration from the gate electrode layer side as a gate insulating layer. More specifically, for example, the following configuration can be adopted. a silicon film containing nitrogen with reduced defects in the film and a silicon film containing nitrogen with reduced hydrogen concentration A semiconductor device including a stacked structure as a gate insulating layer. More specifically, for example, the following configuration can be adopted. For example, it can have the following configuration.

[0013] One aspect of the present invention has a gate electrode layer, a first gate insulating layer on the gate electrode layer, a second gate insulating layer provided on the first gate insulating layer and having a smaller film thickness than the first gate insulating layer, an oxide semiconductor layer on the second gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The first gate insulating layer is a silicon film containing nitrogen with a spin density corresponding to a signal having a g-value of 2.003 in electron spin resonance method being 1×10 spins / c m or less, and the second gate insulating layer is a silicon film containing nitrogen with a lower hydrogen concentration than the first gate insulating layer. spins / c 17 spins / c m 3 or less, and the second gate insulating layer is a silicon film containing nitrogen with a lower hydrogen concentration than the first gate insulating layer. A semiconductor device including a stacked structure as a gate insulating layer. More specifically, for example, the following configuration can be adopted.

[0014] Another aspect of the present invention has a gate electrode layer, a first gate insulating layer on the gate electrode layer, a second gate insulating layer provided on the first gate insulating layer and having a larger film thickness than the first gate insulating layer, and a third gate insulating layer provided on the second gate insulating layer and having a smaller film thickness than the second gate insulating layer. a second gate insulating layer provided on the first gate insulating layer and having a larger film thickness than the first gate insulating layer A semiconductor device including a stacked structure as a gate insulating layer. More specifically, for example, the following configuration can be adopted. a third gate insulating layer, an oxide semiconductor layer on the third gate insulating layer, and a source electrode layer and a drain electrode layer that are electrically connected, and the second gate insulating layer is an electron In the spin resonance method, the spin density corresponding to the signal where the g value appears at 2.003 is 1×10 17 spins / cm 3 or less, a silicon film containing nitrogen, and the first gate insulating layer and and the third gate insulating layer are semiconductor devices that are silicon films containing nitrogen with a hydrogen concentration lower than that of the second gate insulating layer. Note that the gate electrode layer preferably contains copper.

[0015] In the semiconductor device described above, the oxide semiconductor layer may include a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer that have the same constituent elements but different compositions from each other.

[0016] Also, in the semiconductor device described above, a first insulating layer that covers the source electrode layer and the drain electrode layer and is in contact with a part of the oxide semiconductor layer, and a second insulating layer on the first insulating layer are provided. The first insulating layer is a silicon film containing nitrogen with a hydrogen concentration lower than that of the second insulating layer. The second insulating layer preferably has a spin density corresponding to the signal where the g value appears at 2.003 in the electron spin resonance method of 1×10 or less, a silicon film containing nitrogen. 17 spins / cm 3

Advantages of the Invention

[0017] A semiconductor device provided according to one aspect of the present invention is a semiconductor device that has stable electrical characteristics and high reliability, and is manufactured by a manufacturing method that involves few changes from mass production techniques that have been put into practical use.

[0018] Also, according to one aspect of the present invention, a semiconductor device capable of preventing a decrease in yield due to electrostatic breakdown can be provided.

Brief Description of the Drawings

[0019]

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Embodiments for Carrying Out the Invention

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that its form and details can be variously changed. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. ​​​It is not such a thing.

[0021] In addition, in the configuration of the present invention described below, for the same part or parts having the same function, the same reference numerals are commonly used among different drawings, and the repeated description thereof is omitted. Also, when referring to parts having the same function, the hatching pattern is the same, and there are cases where no particular reference numeral is attached. There are cases.

[0022] In each of the drawings described in this specification, the size, film thickness, or area of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0023] In this specification and the like, the ordinal numbers attached as first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Also, in this specification and the like, they do not indicate specific names for identifying the invention.

[0024] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method of manufacturing the semiconductor device will be described with reference to FIGS. 1 to 3. In this embodiment, as an example of a semiconductor device, a bottom gate type transistor having an oxide semiconductor layer is shown.

[0025] Configuration examples of the transistor 300 are shown in FIGS. 1(A) to 1(C). FIG. 1(A) is a plan view of the transistor 300, FIG. 1(B) is a cross-sectional view taken along the dashed line X1 - Y1 in FIG. 1(A), and FIG. 1(C) is a cross-sectional view taken along the dashed line V1 - W1 in FIG. 1(A).

[0026] The transistor 300 includes a gate electrode layer 402 provided on a substrate 400 having an insulating surface. ​and a gate insulating layer 404 on the gate electrode layer 402, an oxide semiconductor layer 408 in contact with the gate insulating layer 404 and overlapping the gate electrode layer 402, and a source electrode layer 410a and a drain electrode layer 410b electrically connected to the oxide semiconductor layer 408. In the transistor 300, the gate insulating layer 404 is composed of a gate insulating layer 404a in contact with the gate electrode layer 402 and a gate insulating layer 404b on the gate insulating layer 404a.

[0027] In the transistor 300, the gate insulating layer 404 is composed of a gate insulating layer 404a in contact with the gate electrode layer 402 and a gate insulating layer 404b on the gate insulating layer 404a.

[0028] A silicon film containing nitrogen is applied as the gate insulating layer 404a and the gate insulating layer 404b. The silicon film containing nitrogen has a higher relative permittivity than a silicon oxide film, and since the film thickness required to obtain the same capacitance is large, the gate insulating layer can be physically thickened. Therefore, it is possible to suppress a decrease in the breakdown voltage of the transistor 300 and further improve the breakdown voltage, thereby suppressing electrostatic breakdown of the semiconductor device. Therefore, it is possible to suppress a decrease in the breakdown voltage of the transistor 300 and further improve the breakdown voltage, thereby suppressing electrostatic breakdown of the semiconductor device.

[0029] Examples of the silicon film containing nitrogen include a silicon nitride film, a silicon oxynitride film, and a silicon nitride oxide film. Since the relative permittivity is higher as the nitrogen content is higher, it is preferable to apply a silicon nitride film. Further, the energy gap of silicon oxide is 8 eV, while the energy gap of silicon nitride is as small as 5.5 eV, and accordingly, the resistivity is also small. Therefore, by using a silicon nitride film, it is possible to impart higher ESD resistance. In contrast, the energy gap of silicon nitride is small at 5.5 eV compared to 8 eV for silicon oxide, and accordingly, the resistivity is also small. Therefore, by using a silicon nitride film, it is possible to impart higher ESD resistance. Furthermore, when forming a silicon nitride film by CVD, it is applicable to the case of forming a silicon film containing oxygen and nitrogen such as a silicon oxynitride film by CVD. ​​​​​​​​​There is no need to use N2O gas which is S. In this specification, silicon oxynitride film refers to a film with an oxygen content higher than that of nitrogen in terms of its composition, and silicon oxynitride film refers to a film with a nitrogen content higher than that of oxygen in terms of its composition.

[0030] In this embodiment, as the gate insulating layer 404a and the gate insulating layer 404b, a silicon nitride film is applied.

[0031] The gate insulating layer 404a has a film thickness thicker than that of the gate insulating layer 404b, and uses a silicon nitride film with reduced defects in the film. For example, the film thickness of the gate insulating layer 404a is set to be 30 0 nm or more and 400 nm or less. Also, in the electron spin resonance method (ESR: Electron Spin Resonance), the spin density corresponding to the signal appearing at the Nc center (g value of 2.003) is preferably 1×10 spins / cm or less, more preferably 17 spins / cm 3 or less, and a silicon nitride film with a spin density of 5×10 or less, more preferably 16 spins / cm 3 or less is applied. In this way, by providing a silicon nitride film with reduced defects in the film at a thick film thickness (for example, 300 nm or more), the breakdown voltage of the gate insulating layer 404a can be set to 300 V or more, for example.

[0032] Also, since the gate insulating layer 404b is in contact with the oxide semiconductor layer 408, it is a silicon nitride film with a reduced hydrogen concentration. The hydrogen concentration of the gate insulating layer 404b is at least lower than that of the gate insulating layer 404a. For example, when forming the gate insulating layer 404a and the gate insulating layer 404b by plasma CVD method, the hydrogen concentration contained in the supply gas is set. By lowering it, the hydrogen concentration of the gate insulating layer 404b can be reduced compared to the gate insulating layer 404a. This can be achieved. Specifically, when forming silicon nitride films as the gate insulating layer 404a and the gate insulating layer 404b, if the ammonia flow rate is reduced compared to the supply gas for forming the gate insulating layer 404a, or if the gate insulating layer 404b is formed without using ammonia, it is fine.

[0033] Also, the film thickness of the gate insulating layer 404b is set to be 25 nm or more and 150 nm or less. By providing a silicon nitride film with a reduced hydrogen concentration as the gate insulating layer 404b, the incorporation of hydrogen or a hydrogen compound (e.g., water) into the oxide semiconductor layer 408 can be reduced. Hydrogen becomes a factor in generating carriers in the oxide semiconductor and a factor in shifting the threshold voltage of the transistor in the negative direction. Therefore, by providing a silicon nitride film with a reduced hydrogen concentration as the gate insulating layer 404b, the electrical characteristics of the transistor can be stabilized. Also, by providing a silicon nitride film with a reduced hydrogen concentration as the gate insulating layer 404b, it also has the effect of acting as a barrier film to prevent the diffusion of impurities such as hydrogen or hydrogen compounds contained in the gate insulating layer 404a into the oxide semiconductor

[0034] In this embodiment, both the gate insulating layer 404a and the gate insulating layer 404b are silicon nitride films. Depending on the material and film formation conditions, the interface between the gate insulating layers may become unclear. Therefore, in FIG. 1, the interface between the gate insulating layer 404a and the gate insulating layer 404 b is schematically illustrated by a dotted line. This is the same in each of the subsequent drawings.

[0035] ​​Hereinafter, the structure of the oxide semiconductor layer will be described.

[0036] The oxide semiconductor layer is roughly classified into a single-crystalline oxide semiconductor layer and a non-single-crystalline oxide semiconductor layer. The non- single-crystalline oxide semiconductor layer refers to an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, and the like.

[0037] The amorphous oxide semiconductor layer is an oxide semiconductor layer in which the atomic arrangement in the film is irregular and has no crystal component. It is typical of an oxide semiconductor layer that has no crystal part even in a minute region and the whole film has a perfect amorphous structure. Even in a minute region, it has no crystal part, and the whole film has a perfect amorphous structure. The oxide semiconductor layer is typical.

[0038] The microcrystalline oxide semiconductor layer contains, for example, microcrystals (also called nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor layer has a higher regularity of atomic arrangement than the amorphous oxide semiconductor layer. Therefore, the microcrystalline oxide semiconductor layer is characterized by having a lower density of defect levels than the amorphous oxide semiconductor layer. That is, it contains microcrystals (also called nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor layer has a higher regularity of atomic arrangement than the amorphous oxide semiconductor layer. Therefore, the microcrystalline oxide semiconductor layer is characterized by having a lower density of defect levels than the amorphous oxide semiconductor layer.

[0039] The CAAC-OS film is one of the oxide semiconductor layers having a plurality of crystal parts, and most of the crystal parts have a size that can be accommodated in a cube with a side length of less than 100 nm. Therefore, the crystal parts included in the CAAC-OS film also include cases where the size can be accommodated in a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. The CAAC-OS film is characterized by having a lower density of defect levels than the microcrystalline oxide semiconductor layer. Hereinafter, the CAAC-OS film will be described in detail. That is, the CAAC-OS film is one of the oxide semiconductor layers having a plurality of crystal parts, and most of the crystal parts have a size that can be accommodated in a cube with a side length of less than 100 nm. Therefore, the crystal parts included in the CAAC-OS film also include cases where the size can be accommodated in a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. The CAAC-OS film is characterized by having a lower density of defect levels than the microcrystalline oxide semiconductor layer. Hereinafter, the CAAC-OS film will be described in detail. Hereinafter, the CAAC-OS film will be described in detail. .

[0040] When the CAAC-OS film is observed by a transmission electron microscope (TEM), clear boundaries between crystal parts, that is, grain boundaries (also referred to as grain boundaries), cannot be confirmed. Therefore, it can be said that the CAAC-OS film is less likely to have a decrease in electron mobility due to grain boundaries. When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film. In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included.

[0041]

[0042]

[0043] And "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0044]

[0045] When the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, no regularity is seen in the arrangement of metal atoms between different crystal parts.

[0044] From the cross-sectional TEM observation and the planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation.

[0045] When performing a structural analysis on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film having crystals of InGaZnO4 by the out-of-plane method, a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. When performing a structural analysis on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film having crystals of InGaZnO4 by the out-of-plane method, a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. When performing a structural analysis on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film having crystals of InGaZnO4 by the out-of-plane method, a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. When performing a structural analysis on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film having crystals of InGaZnO4 by the out-of-plane method, a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. When performing a structural analysis on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film having crystals of InGaZnO4 by the out-of-plane method, a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. When performing a structural analysis on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film having crystals of InGaZnO4 by the out-of-plane method, a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0046] On the other hand, in the analysis of the CAAC-OS film by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed in the vicinity of 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed in the vicinity of 56°. On the other hand, in the analysis of the CAAC-OS film by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed in the vicinity of 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed in the vicinity of 56°. On the other hand, in the analysis of the CAAC-OS film by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed in the vicinity of 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed in the vicinity of 56°. On the other hand, in the analysis of the CAAC-OS film by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed in the vicinity of 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed in the vicinity of 56°. On the other hand, in the analysis of the CAAC-OS film by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed in the vicinity of 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed in the vicinity of 56°. On the other hand, in the analysis of the CAAC-OS film by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed in the vicinity of 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed in the vicinity of 56°. On the other hand, in the analysis of the CAAC-OS film by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed in the vicinity of 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed in the vicinity of 56°.

[0047] From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it can be seen that the film has c-axis orientation and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it can be seen that the film has c-axis orientation and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it can be seen that the film has c-axis orientation and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it can be seen that the film has c-axis orientation and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

[0048] The crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. is formed when. As described above, the c-axis of the crystal is also parallel to the normal vector of the upper surface of the CAAC-OS film is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. When the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. or the upper surface.

[0049] In addition, the crystallinity in the CAAC-OS film does not have to be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. When the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the formed surface. In addition, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. When impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. or regions with different crystallinities may be formed partially.

[0050] In the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak around 2θ = 31°, a peak may also appear around 2θ = 36°. The peak around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. The CAAC-OS film preferably shows a peak around 2θ = 31° and does not show a peak around 2θ = 36°. In the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak around 2θ = 31°, a peak may also appear around 2θ = 36°. The peak around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. The CAAC-OS film preferably shows a peak around 2θ = 31° and does not show a peak around 2θ = 36°. The CAAC-OS film preferably shows a peak around 2θ = 31° and does not show a peak around 2θ = 36°.

[0051] In this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system.

[0052] The transistor using the CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability. Therefore, the transistor has high reliability.

[0053] ​Note that the oxide semiconductor layer 408 may be, for example, an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer , or any structure of a CAAC-OS film, or may include two or more of these structures . Further, it may be a laminated film having two or more of these structures

[0054] The CAAC-OS film is formed, for example, by using a target for sputtering an oxide semiconductor that is polycrystalline and by a sputtering method. When ions collide with the sputtering target , the crystal regions contained in the sputtering target are cleaved from the a-b plane and peeled off as plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a -b plane . In this case, the CAAC-OS film can be formed by the plate-shaped sputtering particles reaching the substrate while maintaining the crystal state

[0055] Further, in order to form the CAAC-OS film, it is preferable to apply the following conditions

[0056] By reducing the incorporation of impurities during film formation, it is possible to suppress the crystal state from being disrupted by impurities . For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced . Also, the impurity concentration in the film formation gas may be reduced. Specifically, a film formation gas having a dew point of -80°C or lower, preferably -100°C or lower, is used

[0057] Further, by increasing the substrate heating temperature during film formation, migration of sputtering particles occurs after adhesion to the substrate . Specifically, the film is formed with the substrate heating temperature being 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower. By increasing the substrate heating temperature during film formation, flat ​When plate-like sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate.

[0058] In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film-forming gas and optimizing the power. The oxygen ratio in the film-forming gas is 30% by volume or more, preferably 100% by volume. and the flat surface of the sputtering particles adheres to the substrate. % by volume.

[0059] As an example of a sputtering target, an In-Ga-Zn-O compound target is shown below. is shown below.

[0060] InO X powder, GaO Y powder, and ZnO Z powder are mixed at a predetermined ratio, and after pressure treatment, heat treatment is performed at a temperature of 1 000 °C or higher and 1500 °C or lower to obtain a polycrystalline In-Ga-Z n-O compound target. Here, X, Y, and Z are arbitrary positive numbers. Here, the predetermined mol ratio is, for example, InO X powder, GaO Y powder, and ZnO Z powder are 2:2 :1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. Note that , the type of powder and the mol ratio for mixing it may be appropriately changed depending on the sputtering target to be produced.

[0061] As a component of the transistor 300, an insulating layer 414 that covers the source electrode layer 410a and the drain electrode layer 410 b and is in contact with the oxide semiconductor layer 408 may be included.

[0062] As the insulating layer 414, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride A recon film, a silicon oxynitride film, an aluminum oxynitride film, a silicon nitride oxide film, or the like can be used. However, by forming the insulating layer 414 into a silicon film containing nitrogen, more preferably a silicon nitride film, it becomes possible to further reduce electrostatic breakdown during the manufacturing process of the semiconductor device or for the semiconductor device after formation, which is preferable.

[0063] An example of a method for manufacturing the transistor 300 will be described below with reference to FIG. 2.

[0064] First, a gate electrode layer 402 is formed on a substrate 400 having an insulating surface.

[0065] There are no major restrictions on the substrate that can be used for the substrate 400 having an insulating surface, but it is necessary to have heat resistance sufficient to withstand at least subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates , sapphire substrates, etc. can be used. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates , etc. can be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 400.

[0066] The gate electrode layer 402 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or an alloy material mainly composed of these. Also, as the gate electrode layer 402, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, a silicide film such as nickel silicide can be used. The gate electrode layer 402 may have a single-layer structure or a stacked structure. ​​​​​​Okay. The gate electrode layer 402 may have a tapered shape. For example, the taper angle may be 30° or more and 70 ° or less. Here, the taper angle refers to the angle between the side surface of the layer having the tapered shape and the bottom surface of the layer.

[0067] Also, as the material of the gate electrode layer 402, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, conductive materials such as indium tin oxide added with silicon oxide can also be applied.

[0068] Alternatively, as the material of the gate electrode layer 402, In-Ga-Zn-based oxide containing nitrogen, In-Sn-based oxide containing nitrogen, In-Ga-based oxide containing nitrogen, In-Zn-based oxide containing nitrogen, Sn-based oxide containing nitrogen, In-based oxide containing nitrogen, metal nitrides (such as indium nitride, zinc nitride, tantalum nitride, tungsten nitride, etc.) may be used. Since these materials have a work function of 5 eV or more, by forming the gate electrode layer 402 using these materials, the threshold voltage of the transistor can be made positive, and a normally-off switching transistor can be realized.

[0069] Next, a gate insulating layer 404 including a gate insulating layer 404a and a gate insulating layer 40 4b is formed so as to cover the gate electrode layer 402 (see Fig. 2(A)). As the gate insulating layer 404, a silicon film containing nitrogen can be applied. In this embodiment, the gate insulating layer 404a made of a silicon nitride film and the gate insulating layer 404b made of a silicon nitride film are laminated. ​​Use it as the gate insulating layer 404. The gate insulating layer 404 is effective in reducing in-plane variations, particle contamination and film formation tact from the viewpoint of reducing film formation tact. It is effective to perform film formation using the CVD method . Also, the CVD method is effective for film formation on a large-area substrate.

[0070] In this embodiment, the gate insulating layer 404a and the gate insulating layer 4 04b are continuously formed. First, the supply gas is a mixed gas of silane (SiH4), nitrogen (N2), and a mmonia (NH3), and a silicon nitride film that becomes the gate insulating layer 404a is formed . Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2) , and a silicon nitride film that becomes the gate insulating layer 404b is formed.

[0071] The silicon nitride film formed with the supply gas of the plasma CVD method as a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH 3) can reduce film defects more than the silicon nitride film formed with the supply gas as a mixed gas of silane (SiH4) and nitrogen . Therefore, the gate insulating layer 404a is a film with fewer defects in the film than at least the gate insulating layer 404b. For example, in the electron spin resonance method (ESR), the spin density corresponding to the signal appearing at the Nc center (g value: 2.003) is preferably 1×10 s pins / cm 17 s pins / cm 3 , more preferably 5×10 16 spins / cm 3 or less. Also, the silicon nitride film formed with ammonia included in the mixed gas can be made into a film with better coating properties than when the supply gas is a mixed gas of silane and nitrogen. Therefore, the gate insulating layer 404a can be made into a film with better coating properties than when the supply gas is a mixed gas of silane and nitrogen. As the gate insulating layer in contact with the top electrode layer 402, it is effective to provide a silicon nitride film using the above-described mixed gas. Also, by providing the gate insulating layer 404a with reduced defects in the film at a film thickness of 30 0 nm or more and 400 nm or less, the breakdown voltage of the gate insulating layer 404 can be set to 300 V or higher.

[0072] On the other hand, the gate insulating layer 404b formed without ammonia in the source gas can be made into a film with a lower hydrogen concentration compared to the gate insulating layer 404a. By providing such a film in a manner in contact with the oxide semiconductor layer 408, the incorporation of hydrogen from the gate insulating layer 404b into the oxide semiconductor layer 408 can be reduced. Further, the gate insulating layer 404b also functions as a barrier film that suppresses the incorporation of hydrogen or hydrogen compounds contained in the gate insulating layer 404a into the oxide semiconductor layer 408.

[0073] As the gate insulating layer 404, by laminating a thick film gate insulating layer 404a with reduced defects in the film and a gate insulating layer 404b with a reduced hydrogen concentration, while improving the breakdown voltage, the diffusion of impurities such as hydrogen into the oxide semiconductor layer 408 can be suppressed. Therefore, electrostatic breakdown of the transistor including the gate insulating layer 404 can be suppressed, and the electrical characteristics can be stabilized.

[0074] Next, an oxide semiconductor layer is formed on the gate insulating layer 404b and processed into an island shape by an etching process to form the oxide semiconductor layer 408 (see FIG. 2(B)).

[0075] The oxide semiconductor layer 408 may have an amorphous structure or a crystalline structure. After film formation When the oxide semiconductor layer has an amorphous structure, heat treatment may be applied in subsequent manufacturing processes to obtain a crystalline oxide semiconductor layer 408. The temperature of the heat treatment for crystallizing the amorphous oxide semiconductor layer is 250°C or higher and 700°C or lower, preferably 400°C or higher, more preferably 500°C or higher, and even more preferably 550°C or higher. Note that this heat treatment can also be combined with other heat treatments in the manufacturing process. The method for forming the oxide semiconductor layer 408 can be appropriately selected from sputtering methods, MBE (Molecular Beam Epitaxy) methods, CVD methods, pulsed laser deposition methods, ALD (Atomic

[0076] Layer Deposition) methods, etc. When forming the oxide semiconductor layer 408, it is preferable to reduce the hydrogen concentration contained in the film as much as possible. To reduce the hydrogen concentration, for example, when using a sputtering method for film formation, high-purity rare gases (typically argon), oxygen, and a mixed gas of rare gas and oxygen from which impurities such as hydrogen, water, water acid groups, or hydrides have been removed are appropriately used as the ambient gas supplied into the film formation chamber of the sputtering apparatus.

[0077] In addition, by introducing a sputtering gas from which hydrogen and moisture have been removed while removing the residual moisture in the film formation chamber to perform film formation, the hydrogen concentration of the formed oxide semiconductor layer can be reduced. To remove the residual moisture in the film formation chamber, it is preferable to use an adsorption-type vacuum pump, such as a cryopump, ion pump, or titanium sublimation pump. Alternatively, a turbo molecular pump with a cold trap added may also be used. A cryopump, for example, can be used.

[0078] Moreover, by introducing a sputtering gas from which hydrogen and moisture have been removed while removing the residual moisture in the film formation chamber to perform film formation, the hydrogen concentration of the formed oxide semiconductor layer can be reduced. To remove the residual moisture in the film formation chamber, it is preferable to use an adsorption-type vacuum pump, such as a cryopump, ion pump, or titanium sublimation pump. Alternatively, a turbo molecular pump with a cold trap added may also be used. A cryopump, for example, can be used. , compounds containing hydrogen atoms such as hydrogen molecules and water (H2O) (more preferably compounds containing carbon atoms as well), etc., have high exhaust capacity, so the concentration of impurities contained in the film formed in the film deposition chamber exhausted using a cryopump can be reduced. Since the exhaust capacity of compounds containing hydrogen atoms such as hydrogen molecules and water (H2O) (more preferably compounds containing carbon atoms as well) is high, the concentration of impurities contained in the film formed in the film deposition chamber evacuated using a cryopump can be reduced. The concentration of impurities contained in the film can be reduced.

[0079] Note that the gate insulating layer 404 and the oxide semiconductor layer are preferably formed continuously without opening to the atmosphere. By continuously forming the gate insulating layer 404 and the oxide semiconductor layer without opening to the atmosphere, the adhesion of hydrogen or hydrogen compounds (for example, adsorbed water, etc.) to the surface of the oxide semiconductor layer can be prevented, so that the incorporation of impurities can be suppressed. Note that it is preferable to continuously form the gate insulating layer 404 and the oxide semiconductor layer without opening to the atmosphere. By continuously forming the gate insulating layer 404 and the oxide semiconductor layer without opening to the atmosphere, the adhesion of hydrogen or hydrogen compounds (for example, adsorbed water, etc.) to the surface of the oxide semiconductor layer can be prevented, so that the incorporation of impurities can be suppressed. By continuously forming the gate insulating layer 404 and the oxide semiconductor layer without opening to the atmosphere, the adhesion of hydrogen or hydrogen compounds (for example, adsorbed water, etc.) to the surface of the oxide semiconductor layer can be prevented, so that the incorporation of impurities can be suppressed. The incorporation of impurities can be suppressed.

[0080] Also, when forming the oxide semiconductor layer by sputtering, the relative density (filling rate) of the metal oxide target used for film formation is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the formed film can be made into a dense film. The relative density (filling rate) of the metal oxide target used for film formation is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the formed film can be made into a dense film. The formed film can be made into a dense film.

[0081] Note that forming the oxide semiconductor layer with the substrate 400 held at a high temperature is also effective in reducing the impurity concentration that may be contained in the oxide semiconductor layer. The temperature at which the substrate 400 is heated may be 150°C or more and 450°C or less, preferably the substrate temperature may be 200°C or more and 350°C or less. Also, by heating the substrate at a high temperature during film formation, a crystalline oxide semiconductor layer can be formed. Note that forming the oxide semiconductor layer with the substrate 400 held at a high temperature is also effective in reducing the impurity concentration that may be contained in the oxide semiconductor layer. The temperature at which the substrate 400 is heated may be 150°C or more and 450°C or less, preferably the substrate temperature may be 200°C or more and 350°C or less. Also, by heating the substrate at a high temperature during film formation, a crystalline oxide semiconductor layer can be formed. A crystalline oxide semiconductor layer can be formed.

[0082] When applying a CAAC-OS film as the oxide semiconductor layer 408, as a method for obtaining the CAAC-OS film, for example, the film formation temperature is 200°C or more and 450°C or less, and the oxide semiconductor layer When applying a CAAC-OS film as the oxide semiconductor layer 408, as a method for obtaining the CAAC-OS film, for example, the film formation temperature is 200°C or more and 450°C or less, and the oxide semiconductor layer There is a method of forming a film and c-axis orienting it approximately perpendicular to the surface. Or, after forming an oxide semiconductor layer with a thin film thickness, heat treatment may be performed at 200 °C or higher and 700 °C or lower to c-axis orient it approximately perpendicular to the surface. Or, after forming a first layer with a thin film thickness, heat treatment may be performed at 200 °C or higher and 700 °C or lower, and then a second layer may be formed and c-axis oriented approximately perpendicular to the surface.

[0083] The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). In particular, it preferably contains indium and zinc (Zn). Further, as a stabilizer for reducing the variation in the electrical characteristics of a transistor using the oxide semiconductor, it preferably has gallium (Ga) in addition to them. Further, as a stabilizer, tin ( Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr) preferably has one or more of them.

[0084] Also, as another stabilizer, any one or more of lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), which are lanthanoids, may be included.

[0085] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn-based oxides, In-Mg-based oxides, In-Ga-based oxides, ternary metal oxides such as In-Ga-Zn-based oxides, In-Al-Zn-based oxides, In-Sn-Zn ​​Oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxide s, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides , In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn oxides, In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, which are oxides of quaternary metals , In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-S n-Hf-Zn oxides, In-Hf-Al-Zn oxides can be used.

[0086] For example, In-Ga-Zn oxides mean oxides having In, Ga, and Zn as main components , and the ratio of In, Ga, and Zn is not limited. Also, other metal elements may be contained.

[0087] Also, as the oxide semiconductor, InMO3(ZnO) m (m > 0 and m is not an integer) represented materials may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Also, as the oxide semiconductor, In2SnO 5(ZnO) (n > 0 and n is an integer) represented materials may be used. n

[0088] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Ga:Z n = 2:2:1 (= 2 / 5:2 / 5:1 / 5), or In:Ga:Zn = 3:1:2 An In-Ga-Zn oxide having an atomic ratio of (=1 / 2:1 / 6:1 / 3) and an oxide in the vicinity of its composition can be used. Alternatively, In:Sn:Zn = 1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (=1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (=1 / 4:1 / 8:5 / 8) atomic ratio In-Sn -Zn oxides and oxides in the vicinity of their compositions may be used.

[0089] However, transistors using indium-containing oxide semiconductors are not limited to these, and those having an appropriate composition according to the required electrical characteristics (field-effect mobility, threshold value, variation, etc.) may be used. Also, in order to obtain the required electrical characteristics, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. appropriate.

[0090] For example, in a transistor using an In-Sn-Zn oxide semiconductor, a relatively high field-effect mobility can be obtained relatively easily. However, even in a transistor using an In-Ga-Zn oxide semiconductor, the field-effect mobility can be increased by reducing the defect density in the bulk.

[0091] Incidentally, for example, the composition of an oxide having an atomic ratio of In:Ga:Zn = a:b:c (a + b + c = 1) is in the vicinity of the composition of an oxide having an atomic ratio of In:Ga:Zn = A:B:C (A + B + C = 1) means that a, b, and c satisfy (a - A) 2 +(b - B) 2 + (c - C) 2 ≦r 2 For r, for example, 0.05 may be used. ​​​​​​​The same applies to other oxides.

[0092] In addition, it is preferable to perform a heat treatment for removing excess hydrogen (including water and hydroxyl groups) contained in the film with respect to the oxide semiconductor layer 408. The temperature of the heat treatment is set to 300°C or higher and 700°C or lower, or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or in a nitrogen atmosphere or the like. By this heat treatment, hydrogen containing impurities that impart n-type conductivity can be removed.

[0093] Note that the heat treatment for dehydration or dehydrogenation may be performed at any timing in the manufacturing process of the transistor as long as it is after the formation of the oxide semiconductor layer. Also, the heat treatment for dehydration or dehydrogenation may be performed multiple times or may be combined with other heat treatments.

[0094] In the heat treatment, it is preferable that nitrogen or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Or, the purity of nitrogen or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99. 99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0095] Also, after heating the oxide semiconductor layer 408 by heat treatment, while maintaining the heating temperature or slowly cooling from that heating temperature, high-purity oxygen gas, high-purity nitrous oxide gas, or ultra-dry ether is introduced into the same furnace. When measured using a dew point meter of the CRDS (Cavity Ring Down Laser Spectroscopy) method, the moisture content is 20 ppm (dew point conversion -55°C) or lower, preferably 1 ppm or lower, more It may be introduced into air preferably at 10 ppb or less. It is preferable that oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or nitrous oxide gas is 1 ppm or less, preferably 0.1 ppm or less). By supplying oxygen, which is the main component material constituting the oxide semiconductor that has been simultaneously reduced by the step of removing impurities by dehydration or dehydrogenation treatment due to the action of oxygen gas or nitrous oxide gas, the oxide semiconductor layer can be purified to a high purity and made i-type (intrinsic).

[0096] Also, since there is a possibility that oxygen, which is the main component material constituting the oxide semiconductor, is simultaneously desorbed and reduced by dehydration or dehydrogenation treatment, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film.

[0097] By introducing oxygen into the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film, the oxide semiconductor layer can be purified to a high purity and made i-type (intrinsic). A transistor having a highly purified and i-type (intrinsic) oxide semiconductor has its electrical characteristic variations suppressed and is electrically stable.

[0098] When introducing oxygen into the oxide semiconductor layer 408, it may be introduced directly into the oxide semiconductor layer 408, or may be introduced into the oxide semiconductor layer 408 through an insulating layer formed later. As a method of introducing oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions), ​​​​​​​​​​​ , ion implantation method, ion doping method, plasma immersion ion implantation method, plasma treatment In addition, a gas containing oxygen can be used for the oxygen introduction process. Gases containing oxygen include oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, and nitrogen monoxide. Carbon or the like can be used. In addition, in the oxygen introduction process, a rare gas can be added to the gas containing oxygen. may be included.

[0099] For example, when oxygen ions are implanted into the oxide semiconductor layer 408 by an ion implantation method, the dose 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 The following would suffice.

[0100] The supply of oxygen to the oxide semiconductor layer 408 can be performed at the timing after the oxide semiconductor layer is formed. The oxygen introduction may be performed multiple times.

[0101] Next, a conductive film is formed over the oxide semiconductor layer 408 and processed to form a source electrode layer 410. A drain electrode layer 410b is formed (see FIG. 2C).

[0102] The source electrode layer 410a and the drain electrode layer 410b are made of, for example, Al, Cr, Cu, A metal film containing an element selected from the group consisting of Ta, Ti, Mo, and W, or a film containing the above-mentioned elements as components. Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) that can In addition, Ti, M, etc. can be applied to the upper or lower side or both sides of the metal film such as Al, Cu, etc. High melting point metal films such as O and W, or metal nitride films of these metals (titanium nitride film, molybdenum nitride film, etc.) A source electrode layer 410a may be formed by laminating a tungsten nitride film and a tungsten nitride film. The source electrode layer 410a and the drain electrode layer 410b may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium tin oxide (In2O3-SnO2), indium zinc oxide (In 2O3-ZnO), or those obtained by adding silicon oxide to these metal oxide materials can be used.

[0103] Further, as the source electrode layer 410a and the drain electrode layer 410b, an In-Ga- Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, an I n-Zn-O film containing nitrogen, an Sn-O film containing nitrogen, an In-O film containing nitrogen, or other metal nitride films can be used. Since these films contain the same constituent elements as the oxide semiconductor layer 408, the interface with the oxide semiconductor layer 408 can be stabilized. For example, as the source electrode layer 410a and the drain electrode layer 410b, a laminated structure of an In-Ga-Zn-O film containing nitrogen and a tungsten film can be applied from the side in contact with the oxide semiconductor layer 408.

[0104] Next, an insulating layer 414 is formed so as to cover the source electrode layer 410a, the drain electrode layer 410b, and the exposed oxide semiconductor layer 4 08 (see Fig. 2(D)).

[0105] The insulating layer 414 can be formed by a plasma CVD method or a sputtering method, and a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. However, the insulating layer 414 is a layer containing a silicon film containing nitrogen, more preferably a silicon nitride film. ​​​​​​​By this, electrostatic damage to the semiconductor device during or after the manufacturing process of the semiconductor device can be prevented. This is preferable because it is possible to further reduce the

[0106] After the insulating layer 414 is formed, heat treatment may be performed. The temperature of the heat treatment is preferably 200° C. or higher. For example, 220° C. may be used.

[0107] In this manner, the transistor 300 of this embodiment can be formed.

[0108] FIG. 3A illustrates a configuration example of a transistor 310. The transistor 310 illustrated in FIG. The transistor is a gate electrode provided on a substrate 400 having an insulating surface, similar to the transistor 300 in FIG. A gate electrode layer 402, a gate insulating layer 404a on the gate electrode layer 402, and a gate insulating layer 4 A gate insulating layer 404 including a gate electrode layer 404b is provided on the gate insulating layer 404b. An oxide semiconductor layer 408 overlapping with the oxide semiconductor layer 402 and a solder joint electrically connected to the oxide semiconductor layer 408 The source electrode layer 410a and the drain electrode layer 410b are also included. The insulating layer 414 covers the oxide semiconductor layer 408 and the drain electrode layer 410b. It may be a component of the transistor 310.

[0109] The transistor 310 is a transistor having a stacked structure in that the oxide semiconductor layer 408 has a stacked structure. That is, the oxide semiconductor layer 408 in the transistor 310 is The oxide semiconductor layer 408a in contact with the gate insulating layer 404 and the oxide semiconductor layer 414 in contact with the insulating layer 414 are and a conductor layer 408b.

[0110] Note that the components of the transistor 310 other than the oxide semiconductor layer 408 are the same as those of the transistor It is the same as 300, and the description of the transistor 300 can be referred to.

[0111] The oxide semiconductor layer 408a and the oxide semiconductor layer 408b included in the oxide semiconductor layer 408 Preferably have the same constituent elements and different compositions. The oxide semiconductor layer 408a and the oxide semiconductor layer 408b are formed as oxide semiconductor layers containing indium and gallium When doing so, the content ratios of indium and gallium in the oxide semiconductor layer 408a on the side close to the gate electrode layer 402 (channel side) may be In>Ga. Also, the content ratios of indium and gallium in the oxide semiconductor layer 408b on the side far from the gate electrode layer 402 (back channel side) may be In≦Ga. side (back channel side) of the oxide semiconductor layer 408b of indium and gallium content ratio of I n≦Ga is good.

[0112] In an oxide semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction. Since increasing the indium content tends to increase the overlap of s orbitals, oxides with a composition of In> Ga have higher mobility compared to oxides with a composition of In≦Ga. Also, since Ga has a larger oxygen deficiency formation energy and is less likely to generate oxygen deficiency compared to In, oxides with a composition of In≦Ga are more stable compared to oxides with a composition of In>Ga. characteristics.

[0113] By applying an oxide semiconductor with a composition of In>Ga to the channel side and an oxide semiconductor with a composition of In≦ Ga to the back channel side, it is possible to further improve the mobility and reliability of the transistor. For example, the atomic ratio of the oxide semiconductor layer 408a can be In:G a:Zn = 3:1:2, and the atomic ratio of the oxide semiconductor layer 408b can be In:Ga:Zn = 1 :1:1. is also acceptable.

[0114] The oxide semiconductor layers 408a and 408b are formed using oxide semiconductors having different crystallinity. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor, A conductor, an amorphous oxide semiconductor, or a CAAC-OS may be appropriately combined. However, amorphous oxide semiconductors are prone to absorbing impurities such as hydrogen, and oxygen vacancies occur. Therefore, the oxide semiconductor layer 408a on the channel side is easily converted to an n-type oxide semiconductor layer. It is preferable to use a crystalline oxide semiconductor such as AC-OS.

[0115] In addition, when an amorphous oxide semiconductor is used for the oxide semiconductor layer 408b on the back channel side, The source electrode layer 410a and the drain electrode layer 410b are formed by etching, which causes oxygen deficiency. The oxide semiconductor layer 408b is a crystalline oxide semiconductor. It is preferred to apply

[0116] Note that the oxide semiconductor layer 408 can be formed by a sputtering method. If the deposition target contains indium, the generation of particles during deposition can be reduced. Therefore, the oxide semiconductor layer 408a containing indium and the oxide semiconductor layer 408b containing indium can be formed. It is more preferable to use a nitride semiconductor layer 408b.

[0117] Note that the thickness of a region of the oxide semiconductor layer 408b in contact with the insulating layer 414 is set to be equal to or larger than the source potential. The thickness may be smaller than that of a region in contact with the electrode layer 410a and the drain electrode layer 410b. For example, when a conductive film to be the source electrode layer 410a and the drain electrode layer 410b is processed, Alternatively, the source electrode layer 410a and the drain electrode layer 410 may be removed by etching the portions of the By performing an etching process on the exposed region of the oxide semiconductor layer 408b after forming b, a region with a small film thickness can be formed. By reducing the film thickness of the region that functions as the channel formation region of the transistor 310, the resistance of the region in contact with the source electrode layer 410a and the drain electrode layer 410b can be reduced as compared with the channel formation region. Thus, the contact resistance with the source electrode layer 410a and the drain electrode layer 410b can be reduced.

[0118] FIG. 3(B) shows a configuration example of the transistor 320. The transistor 320 shown in FIG. 3(B) is, similar to the transistor 300 in FIG. 1, a gate electrode layer 402 provided on a substrate 400 having an insulating surface, a gate insulating layer 404a and a gate insulating layer 404 including a gate insulating layer 404b on the gate electrode layer 402, an oxide semiconductor layer 408 provided on the gate insulating layer 404b and overlapping the gate electrode layer 402, a source electrode layer 410a and a drain electrode layer 410b electrically connected to the oxide semiconductor layer 408, and includes an insulating layer 414 that covers the source electrode layer 410a

[0119] and the drain electrode layer 410b and is in contact with the oxide semiconductor layer 408. The transistor 320 is different from the transistor 300 in that the insulating layer 414 includes an insulating layer 414a in contact with a part of the oxide semiconductor

[0120] layer 408 and an insulating layer 414b in contact with the insulating layer 414a. The insulating layer 414a can have the same configuration as the gate insulating layer 404b. By providing the insulating layer 414a, the incorporation of hydrogen or a hydrogenTherefore, the electrical characteristics of the transistor can be further stabilized.

[0121] Further, the insulating layer 414b can have the same configuration as the gate insulating layer 404a. . By providing the insulating layer 414b, electrostatic breakdown of the semiconductor device during the manufacturing process or after formation can be further reduced.

[0122] Note that other components of the transistor 320 can have the same configuration as the transistor 300, and the description of the transistor 300 can be referred to.

[0123] FIG. 3(C) shows a configuration example of the transistor 330. The transistor 330 shown in FIG. 3(C) is, like the transistor 300 in FIG. 1, provided on a substrate 400 having an insulating surface, a gate electrode layer 402, a gate insulating layer 404 on the gate electrode layer 402, an oxide semiconductor layer 408 in contact with the gate insulating layer 404 and overlapping the gate electrode layer 402, and a source electrode layer 410a and a drain electrode layer 410b electrically connected to the oxide semiconductor layer 408. Further, an insulating layer 414 covering the source electrode layer 410a and the drain electrode layer 410b and in contact with the oxide semiconductor layer 408 may be a component of the transistor 330.

[0124] The transistor 330 is different from the transistor 300 in that the gate insulating layer 404 includes a gate insulating layer 404c in contact with the gate electrode layer 402, a gate insulating layer 404a in contact with the gate insulating layer 404c, and a gate insulating layer 404b on the gate insulating layer 404a. In the transistor 330, the configuration other than the gate insulating layer 404 is the same as that of the transistor 300, and the description of the transistor 300 can be referred to. ​​​​​​​​​​​

[0125] In this embodiment, silicon nitride films are used as the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 40 4b, and each gate insulating layer is continuously formed by plasma CVD method. Specifically, after supplying a mixed gas of silane (SiH4) and nitrogen (N2) to form a silicon nitride film that becomes the gate insulating layer 404c, the supply gas is switched to a mixed gas of silane (Si H4), nitrogen (N2), and ammonia (NH3) to form a silicon nitride film that becomes the gate insulating layer 404a. Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2) to form a silicon nitride film that becomes the gate insulating layer 404b.

[0126] The ammonia in the film formation atmosphere and in the film of the gate insulating layer 404 c formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) can be reduced compared to the gate insulating layer 404a formed by supplying at least a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3). Ammonia becomes a ligand of a metal complex due to the action of the lone pair of electrons on the nitrogen atom. Therefore, for example, when copper is used as the gate electrode layer 402, if a gate insulating layer with a high ammonia content is provided in a manner that contacts the gate electrode layer, copper may diffuse into the gate insulating layer by the reaction shown in the following formula (1 ). )

[0127]

Equation

[0128] In the transistor 330 shown in FIG. 3(C), the ammonia is at least less than that in the gate insulating layer 404a. ​​​​​A gate insulating layer 404c with a low content of monia is provided in a manner in contact with the gate electrode layer 402. By doing so, it is possible to suppress the diffusion of the material (for example, copper) of the gate electrode layer 402 into the gate insulating layer 404. That is, the gate insulating layer 404c can function as a barrier film against the metal material constituting the gate electrode layer 402. By providing the gate insulating layer 404c, the reliability of the transistor can be further improved.

[0129] Note that the configurations of the gate insulating layer 404a and the gate insulating layer 404b included in the transistor 330 can be the same as those of the transistor 310. By including the gate insulating layer having the above-described configuration, electrostatic breakdown of the transistor can be prevented, and stable electrical characteristics can be imparted to the transistor, making it possible to obtain a highly reliable semiconductor device.

[0130] The film thickness of the gate insulating layer 404c is 30 nm or more and 100 nm or less, preferably 30 nm or more and 50 nm or less. Also, as described above, the film thickness of the gate insulating layer 404a provided as a measure against electrostatic breakdown of the transistor is preferably 300 nm or more and 400 nm or less, and the film thickness of the gate insulating layer 404b that functions as a barrier film for preventing the diffusion of hydrogen into the oxide semiconductor layer 408 is preferably 25 nm or more and 150 nm or less. However, it is preferable to appropriately adjust the film thickness of each gate insulating layer so that the film thickness of the gate insulating layer 404 (the total of the film thicknesses of the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 404b) is 355 nm or more and 550 nm or less.

[0131] Fig. 3(D) shows a configuration example of the transistor 340. The transistor 340 shown in Fig. 3(D) ​​​​​​​​​​​​The gate insulating layer 404 (more specifically, the gate insulating layer 404b) and the oxide semiconductor layer 4 3C in that the gate insulating layer 407 is provided between the first and second transistors 330 and 330. In the transistor 340, the components other than the gate insulating layer 407 are the same as those of the transistor 330, the description of the transistor 330 can be referred to.

[0132] The gate insulating layer 407 in contact with the oxide semiconductor layer 408 may be a silicon oxide film, a gallium oxide film, or the like. It is preferable to use an insulating layer containing oxygen, such as an aluminum film or an aluminum oxide film. The insulating layer 407 includes a region that contains oxygen in excess of the stoichiometric composition (oxygen excess region). When the insulating layer in contact with the oxide semiconductor layer 408 includes an oxygen excess region, Oxygen can be supplied to the oxide semiconductor layer 408. This is because it is possible to prevent oxygen from being released and to compensate for oxygen vacancies. To provide an oxygen excess region in the insulating layer 407, for example, the gate insulating layer 407 is etched in an oxygen atmosphere. Alternatively, oxygen may be introduced into the gate insulating layer 407 after the film formation to form an oxygen-excess region. A region may be formed.

[0133] The thickness of the gate insulating layer 407 is set to 25 nm or more and 100 nm or less. The thickness of 404 (gate insulating layer 404c, gate insulating layer 404a, and gate insulating layer 404b The total thickness of the gate insulating layer 407 and the gate insulating layer 408 is set to 355 nm or more and 550 nm or less. It is preferable to appropriately adjust the film thickness of each gate insulating layer so that the thickness is equal to or less than m.

[0134] The transistors shown in FIG. 1 and FIG. 3 have partially different configurations, but the present invention One aspect is not particularly limited, and various combinations are possible.

[0135] The transistor shown in this embodiment has, as a gate insulating layer, a silicon film containing nitrogen with reduced film defects in a thick film (for example, a film thickness of 300 nm) on the gate electrode layer side and a silicon film containing nitrogen with a reduced hydrogen concentration, and has a laminated structure. Therefore, the transistor has suppressed fluctuations in electrical characteristics and suppressed electrostatic breakdown. By including such a transistor, a highly reliable semiconductor device can be provided with a high yield.

[0136] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. It can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0137] (Embodiment 2) A semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistor shown in Embodiment 1. Also, part or all of the drive circuit including the transistor can be integrally formed on the same substrate as the pixel portion to form a system-on-panel. In FIG. 4(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the substrate 4001 and is sealed by the substrate 4006. In FIG. 4(A)

[0138] In the region different from the region surrounded by the sealing material 4005 on the substrate 4001, an IC chip, or a scanning line drive circuit 4004 and a signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate are mounted. Also, various signals given to the pixel portion 4002 through the signal line drive circuit 4003 and the scanning line drive circuit 4004 and The potential is supplied from FPC (Flexible printed circuit) 4018a and 4 018b.

[0139] In FIGS. 4(B) and 4(C), a sealing material 4005 is provided so as to surround a pixel portion 4002 provided on a substrate 4001 and a scanning line driving circuit 4004. Also, a substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with a display element by the substrate 4001, the sealing material 4005, and the substrate 4006. In FIGS. 4(B) and 4(C), in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, an IC chip, or a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is mounted. In FIGS. 4(B) and 4(C), various signals and potentials applied to the pixel portion 4002 through the signal line driving circuit 4003 and the scanning line driving circuit 4004 are supplied from the FPC 4018. Also, in FIGS. 4(B) and 4(C), an example in which the signal line driving circuit 4003 is separately formed and mounted on the substrate 4001 is shown, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or only a part of the scanning line driving circuit may be

[0140] separately formed and mounted. Note that the connection method of the separately formed driving circuit is not particularly limited, and COG (Chip On Glass) method, wire bonding method, or TAB (Tape A

[0141] Note that the connection method of the separately formed driving circuit is not particularly limited, and COG (Chip On Glass) method, wire bonding method, or TAB (Tape A ​utomated Bonding) method can be used. Figure 4(A) shows an example of implementing the signal line driving circuit 4003 and the scanning line driving circuit 4004 by the C OG method, Figure 4(B) shows an example of implementing the signal line driving circuit 4003 by the COG method, and Figure 4(C ) shows an example of implementing the signal line driving circuit 4003 by the TAB method.

[0142] Note that the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted thereon. That is, the display device described in this specification refers to an image display device, a display device, or a light source (including a lighting device). In addition, not only the panel in a state where the display element is sealed, but also a module to which a connector, for example, an FP C or TCP is attached, a module in which a printed wiring board is provided at the tip of the TCP , or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG method shall all be included in the display device.

[0143] In addition, the pixel portion and the scanning line driving circuit provided on the substrate have a plurality of transistors, and the transistors shown in Embodiment 1 can be applied.

[0144] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element ( also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage within its scope. Specifically, it includes inorganic EL (Electro Lu minescence), organic EL, etc. In addition, a display medium such as an electronic ink display device (electronic paper per) whose contrast changes by an electric action can also be applied. .

[0145] A form of the semiconductor device will be described with reference to FIGS. 4 to 6. FIG. 6 corresponds to a cross-sectional view taken along the line M -N in FIG. 4(B).

[0146] As shown in FIGS. 4 and 6, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 4016, and the connection terminal electrodes 4015 and the terminal electrodes 4016 are electrically connected via an anisotropic conductive layer 4019 to the terminals of the FPCs 4018, 4018b which they have.

[0147] The connection terminal electrode 4015 is formed of the same conductive layer as the first electrode layer 4034, and the terminal electrode 4 016 is formed of the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4010, 4011.

[0148] Also, the pixel portion 4002 provided on the substrate 4001 and the scanning line drive circuit 4004 each have a plurality of transistors. In FIG. 6, the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scanning line drive circuit 4004 are illustrated. In FIG. 6(A ) an insulating layer 4032 is provided over the transistors 4010, 4011, and in FIG. 6(B) an insulating layer 4021 which functions as a planarizing insulating layer is further provided.

[0149] As the transistors 4010, 4011, the transistors shown in Embodiment 1 can be applied. In this embodiment, an example in which transistors having the same structure as the transistor 300 shown in Embodiment 1 are applied is shown. The transistors 4010, 4011 are transistors having a bottom gate structure.

[0150] ​​​​​The transistors 4010 and 4011 have a thick film (for example, a thickness of The gate insulating layer 402 includes a silicon film containing nitrogen with reduced defects in the film (300 nm). 0b is a transistor having a silicon film containing nitrogen with a reduced hydrogen concentration. Therefore, the transistors 4010 and 4011 are suppressed in terms of fluctuation in electrical characteristics and are less susceptible to electrostatic breakdown. It is suppressed.

[0151] In addition, the oxide semiconductor layer of the transistor 4011 for the driver circuit overlaps with a channel formation region of the oxide semiconductor layer. A conductive layer may be further provided at a position overlapping with the channel formation region of the oxide semiconductor layer. By providing the transistor 4011 at a position closer to the threshold voltage Vth, the amount of change in the threshold voltage of the transistor 4011 can be further reduced. In addition, the conductive layer can be electrically connected to the gate electrode layer of the transistor 4011. It may be the same or different and may also function as the second gate electrode layer. The potential of the conductive layer may be in a floating state.

[0152] The conductive layer also shields the external electric field, i.e., prevents the external electric field from reaching the internal (including the transistor) It also has a function (particularly an electrostatic shielding function against static electricity) to prevent the electrical resistance of the device from acting on other components (including the circuitry). The shielding function of the conductive layer prevents the transistor from being electrically damaged by external electric fields such as static electricity. Fluctuations in characteristics can be prevented.

[0153] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display an image. can be used.

[0154] Fig. 6(A) shows an example of a liquid crystal display device using a liquid crystal element as a display element. In Fig. 6(A), the liquid crystal element 4013 includes a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer 4008. Insulating layers 4 038 and 4033 that function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the substrate 4006 side, and the first electrode layer 4034 and the second electrode layer 4031 are stacked via the liquid crystal layer 4008 to form a structure.

[0155] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Note that a spherical spacer may be used. When a liquid crystal element is used as the display element, thermotropic liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials may be low molecular weight compounds or high molecular weight compounds. These liquid crystal materials (liquid crystal compositions) exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

[0156] Also, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008, the first electrode layer 4034, and the second electrode layer 4031 have a structure in which they are in contact with each other. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. The blue phase can be expressed by using a liquid crystal composition in which a liquid crystal and a chiral agent are mixed. Also, blue

[0157] In order to widen the temperature range in which the phase appears, a polymerizable monomer is added to a liquid crystal composition that exhibits a blue phase and a polymerization initiator or the like are added, and a process for polymer stabilizing is performed to form a liquid crystal layer can also be achieved. The liquid crystal composition that exhibits a blue phase has a short response time and is optically isotropic, so alignment treatment is unnecessary, and the viewing angle dependence is small. Also, since an alignment film does not need to be provided, rubbing treatment is also unnecessary, so electrostatic breakdown caused by rubbing treatment can be prevented and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0158] Also, the specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. Note that the value of the specific resistance in this specification is the value measured at 20°C.

[0159] The size of the holding capacitance provided in the liquid crystal display device is set so that it can hold charges for a predetermined period considering the leakage current etc. of the transistor arranged in the pixel portion. The size of the holding capacitance may be set in consideration of the off-current etc. of the transistor. By using the transistor having an oxide semiconductor layer disclosed in this specification, it is sufficient to provide a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance for each pixel.

[0160] The transistor using the oxide semiconductor layer disclosed in this specification can control the current value in the off state (off-current value) to be low. Therefore, the holding time of an electrical signal such as an image signal ​​It can be lengthened, and the writing interval can also be set to be long. Therefore, the frequency of the refresh operation can be reduced, and thus the effect of suppressing power consumption is achieved.

[0161] In addition, the transistor using the oxide semiconductor layer disclosed in this specification has a relatively high field effect mobility, so high-speed driving is possible. For example, by using such a transistor in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the drive circuit portion can be formed on the same substrate. Also, in the pixel portion as well, by using such a transistor, a high-quality image can be provided.

[0162] Liquid crystal display devices can use TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS (Fringe Field Swit ching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq uid Crystal) mode, etc.

[0163] Moreover, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. Examples of the vertical alignment mode include, but are not limited to, for example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode ​ 、 etc., the ASV (Advanced Super View) mode can be used. It can also be applied to a VA type liquid crystal display device. A VA type liquid crystal display device is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. A VA type liquid crystal display device is a method in which liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. Also, pixels can be divided into several regions (sub-pixels), and a multi-domain or multi-domain design can be used, in which the molecules are arranged to be tilted in different directions. This is called the multi-domain or multi-domain design method. can be used.

[0164] Also, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and a reflection prevention member are appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source. board may be used. Also, a backlight, a side light, etc. may be used as the light source. may be used.

[0165] Also, as the display method in the pixel portion, a progressive method, an interlace method, etc. can be used. Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white) or a color obtained by adding one or more colors such as yellow, cyan, and magenta to RGB. Note that the size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device, and can also be applied to a monochrome display device. can also be applied.

[0166] Also, as a display element included in the display device, a light-emitting element using electroluminescence can be applied. A light-emitting element that utilizes electroluminescence is distinguished by whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is an organic E L element, and the latter is called an inorganic EL element.

[0167] In an organic EL element, by applying a voltage to the light-emitting element, electrons and holes are respectively injected into a layer containing a light-emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, causing the light-emitting organic compound to form an excited state and emit light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. In this embodiment, an example of using an organic EL element as the light-emitting element is shown.

[0168] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. A dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. A thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers, and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used as the light-emitting element for explanation.

[0169] For the light-emitting element, at least one of the pair of electrodes may be light-transmissive in order to extract light emission. Thus, a transistor and a light-emitting element are formed on a substrate, and light emission is extracted from the surface opposite to the substrate for surface emission, light emission is extracted from the surface on the substrate side for bottom emission, or light emission is extracted from both the substrate side and the side opposite to the substrate ​There is a light-emitting element with a double-sided injection structure for extracting light from the surface, and any light-emitting element with an injection structure can be applied. It can be applied.

[0170] Figs. 5(A) and (B) and Fig. 6(B) show examples of light-emitting devices using a light-emitting element as a display element. .

[0171] Fig. 5(A) is a plan view of the light-emitting device, and the cross-sections taken along the dashed-dotted lines S1-T1, S2-T2, , and S3-T3 in Fig. 5(A) correspond to Fig. 5(B). In the plan view of Fig. 5(A), the electroluminescent layer 542 and the second electrode layer 543 are omitted and not shown.

[0172] The light-emitting device shown in Fig. 5 has a transistor 510, a capacitor element 520, and a wiring layer crossing portion 530 on a substrate 500, and the transistor 510 is electrically connected to the light-emitting element 540. Note that Fig. 5 is a bottom emission type light-emitting device that extracts light from the light-emitting element 540 through the substrate 500.

[0173] As the transistor 510, the transistor shown in Embodiment 1 can be applied. In this embodiment, an example of applying a transistor having the same structure as the transistor 300 shown in Embodiment 1 is shown. The transistor 510 is a transistor with a bottom gate structure. It is a transistor.

[0174] The transistor 510 includes a gate electrode layer 511a, 511b, a gate insulating layer 502a, 502 b, 502c including a gate insulating layer 502, an oxide semiconductor layer 512, and a conductive layer 513a, 513b that functions as a source electrode layer or a drain electrode layer. Further, an insulating layer 525 is formed on the transistor 510. It is formed.

[0175] The capacitive element 520 includes a conductive layer 521a, 521b, a gate insulating layer 502, an oxide semiconductor layer 5 22, and a conductive layer 523. The conductive layers 521a, 521b and the conductive layer 523 sandwich the gate insulating layer 502 and the oxide semiconductor layer 522 to form a capacitance.

[0176] The wiring layer intersection 530 is at the intersection of the gate electrode layers 511a, 511b and the conductive layer 533 where the gate electrode layers 511a, 511b and the conductive layer 533 intersect with the gate insulating layer 502 interposed therebetween.

[0177] In this embodiment, a titanium film with a thickness of 30 nm is used as the gate electrode layer 511a and the conductive layer 521a, and a copper thin film with a thickness of 200 nm is used as the gate electrode layer 511b and the conductive layer 521b. Therefore, the gate electrode layer has a laminated structure of a titanium film and a copper thin film.

[0178] The transistor 510 includes a silicon film containing nitrogen that functions as a barrier film of copper with a reduced ammonia content as the gate insulating layer 502c, includes a silicon film containing nitrogen with a reduced film thickness (for example, a film thickness of 300 nm) of the film in the gate insulating layer 502a, and has a silicon film containing nitrogen with a reduced hydrogen concentration as the gate insulating layer 502b. It is a transistor. With such a configuration, the electrical characteristics of the transistor 510 can be improved, and electrostatic breakdown of the transistor 510 can be prevented. Therefore, it is possible to provide a highly reliable semiconductor device with a high yield. film (e.g., film thickness 300 nm) having reduced film defects, and a silicon film containing nitrogen with a reduced hydrogen concentration as the gate insulating layer 502b. It is a transistor. By having such a configuration, the electrical characteristics of the transistor 510 can be improved, and electrostatic breakdown of the transistor 510 can be prevented. Therefore, it is possible to provide a highly reliable semiconductor device with a high yield. By having such a configuration, the electrical characteristics of the transistor 510 can be improved, and electrostatic breakdown of the transistor 510 can be prevented. Therefore, it is possible to provide a highly reliable semiconductor device with a high yield. Moreover, electrostatic breakdown of the transistor 510 can be prevented. Therefore, it is possible to provide a highly reliable semiconductor device with a high yield. Moreover, electrostatic breakdown of the transistor 510 can be prevented. Therefore, it is possible to provide a highly reliable semiconductor device with a high yield.

[0179] An In-Ga-Zn-O film with a thickness of 25 nm is used as the oxide semiconductor layers 512, 522.

[0180] ​ On the transistor 510, the capacitive element 520, and the wiring layer intersection 530, an interlayer insulating layer 504 is formed, and a color filter layer 505 is provided in a region that overlaps with the light-emitting element 540 on the interlayer insulating layer 504. An insulating layer 506 that functions as a planarizing insulating layer is provided on the interlayer insulating layer 504 and the color filter layer 505. On the interlayer insulating layer 504 and the color filter layer 505, an insulating layer 506 that functions as a planarizing insulating layer is provided.

[0181] On the insulating layer 506, a light-emitting element 540 including a stacked structure in which a first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are stacked in this order is provided. The light-emitting element 540 and the transistor 510 are electrically connected by the first electrode layer 541 and the conductive layer 513a being in contact with each other at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reach the conductive layer 513a. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening. On the insulating layer 506, a light-emitting element 540 including a stacked structure in which a first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are stacked in this order is provided. The light-emitting element 540 and the transistor 510 are electrically connected by the first electrode layer 541 and the conductive layer 513a being in contact with each other at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reach the conductive layer 513a. The light-emitting element 540 and the transistor 510 are electrically connected by the first electrode layer 541 and the conductive layer 513a being in contact with each other at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reach the conductive layer 513a. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening.

[0182] For the insulating layer 506, a photosensitive acrylic film with a film thickness of 1500 nm can be used, and for the partition wall 507, a photosensitive polyimide film with a film thickness of 1500 nm can be used.

[0183] As the color filter layer 505, for example, a colored light-transmissive resin can be used. As the colored light-transmissive resin, a photosensitive or non-photosensitive organic resin can be used, but using a photosensitive organic resin layer can reduce the number of resist masks, so the process is simplified and preferable. As the colored light-transmissive resin, a photosensitive or non-photosensitive organic resin can be used, but using a photosensitive organic resin layer can reduce the number of resist masks, so the process is simplified and preferable. Using a photosensitive organic resin layer can reduce the number of resist masks, so the process is simplified and preferable.

[0184] Colored refers to colors excluding achromatic colors such as black, gray, and white, and the color filter layer is formed of a material that transmits only the colored light that is colored. As the colored color, red, green, blue, etc. can be used. The color filter layer is formed of a material that transmits only the colored light that is colored. As the colored color, red, green, blue, etc. can be used. ​​​​​It is possible. Also, cyan, magenta, yellow (yellow), etc. may be used. Coloring Only transmitting the colored light that has been colored means that the transmitted light in the color filter layer has a peak at the wavelength of the colored light. The color filter layer may appropriately control the optimal film thickness in consideration of the relationship between the concentration of the coloring material to be included and the light transmittance. For example, the film thickness of the color filter layer 505 may be 1500 nm or more and 2000 nm or less.

[0185] In the light-emitting device shown in FIG. 6(B), the light-emitting element 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The configuration of the light-emitting element 4513 is a stacked structure of the first electrode layer 4034, the electroluminescent layer 4511, and the second electrode layer 4031, but is not limited to the illustrated configuration. The configuration of the light-emitting element 4513 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4513, etc.

[0186] The partition walls 4510 and 507 are formed using an organic insulating material or an inorganic insulating material. In particular, using a photosensitive resin material, an opening is formed on the first electrode layers 4034 and 541, and it is preferably formed so that the side walls of the opening become inclined surfaces formed with a continuous curvature.

[0187] The electroluminescent layers 4511 and 542 may be configured either by a single layer or by a plurality of layers laminated together.

[0188] A protective film may be formed on the second electrode layers 4031 and 543 and the partition walls 4510 and 507 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting elements 4513 and 540. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed. ​​​​ .

[0189] Further, a layer containing an organic compound covering the light-emitting elements 4513 and 540 may be formed by vapor deposition so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting elements 4513 and 540. Also, a layer containing an organic compound covering the light-emitting elements 4513 and 540 may be formed by vapor deposition so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting elements 4513 and 540.

[0190] In addition, in the space sealed by the substrates 4001, 4006, and the sealing material 4005, a filler 4514 is provided and sealed. In this way, the airtightness is high so as not to be exposed to the outside air, and it is preferable to package (encase) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material having little outgassing. a filler 4514 is provided and sealed. In this way, the airtightness is high so as not to be exposed to the outside air, and it is preferable to package (encase) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material having little outgassing. a filler 4514 is provided and sealed. In this way, the airtightness is high so as not to be exposed to the outside air, and it is preferable to package (encase) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material having little outgassing.

[0191] As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, poly imide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate copolymer) can be used. For example, nitrogen can be used as the filler .

[0192] In addition, if necessary, a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and can reduce reflection can be performed. a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and can reduce reflection can be performed. a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and can reduce reflection can be performed.

[0193] In addition, as a display device, it is also possible to provide an electronic paper that drives electrophoretic ink. Electronic paper is also called an electrophoretic display device (electrophoretic display), and paper It has the advantages of being as easy to read as, consuming less power than other display devices, and being able to have a thin and light shape. It has the following advantages.

[0194] Although various forms of electrophoretic display devices can be considered, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent in a plurality, and by applying an electric field to the microcapsule, only the color of the particles that have moved in opposite directions to each other and gathered on one side is displayed. That is, it displays only the color of the particles that have moved in opposite directions to each other and gathered on one side by moving the particles in the microcapsule. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0195] The one in which the above microcapsules are dispersed in a solvent is called electronic ink. Color display is also possible by using particles having a color filter or a dye.

[0196] Note that in FIGS. 4 to 6, as the substrates 4001, 500, and substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having translucency, such as a plate, can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, if translucency is not required, a metal substrate (metal film) such as aluminum or stainless steel can be used. For example, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can also be used. For example, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. It is also possible to use a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film.

[0197] In addition, the insulating layers 4021 and 506 that function as a planarization insulating layer can be made of heat-resistant organic materials such as acrylic resin, polyimide, benzocyclobutene-based resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (low-k materials) such as siloxane-based resin, PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass) can also be used. Note that the insulating layers 4021 and 506 can be formed by laminating a plurality of insulating layers made of these materials. The method for forming the insulating layers 4021 and 506 is not particularly limited, and depending on the material, sputtering method, spin coating, dipping, spray coating, droplet ejection method (inkjet method), screen printing, offset printing, etc. can be used. The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 can be made of conductive materials with light transmittance such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and graphene. In addition, the first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 can be made of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag).

[0198]

[0199]

[0200] ​​​​​​​​​​​​One or more of metals such as Ag), or alloys thereof, or metal nitrides thereof are used. It can be formed.

[0201] In this embodiment, since the light-emitting device shown in FIG. 5 is a bottom emission type, the first electrode layer 541 has translucency, and the second electrode layer 543 has reflectivity. Therefore, when a metal film is used for the first electrode layer 541 the film thickness is made thin enough to maintain translucency, and when a conductive layer having translucency is used for the second electrode layer 543 it is advisable to laminate a conductive layer having reflectivity.

[0202] Also, as the first electrode layers 4034 and 541 and the second electrode layers 4031 and 543, they can be formed using a conductive composition containing a highly conductive molecule (also referred to as a conductive polymer). As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example , polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers composed of two or more of aniline, pyrrole, and thiophene or their derivatives and the like can be mentioned.

[0203] Also, a protection circuit for protecting the drive circuit may be provided. The protection circuit is preferably configured using a non-linear element.

[0204] By applying the transistor shown in Embodiment 1 as described above, a semiconductor device having various functions can be provided.

[0205] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0206] (Embodiment 3) An image sensor device having a function of reading information of an object can be manufactured using the transistor shown in Embodiment 1.

[0207] FIG. 7(A) shows an example of a semiconductor device having an image sensor function. FIG. 7(A) is an equivalent circuit of a photo sensor, and FIG. 7(B) is a cross-sectional view showing a part of the photo sensor.

[0208] One electrode of the photodiode 602 is electrically connected to the photodiode reset signal line 658, and the other electrode is electrically connected to the gate of the transistor 640. One of the source or drain of the transistor 640 is electrically connected to the photo sensor reference signal line 672, and the other of the source or drain is electrically connected to one of the source or drain of the transistor 656. The gate of the transistor 656 is electrically connected to the gate signal line 659, and the other of the source or drain is electrically connected to the photo sensor output signal line 671.

[0209] Note that in the circuit diagrams in this specification, as can be clearly determined for transistors using an oxide semiconductor layer, the symbol for a transistor using an oxide semiconductor layer is described as "OS". In FIG. 7(A), the transistors 640 and 656 can be the transistors shown in Embodiment 1, and are transistors using an oxide semiconductor layer. In this embodiment, an example in which a transistor having the same structure as the transistor 300 shown in Embodiment 1 is applied is shown. The transistor 640 is a transistor having a bottom gate structure.

[0210] FIG. 7(B) shows the photodiode 602 and the transistor 640 in the photo sensor. ​​​​​​​It is a cross-sectional view showing that a photodiode 602 and a transistor 640 that function as sensors are provided on a substrate 601 (element substrate) having an insulating surface. A substrate 613 is provided on the photodiode 602 and the transistor 640 using an adhesive layer 608. .

[0211] An insulating layer 632, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided on the transistor 640. The photodiode 602 includes an electrode layer 641b formed on the interlayer insulating layer 633, a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c that are sequentially stacked on the electrode layer 641b, an electrode layer 642 provided on the interlayer insulating layer 634 and electrically connected to the electrode layer 641b through the first to third semiconductor films, and an electrode layer 641a provided in the same layer as the electrode layer 641b and electrically connected to the electrode layer 642.

[0212] The electrode layer 641b is electrically connected to a conductive layer 643 formed in the interlayer insulating layer 634, and the electrode layer 642 is electrically connected to a conductive layer 645 through the electrode layer 641a. The conductive layer 645 is electrically connected to the gate electrode layer of the transistor 640, and the photodiode 60 2 is electrically connected to the transistor 640.

[0213] Here, an example of a pin-type photodiode is illustrated in which a semiconductor film having a p-type conductivity type is used as the first semiconductor film 606a, a high-resistance semiconductor film (i-type semiconductor film) is used as the second semiconductor film 606b, and a semiconductor film having an n-type conductivity type is used as the third semiconductor film 606c.

[0214] The first semiconductor film 606a is a p-type semiconductor film and contains an amorphous impurity element that imparts a p-type. It can be formed by an amorphous silicon film. For the formation of the first semiconductor film 606a, a semiconductor material gas containing a group 13 impurity element (e.g., boron (B)) is used in the plasma CVD method to form it. Silane (SiH4) may be used as the semiconductor material gas. Or, S i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Also, after forming an amorphous silicon film that does not contain an impurity element, an impurity element may be introduced into the amorphous silicon film using a diffusion method or an ion implantation method. After introducing an impurity element by an ion implantation method or the like heating or the like may be performed to diffuse the impurity element. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor growth method, or a sputtering method or the like may be used. The film thickness of the first semiconductor film 606a is preferably formed to be 10 nm or more and 5 0 nm or less.

[0215] The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is formed by an amorphous silicon film. For the formation of the second semiconductor film 606b, an amorphous silicon film is formed by the plasma CVD method using a semiconductor material gas. As the semiconductor material gas, silane (SiH4) may be used. Or, Si2H6, SiH2Cl2, SiHCl3, S iCl4, SiF4, etc. may also be used. The formation of the second semiconductor film 606b may be performed by an LPCVD method, a vapor growth method, a sputtering method, or the like. The film thickness of the second semiconductor film 606b is preferably formed to be 2 00 nm or more and 1000 nm or less.

[0216] The third semiconductor film 606c is an n-type semiconductor film and is an amorphous containing an impurity element that imparts an n-type It is formed of a fast silicon film. For the formation of the third semiconductor film 606c, a semiconductor material gas containing a Group 15 impurity element (e.g., phosphorus (P)) is used to form it by plasma CVD method. Silane (SiH4) may be used as the semiconductor material gas. Alternatively, Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Also, after forming an amorphous silicon film containing no impurity element, an impurity element may be introduced into the amorphous silicon film using a diffusion method or an ion implantation method. After introducing an impurity element by an ion implantation method or the like, heating or the like may be performed to diffuse the impurity element. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor growth method, a sputtering method, or the like may be used. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less.

[0217] Also, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or may be formed using a microcrystalline (Semi Amorphous Semiconductor: SAS) semiconductor.

[0218] Also, since the mobility of holes generated by the photoelectric effect is smaller than that of electrons, a pin-type photodiode exhibits better characteristics when the p-type semiconductor film side is the light-receiving surface. Here, an example is shown in which light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed is converted into an electric signal. Also, since light from the semiconductor film side having a conductivity type opposite to that of the semiconductor film side used as the light-receiving surface becomes disturbing light, the electrode layer uses a conductive layer having light-shielding properties. ​​​​​​​​​​​​​​ In addition, the n-type semiconductor film side can be used as the light receiving surface.

[0219] The transistor 640 has a thick film (for example, 300 nm thick) as a gate insulating layer 631a. The gate insulating layer 631b includes a silicon film containing nitrogen with reduced defects in the film, and The transistor has a silicon film containing reduced concentration of nitrogen. The transistor 640 is designed to suppress fluctuations in electrical characteristics and electrostatic breakdown. By including the transistor 640, it is possible to provide a highly reliable semiconductor device with a high yield. can.

[0220] The insulating layer 632, the interlayer insulating layer 633, and the interlayer insulating layer 634 are made of an insulating material. Depending on the material, sputtering, plasma CVD, spin coating, dip coating, sputtering, etc. Using laser coating, droplet ejection method (inkjet method), screen printing, offset printing, etc. It can be formed by:

[0221] The interlayer insulating layers 633 and 634 function as planarizing insulating layers to reduce surface irregularities. The interlayer insulating layers 633 and 634 are preferably made of, for example, polyimide or acrylic. Heat-resistant organic resins such as resins, benzocyclobutene-based resins, polyamides, and epoxy resins In addition to the above organic insulating materials, low-dielectric materials can be used. k materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. A single layer or a laminate of these can be used.

[0222] By detecting the light incident on the photodiode 602, information on the detected object is read. This is possible. When reading the information of the detected object, a light source such as a backlight is used. This is possible.

[0223] The configurations, methods, etc. shown in this embodiment can be appropriately combined with those shown in other embodiments and used. This can be used in combination.

[0224] (Embodiment 4) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, audio playback devices, gaming machines (such as pachinko machines, slot machines, etc.), and game cabinets. Specific examples of these electronic devices are shown in FIG. 8. FIG. 8(A) shows a table 9000 having a display unit. The table 9000 has a display unit 9003 incorporated in a housing 9001, and the display unit 9003 can display an image.

[0225] It shows a configuration in which the housing 9001 is supported by four legs 9002. The housing 9001 also has a power cord 9005 for power supply. It is incorporated in the housing 9001, and the display unit 9003 can display an image. A configuration in which the housing 9001 is supported by four legs 9002 is shown. Also, the housing 9001 has a power cord 9005 for power supply.

[0226] The semiconductor device shown in any of the above embodiments can be used for the display unit 9003 and can impart high reliability to the electronic device. This can be used for the display unit 9003 and can impart high reliability to the electronic device.

[0227] The display unit 9003 has a touch input function, and by touching the display button 9004 displayed on the display unit 9003 of the table 9000 with a finger or the like, screen operations and information can be input. By touching the display button 9004 displayed on the display unit 9003 of the table 9000 with a finger or the like, screen operations and information can be input. It is possible to communicate with or control other household appliances, and by doing so, the screen It may also be used as a control device for controlling other household appliances by screen operations. For example, if a semiconductor device having the image sensor function shown in Embodiment 3 is used, a touch

[0228] input function can be provided to the display unit 9003. Also, the screen of the display unit 9003 can be set perpendicular to the floor by a hinge provided on the housing 9001, and it can also be used as a television device. In a narrow room, installing a large screen television device will narrow the free space, but if the display unit is built into the table, the space in the room can be effectively utilized.

[0229] FIG. 8(B) shows a television device 9100. The television device 9100 has a display unit 9103 incorporated in a housing 9101, and it is possible to display an image by the display unit 9103. Here, a configuration in which the housing 9101 is supported by a stand 9105 is shown.

[0230] Operations of the television device 9100 can be performed by operation switches provided on the housing 9101 or by a separate remote control unit 9110. Channel and volume operations can be performed by operation keys 9109 provided on the remote control unit 9110, and the image displayed on the display unit 9103 can be operated. Also, the remote control unit 9110 may be configured to be provided with a display unit 9107 for displaying information output from the remote control unit 9110.

[0231] The television device 9100 shown in FIG. 8(B) is provided with a receiver, a modem, etc. Tele ​​​The vision device 9100 can receive general TV broadcasts by means of a receiver, and further connects to a wired or wireless communication network via a modem, enabling one-way ( from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0232] The semiconductor device shown in any of the above embodiments can be used for the display units 9103 and 9107, and can endow high reliability to a television set and a remote control operation device.

[0233] FIG. 8(C) is a computer, including a main body 9201, a housing 9202, a display unit 9203, a key board 9204, an external connection port 9205, a pointing device 9206, etc.

[0234] The semiconductor device shown in any of the above embodiments can be used for the display unit 9203, and can endow high reliability to a computer.

[0235] FIGS. 9(A) and 9(B) are foldable tablet terminals. FIG. 9(A) shows the open state, and the tablet terminal includes a housing 9630, display units 9631a, 963 1b, a display mode switch 9034, a power switch 9035, a power saving mode switch 9036, a fastener 9033, an operation switch 9038.

[0236] The semiconductor device shown in any of the above embodiments can be used for the display units 9631a and 9631b, and can be made into a highly reliable tablet terminal.

[0237] ​The display unit 9631a can have a part as the area 9632a of the touch panel, and data can be input by touching the displayed operation key 9638. In the display unit 963 1a, as an example, a configuration in which half of the area has only a display function and the other half has a touch panel function is shown, but it is not limited to this configuration. It is also possible to have a configuration in which all areas of the display unit 963 1a have a touch panel function. For example, the entire surface of the display unit 96 31a can be made to display keyboard buttons to serve as a touch panel, and the display unit 9631b can be used as a display screen.

[0238] Also, in the display unit 9631b, similar to the display unit 9631a, a part of the display unit 9631b can be made the area 9632b of the touch panel. Also, by touching the position where the keyboard display switching button 9639 of the touch panel is displayed with a finger or a stylus, etc., keyboard buttons can be displayed on the display unit 9631b.

[0239] Also, touch input can be performed simultaneously on the area 9632a of the touch panel and the area 9632b of the touch panel.

[0240] Also, the display mode switching switch 9034 can select switching of the display orientation such as vertical display or horizontal display, switching between black and white display and color display, etc. The power saving mode switching switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built into the tablet-type terminal during use. The tablet-type terminal may incorporate not only an optical sensor but also other detection devices such as sensors for detecting inclination such as a gyro and an acceleration sensor.

[0241] In addition, FIG. 9(A) shows an example in which the display areas of display unit 9631b and display unit 9631a are the same, but it is not particularly limited, and one size and the other size may be different, and the display quality may also be different. For example, one may be a display panel capable of performing higher-definition display than the other, and that's fine too.

[0242] FIG. 9(B) shows a closed state, and the tablet terminal includes a housing 9630, a solar cell 963 3, and a charge / discharge control circuit 9634. Note that in FIG. 9(B), an example of a configuration having a battery 9635 and a DCDC converter 9636 as the charge / discharge control circuit 9634 is shown.

[0243] Since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Therefore, the display units 9631a and 9631b can be protected, and a tablet terminal with excellent durability and reliability from the perspective of long-term use can be provided.

[0244] In addition, the tablet terminal shown in FIGS. 9(A) and 9(B) can also have functions such as displaying various information ( still images, videos, text images, etc.), a function of displaying a calendar, date, or time on a display unit, a touch input function of touching and inputting or editing the information displayed on the display unit, a function of controlling processing by various software (programs), and so on.

[0245] Power can be supplied to the touch panel, display unit, or video signal processing unit, etc. by the solar cell 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 is housed It can be provided on one or both sides of the body 9630, and the battery 9635 can be efficiently charged. When a lithium-ion battery is used as the battery 9635, there are advantages such as downsizing.

[0246] Also, the configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 9(B) will be described with reference to the block diagram in FIG. 9(C). FIG. 9(C) shows the solar cell 9633, the battery 9635, the DCDC converter 9636, the converter 9637, the switches SW1 to SW3, and the display unit 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 correspond to the parts of the charge / discharge control circuit 963 4 shown in FIG. 9(B).

[0247] First, an example of the operation when power is generated by the solar cell 9633 by external light will be described. The power generated by the solar cell is stepped up or down by the DCD C converter 9636 to become a voltage for charging the battery 9635. When the power from the solar cell 9633 is used for the operation of the display unit 9631, the switch SW1 is turned on, and the converter 96 37 steps up or down the voltage required for the display unit 9631. When the display on the display unit 96 31 is not performed, SW1 can be turned off and SW2 can be turned on to charge the battery 96 35.

[0248] The solar cell 9633 is shown as an example of the power generation means, but it is not particularly limited, and the battery 9635 may be charged by other power generation means such as piezoelectric elements (piezoelectric elements) and thermoelectric conversion elements (Peltier elements). For example, power can be transmitted and received wirelessly (non-contact). ​ A contactless power transmission module that charges by believing, or a configuration that combines other charging means may also be used.

[0249] The configuration, method, etc. shown in this embodiment can be appropriately combined with the configuration, method, etc. shown in other embodiments and used.

Example

[0250] In this example, the evaluation results of the film quality of a silicon nitride film formed by the plasma CVD method will be described. Specifically, the silicon nitride film formed with the supply gas as a mixed gas of silane and nitrogen and the silicon nitride film formed with the supply gas as a mixed gas of silane, nitrogen, and ammonia are shown in the results of the ESR measurement.

[0251] In this example, the method for preparing the sample used in the ESR measurement will be described below.

[0252] For the ESR measurement, samples 1 to 5 with a 300 nm thick silicon nitride film formed on a quartz substrate were used. The silicon nitride film was formed by placing the quartz substrate in the film formation chamber of a plasma CVD apparatus, controlling the pressure in the film formation chamber to 100 Pa, and supplying 2000 W of power with a 27.12 MHz high-frequency power supply. Also, the substrate temperature was set to 350 °C. The plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm ². Sample 1 had a supply gas of a mixed gas of silane and nitrogen. Also, samples 2 to 5 had a supply gas of a mixed gas of silane nitrogen, and ammonia. The film formation conditions for each sample are shown in Table 1 below. 2 is nitrogen. Also, samples 2 to 5 had a supply gas of a mixed gas of silane nitrogen, and ammonia. The film formation conditions for each sample are shown in Table 1 below.

[0253]

Table 1

[0254] ESR measurements were performed on the prepared Samples 1 to 5. The ESR measurements were carried out under the following conditions. The measurement temperature was -170°C, the high-frequency power (microwave power) at 9.2 GHz was 1 mW, and the direction of the magnetic field was parallel to the surface of the silicon nitride film of the prepared Samples 1 to 5. The detection limit of the spin density corresponding to the signal appearing at g = 2.003 derived from the Nc centers contained in the silicon nitride film was 8.1×10 spins / cm 15 spins / cm 3 It is.

[0255] The results of the ESR measurement are shown in Fig. 10(A). From Fig. 10(A), the spin density derived from the Nc centers of Sample 1 that does not contain ammonia in the supply gas is 2.7×10 spins / cm 17 spins / cm 3 It was confirmed that it is a silicon nitride film with many defects in the film. On the other hand, in Samples 2 to 5 containing ammonia in the supply gas, the spin density derived from the Nc centers is 5.1 ×10 ×10 16 spins / cm 3 (Sample 2), 5.2×10 16 spins / cm 3 (Sample 3), 6.0×10 16 spins / cm 3 (Sample 4), 5.5×10 16 spins / cm 3 (Sample 5), showing uniformly low values regardless of the ammonia flow rate, and it was confirmed that it is a silicon nitride film with reduced defects in the film. It was confirmed.

[0256] In addition, the first derivative curve obtained by the ESR measurement is shown in Fig. 10(B). From Fig. 10(B), at a g value of 2.003, in Sample 1, the signal derived from the defects (Nc centers) in the film is It was detected with strong intensity. On the other hand, in Samples 2 to 5, it was confirmed that the signal intensity at a g value of 2.003 was small.

[0257] From the above, by using a mixed gas of silane, nitrogen, and ammonia as the supply gas when forming a silicon nitride film by the plasma CVD method, it was shown that it is possible to form a silicon nitride film with reduced defects in the film. By using the silicon nitride film as a gate insulating layer, it is possible to realize a gate insulating layer with good breakdown voltage, and it is suggested that it is possible to make a transistor including the gate insulating layer have good ESD resistance.

Example

[0258] In this example, the properties of the silicon nitride film formed by the plasma CVD method as a barrier film were evaluated. The evaluation results are shown in Fig. 11. As the evaluation method, the thermal desorption spectroscopy (TDS) was used.

[0259] In this example, Samples 6 to 8 in which a silicon nitride film was formed on a quartz substrate by the plasma CVD method were used for evaluation. The sample preparation method is shown below.

[0260] For the formation of the silicon nitride film, a quartz substrate was placed in the film formation chamber of a plasma CVD apparatus, the pressure in the film formation chamber was controlled to 100 Pa, and electric power of 2000 W was supplied by a 27.12 MHz high-frequency power supply. Also, the substrate temperature was 350 °C. The plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm². 2

[0261] ​​​​​​​​​​​​​Sample 6 was formed with a silicon nitride film having a thickness of 300 nm using a mixed gas of silane, nitrogen, and ammonia as the supply gas (SiH4 flow rate: 200 scc m, N2 flow rate: 2000 sccm, NH3 flow rate: 2000 sccm).

[0262] Sample 7 was formed with a first silicon nitride film having a thickness of 275 nm using a mixed gas of silane, nitrogen, and ammonia as the supply gas (SiH4 flow rate: 200 scc m, N2 flow rate: 2000 sccm, NH3 flow rate: 2000 sccm). After forming the first silicon nitride film, in the same film formation chamber, a mixed gas of silane and nitrogen was used as the supply gas (SiH4 flow rate: 200 sccm, N2 flow rate: 5000 sccm) to form a second silicon nitride film having a thickness of 50 nm.

[0263] Sample 8 was formed with a first silicon nitride film having a thickness of 275 nm using a mixed gas of silane, nitrogen, and ammonia as the supply gas (SiH4 flow rate: 200 scc m, N2 flow rate: 2000 sccm, NH3 flow rate: 2000 sccm). After forming the first silicon nitride film, in the same film formation chamber, the flow rate of ammonia was reduced to SiH4 flow rate: 200 sccm, N2 flow rate: 2000 sccm, NH3 flow rate: 100 sccm to form a second silicon nitride film having a thickness of 50 nm.

[0264] Figure 11 shows the evaluation results of the TDS measurement of M / z = 2 (H2) for each sample. Figure 11(A) shows the evaluation results of the TDS measurement of M / z = 2 (H2) for Sample 6 and Sample 7 fabricated in this example , and Figure 11(B) shows the evaluation results of the TDS measurement of M / z = 2 (H2) for Sample 6 and Sample 8 .

[0265] From Figure 11(A) and Figure 11(B), in Sample 6 where a single layer of a silicon nitride film with a high hydrogen concentration in the film was provided , hydrogen release was confirmed by heat treatment. On the other hand, the hydrogen in the film​​​​ In Samples 7 and 8 with a silicon nitride film having a reduced concentration laminated on the upper layer, hydrogen emission was not observed around 450 °C where hydrogen emission was confirmed in Sample 6, and even after further heat treatment was performed, it was confirmed that hydrogen emission was extremely reduced.

[0266] Therefore, it was shown that by providing a silicon nitride film with a reduced hydrogen concentration on the upper layer in contact with a silicon nitride film with a high hydrogen concentration, a hydrogen blocking effect is achieved. As shown in Example 1, the silicon nitride film formed by plasma CVD using silane, nitrogen, and ammonia as supply gases is a film with high breakdown voltage and reduced defects in the film. Thus,

[0267] the structure in which a silicon nitride film with a reduced hydrogen concentration is laminated on the silicon nitride film with reduced defects in the film can reduce the emission of hydrogen that can become a donor of the oxide semiconductor layer while maintaining high ESD resistance, and thus is preferably applicable as the gate insulating layer of a transistor.

[0268]

Example

[0268] In this example, the difference in film quality due to the difference in supply gases was evaluated for the silicon nitride film formed by plasma CVD. Specifically, the measurement results of the film density and wet etching rate of the silicon nitride film formed using a mixed gas of silane and nitrogen as the supply gas and the silicon nitride film formed using a mixed gas of silane, nitrogen, and ammonia as the supply gas are shown.

[0269]

[0270] In this example, the method for preparing the samples used in the measurement will be described below.

[0270] For the measurement, Samples 9 to 11 with a silicon nitride film formed on a quartz substrate were used. The silicon The formation of the silicon nitride film was carried out by placing a quartz substrate in the film formation chamber of a plasma CVD apparatus, and controlling the pressure in the film formation chamber to 100 Pa and supplying 2000 W of power with a high-frequency power source of 27.12 MHz. Also, the substrate temperature was set at 350 °C. The plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 c m 2 . For Sample 9, the supply gas was a mixed gas of silane and nitrogen . For Samples 10 and 11, the supply gas was a mixed gas of silane, nitrogen, and ammonia . The film formation conditions for each sample are shown in Table 2 below.

[0271]

Table 2

[0272] As shown in Table 2, the film formation conditions for Sample 9 are the same as those for Sample 1 in Example 1, the film formation conditions for Sample 10 are the same as those for Sample 2 in Example 1, and the film formation conditions for Sample 11 are the same as those for Sample 5 in Example 1.

[0273] For the prepared Samples 9 to 11, measurements of the wet etching rate and measurements of the film density using the X-ray reflectometry (XRR) method were performed. The measurement of the wet etching rate was calculated from the etching amount in the case of treatment with 0.5% hydrofluoric acid for 60 seconds.

[0274] The measurement results of the film density and the wet etching rate are shown in FIG. 12. From FIG. 12, in Sample 11 with a large ammonia flow ratio in the supply gas, the film density is low and the wet etching rate is fast. On the other hand, in Samples with a reduced ammonia flow ratio or without ammonia in the supply gas In the case of the material 9 and the sample 10, it was confirmed that the film density was high and the wet etching rate was slow. Therefore, by reducing the ammonia flow rate ratio of the supply gas, or by not containing ammonia in the supply gas, a dense silicon nitride film can be formed, and the dense silicon nitride film can function as a blocking film for metal elements such as copper and / or hydrogen. It can be said that it is possible.

[0275] In addition, FIG. 13 shows cross-sectional STEM (Scanning Transmission Electron Microscope) photographs of transistors including the first silicon nitride film to the third silicon nitride film formed by changing the ammonia flow rate. Note that FIG. 13(B) is a partially enlarged view of the region surrounded by a square in the transistor shown in FIG. 13(A). It is.

[0276] The transistors shown in FIGS. 13(A) and 13(B) are formed on a tungsten film 702 formed on a glass substrate 700, and include a gate insulating layer composed of a first silicon nitride film 704a, a second silicon nitride film 704b, a third silicon nitride film 704c, and a silicon oxynitride film 706. On the gate insulating layer, an oxide semiconductor layer 708 composed of an In-Ga-Zn-based oxide semiconductor layer, and an electrode layer 710 in contact with the oxide semiconductor layer 708, which is a laminate of a tungsten film, an aluminum film, and a titanium film. And a silicon oxynitride film 712 on the electrode layer 710 and the oxide semiconductor layer 708.

[0277] In this embodiment, the first silicon nitride film 704a to the third silicon nitride film 704c that function as a gate insulating layer, and the silicon oxynitride film 706 were continuously formed. Specifically ​​​​​​​​​​​​First, the supply gas was a mixed gas of silane, nitrogen, and ammonia (SiH4 flow rate 200 scc m: N2 flow rate 2000 sccm: NH3 flow rate 100 sccm). After forming the first silicon nitride film 704a with a thickness of 50 nm, only the ammonia flow rate was changed to 2000 sccm, and the second silicon nitride film 704b with a thickness of 300 nm was formed. Then, the ammonia flow rate was changed back to 100 sccm, and after forming the third silicon nitride film 704 c with a thickness of 50 nm, the supply gas was changed to a mixed gas of silane and dinitrogen monoxide (SiH4 flow rate 20 sccm: N2O flow rate 3000 sccm), and a silicon oxynitride film 706 with a thickness of 50 nm was formed.

[0278] In addition, in the formation of the first silicon nitride film 704a to the third silicon nitride film 704c, the pressure in the film formation chamber was controlled to 100 Pa, and 2000 W of power was supplied by a 27.12 MHz high-frequency power source. Also, in the formation of the silicon oxynitride film 706, the pressure in the film formation chamber was controlled to 40 Pa, and 100 W of power was supplied by the high-frequency power source. Also, for the first silicon nitride film 704a to the third silicon nitride film 704c, and the silicon oxynitride film 706, the substrate temperature was set to 350 °C during film formation. The plasma CVD apparatus used for film formation had an electrode area of 6000 cm and was a parallel plate type plasma CVD apparatus. 2

[0279] From the results of the film density measurement shown in FIG. 12, the first silicon nitride film 704a and the third silicon nitride film 704c with a low ammonia flow rate in the supply gas are dense silicon nitride films with a high film density. In the STEM photographs of FIGS. 13(A) and 13(B), the first silicon nitride film ​​​​​​In the third silicon nitride film 704c to the 704a, a density difference is recognized, and it can be said that the difference in the film characteristics due to the flow rate ratio of the supply gas can also be confirmed from the STEM photograph.

Example

[0280] In this example, when the silicon nitride film is laminated by changing the ammonia flow rate in the supply gas the measurement results of the hydrogen concentration in the film of each silicon nitride film are shown.

[0281] In this example, the method for preparing the sample used for the measurement will be described below.

[0282] For the measurement, samples 12 and 13 in which silicon nitride films were laminated by changing the ammonia flow rate in the supply gas were used on a silicon substrate. The silicon nitride film was formed by placing a quartz substrate in the film formation chamber of a plasma CVD apparatus, controlling the pressure in the film formation chamber to 100 Pa, and supplying 2000 W of power with a 27.12 M Hz high-frequency power supply. The substrate temperature was set to 350°C. In addition, the plasma CVD apparatus is a parallel plate type plasma CV 2 D apparatus with an electrode area of 6000 cm D.

[0283] Sample 12 was formed by using a first supply gas containing no ammonia as a source gas on a silicon substrate to form a silicon nitride film with a thickness of 50 nm, changing the gas flow rate, and using a second supply gas with a large ammonia flow rate as a source gas to form a silicon nitride film with a thickness of 300 nm. Then, the gas flow rate was changed back to the first supply gas again to form a silicon nitride film with a thickness of 50 nm. Sample 13 was formed by using a third supply gas with a low ammonia flow rate as a source gas on a silicon substrate and then,

[0284] Sample 13 was formed by using a third supply gas with a low ammonia flow rate as a source gas on a silicon substrate Then, a silicon nitride film with a thickness of 50 nm was formed, and the gas flow rate was changed. The ammonia flow rate of a second supply gas with a large amount was used as the source gas. After forming a silicon nitride film with a thickness of 300 nm, again, the gas flow rate was changed to a third supply gas, and a silicon nitride film with a thickness of 50 nm was formed .

[0285] Details of the first to third supply gases are shown in Table 3 below.

[0286]

Table 3

[0287] Regarding the fabricated silicon nitride film with a laminated structure, the hydrogen concentration and oxygen concentration were measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrome try). The measurement results of the hydrogen concentration in the film of Sample 12 are shown in Fig. 14(A), and the measurement results of the oxygen concentration in the film of Sample 12 are shown in Fig. 14(B). Also, Fig. 14(C) shows the measurement results of the hydrogen concentration in the film of Sample 13, and Fig. 14(D) shows the measurement

[0288] results of the oxygen concentration in the film of Sample 13. From Fig. 14(A) and Fig. 14(C), in the silicon nitride film formed using the second supply gas with a large ammonia flow rate in the supply gas, that is, a high hydrogen concentration in the supply gas, an increase in the hydrogen concentration profile was confirmed.

[0289] Therefore, it was shown that by reducing the ammonia flow rate in the supply gas or not containing ammonia, that is, reducing the hydrogen concentration in the supply gas, it is possible to reduce the hydrogen concentration of the formed silicon nitride film.

Example

[0290] In this embodiment, regarding the gate insulating layer including a thick silicon nitride film with reduced defects in the film , the results of evaluating the breakdown voltage and ESD resistance are shown.

[0291] In this embodiment, the manufacturing methods of Example Element 1 and Example Element 2 used for measurement, as well as Comparative Element 1 and Comparative Element 2 are shown below. In this embodiment, an element in which a gate wiring crosses a source wiring (or drain wiring) through a gate insulating layer was manufactured. Note that the size of the crossing portion was set to 10 μm × 10 μm. Also, in each of the following elements, for the formation of the gate insulating layer , a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 was used as the plasma CVD apparatus . In the plasma CVD apparatus, the power supply power was supplied by a high-frequency power supply of 27.12 MHz .

[0292] Example Element 1 has a tantalum nitride film with a film thickness of 30 nm, a copper film with a film thickness of 200 nm , and a tungsten film with a film thickness of 5 nm laminated as the gate wiring, and a gate insulating layer was formed in contact with the tungsten film. The gate insulating layer was continuously formed by the plasma CVD method with a silicon nitride film having a film thickness of 325 nm and a silicon oxynitride film having a film thickness of 50 nm .

[0293] The silicon nitride film in Example Element 1 was formed by setting the pressure of the plasma CVD apparatus to 100 Pa and the power supply power to 2000 W, and using a supply gas with a large ammonia flow rate as the source gas for film formation , thereby obtaining a silicon nitride film with few defects in the film. Specifically, a mixed gas of silane, nitrogen, and ammonia was supplied at a flow rate ratio of 200 sccm:2000 sccm:2000 sccm (= SiH4: N2:NH3).

[0294] For Example Element 2, a tungsten film with a thickness of 200 nm was formed as the gate wiring, and a gate insulating layer was formed in contact with the tungsten film. The manufacturing conditions of the gate insulating layer of Example Element 2 are the same as those of Example Element 1.

[0295] For Comparative Element 1, as the gate wiring, a tantalum nitride film with a thickness of 30 nm and a copper film with a thickness of 200 nm were laminated, and a gate insulating layer was formed in contact with the copper film. The gate insulating layer was formed by plasma CVD method to continuously form a silicon nitride film with a thickness of 50 nm and a silicon oxynitride film with a thickness of 270 nm. The silicon nitride film in Comparative Element 1 was formed by using a supply gas without ammonia as the source gas with the pressure of the plasma CVD apparatus set to 60 Pa and the power supply power set to 150 W, resulting in a silicon nitride film with many defects in the film. Specifically, a mixed gas of silane and nitrogen was supplied at a flow rate ratio of 50 sccm:5000 sccm (=SiH4:N2).

[0296]

[0297] For Comparative Element 2, a tungsten film with a thickness of 200 nm was formed as the gate wiring, and a gate insulating layer was formed in contact with the tungsten film. The manufacturing conditions of the gate insulating layer of Comparative Element 2 are the same as those of Comparative Element 1.

[0298] The configuration conditions of the fabricated Example Element 1, Example Element 2, Comparative Element 1, and Comparative Element 2 are shown in Table 4 below.

[0299]

Table 4

[0300] Next, using the fabricated device, the breakdown voltage of the gate insulating layer was measured and the ESD resistance was evaluated. This was done.

[0301] In this example, for the measurement of the breakdown voltage, the terminal of the source wiring (or drain wiring) was fixed at 0 V (G ND), a bias voltage was applied to the terminal of the gate wiring, and when the current reached 1 × 10 -6 A flowed, the voltage value at that time was determined as the breakdown voltage. The bias voltage was applied in steps of +10 V from 0 V to + 500 V, and the delay time was 0.5 s. For the measurement, a picoammeter (model number 64 87) manufactured by Case Instruments Co., Ltd. was used.

[0302] Fig. 15 shows the measurement results of the breakdown voltage of the gate insulating layer. In Fig. 15, the vertical axis represents the current (A ), and the horizontal axis represents the voltage (V). From Fig. 15, in Comparative Element 1 containing a thin film (50 nm) of silicon nitride with many defects in the film as the gate insulating layer, breakdown of the gate insulating layer was confirmed at 20 V. Also, similarly, in Comparative Element 2, although an improvement in the breakdown voltage was observed by using a tungsten film as the gate electrode layer, breakdown of the gate insulating layer was confirmed at 230 V. On the other hand, in Example Element 1 containing a thick film (325 nm) of silicon nitride with few defects in the film as the gate insulating layer, the voltage value when the current exceeded 1 × 10 A was 320 V and it showed a high breakdown voltage. Also, similarly, in Example Element 2, the voltage value when the current exceeded 1 × 10 A was 370 V, showing a high breakdown voltage. Therefore, with fewer defects in the film

[0303] On the other hand, in Example Element 1 containing a thick film (325 nm) of silicon nitride with few defects in the film as the gate insulating layer, the voltage value when the current exceeded 1 × 10 A was 320 V -6 and it showed a high breakdown voltage. Also, similarly, in Example Element 2, the voltage value when the current exceeded 1 × 10 A was 370 V, showing a high breakdown voltage. Therefore, with fewer defects in the film -6 and flowing through, the voltage value was 370 V, showing a high breakdown voltage. Thus, with fewer defects in the film By providing a thick film of silicon nitride film without a nitride film, the breakdown voltage can be improved to 300 V or higher. It was shown that this is possible.

[0304] Next, the ESD resistance of the fabricated example elements was evaluated. In this example, the evaluation of ESD resistance adopted the HBM (Human Body Model), with a capacitance value C = 100 pF and a resistance value R = 1.5 kΩ. The voltage value was increased in 50 V increments from 50 V to the breakdown voltage, and bipolar voltages were applied three times each. That is, the forward bias voltage and the reverse bias voltage of the same value were applied three times each. The voltage application was performed at room temperature in an air atmosphere. Then, at the time when a breakdown mark was confirmed in the element by optical microscope inspection after the application, the applied voltage was defined as the breakdown voltage.

[0305] In Example Element 1, the applied voltage at the time when a breakdown mark was confirmed was 600 V. Also, in Example Element 2, the applied voltage at the time when a breakdown mark was confirmed was 750 V.

[0306] From the above, it was confirmed that both Example Element 1 and Example Element 2 have high ESD resistance. This was consistent with the results showing high breakdown voltage in the evaluation of the breakdown voltage of the gate insulating layer shown in Fig. 15 for Example Element 1 and Example Element 2. Also, in the evaluation of ESD resistance, a breakdown mark was confirmed in the element at a voltage approximately twice that of the voltage at which the gate insulating layer was broken down.

Description of Symbols

[0307] 300 Transistor 310 Transistor 320 Transistor 330 Transistor 340 Transistor 400 Substrate 402 Gate electrode layer 404 Gate insulating layer 404a Gate insulating layer 404b Gate insulating layer 404c Gate insulating layer 407 Gate insulating layer 408 Oxide semiconductor layer 408a Oxide semiconductor layer 408b Oxide semiconductor layer 410a Source electrode layer 410b Drain electrode layer 414 Insulating layer 414a Insulating layer 414b Insulating layer 500 Substrate 502 Gate insulating layer 502a Gate insulating layer 502b Gate insulating layer 502c Gate insulating layer 504 Interlayer insulating layer 505 Color filter layer 506 Insulating layer 507 Partition wall 510 Transistor 511a Gate electrode layer 511b Gate electrode layer 512 Oxide semiconductor layer 513a Conductive layer 513b Conductive layer 520 Capacitor element 521a Conductive layer 521b Conductive layer 522 Oxide semiconductor layer 523 Conductive layer 525 Insulating layer 530 Wiring layer intersection 533 Conductive layer 540 Light-emitting element 541 Electrode layer 542 Electroluminescent layer 543 Electrode layer 601 Substrate 602 Photodiode 606a Semiconductor film 606b semiconductor film 606c semiconductor film 608 adhesive layer 613 substrate 631a gate insulating layer 631b gate insulating layer 632 insulating layer 633 interlayer insulating layer 634 interlayer insulating layer 640 transistor 641a electrode layer 641b electrode layer 642 electrode layer 643 conductive layer 645 conductive layer 656 transistor 658 photodiode reset signal line 659 gate signal line 671 photosensor output signal line 672 photosensor reference signal line 700 glass substrate 702 tungsten film 704a first silicon nitride film 704b second silicon nitride film 704c third silicon nitride film 706 silicon oxynitride film 708 oxide semiconductor layer 710 electrode layer 712 silicon oxynitride film 4001 substrate 4002 pixel section 4003 signal line driving circuit 4004 scanning line driving circuit 4005 sealing material 4006 substrate 4008 liquid crystal layer 4010 transistor 4011 transistor 4013 liquid crystal element 4015 connection terminal electrode 4016 terminal electrode 4018 FPC 4019 anisotropic conductive layer 4020a Gate insulating layer 4020b Gate insulating layer 4021 Insulating layer 4031 Electrode layer 4032 Insulating layer 4033 Insulating layer 4034 Electrode layer 4035 Spacer 4038 Insulating layer 4510 Partition wall 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9000 Table 9001 Housing 9002 Leg 9003 Display unit 9004 Display button 9005 Power cord 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9100 Television apparatus 9101 Housing 9103 Display unit 9105 Stand 9107 Display unit 9109 Operation key 9110 Remote control operation unit 9201 Main body 9202 Housing 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Pointing device 9630 Housing 9631 Display unit 9631a Display unit 9631b Display unit 9632a Region 9632b Region 9633 Solar cell 9634 Charge and discharge control circuit 9635 Battery 9636 DCDC Converter 9637 Converter 9638 Operation Key 9639 Button

Claims

【Claim 1】 A gate electrode layer, a first gate insulating layer on the gate electrode layer, a second gate insulating layer provided on the first gate insulating layer and having a smaller film thickness than the first gate insulating layer, an oxide semiconductor layer on the second gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer, The first gate insulating layer is a silicon nitride film containing nitrogen, in which the spin density corresponding to the signal with a g-value of 2.003 in the electron spin resonance method is 1×10 １７ spins / cm ３ or less. wherein the second gate insulating layer is a silicon nitride film containing nitrogen with a lower hydrogen concentration than the first gate insulating layer. A semiconductor device.

Images