Photoelectric conversion device

Abstract

To provide a photoelectric conversion device with improved accuracy.SOLUTION: The photoelectric conversion device includes a pixel array in which a plurality of pixels are arranged to form a plurality of columns and a column circuit arranged to correspond to each of the plurality of columns of the pixel array. The column circuit includes a sample hold part and a plurality of potential lines including a potential line for supplying potential to the sample hold part. The plurality of potential lines are common or separate in the photoelectric conversion device.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] Patent Document 1 discloses a solid-state imaging device including a sample-and-hold unit that holds a signal output from a pixel.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the photoelectric conversion device as described in Patent Document 1, further improvement in accuracy is required.

[0005] Therefore, an object of the present invention is to provide a photoelectric conversion device with improved accuracy.

Means for Solving the Problems

[0006] According to one aspect of the present invention, there is provided a photoelectric conversion device including a pixel array in which a plurality of pixels are arranged to form a plurality of columns, and column circuits arranged corresponding to each of the plurality of columns of the pixel array, wherein the column circuit includes a cascade-connected first inverter amplifier and a first source follower circuit, a first sample-and-hold unit that holds a signal output from a pixel in a corresponding column, an analog-to-digital conversion circuit that converts an analog signal based on the signal into a digital signal, a first potential line that supplies a driving potential to at least one of the first inverter amplifier and the first source follower circuit, and a third potential line that supplies a driving potential to a part of the analog-to-digital conversion circuit, and the first potential line and the third potential line are separated in the photoelectric conversion device.

Advantages of the Invention

[0007] According to the present invention, there is provided a photoelectric conversion device with improved accuracy.

Brief Description of the Drawings

[0008]

Figure 1

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Figure 4

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Figure 17

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same elements or corresponding elements are given common reference numerals throughout the plurality of drawings, and the description thereof may be omitted or simplified.

[0010] [First Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device 100 according to the present embodiment. The photoelectric conversion device 100 includes a pixel array 10, a vertical scanning circuit 20, a load circuit section 30, a signal holding section 40, an analog-digital conversion section (AD conversion section) 50, a digital memory section 60, a horizontal scanning circuit 64, a digital signal processing section 70, an output section 80, and a control circuit 90. These circuits can be formed on one or more semiconductor substrates. Note that the photoelectric conversion device 100 of the present embodiment is assumed to be an imaging device that acquires an image, but is not limited thereto. For example, the photoelectric conversion device may be a focus detection device, a distance measurement device, a TOF (Time-Of-Flight) camera, or the like.

[0011] The pixel array 10 includes a plurality of pixels 12 arranged in a plurality of rows and a plurality of columns. The vertical scanning circuit 20 is a scanning circuit that supplies a control signal for controlling the transistors included in the pixels 12 to be on (conducting state) or off (non-conducting state) to each row of the pixels 12 via a control signal line 14 provided for each row. The vertical scanning circuit 20 can be configured by a shift register or an address decoder. Here, since the control signal supplied to each pixel 12 can include a plurality of types of control signals, the control signal line 14 for each row can be configured as a set of a plurality of drive wirings. A column signal line 16 is provided for each column of the pixels 12, and signals from the pixels 12 are read out to the column signal line 16 for each column.

[0012] The load circuit section 30 has a load circuit 32 corresponding to each column of the pixels 12. The load circuit 32 supplies a bias current for reading out a signal from the pixels 12 to the column signal line 16 of the corresponding column. The signal holding section 40 has a sample-and-hold section 42 corresponding to each column of the pixels 12. The sample-and-hold section 42 holds the signal output from the pixels 12.

[0013] The AD conversion unit 50 includes analog-digital conversion circuits (AD conversion circuits) 52 corresponding to each column of the pixels 12. The AD conversion circuit 52 converts an analog signal based on the signal held in the sample hold unit 42 into a digital signal. The digital memory unit 60 includes digital memories 62 corresponding to each column of the pixels 12. The digital memory 62 stores the digital signal output from the AD conversion unit 50.

[0014] The horizontal scanning circuit 64 supplies a control signal for controlling the digital memory unit 60 to sequentially output digital signals to the digital signal processing unit 70 for each column. The horizontal scanning circuit 64 can be constituted by a shift register or an address decoder. The digital signal processing unit 70 is a circuit that performs various signal processes on the input digital signal. The output unit 80 outputs the processed digital signal to the outside of the optoelectronic conversion device 100. The control circuit 90 controls the operation timings of the vertical scanning circuit 20, the load circuit unit 30, the signal holding unit 40, the analog-digital conversion unit (AD conversion unit) 50, the digital memory unit 60, the horizontal scanning circuit 64, and the output unit 80.

[0015] As described above, a load circuit 32, a sample hold unit 42, an AD conversion circuit 52, and a digital memory 62 are arranged corresponding to each column of the pixel array 10. The circuits for reading signals corresponding to each column of the pixel array 10 may be called column circuits.

[0016] FIG. 2 is a circuit diagram of the pixel 12 according to the present embodiment. The pixel 12 includes a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. These transistors can be constituted by N-type MOS transistors having a gate electrode as a control electrode. Control signals PTX, PRES, and PSEL for controlling these transistors are respectively input to the gates of the transfer transistor M1, the reset transistor M2, and the selection transistor M4 from the vertical scanning circuit 20 via the control signal line 14.

[0017] The photoelectric conversion unit PD is a photoelectric conversion element that generates charges corresponding to incident light by photoelectric conversion and accumulates the charges. The photoelectric conversion unit PD can be constituted by a photodiode formed in a semiconductor substrate. The anode of the photodiode constituting the photoelectric conversion unit PD is connected to a potential line having a ground potential GND, and the cathode is connected to the source of the transfer transistor M1.

[0018] The drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected to each other. This connection node is a so-called floating diffusion. When the transfer transistor M1 is turned on, the charges of the photoelectric conversion unit PD are transferred to the floating diffusion. The floating diffusion has a capacitance, and due to this capacitance, the potential of the floating diffusion changes according to the charges transferred from the photoelectric conversion unit PD.

[0019] The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a potential line having a power supply potential VDD. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the column signal line 16. The amplification transistor M3 constitutes a source follower circuit together with a current source in the load circuit 32 connected to the column signal line 16. This source follower circuit outputs a signal based on the voltage of the floating diffusion to the column signal line 16 via the selection transistor M4. When the reset transistor M2 is turned on, the potential of the floating diffusion is reset.

[0020] Each of the pixels 12 may have a microlens and a color filter arranged on the optical path until the incident light is guided to the photoelectric conversion unit PD. The microlens condenses the incident light onto the photoelectric conversion unit PD. The color filter selectively transmits light of a predetermined color.

[0021] FIG. 3 is a timing chart for explaining the signal readout operation from pixel 12 according to this embodiment. FIG. 3 shows the timings of control signals PSEL, PRES, and PTX output from vertical scanning circuit 20 to one row among a plurality of pixels 12, and the output potential VOUT output from pixel 12 to the column signal lines 16 of the corresponding column.

[0022] At time T1, control signal PSEL becomes high level. As a result, selection transistor M4 turns on, the pixels 12 in the row are selected, and a signal based on the voltage of the floating diffusion is output to column signal lines 16.

[0023] At time T2, control signal PRES becomes high level and then low level. By this operation, reset transistor M2 is temporarily turned on, and the potential of the floating diffusion is reset to a potential corresponding to power supply potential VDD. As a result, output potential VOUT becomes a potential based on the reset state of pixel 12. This potential is held as a reset signal (second signal) in sample hold section 42.

[0024] At time T3, control signal PTX becomes high level and then low level. By this operation, transfer transistor M1 is temporarily turned on, and the charge accumulated in photoelectric conversion section PD is transferred to the floating diffusion. As a result, output potential VOUT becomes a potential based on the charge accumulated in photoelectric conversion section PD in response to incident light. This potential is held as a pixel signal (first signal) in sample hold section 42.

[0025] At time T4, control signal PSEL becomes low level. As a result, selection transistor M4 turns off, and the selection of pixels 12 in the row is released.

[0026] FIG. 4 is a block diagram showing the circuit configuration and wiring connection of one column according to this embodiment. In FIG. 4, only a part of the block of pixel 12 and the column circuit corresponding to pixel 12 described in FIG. 1 is shown in an excerpted form for one column.

[0027] Also, FIG. 4 shows an element region R1 of the photoelectric conversion device 100 in which a pixel array 10, a column circuit, etc. are arranged, and a pad region R2 in which pads, which are external terminals for supplying a driving potential to the photoelectric conversion device 100 from the outside, are arranged. The element region R1 and the pad region R2 can be arranged in different regions on the semiconductor substrate. FIG. 4 schematically shows that a pixel array 10, a load circuit 32, a sample hold section 42, and an AD conversion circuit 52 are arranged in the element region R1. Also, FIG. 4 schematically shows that pads P1, P2, P3, and P4 are arranged in the pad region R2. The pads P1, P2, P3, and P4 can be, for example, metal films to which mounting members such as bonding wires and bumps are connected.

[0028] In the following description, it is assumed that the pads P1, P2, P3, and P4 are ground terminals for supplying a ground potential, but these pads may be power supply terminals for supplying a power supply potential or reference potential terminals for supplying a reference potential in each circuit. The ground potential, the power supply potential, and the reference potential may also be called a driving potential as a more general term. In other words, the pads P1, P2, P3, and P4 can be external terminals for supplying a driving potential to each circuit of the photoelectric conversion device 100.

[0029] The pixel array 10 has a plurality of pixels 12, and the ground wiring of the pixel 12 is connected to the pad P1. The load circuit 32 has a current source 34 connected to the column signal line 16. The ground wiring of the current source 34 is connected to the pad P2.

[0030] The sample hold unit 42 includes a first sample hold unit 44S, a second sample hold unit 44N, and a resistor R. The column signal line 16 is connected to the first sample hold unit 44S and the second sample hold unit 44N. The first sample hold unit 44S acquires and holds the pixel signal output from the pixel 12 via the column signal line 16. The second sample hold unit 44N acquires and holds the reset signal output from the pixel 12 via the column signal line 16.

[0031] The second sample hold unit 44N is connected to the first sample hold unit 44S via a signal line IL1, the resistor R, and a signal line IL2 in sequence. Thereby, the second sample hold unit 44N can supply a current based on the held reset signal to the first sample hold unit 44S. The first sample hold unit 44S outputs a current based on the difference between the pixel signal and the reset signal to the AD conversion circuit 52 via a signal line IL3. Thereby, correction processing by correlated double sampling of the pixel signal and the reset signal is performed.

[0032] The ground wiring GL1 (first potential line) of the first sample hold unit 44S and the ground wiring GL2 (second potential line) of the second sample hold unit 44N are shared at a node N1 outside the element region R1. The shared ground wiring is connected to the pad P3. Note that the node N1 may be in the element region R1 or the pad region R2, and it is sufficient that the ground wiring is shared at least on the sample hold unit 42 side from the pad P3. The ground wiring GL3 (third potential line) of the AD conversion circuit 52 is connected to the pad P4.

[0033] FIG. 5 is a block diagram showing the configuration of the second sample hold unit 44N for the reset signal according to the present embodiment. The second sample hold unit 44N includes a sample hold circuit group 46N and an amplification unit 48N.

[0034] The sample hold circuit group 46N includes N sample hold circuits 462N1 to 462N n ~462N Nhaving (N is an integer of 2 or more, n is an integer of 1 or more and less than N). The sample-and-hold circuit 462N1 has switches S11, S21, and capacitor C11. The sample-and-hold circuit 462N n has switches S1 n , S2 n and capacitor C1 n . Thus, each of the sample-and-hold circuits 462N1 to 462N N-1 has two switches and one capacitor. The sample-and-hold circuit 462N N has switches S1 N and capacitor C1 N .

[0035] The amplification unit 48N has an inverting amplifier 482N, a transistor M5, a current source 484N, and switches S3, S4, S5. The transistor M5 is a P-type MOS transistor. The plurality of switches included in the sample-and-hold circuit group 46N and the amplification unit 48N are controlled to be turned on or off based on the control from the control circuit 90.

[0036] The column signal line 16 is connected to the first terminals of switches S11 to S1 N . The second terminal of switch S11 is connected to the first terminals of switch S21 and capacitor C11. The second terminal of switch S21 is connected to the second terminal of switch S12, the first terminal of switch S22, and the first terminal of capacitor C12 included in the adjacent sample-and-hold circuit 462N2. The sample-and-hold circuits 462N2 to 462N N-1 also have the same configuration. The second terminal of switch S1 N is connected to the second terminal of switch S2 N-1 , the first terminal of capacitor C1 N , and the first terminal of switch S4. The second terminals of capacitors C11 to C1 N are connected to the input terminal of the inverting amplifier 482N and the first terminal of switch S3.

[0037] The output terminal of the inverting amplifier 482N is connected to the second terminal of the switch S3 and the first terminal of the switch S5. The second terminal of the switch S5 is connected to the gate of the transistor M5. The second terminal of the switch S4 is connected to the current source 484N and the source of the transistor M5. The power supply terminal of the current source 484N is connected to a potential line having the power supply potential VDD. The connection node of the second terminal of the switch S4, the current source 484N, and the source of the transistor M5 forms the output terminal of the second sample hold unit 44N and is connected to the signal line IL1. The ground terminal of the inverting amplifier 482N and the drain of the transistor M5 are connected to the ground wiring GL2.

[0038] In this way, the amplification unit 48N forms an amplification circuit in which the inverting amplifier 482N (second inverting amplifier) and the source follower circuit (second source follower circuit) composed of the current source 484N and the transistor M5 are connected in cascade. The amplification unit 48N can output a current corresponding to the voltage held in the capacitors C11 to C1 N to the signal line IL1.

[0039] FIG. 6 is a block diagram showing the configuration of the first sample hold unit 44S for pixel signals according to the present embodiment. The first sample hold unit 44S has a sample hold circuit group 46S and an amplification unit 48S.

[0040] The sample hold circuit group 46S has N sample hold circuits 462S1 to 462S n ~462S N . The sample hold circuit 462S1 has switches S61, S71, and a capacitor C21. The sample hold circuit 462S n has switches S6 n , S7 n , and a capacitor C2 n . In this way, the sample hold circuits 462S1 to 462S N-1 have two switches and one capacitor. The sample hold circuit 462S N has a switch S6 N and a capacitor C2N It has. Since the connection relationship of the circuits in the sample hold circuit group 46S is the same as that of the sample hold circuit group 46N, the description thereof is omitted.

[0041] The amplification unit 48S includes an inverting amplifier 482S, a transistor M6, a current source 484S, and switches S8, S9, and S10. The transistor M6 is a P-type MOS transistor. A plurality of switches included in the sample hold circuit group 46S and the amplification unit 48S are controlled to be turned on or off based on control from the control circuit 90.

[0042] The connection relationship of the inverting amplifier 482S, the transistor M6, the current source 484S, and the switches S8, S9, and S10 is generally the same as that of the amplification unit 48N. Therefore, the differences from the amplification unit 48N will be described below.

[0043] The connection node of the second terminal of the switch S9, the current source 484S, and the source of the transistor M6 is connected to the signal line IL2. A current is input to this node from the second sample hold unit 44N. The ground terminal of the inverting amplifier 482S is connected to the ground wiring GL1. The drain of the transistor M6 forms the output terminal of the first sample hold unit 44S and is connected to the signal line IL3.

[0044] The amplification unit 48S forms an amplification circuit in which an inverting amplifier 482S (first inverting amplifier) and a source follower circuit (first source follower circuit) constituted by the current source 484S and the transistor M6 are connected in cascade. The amplification unit 48S can output a current corresponding to the difference between the current corresponding to the voltage held in the capacitances C21 to C2 N and the current input from the signal line IL2 to the signal line IL3.

[0045] While referring to FIGS. 3 to 6 with reference to each other, the outline of the operation of the sample hold unit 42 will be described. During the output period of the reset signal from time T2 to time T3 in FIG. 3, the switches S11 to S1 N , S3, S6 n+1 ~S6N , S8 is turned on. During this period, the other switches are in the off state. After that, switches S11 to S1 N , S3, S6 n+1 ~S6 N , S8 is turned off. By these operations, voltages based on the reset signal are held in capacitors C11 to C1 N , C2 n+1 ~C2 N .

[0046] After that, during the output period of the pixel signal between time T3 and time T4 in FIG. 3, switches S21 to S2 N―1 , S4, S5, S61 to S6 n , S8 are turned on. During this period, the other switches are in the off state. By this operation, capacitors C11 to C1 N are connected in parallel, and the second sample hold unit 44N outputs a current corresponding to the voltage held in capacitors C11 to C1 N to the signal line IL1. After that, switches S61 to S6 n , S8 are turned off. By these operations, voltages based on the pixel signal are held in capacitors C21 to C2 n .

[0047] After that, switches S21 to S2 N―1 , S4, S5, S71 to S7 N―1 , S9, S10 are turned on. The other switches are in the off state. By this operation, capacitors C21 to C2 N are connected in parallel, and the first sample hold unit 44S outputs a current corresponding to the difference between the current corresponding to the voltage held in capacitors C21 to C2 N and the current input from the signal line IL2 to the signal line IL3.

[0048] By the above operations, a current signal obtained by performing correction processing by correlated double sampling of the pixel signal and the reset signal can be output to the signal line IL3. Also, in the sample hold circuit group 46S, the pixel signals held in n capacitors C21 to C2 n , and the N - n capacitors C2n+1 ~C2 N The reset signal held in N and the pixel signal are weighted-averaged according to the number of capacitors. As a result, the voltage difference between the reset signal and the pixel signal is attenuated by n / N times. Therefore, the voltage range of the input signal in the column circuit can be extended.

[0049] FIG. 7 is a block diagram showing the configuration of the AD conversion circuit 52 according to the present embodiment. The AD conversion circuit 52 illustrated in the present embodiment is a delta-sigma type AD conversion circuit, but is not limited thereto. For example, the AD conversion circuit 52 may be an AD conversion circuit that compares a ramp signal and an input voltage and measures the time until the magnitude relationship is inverted using a counter. Further, the AD conversion circuit 52 may be a successive approximation type AD conversion circuit that repeatedly compares the output voltage of a DA conversion circuit and the input voltage to obtain a digital value close to the input voltage. Note that, in the present embodiment, a 1-bit AD conversion circuit is illustrated, but the number of bits is not limited thereto, and actually, AD conversion with a larger number of bits can be performed.

[0050] The AD conversion circuit 52 includes digital-to-analog conversion circuits (DA conversion circuits) 54a and 54b, capacitors Ca and Cb, a voltage-current conversion unit 56, a quantizer 58, a decimation filter DF, and buffers B1 and B2. As described above, a current signal after being processed by correlated double sampling is input to the AD conversion circuit 52 from the sample hold unit 42 via the signal line IL3.

[0051] The signal line IL3 is connected to the output terminal of the DA conversion circuit 54a, the first terminal of the capacitor Ca, and the input terminal of the voltage-current conversion unit 56. The output terminal of the voltage-current conversion unit 56 is connected to the output terminal of the DA conversion circuit 54b, the first terminal of the capacitor Cb, and the input terminal of the quantizer 58. The output terminal of the quantizer 58 is connected to the input terminal of the decimation filter DF and the input terminal of the buffer B1. The output terminal of the buffer B1 is connected to the input terminal of the DA conversion circuit 54b and the input terminal of the buffer B2. The output terminal of the buffer B2 is connected to the input terminal of the DA conversion circuit 54a. The ground terminals of the DA conversion circuits 54a and 54b, the second terminals of the capacitors Ca and Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3. The output terminal of the decimation filter DF is the output terminal of the AD conversion circuit 52.

[0052] According to the amount of current flowing through the signal line IL3 and the passage of time, charge is accumulated in the capacitor Ca. The voltage-current conversion unit 56 outputs a current signal corresponding to the potential of the first terminal of the capacitor Ca from the output terminal. In this way, the capacitor Ca functions as an integrator.

[0053] According to the amount of current output from the voltage-current conversion unit 56 and the passage of time, charge is accumulated in the capacitor Cb. In this way, the capacitor Cb and the voltage-current conversion unit 56 also function as integrators. The quantizer 58 can be a comparison circuit. The quantizer 58 compares the potential of the first terminal of the capacitor Cb with a predetermined threshold value and outputs a 1-bit digital signal indicating the comparison result. Thereby, the quantizer 58 performs 1-bit analog-to-digital conversion. Note that the quantizer 58 performs oversampling at a frequency higher than the desired sampling frequency.

[0054] The digital signal output from the quantizer 58 is input to the buffer B1. This digital signal is fed back to the DA conversion circuits 54a and 54b via the buffers B1 and B2. The DA conversion circuits 54a and 54b include a current source, switches, etc. The DA conversion circuit 54a performs digital-to-analog conversion to pass a current corresponding to the input digital signal, extracts a charge corresponding to the digital signal from the first terminal of the capacitor Ca, and passes it to the ground wiring GL3. Similarly, the DA conversion circuit 54b extracts a charge corresponding to the input digital signal from the first terminal of the capacitor Cb and passes it to the ground wiring GL3. In this way, the digital signal output from the quantizer 58 is fed back to the input side of the integrator or the quantizer 58. This feedback loop operates to reduce the quantization error in the low-frequency region.

[0055] As shown in FIG. 7, since the AD conversion circuit 52 of the present embodiment tends to have a circuit layout extending in one direction, the wiring for feedback may become long. By providing the buffers B1 and B2, the influence of voltage drop and the like caused by the long feedback wiring is reduced. However, when the influence of the feedback wiring is acceptable, the buffers B1 and B2 may not be provided.

[0056] The decimation filter DF performs a process of reducing the sampling frequency by thinning out the signal output from the quantizer 58. Thereby, the noise in the high-frequency region is reduced.

[0057] As described above, the AD conversion circuit 52 of the present embodiment employs a delta-sigma type suitable for high precision and high resolution. Thereby, a high-precision digital signal can be output.

[0058] In this embodiment, as shown in FIG. 4, the effect of sharing the ground wiring GL1 of the first sample hold unit 44S and the ground wiring GL2 of the second sample hold unit 44N will be described. Due to the operation of the circuits in the photoelectric conversion device 100 and the influence of external noise or the like, the potential of the ground wiring may fluctuate. This potential fluctuation can be a factor that reduces the accuracy of the output signal.

[0059] In this embodiment, the ground wiring GL1 of the first sample hold unit 44S and the ground wiring GL2 of the second sample hold unit 44N are shared. Therefore, the influence of the ground potential fluctuation is superimposed on the first sample hold unit 44S and the second sample hold unit 44N to the same extent. Here, the reset signal held in the second sample hold unit 44N is a signal used for correlated double sampling with the pixel signal held in the first sample hold unit 44S. Therefore, due to the potential fluctuation of the ground wiring, the influence of the noise received by the second sample hold unit 44N and the first sample hold unit 44S is reduced by performing correlated double sampling. Therefore, according to this embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0060] [Second Embodiment] The photoelectric conversion device 100 of this embodiment is a modified example in which the position where the ground wiring GL1 of the first sample hold unit 44S and the ground wiring GL2 of the second sample hold unit 44N are shared is changed from the configuration of the first embodiment. Since the other elements are the same as those in the first embodiment, the description is omitted.

[0061] FIG. 8 is a block diagram showing the circuit configuration and wiring connection of one column according to this embodiment. As shown in FIG. 8, the ground wiring GL1 of the first sample hold unit 44S and the ground wiring GL2 of the second sample hold unit 44N are shared at the node N2 in the sample hold unit 42. Although only one column is shown in FIG. 8, the node N2 where the ground wiring is shared can be provided for each column circuit.

[0062] In this embodiment, unlike the first embodiment, instead of sharing the ground wiring outside the element region R1, a node N2 for sharing is provided for each column. Since the ground wiring is shared for each unit of correlated double sampling, the effect of noise reduction can be further improved.

[0063] Note that in the configuration of the first embodiment, the ground wiring is shared at the node N1 closer to the pad P3. Also, the node N1 can be provided in common for a plurality of column circuits. In this configuration, the common impedance generated by the wiring between the node N1 and the pad P3 can be reduced. Therefore, depending on the design, the configuration of the first embodiment may be able to reduce noise in some cases. The configuration of the first embodiment and the configuration of the second embodiment can be appropriately selected in consideration of conditions such as circuit design and layout.

[0064] [Third Embodiment] The photoelectric conversion device 100 of this embodiment is a modified example in which the configuration of the ground wiring of the AD conversion circuit 52 is changed from the configuration of the first embodiment. Since the other elements are the same as those of the first embodiment, the description thereof is omitted.

[0065] FIG. 9 is a block diagram showing the circuit configuration and wiring connection of one column according to this embodiment. As shown in FIG. 9, the ground wiring GL4 (fourth potential line) of a part of the circuit of the AD conversion circuit 52 is shared with the ground wiring GL1 and the ground wiring GL2 at the node N3.

[0066] FIG. 10 is a block diagram showing the configuration of the AD conversion circuit 52 according to this embodiment. As shown in FIG. 10, the ground terminal of the DA conversion circuit 54a is connected to the ground wiring GL4. The ground terminals of the DA conversion circuit 54b, the second terminals of the capacitors Ca and Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3.

[0067] In this embodiment, the ground wiring GL3 connected to the part that performs the AD conversion operation such as the quantizer 58 in the AD conversion circuit 52 and the ground wiring GL4 of the DA conversion circuit 54a arranged on the input side of the AD conversion circuit 52 are separated. As a result, the kickback in which the potential fluctuation that may occur due to the AD conversion operation affects the input-side node can be reduced. Further, since the ground wiring GL3 is also separated from the grounds of the first sample hold unit 44S and the second sample hold unit 44N, the kickback to the first sample hold unit 44S and the second sample hold unit 44N is also reduced. Therefore, according to this embodiment, the photoelectric conversion device 100 with improved accuracy is provided.

[0068] Also, in this embodiment as well as in the first embodiment, at the node N3, the ground wiring GL1 and the ground wiring GL2 are shared. As a result, for the same reason as in the first embodiment, the influence of noise on the first sample hold unit 44S and the second sample hold unit 44N can be reduced.

[0069] [Fourth Embodiment] The photoelectric conversion device 100 of this embodiment is a modified example in which the positions where the ground wirings GL1, GL2, and GL4 are shared are changed from the configuration of the third embodiment. Since the other elements are the same as those in the third embodiment, the description thereof is omitted.

[0070] FIG. 11 is a block diagram showing the circuit configuration and wiring connection of one column according to this embodiment. As shown in FIG. 11, the ground wiring GL1, the ground wiring GL2, and the ground wiring GL4 are shared at the node N4 in the sample hold unit 42. Although only one column is shown in FIG. 11, the node N4 at which the ground wiring is shared can be provided for each column circuit.

[0071] In this embodiment, unlike the third embodiment, instead of sharing the ground wiring outside the element region R1, a node N4 for sharing is provided for each column. Since the ground wiring is shared for each unit of correlated double sampling and AD conversion, the effect of noise reduction can be further improved.

[0072] In the configuration of the third embodiment, the ground wiring is shared at the node N3 closer to the pad P3. Also, the node N3 can be provided in common for a plurality of column circuits. In this configuration, the common impedance generated by the wiring between the node N3 and the pad P3 can be reduced. Therefore, depending on the design, the configuration of the third embodiment may be able to reduce noise in some cases. The configuration of the third embodiment and the configuration of the fourth embodiment can be appropriately selected in consideration of conditions such as circuit design and layout.

[0073] [Fifth Embodiment] The photoelectric conversion device 100 of this embodiment is a modified example in which the configuration of the ground wiring GL1 of the first sample hold unit 44S and the arrangement of the pads are changed from the configuration of the third embodiment. Since the other elements are the same as those in the third embodiment, the description thereof is omitted.

[0074] FIG. 12 is a block diagram showing the circuit configuration and wiring connection of one column according to this embodiment. As shown in FIG. 12, the ground wiring GL4 of a part of the AD conversion circuit 52 is shared with the ground wiring GL2 of the second sample hold unit 44N at the node N5. The node N5 is connected to the pad P3. The ground wiring GL1 of the first sample hold unit 44S is not connected to the node N5 and is connected to the pad P5.

[0075] Also in this embodiment, similar to the third embodiment, since the ground wiring GL3 and the ground wiring GL4 are separated, the effect of noise reduction by reducing kickback can be obtained. Therefore, according to this embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0076] In addition, in FIG. 12, the ground wiring GL4 is shared with the ground wiring GL2 at the node N5, and the ground wiring GL1 is separated from these. However, the ground wiring GL4 may be shared with the ground wiring GL1, and the ground wiring GL2 may be separated from these.

[0077] [Sixth Embodiment] The photoelectric conversion device 100 of the present embodiment is a modified example in which the positions where the ground wirings GL2 and GL4 are shared are changed from the configuration of the fifth embodiment. Since the other elements are the same as those of the fifth embodiment, the description thereof is omitted.

[0078] FIG. 13 is a block diagram showing the circuit configuration and wiring connection of one row according to the present embodiment. As shown in FIG. 13, the ground wiring GL2 and the ground wiring GL4 are shared at the node N6 in the sample hold unit 42. Although only one row is shown in FIG. 13, the node N6 where the ground wirings are shared can be provided for each column circuit.

[0079] In the present embodiment, unlike the fifth embodiment, instead of sharing the ground wiring outside the element region R1, a node N6 for sharing is provided for each column. Since the ground wiring is shared for each unit of AD conversion, the effect of noise reduction can be further improved.

[0080] In the configuration of the fifth embodiment, the ground wiring is shared at the node N5 closer to the pad P3. Further, the node N5 can be provided in common for a plurality of column circuits. In this configuration, the common impedance generated by the wiring between the node N5 and the pad P3 can be reduced. Therefore, depending on the design, the configuration of the fifth embodiment may be able to reduce noise in some cases. The configuration of the fifth embodiment and the configuration of the sixth embodiment can be appropriately selected in consideration of conditions such as circuit design and layout.

[0081] In FIG. 13, the ground wiring GL4 is shared with the ground wiring GL2 at the node N6, and the ground wiring GL1 is separated from these. However, the configuration may be such that the ground wiring GL4 is shared with the ground wiring GL1 and the ground wiring GL2 is separated from these.

[0082] [Seventh Embodiment] The photoelectric conversion device 100 of the present embodiment is a modified example in which the configuration of the ground wiring in the AD conversion circuit 52 is changed from the configuration of any one of the third to sixth embodiments. Since the other elements are the same as those in the third to sixth embodiments, the description thereof is omitted.

[0083] FIG. 14 is a block diagram showing the configuration of the AD conversion circuit 52 according to the present embodiment. As shown in FIG. 14, the ground terminal of the DA conversion circuit 54a and the second terminal of the capacitor Ca are connected to the ground wiring GL4. The ground terminal of the DA conversion circuit 54b, the second terminal of the capacitor Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3.

[0084] In the present embodiment, the ground wiring GL3 connected to the portion that performs the AD conversion operation such as the quantizer 58 in the AD conversion circuit 52 is separated from the ground wiring GL4 of the second terminal of the DA conversion circuit 54a and the capacitor Ca arranged on the input side of the AD conversion circuit 52. Thereby, the kickback in which the potential fluctuation that may occur due to the AD conversion operation affects the input-side node can be reduced. Therefore, according to the present embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0085] As separation methods of ground wirings GL3 and GL4 in the AD conversion circuit 52, two examples in FIGS. 10 and 14 are shown, but the present invention is not limited thereto. For example, the ground wiring may be separated at a node between the ground terminal of the voltage-current conversion unit 56 and the ground terminal of the DA conversion circuit 54b. Also, the ground wiring may be separated at a node between the ground terminal of the DA conversion circuit 54b and the second terminal of the capacitor Cb. Further, the ground wiring may be separated at a node between the second terminal of the capacitor Cb and the ground terminal of the quantizer 58. Thus, if at least the ground terminal of the quantizer 58 and the ground terminal of the element at a stage earlier than that are separated, an effect of reducing kickback can be obtained.

[0086] [Eighth Embodiment] The photoelectric conversion device 100 of the present embodiment further specifies the arrangement of the sample hold unit 42 described in the first embodiment. The configuration of the sample hold unit 42 described in the present embodiment is applicable to any of the first to seventh embodiments, and descriptions of overlapping parts with the first to seventh embodiments are omitted.

[0087] FIG. 15 is a block diagram showing the arrangement of the sample hold unit 42 according to the eighth embodiment. In FIG. 15, sample hold circuits 462N1 to 462N N , amplification unit 48N, sample hold circuits 462S1 to 462S N and the arrangement of the amplification unit 48S are schematically shown. Since the connection relationship of each part is the same as that shown in FIGS. 5 and 6, the description thereof is omitted. As shown in FIG. 15, the column signal line 16, signal lines IL1, IL2, and IL3 extend in the first direction (the vertical direction in FIG. 15). And, as shown in FIG. 15, the sample hold circuits 462N1 to 462N N , amplification unit 48N, sample hold circuits 462S1 to 462S N and each block of the amplification unit 48S also extend in the first direction in this order. Thus, by arranging each circuit and the signal lines in parallel, these elements can be efficiently laid out.

[0088] [Embodiment 9] The imaging system according to the ninth embodiment of the present invention will be described with reference to FIG. 16. FIG. 16 is a block diagram showing a schematic configuration of the imaging system according to the present embodiment.

[0089] The photoelectric conversion device 100 described in the above-described first to eighth embodiments is applicable to various photoelectric conversion systems. An example of a photoelectric conversion system is an imaging system. Examples of imaging systems to which the photoelectric conversion device 100 can be applied include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and the like. Further, a camera module including an optical system such as a lens and a photoelectric conversion device is also included in the imaging system. FIG. 16 exemplifies a block diagram of a digital still camera as an example of these.

[0090] The imaging system 200 illustrated in FIG. 16 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, a diaphragm 204 for variably controlling the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and the diaphragm 204 are an optical system that condenses light onto the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to eighth embodiments, and converts the optical image formed by the lens 202 into image data.

[0091] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output from the imaging device 201. Further, the signal processing unit 208 performs operations of outputting image data by performing various corrections and compressions as necessary.

[0092] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out to / from the recording medium 214. Note that the recording medium 214 may be built in the imaging system 200 or may be detachable.

[0093] The imaging system 200 further includes an overall control and arithmetic unit 218 that performs various operations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from the outside, and the imaging system 200 may have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0094] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0095] As described above, according to this embodiment, an imaging system to which the photoelectric conversion device 100 according to the first to eighth embodiments is applied can be realized.

[0096] [Embodiment 10] The imaging system and the moving body according to the tenth embodiment of the present invention will be described with reference to FIG. 17. FIG. 17 is a diagram showing the configuration of the imaging system and the moving body according to this embodiment.

[0097] FIG. 17(a) shows an example of an imaging system for an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to eighth embodiments above. The imaging system 300 includes an image processing unit 312 that performs image processing on a plurality of pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of a parallax image) from the plurality of pieces of image data acquired by the imaging system 300. Further, the imaging system 300 includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means for acquiring distance information to an object. That is, the distance information is information related to parallax, defocus amount, distance to an object, and the like. The collision determination unit 318 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicatedly designed hardware, or may be realized by a software module. Further, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or may be realized by a combination of these.

[0098] The imaging system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the imaging system 300 is connected to a control ECU 330 which is a control device that outputs a control signal for generating a braking force for the vehicle based on the determination result of the collision determination unit 318. Further, the imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, when the collision determination unit 318 determines that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and reduce damage, such as applying the brakes, returning the accelerator, and suppressing the engine output. The alarm device 340 warns the user by sounding an alarm such as a sound, displaying alarm information on the screen of a car navigation system, or applying vibration to the seat belt or steering wheel.

[0099] In the present embodiment, the imaging system 300 images the surroundings of the vehicle, for example, the front or the rear. FIG. 17(b) shows the imaging system when imaging the front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends an instruction to the imaging system 300 or the imaging device 310. With such a configuration, the ranging accuracy can be further improved.

[0100] In the above, an example of controlling so as not to collide with other vehicles has been described, but it is also applicable to control for automatically driving while following other vehicles and control for automatically driving so as not to deviate from the lane. Further, the imaging system is not limited to vehicles such as the host vehicle, and can be applied to moving bodies (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving bodies but also to devices that widely use object recognition, such as an advanced road traffic system (ITS).

[0101] [Modified Embodiment] The present invention is not limited to the above-described embodiments and can be variously modified. For example, an example in which a part of the configuration of any one of the embodiments is added to another embodiment or an example in which a part of the configuration of another embodiment is replaced is also an embodiment of the present invention.

[0102] In addition, the imaging systems described in the above-described ninth and tenth embodiments are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and the imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in FIGS. 16 and 17.

[0103] In the above-described embodiments, two types of examples are shown: an example in which a node to which a ground wiring is shared is provided corresponding to each of the column circuits, and an example in which it is provided in common for a plurality of column circuits. However, the present invention is not limited to this. For example, when any two columns out of a plurality of columns are defined as the first column and the second column, the ground wiring of the first column may be shared with the ground wiring of the second column. Here, the first column and the second column may be adjacent columns or non-adjacent columns. Examples of non-adjacent columns include cases where both the first column and the second column are even-numbered columns, or cases where both the first column and the second column are odd-numbered columns. As another example, the first column and the second column may be columns in which color filters of the same color are arranged in the pixel 12. As still another example, in a configuration in which column circuits extend both upward and downward from the pixel array 10, the first column and the second column may be columns arranged in different upward and downward directions.

[0104] In addition, in the above-described embodiments, various examples in which ground wirings for supplying a ground potential are shared or separated are given, but the present invention is not limited to this. For example, in the same manner as the above-described ground wiring, a power supply wiring for supplying a power supply potential may be shared or separated, and a reference potential wiring for supplying a reference potential may be shared or separated. The same effects can be obtained in these examples. The ground wiring, the power supply wiring, and the reference potential wiring may more generally be called potential lines.

[0105] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0106] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0107] 10 Pixel Array 12 pixels 44S 1st sample hold section 44N Second sample and hold section 52 AD conversion circuit 100 Photoelectric conversion device GL1, GL2, GL3 Ground wiring

Claims

1. A photoelectric conversion device having a pixel array in which a plurality of pixels are arranged to form a plurality of columns, and column circuits arranged corresponding to each of the plurality of columns of the pixel array, wherein the column circuit includes a first sample-and-hold unit that includes a cascade-connected first inverting amplifier and a first source follower circuit and holds a signal output from pixels in the corresponding column, an analog-to-digital conversion circuit that converts an analog signal based on the signal into a digital signal, a first potential line that supplies a drive potential to at least one of the first inverting amplifier and the first source follower circuit, and a third potential line that supplies a drive potential to a part of the analog-to-digital conversion circuit, and the first potential line and the third potential line are separated in the photoelectric conversion device. A photoelectric conversion device characterized by the above.

2. The analog-to-digital conversion circuit is a delta-sigma type including a digital-to-analog conversion circuit, an integrator, and a quantizer, the third potential line supplies a drive potential to the quantizer, the column circuit further has a fourth potential line that supplies a drive potential to the digital-to-analog conversion circuit, and the third potential line and the fourth potential line are separated in the photoelectric conversion device. The photoelectric conversion device according to claim 1, characterized by the above.

3. The first potential line and the fourth potential line are shared in the photoelectric conversion device. The photoelectric conversion device according to claim 2, characterized by the above.

4. Nodes at which the first potential line and the fourth potential line are shared are provided corresponding to each of the plurality of column circuits. The photoelectric conversion device according to claim 3, characterized by the above.

5. Nodes at which the first potential line and the fourth potential line are shared are commonly provided for the plurality of column circuits. The photoelectric conversion device according to claim 3, characterized by the above.

6. The first potential line and the fourth potential line included in the column circuit of the first column among the plurality of columns are shared with the first potential line and the fourth potential line included in the column circuit of the second column among the plurality of columns. The photoelectric conversion device according to claim 3, characterized by the above.

7. The third potential line supplies a drive potential to the integrator. The photoelectric conversion device according to any one of claims 2 to 6, characterized by the above.

8. The fourth potential line supplies a drive potential to the integrator. The photoelectric conversion device according to any one of claims 2 to 6, characterized by the above.

9. ​ ​ ​ ​ The first sample hold unit holds a first signal based on incident light to pixels in the corresponding column, The column circuit, includes a second inverting amplifier and a second source follower circuit connected in series, and a second sample hold unit that holds a second signal based on the reset state of pixels in the corresponding column, a second potential line that supplies a driving potential to at least one of the second inverting amplifier and the second source follower circuit, further has, the first potential line and the second potential line are shared in the photoelectric conversion device The photoelectric conversion device according to any one of claims 1 to 8, characterized in that.

10. The driving potential is any one of a power supply potential, a ground potential, and a reference potential The photoelectric conversion device according to any one of claims 1 to 9, characterized in that.

11. A photoelectric conversion device according to any one of claims 1 to 10, signal processing means for processing a signal output from the photoelectric conversion device, A photoelectric conversion system characterized by comprising.

12. A moving body, A photoelectric conversion device according to any one of claims 1 to 10, distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device, control means for controlling the moving body based on the distance information, A moving body characterized by comprising.

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