Super junction semiconductor device

Abstract

To provide a super junction semiconductor device capable of mitigating an electric field near a channel stopper and preventing a decrease in breakdown voltage in an edge termination region.SOLUTION: A super junction semiconductor device 40 has an active region 30 and a termination structure portion 31. An active region 30 and the termination structure portion 31 have a first conductivity type of semiconductor substrate, a first conductivity type of a first semiconductor layer and a parallel pn structure 19 in which a striped first conductivity type of first column 4 and a striped second conductivity type of second column 3 are repeatedly arranged alternately in a direction parallel to the front surface. The termination structure portion 31 has a channel stopper on the surface layer of the parallel pn structure 19, and in the parallel pn structure 19, the second column 3 is separated from the channel stopper by 0.1 μm or more in the longitudinal direction of the second column 3.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This invention relates to a superjunction semiconductor device.

Background Art

[0002] In a normal n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), among the plurality of semiconductor layers formed in a semiconductor substrate, the n-type conductive layer (drift layer) is the semiconductor layer with the highest resistance. The electrical resistance of this n-type drift layer greatly affects the on-resistance of the entire vertical MOSFET. Reduction of the on-resistance of the entire vertical MOSFET can be achieved by thinning the thickness of the n-type drift layer and shortening the current path.

[0003] However, a vertical MOSFET also has a function of maintaining a breakdown voltage because in the off state, the depletion layer spreads up to the high-resistance n-type drift layer. For this reason, when the n-type drift layer is thinned to reduce the on-resistance, the spread of the depletion layer in the off state becomes shorter, so it easily reaches the breakdown electric field strength at a low applied voltage, and the breakdown voltage decreases. On the other hand, in order to increase the breakdown voltage of a vertical MOSFET, it is necessary to increase the thickness of the n-type drift layer, and the on-resistance increases. Such a relationship between on-resistance and breakdown voltage is called a trade-off relationship, and it is generally difficult to improve both of them in the trade-off relationship.

[0004] As a structure of a semiconductor device for solving the above problems, a superjunction (SJ: Super Junction) structure is known. For example, a MOSFET having a superjunction structure (SJ structure) (hereinafter, SJ-MOSFET) is known.

[0005] FIG. 24 is a plan view showing the structure of a conventional superjunction semiconductor device. As shown in FIG. 24, the SJ-MOSFET 140 includes an active region 130 and an edge termination region 131 surrounding the periphery of the active region 130. The active region 130 is a region through which current flows when in the on state. The edge termination region 131 is a region that relaxes the electric field on the front surface side of the substrate of the drift region and maintains the breakdown voltage.

[0006] The SJ-MOSFET 140 has a parallel structure (hereinafter referred to as a parallel pn structure 119) in which p-type column regions 103 and n-type column regions 104 are alternately and repeatedly arranged in the active region 130 and the edge termination region 131. In the parallel pn structure 119, by making the amounts of impurities contained in the p-type column region 103 and the n-type column region 104 substantially equal, a pseudo non-doped layer can be created in the off state to achieve a high breakdown voltage.

[0007] FIG. 25 is a cross-sectional view showing the structure of a conventional superjunction semiconductor device. FIG. 25(a) is a Y-Y' cross-sectional view of FIG. 24. FIG. 25(b) is an X-X' cross-sectional view of FIG. 24. FIG. 25(c) is an X1-X1' cross-sectional view of FIG. 24. Also, FIG. 25(b) is a cross-sectional view of the portion A in FIG. 25(a). FIG. 25(c) is a cross-sectional view of the portion B in FIG. 25(a).

[0008] As shown in FIGS. 25(a) to 25(c), the SJ-MOSFET 140 uses a wafer in which an n-type drift layer 102 is grown on an n-type semiconductor substrate 101 having a high impurity concentration. In the n-type drift layer 102, a p-type column region 103 that penetrates the n-type drift layer 102 from the wafer surface, extends in a direction perpendicular to the main surface of the substrate, and has a narrow width in a plane parallel to the main surface of the substrate, and an n-type column region 104 sandwiched between the p-type column regions 103 are alternately and repeatedly arranged in a plane parallel to the main surface of the substrate, having a parallel pn structure 119. In FIGS. 25(a) and 25(b), the p-type column region 103 reaches the n + -type semiconductor substrate 101, but it does not have to reach the n + -type semiconductor substrate 101. + It is not necessary to reach the type semiconductor substrate 101.

[0009] In the active region 130, a p-type base region 106 is provided on the parallel pn structure 119 of the SJ-MOSFET 140. Inside the p-type base region 106, an n + -type source region 107 is provided. A p + -type contact region may be provided inside the p-type base region 106. Further, a trench 118 is provided that penetrates the p-type base region 106 and the n + -type source region 107 and reaches the p-type column region 103. An n + -type source region 107 is arranged so as to be in contact with the side surface of this trench 118.

[0010] Also, inside the parallel pn structure 119, a first p + -type base region 114 is selectively provided so as to cover the entire bottom surface of the trench 118. On the surface layer opposite to the n + -type semiconductor substrate 101 side of the parallel pn structure 119, a second p + -type base region 115 is selectively provided.

[0011] The inner wall surface of the trench 118 is covered with a gate insulating film 109 formed of an oxide film or the like, and the inside of the trench 118 is filled with a gate electrode 110 formed on the surface of the gate insulating film 109. In this way, a trench gate structure is configured. Also, an ohmic electrode (not shown) is in electrical contact with the p-type base region 106 and the n + -type source region 107 through a contact hole formed in an interlayer insulating film (not shown).

[0012] And on the back surface side of the n + -type semiconductor substrate 101, a back surface electrode (not shown) electrically connected to the n + -type semiconductor substrate 101 is formed.

[0013] In the edge termination region 131, the p-type base region 106, the second p +The type base region 115 is removed, and a step (recessed on the drain side) is formed with the edge termination region 131 lower than the active region 130, and the parallel pn structure 119 is exposed on the bottom surface of the step. Note that this step is for removing the p-type base region 106 in the edge termination region 131 when the p-type base region 106 is formed by epitaxial growth, and is not necessary when the p-type base region 106 is formed by ion implantation.

[0014] Also, in the edge termination region 131, a JTE structure in which a plurality of p-type regions (here, two, the first JTE region 120 and the second JTE region 121) are arranged adjacent to each other is provided. Further, an n-type region 122 that functions as a channel stopper is provided outside the JTE structure (on the chip end side). + is provided.

[0015] The first JTE region 120 and the second JTE region 121 are respectively selectively provided at the portions of the parallel pn structure 119 that are exposed on the bottom surface of the step. When a high voltage is applied, the lateral high voltage outside the active region 130 is ensured by the pn junction between the first JTE region 120, the second JTE region 121, and the n-type column region 104.

[0016] It is known that the SJ structure has a low avalanche tolerance in a design where the impurity amounts contained in the p-type column region 103 and the n-type column region 104 are substantially equal, the charge balance is achieved, and the static breakdown voltage is the highest. And it is known that the avalanche tolerance is high in a state slightly deviated from the charge balance, particularly in a (p-rich) structure where the charge amount of the p-type column region 103 is larger than the charge amount of the n-type column region 104. Also, in the depth direction of the SJ structure, by making the surface side p-rich and the substrate side (drain side) a (n-rich) structure where the charge amount of the n-type column region 104 is larger than the charge amount of the p-type column region 103, the margin for charge amount variation is improved or the avalanche tolerance is improved.

[0017] Also, when turning off the MOSFET and the SJ structure is depleted, the average positive charge density ρ(x) at a predetermined depth position of the SJ structure is represented by an upwardly convex and rightward rising curve, and there is a known MOSFET that can make the variation in switching characteristics when turning off smaller than before (see, for example, Patent Document 1 below). Further, in the longitudinal direction of the p-type column region, the p-type column region does not reach the channel stopper, and there is a known semiconductor device in which the p-type column region is not provided under the channel stopper in the direction in which the n-type column region and the p-type column region are arranged (see, for example, Patent Document 2 below).

[0018] Also, in the peripheral region, there is a known semiconductor device provided with a charge balance change region in which the amount of N-type charge in the superjunction structure gradually becomes larger than the amount of P-type charge as it goes in the outer peripheral direction of the cell region (see, for example, Patent Document 3 below). Further, in addition to an n-type drift layer that conducts drift current in the on state and is depleted in the off state and a p-type drift layer that is depleted in the off state, a second n-type drift layer and a second p-type drift layer formed in at least one of two directions orthogonal to each other are provided in the junction termination region part, and there is a known semiconductor device (see, for example, Patent Document 4 below). Further, there is a known semiconductor device that forms a final edge structure including a plurality of N-type stacked semiconductor layers and two columns inserted in a plurality of stacked semiconductor layers composed of a stack of a plurality of P-type doped regions, and the column closer to the high-voltage semiconductor device is deeper than the column farther from the device (see, for example, Patent Document 5 below). Further, there is a known semiconductor device having a superjunction structure in which pairs of p-type epitaxial buried layers and n-type epitaxial layers are alternately arranged, a p-type lateral RESURF region is provided at the termination part, and each p-type epitaxial buried layer at the termination part has no p-type lateral RESURF region in at least a part of the surface part and no overlap (see, for example, Patent Document 6 below).

Prior Art Documents

Patent Documents

[0019]

Patent Document 1

[0020] However, when the surface part becomes p-rich and a JTE structure is formed in the p-type column region 103, it becomes even more p-rich, making it difficult for the p-type column region 103 to be depleted. There is a risk that the electric field will concentrate easily between the p-type column region 103 and the channel stopper, resulting in a decrease in breakdown voltage.

[0021] Also, since the p-type column region 103 exists on the outer peripheral side of the edge termination region 131, when a relatively low voltage at which the p-type column region 103 is not completely depleted causes a neutral region of the source potential to exist in the p-type column region 103, there is a concern that a high electric field will be applied between the drain potential and the channel stopper, resulting in a decrease in breakdown voltage.

[0022] Even in such a case, when a higher voltage is applied, the p-type column region 103 is completely depleted, so the electric field is relaxed. However, there is a concern that an avalanche current will flow during the voltage rise process. In particular, this problem is more likely to occur when the p-rich is achieved for improving the avalanche tolerance or when the surface side is made p-rich.

[0023] FIG. 26 is a diagram showing the spread of the depletion layer at a low voltage (Vds1) in the edge termination region of a conventional superjunction semiconductor device. FIG. 26(a) is a plan view, and FIG. 26(b) is a cross-sectional view taken along the line X-X' of FIG. 26(a). Here, the depletion layers on the n-type column region 104 side and the channel stopper side are not shown. The same applies to FIGS. 27(a) to 28(b). As shown in FIGS. 26(a) and 26(b), at a low drain-source voltage Vds1, the source-drain voltage is applied to the depletion layer 132 extending from the junction between the drain potential channel stopper (n + -type region 122) and the p-type column region 103. The breakdown voltage at this time is the breakdown voltage of the junction between the channel stopper (n + -type region 122) and the p-type column region 103.

[0024] FIG. 27 is a diagram showing the spread of the depletion layer at a medium voltage (Vds2) in the edge termination region of a conventional superjunction semiconductor device. FIG. 27(a) is a plan view, and FIG. 27(b) is a cross-sectional view taken along the line X-X' of FIG. 27(a). As shown in FIGS. 27(a) and 27(b), at a higher voltage Vds2, the depletion layer 132 extending from the junction between the p-type column region 103 and the n-type column region 104 is connected to the depletion layer 132 extending from the junction between the channel stopper (n + -type region 122) and the p-type column region 103.

[0025] FIG. 28 is a diagram showing the spread of the depletion layer at a high voltage (Vds3) in the edge termination region of a conventional superjunction semiconductor device. FIG. 28(a) is a plan view, and FIG. 28(b) is a cross-sectional view taken along the line X-X' of FIG. 28(a). As shown in FIGS. 28(a) and 28(b), if the voltage Vds2 is below the breakdown voltage of the junction between the channel stopper (n + -type region 122) and the p-type column region 103, when the drain-source voltage is increased to Vds3, the depletion layer 132 extending from the junction between the p-type column region 103 and the n-type column region 104 further spreads, and the distance between the neutral region 133 and the channel stopper (n + -type region 122) increases, so it does not break down at a low voltage, but at a voltage lower than Vds2, the channel stopper (n +When the junction breakdown voltage between the p-type region 122 and the p-type column region 103 is exceeded, breakdown occurs at a low voltage. Problems are particularly likely to occur when the p-type region is made p-rich to increase the avalanche breakdown voltage or when the p-type region is made p-rich on the surface side.

[0026] Also, Figure 29 is a diagram showing the breakdown location at high temperature (175°C) of a 1200V class SJ-SiCMOSFET. Figures 29(a) and 29(b) are examples of different chips, and the breakdown location can be identified by observing light emission from the surface when the chip is +50% p-rich and at high temperature (175°C).

[0027] As shown by the arrow A in FIG. 29( a ), the first JTE region 120 is annular and surrounds the active region 130 , and the second JTE region 121 is annular and further surrounds the active region 130 . + It can be seen that light is emitted from the p-type column region 103 in the portion in contact with the n-type region 122. Also, as shown by the arrow B in FIG. 29(b), the n-type column region 103 outside the first JTE region 120 and the second JTE region 121 + It can be seen that light is emitted along the p-type region 122, and also outside the p-type column region 103. Also, as shown in Figures 29(a) and 29(b), it can be seen that light is not emitted along the top and bottom edges of the chip, but is emitted in the left and right directions of the chip, that is, at the longitudinal ends of the p-type column region 103. This is because + Since the p-type column region 103 overlapping with the drain region 122 is not directly connected to the source potential, the p-type column region 103 becomes floating due to the progress of depletion of the JTE regions 120, 121 at a low voltage, and even if a neutral region exists in the p-type column region 103, its potential is between the drain potential and the source potential, so no breakdown occurs.

[0028] In this way, in the structure of the SJ-MOSFET 140, the breakdown voltage decreases at high temperatures, and in the state where the breakdown voltage is decreased, the p-type column region 103 and the high concentration n +The electric field concentrates at the location where the p-type region 122 is in contact, resulting in breakdown. In SiC, Al is used as a p-type impurity, and Al has the shallowest acceptor level as a p-type. Also, in SiC, deep electron traps and hole traps exist, and it is known that a large number of deep electron traps and deep hole traps are generated particularly by Al ion implantation. For this reason, it is considered that at room temperature, the depletion layer shrinks due to the majority carriers trapped in the deep traps being detrapped at high temperatures.

[0029] An object of the present invention is to provide a superjunction semiconductor device that can relax the electric field near the channel stopper and prevent a decrease in breakdown voltage in the edge termination region in order to solve the problems caused by the above-described prior art.

Means for Solving the Problems

[0030] In order to solve the above problems and achieve the object of the present invention, the superjunction semiconductor device according to the present invention has the following features. The superjunction semiconductor device has an active region through which current flows and a termination structure portion disposed outside the active region and having a breakdown voltage structure formed therein. The active region and the termination structure portion include a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, which is provided on the front surface of a semiconductor substrate of the first conductivity type, and a parallel pn structure in which stripe-shaped first columns of the first conductivity type and stripe-shaped second columns of the second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface, which is provided on the surface of the first semiconductor layer. The termination structure portion includes a channel stopper disposed so as to surround the parallel pn structure in a plan view. The second column of the parallel pn structure is provided apart from the channel stopper in the longitudinal direction of the second column. At an end portion in the longitudinal direction of the second column of the parallel pn structure, the product of the width of the second column and the impurity concentration of the second column is the same as or greater than the product of the width of the first column and the impurity concentration of the first column, and in the longitudinal direction of the second column, the second column and the channel stopper are separated by 0.1 μm or more. The second column is implanted with impurities of the second conductivity type, and the activation rate of the implanted impurities is greater than 70% and less than or equal to 90%.

[0031] In order to solve the above-described problems and achieve the object of the present invention, a superjunction semiconductor device according to the present invention has the following features. The superjunction semiconductor device includes an active region through which current flows, and a termination structure portion disposed outside the active region and having a breakdown voltage structure formed therein. The active region and the termination structure portion include a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the front surface of a semiconductor substrate of the first conductivity type, and a parallel pn structure provided on the surface of the first semiconductor layer, in which stripe-shaped first columns of the first conductivity type and stripe-shaped second columns of the second conductivity type are repeatedly arranged alternately in a direction parallel to the front surface. The termination structure portion includes a channel stopper disposed so as to surround the parallel pn structure in a plan view. The second column of the parallel pn structure is provided at a distance from the channel stopper in the longitudinal direction of the second column. At an end portion in the longitudinal direction of the second column of the parallel pn structure, the product of the width and the impurity concentration of the second column is larger than the product of the width and the impurity concentration of the first column, the width of the second column is +50% or less with respect to the width of the first column, and in the longitudinal direction of the second column, the second column and the channel stopper are separated by 0.4 μm or more.

[0032] Further, in the superjunction semiconductor device according to the present invention, in the above-described invention, the distance at which the second column of the parallel pn structure is separated from the channel stopper in the longitudinal direction of the second column directly connected to the surface electrode potential is uniform in a straight portion of the channel stopper, and is the same as or longer than the distance of the straight portion at a corner portion of the channel stopper.

[0033] Further, in the superjunction semiconductor device according to the present invention, in the above-described invention, each of the end portions in the longitudinal direction of the second column of the parallel pn structure is inclined in accordance with the curvature of the channel stopper at a corner portion of the channel stopper.

[0034] Further, in the superjunction semiconductor device according to this invention, in the above-described invention, the active region includes a second semiconductor layer of a second conductivity type provided on the surface side of the parallel pn structure, a first semiconductor region of a first conductivity type selectively provided on the surface layer of the second semiconductor layer, a gate insulating film provided on the surface side of the second semiconductor layer and in contact with the second semiconductor layer, and a gate electrode provided on the surface side opposite to the surface in contact with the second semiconductor layer of the gate insulating film.

[0035] Further, in the superjunction semiconductor device according to this invention, in the above-described invention, the first column and the second column of the parallel pn structure do not reach the semiconductor substrate.

[0036] Further, in the superjunction semiconductor device according to this invention, in the above-described invention, the semiconductor substrate is made of a wide bandgap semiconductor.

[0037] Further, in the superjunction semiconductor device according to this invention, in the above-described invention, the channel stopper is of a first conductivity type.

[0038] Further, in the superjunction semiconductor device according to this invention, in the above-described invention, the semiconductor substrate is a silicon carbide semiconductor, the first conductivity type is an n-type formed by adding nitrogen to the silicon carbide semiconductor, and the second conductivity type is a p-type formed by adding aluminum to the silicon carbide semiconductor.

[0039] According to the above-described invention, in the p-type column region (the second column of the second conductivity type) in the terminal region second parallel pn structure, n +Since it is separated from the p-type region (channel stopper), the amount of p-type impurities in the second parallel pn structure in the terminal region is made less than the amount of p-type impurities in the active region parallel pn structure and the first parallel pn structure in the terminal region. As a result, it is possible to prevent the electric field from concentrating at the portion where the channel stopper and the p-type column region overlap in the state where the neutral region remains in the edge terminal region with a low voltage, relax the electric field near the channel stopper, and prevent a decrease in the breakdown voltage in the edge terminal region.

Effect of the Invention

[0040] According to the superjunction semiconductor device of the present invention, there is an effect that the electric field near the channel stopper can be relaxed and a decrease in the breakdown voltage in the edge terminal region can be prevented.

Brief Description of the Drawings

[0041]

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Embodiments for Carrying Out the Invention

[0042] With reference to the accompanying drawings, a preferred embodiment of the superjunction semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, for layers and regions preceded by n or p, it means that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layers and regions to which they are not attached, respectively. When the notations of n and p including + and - are the same, it indicates that they have similar concentrations, but the concentrations are not necessarily equal. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same configurations, and redundant descriptions are omitted.

[0043] (Embodiment 1) The superjunction semiconductor device 40 according to the present invention is configured using a wide-bandgap semiconductor. In Embodiment 1, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as the wide-bandgap semiconductor will be described by taking a superjunction MOSFET as an example.

[0044] FIG. 1 is a plan view showing the structure of the superjunction semiconductor device according to Embodiment 1. As shown in FIG. 1, the SJ-MOSFET 40 includes an active region 30 and an edge termination region 31 surrounding the periphery of the active region 30. In FIG. 1, the region inside the dotted line C is the active region 30, and the region between the dotted line C and the dotted line D is the edge termination region 31.

[0045] The SJ-MOSFET 40 has a parallel structure (hereinafter referred to as a parallel pn structure 19) in which p-type column regions 3 and n-type column regions 4 are alternately and repeatedly arranged in the active region 30 and the edge termination region 31. In the parallel pn structure 19, by making the amount of impurities contained in the p-type column region 3 and the n-type column region 4 substantially equal to achieve charge balance, a pseudo non-doped layer can be created in the off state to increase the breakdown voltage.

[0046] The parallel pn structure 19 is composed of an active region parallel pn structure 19a, a first parallel pn structure 19b in the termination region, and a second parallel pn structure 19c in the termination region. The first parallel pn structure 19b in the termination region is a portion of the parallel pn structure 19 on the active region 30 side in the longitudinal direction (x direction) of the p-type column region 3 and the n-type column region 4, and the second parallel pn structure 19c in the termination region is a portion of the parallel pn structure 19 on the outer peripheral side in the longitudinal direction (x direction).

[0047] FIG. 2 is a cross-sectional view of FIG. 1 showing the structure of the superjunction semiconductor device according to Embodiment 1. FIG. 2(a) is a Y-Y' cross-sectional view of FIG. 1. FIG. 2(b) is an X-X' cross-sectional view of FIG. 1. FIG. 2(c) is an X1-X1' cross-sectional view of FIG. 1. Further, FIG. 2(b) is a cross-section of the portion A of FIG. 2(a), and FIG. 2(c) is a cross-section of the portion B of FIG. 2(a). C and D in FIGS. 2(a) to 2(c) correspond to the positions of the dotted lines C and D in FIG. 1.

[0048] FIGS. 2(a) to 2(c) show a superjunction semiconductor device incorporating two unit cells (functional units of the element), but an actual superjunction semiconductor device incorporates more than two unit cells. The superjunction semiconductor device 40 shown in FIGS. 2(a) to 2(c) is a superjunction MOSFET having a MOS gate on the front surface (the surface on the p-type base region 6 side) of a semiconductor substrate made of silicon carbide (silicon carbide substrate: semiconductor chip).

[0049] The silicon carbide substrate is formed by epitaxially growing a silicon carbide layer to be an n-type drift layer 2 on the first main surface (front surface) of an n-type semiconductor substrate (semiconductor substrate of the first conductivity type) 1. + The MOS gate is composed of a p-type base region (second semiconductor layer of the second conductivity type) 6, an n-type source region (first semiconductor region of the first conductivity type) 7, a gate insulating film 9, and a gate electrode 10. +

[0050] ​The n-type drift layer 2 is provided with a parallel pn structure 19. The parallel pn structure 19 is formed by alternately and repeatedly joining a p-type column region (a second semiconductor region of the second conductivity type) 3 and an n-type region (n-type column region 4) sandwiched between the p-type column regions 3. The p-type column region 3 penetrates the n-type drift layer 2 from the bottom surface of the p-type base region 6 (the surface on the side of the n-type semiconductor substrate 1) and reaches the surface of the n-type semiconductor substrate 1. As shown in FIG. 1, the planar shapes of the p-type column region 3 and the n-type column region 4 are stripe-shaped (rectangular). + type semiconductor substrate 1 side surface), through the n-type drift layer 2, and reaches the surface of the n-type semiconductor substrate 1. As shown in FIG. 1, the planar shapes of the p-type column region 3 and the n-type column region 4 are stripe-shaped (rectangular). + type semiconductor substrate 1 side surface), through the n-type drift layer 2, and reaches the surface of the n-type semiconductor substrate 1. As shown in FIG. 1, the planar shapes of the p-type column region 3 and the n-type column region 4 are stripe-shaped (rectangular).

[0051] A p-type base region 6 is provided on the surface layer on the source side (ohmic electrode side) of the n-type drift layer 2. A trench structure is formed on the first main surface side (p-type base region 6 side) of the silicon carbide substrate. Specifically, the trench 18 penetrates the p-type base region 6 from the surface on the side opposite to the n-type semiconductor substrate 1 side (the first main surface side of the silicon carbide substrate) and reaches the p-type column region 3. Along the inner wall of the trench 18, a gate insulating film 9 is formed on the bottom and side walls of the trench 18, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 18. The gate electrode 10 is insulated from the n-type column region 4 and the p-type base region 6 by the gate insulating film 9. A part of the gate electrode 10 may protrude from above the trench 18 (the first main surface side) to the ohmic electrode side. + type semiconductor substrate 1 side surface), through the n-type drift layer 2, and reaches the surface of the n-type semiconductor substrate 1. As shown in FIG. 1, the planar shapes of the p-type column region 3 and the n-type column region 4 are stripe-shaped (rectangular).

[0052] A first p + type base region 14 may be provided under the trench 18, and the width of the first p + type base region 14 may be wider than the width of the trench 18. A second p + type base region 15 may be selectively provided on the surface layer on the side opposite to the n-type semiconductor substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate) so as to be connected to the p-type base region 6. The first p + type base region 14 and the second p + type base region 15 are doped with, for example, aluminum. + type base region 15 are doped with, for example, aluminum.

[0053] First p + The depth position of the drain side end of the base region 14 of the first p-type and the base region 15 of the second p-type + is such that the pn junction between the base region 14 of the first p-type, the base region 15 of the second p-type, and the n-type column region 4 is at a position deeper on the drain side than the bottom surface of the trench 18, and can be variously changed according to the design conditions. The base region 14 of the first p-type + and the base region 15 of the second p-type + can prevent a high electric field from being applied to the gate insulating film 9 at the portion along the bottom surface of the trench 18. The base region 14 of the first p-type + and the base region 15 of the second p-type + can prevent a high electric field from being applied to the gate insulating film 9 at the portion along the bottom surface of the trench 18.

[0054] Inside the p-type base region 6, an n-type source region 7 is selectively provided on the main surface side of the substrate. Also, a p-type contact region (not shown) may be selectively provided. In this case, the n-type source region 7 + and the p-type contact region may be in contact with each other. The depth of the p-type contact region may be shallower or deeper than, for example, the n-type source region 7. Also, in the depth direction (x-axis direction) of the trench 18, the p-type contact region + and the n-type source region 7 are provided side by side. + and the p-type contact region + may be in contact with each other. The depth of the p-type contact region may be shallower or deeper than, for example, the n-type source region 7. Also, in the depth direction (x-axis direction) of the trench 18, the p-type contact region + and the n-type source region 7 are provided side by side. + and the p-type contact region may be shallower or deeper than, for example, the n-type source region 7. Also, in the depth direction (x-axis direction) of the trench 18, the p-type contact region + and the n-type source region 7 are provided side by side. + and the n-type source region 7 are provided side by side.

[0055] The interlayer insulating film (not shown) is provided so as to cover the gate electrode 10 embedded in the trench 18 on the entire main surface side of the silicon carbide substrate. The ohmic electrode (not shown) is in contact with the n-type source region 7 + and the p-type base region 6 through a contact hole opened in the interlayer insulating film. When a p-type contact region is provided, the n-type source region 7 + and the p-type contact region + and the p-type contact region +It is in contact with the type contact region. The ohmic electrode is electrically insulated from the gate electrode 10 by an interlayer insulating film. A source electrode pad (not shown) is provided on the ohmic electrode. A barrier metal (not shown) for preventing the diffusion of metal atoms from the ohmic electrode toward the gate electrode 10 side may be provided between the ohmic electrode and the interlayer insulating film.

[0056] n + A back electrode (not shown) is provided on the second main surface (the back surface, i.e., the back surface of the semiconductor substrate) of the n-type semiconductor substrate 1. The back electrode constitutes a drain electrode.

[0057] Also, as shown in FIGS. 2(a) to 2(c), the edge termination region 31 is provided with a junction termination (JTE) structure. In the edge termination region 31, the p-type base region 6 is removed throughout the region, and a step is formed on the front surface of the silicon carbide substrate such that the edge termination region 31 is lower than the active region 30 (recessed toward the drain side), and the parallel pn structure 19 is exposed on the bottom surface of the step. Further, in the edge termination region 31, a plurality of p-type low concentration regions (here, two, denoted as p-type, p-type, and numbered 20 and 21 from the inside) with lower impurity concentration as they are arranged closer to the outside (chip end side) are arranged adjacent to each other to form a JTE structure, i.e., a first JTE region 20 and a second JTE region 21 are provided. Also, an n-type region 22 that functions as a channel stopper is provided outside (chip end side) of the second JTE region 21. A guard ring may be provided instead of the JTE structure. In FIG. 2(b), the p-type column region 3 terminates at the region covering the second JTE region 21, but as indicated by the dotted line after ⇒ in FIG. 2(b), it may also terminate between the second JTE region 21 and the n-type region 22. - type low concentration regions (here, two, p-type from the inside - type, p -- type, denoted as 20 and 21) are arranged adjacent to each other as a JTE structure, and a first JTE region 20 and a second JTE region 21 are provided. Also, an n-type region 22 that functions as a channel stopper is provided outside (chip end side) of the second JTE region 21. + type region 22 is provided. A guard ring may be provided instead of the JTE structure. In FIG. 2(b), although the p-type column region 3 terminates at the region covering the second JTE region 21, as shown by the dotted line after ⇒ in FIG. 2(b), it may terminate between the second JTE region 21 and the n + type region 22.

[0058] In Embodiment 1, the amount of p-type impurities in the terminal region second parallel pn structure 19c is less than the amount of p-type impurities in the active region parallel pn structure 19a and the terminal region first parallel pn structure 19b. The amount of p-type impurities in the terminal region second parallel pn structure 19c is the product of the width w, the length l, the depth d, and the p-type impurity concentration of the p-type column region 3 existing in the terminal region second parallel pn structure 19c (see FIGS. 1 and 2(a)). The amount of p-type impurities in the active region parallel pn structure 19a and the terminal region first parallel pn structure 19b is the same.

[0059] In FIG. 1, in the longitudinal direction (x direction) of the p-type column region 3, which is orthogonal to the direction in which the p-type column region 3 and the n-type column region 4 are arranged, the p-type column region 3 in the terminal region second parallel pn structure 19c is separated from the n + type region 22 (see FIGS. 2(a) to 2(c)) that functions as a channel stopper. The amount of p-type impurities in the terminal region second parallel pn structure 19c is less than the amount of p-type impurities in the active region parallel pn structure 19a and the terminal region first parallel pn structure 19b. In FIG. 1, the n + type region 22 is arranged so as to surround the outside of the dotted line D on the outer periphery of the edge terminal region 31.

[0060] For example, the end of the p-type column region 3 in the terminal region second parallel pn structure 19c may be on the active region 30 side from the end on the outer peripheral side of the second JTE region 21 (see FIG. 2(a)). Further, if the end of the p-type column region 3 in the terminal region second parallel pn structure 19c does not reach the n + type region 22 side, it may be on the n + type region 22 side from the second JTE region 21.

[0061] FIG. 3 is a plan view simulating the edge terminal region in the superjunction semiconductor device according to Embodiment 1. FIG. 3(a) is a plan view showing the spread of the depletion layer in the simulation of the low voltage (Vds1) in the edge terminal region. FIG. 3(b) is a cross-sectional view taken along the line X-X' of FIG. 3(a). As shown in FIGS. 3(a) and 3(b), at the low voltage Vds1, the channel stopper (n +A source-drain voltage is applied to the depletion layer 32 extending from the junction between the n-type region (n-type column region 4) in contact with the p-type region 22) and the p-type column region 3. Since there is an n-type column region 4 between the p-type column region 3 and the channel stopper, the breakdown voltage between the channel stopper and the p-type column region 3 increases.

[0062] FIG. 4 is a plan view simulating an edge termination region in the superjunction semiconductor device according to Embodiment 1. FIG. 4(a) is a plan view showing the spread of the depletion layer in the simulation of the intermediate voltage (Vds2) in the edge termination region. FIG. 4(b) is a cross-sectional view taken along the line X-X' of FIG. 4(a). As shown in FIGS. 4(a) and 4(b), when Vds is increased, the depletion layer 32 on the p-type column region 3 side spreads, and the distance between the neutral region 33 of the p-type column region 3 and the channel stopper increases, so the electric field is relaxed.

[0063] FIG. 5 is a plan view simulating an edge termination region in the superjunction semiconductor device according to Embodiment 1. FIG. 5(a) is a plan view showing the spread of the depletion layer in the simulation of the high voltage (Vds3) in the edge termination region. FIG. 5(b) is a cross-sectional view taken along the line X-X' of FIG. 5(a). As shown in FIGS. 5(a) and 5(b), when the voltage is increased from Vds2 to Vds3, the neutral region 33 rapidly retreats due to the effect of the SJ structure.

[0064] In this way, the impurity amount (charge amount) of the p-type column region 3 in the edge termination region 31 is reduced on the drain potential side (channel stopper side), and the edge termination region 31 is in an n-rich state. Therefore, in the low voltage state (Vds1) where a neutral region (region at the source potential) remains in the edge termination region 31, it is possible to prevent the electric field from concentrating at the overlapping portion between the channel stopper and the p-type column region 3, relax the electric field near the channel stopper, and prevent a decrease in the breakdown voltage in the edge termination region 31.

[0065] (Method for manufacturing a superjunction semiconductor device according to Embodiment 1) Next, a method for manufacturing super junction semiconductor device 40 according to the first embodiment will be described. Fig. 6 is a cross-sectional view showing a state during the manufacturing process of the super junction semiconductor device according to the first embodiment.

[0066] First, we used n-type single crystal 4H-SiC. + A type semiconductor substrate 1 is prepared. + The lower n-type drift layer 2a made of silicon carbide is epitaxially grown on the surface of the n-type semiconductor substrate 1 while doping it with n-type impurities. The state up to this point is shown in FIG. 6(a). + A substrate having epitaxially grown layers such as lower n-type drift layer 2a formed on n-type semiconductor substrate 1 is referred to as a single crystal 4H-SiC epitaxial substrate.

[0067] Next, an ion implantation mask 34 having a predetermined opening is formed on the surface of the lower n-type drift layer 2a by photolithography, for example, using an oxide film. Then, p-type impurities are implanted into the opening of the oxide film to form the lower p-type column region 3a. The lower p-type column region 3a is an n-type ion implantation mask that functions as a channel stopper. + The mask 34 for ion implantation is then removed.

[0068] Next, on the surfaces of the lower n-type drift layer 2a and the lower p-type column region 3a, an upper n-type drift layer 2b made of silicon carbide is epitaxially grown while doping with n-type impurities. The state up to this point is shown in FIG. 6(c). Next, an ion implantation mask 34 having a predetermined opening is formed, for example, from an oxide film, on the surface of the upper n-type drift layer 2b formed here by photolithography. Then, p-type impurities are implanted into the openings in the oxide film to form the upper p-type column region 3b. The upper p-type column region 3b, like the lower p-type column region 3a, is formed of n-type impurities that function as a channel stopper. + The mask 34 for ion implantation is then removed.

[0069] Next, the processes of epitaxial growth in FIG. 6(c) and ion implantation in FIG. 6(d) are repeated a predetermined number of times to form the p-type column regions 3 and the n-type column regions 4. The lower p-type column region 3a and the upper p-type column region 3b are part of the p-type column region 3, and the lower n-type drift layer 2a and the upper n-type drift layer 2b are part of the n-type column region 4. Also, after forming the n-type column region 4, a part of the n-type column region 4 is turned back to form a first p + -type base region 14 (not shown) and a second p + -type base region 15 (not shown). Note that the above is the so-called multi-epi method, but it may also be formed by the so-called trench refill method in which trenches are formed in a drift region of one conductivity type and an epitaxial layer containing impurities of the other conductivity type is grown in the trenches.

[0070] Next, although the figures showing the processes in order are omitted, as shown in the cross-sectional view of FIG. 2(a), a p-type base region 6 doped with p-type impurities such as aluminum is formed on the surfaces of the p-type column regions 3 and the n-type column regions 4. Next, by photolithography and etching, a step is formed, for example, to a depth of 0.3 μm on the surface of the p-type base region 6 in the edge termination region 31, and in the edge termination region 31, the p-type base region 6 is removed to expose the n-type drift layer 2. Next, an ion implantation mask having a predetermined opening is formed on the surface of the p-type base region 6 by photolithography, for example, with a resist, an oxide film, a semiconductor film, or a laminated structure of an oxide film / semiconductor film. N-type impurities such as phosphorus (P) are ion-implanted into this opening, and an n + -type source region 7 is formed in a part of the surface of the p-type base region 6. Next, the ion implantation mask used for forming the n + -type source region 7 is removed. Next, in the same manner, an ion implantation mask having a predetermined opening is formed, n-type impurities are ion-implanted into a part of the surface of the n-type drift layer 2, and an n + -type region 22 is formed. Next, the ion implantation mask used for forming the n + -type region 22 is removed. Note that the n + -type region 22 is formed with the same mask for the n +It may be formed simultaneously with the p-type source region 7.

[0071] Next, in the same manner, a mask for ion implantation having a predetermined opening is formed, and p-type impurities such as aluminum are ion-implanted into a part of the surface of the p-type base region 6 to form a p- + type contact region. The impurity concentration of the p- + type contact region is set to be higher than the impurity concentration of the p-type base region 6. Next, on the step of the edge termination region 31 and the surface of the n-type drift layer 2, a mask for ion implantation having a predetermined opening is formed, for example, with an oxide film by photolithography. P-type impurities are ion-implanted into this opening, and the first JTE region 20 and the second JTE region 21 are formed in a part of the surface of the step and the n-type drift layer 2. Next, the mask for ion implantation used for forming the first JTE region 20 and the second JTE region 21 is removed.

[0072] Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700 °C to perform activation treatment on the p-type column region 3, the n- + type source region 7, the p- + type contact region, etc. Note that, as described above, each ion implantation region may be activated collectively by one heat treatment, or heat treatment may be performed each time ion implantation is performed to activate it.

[0073] Next, on the surface of the p-type base region 6, a mask for trench formation having a predetermined opening is formed, for example, with an oxide film by photolithography. Next, a trench 18 that penetrates the p-type base region 6 and reaches the n-type column region 4 is formed by dry etching. The bottom of the trench 18 may reach the first p- + type base region 14 formed in the n-type column region 4. Next, the mask for trench formation is removed.

[0074] Before removing the trench-forming mask, isotropic etching for removing damage to the trench 18, heat treatment or sacrificial oxidation for rounding the corners of the bottom and the opening of the trench 18 may be performed with the trench-forming mask attached. Only one of isotropic etching and sacrificial oxidation may be performed. Also, sacrificial oxidation may be performed after isotropic etching. The trench-forming mask is removed simultaneously with the oxide film formed by sacrificial oxidation.

[0075] Next, n + A gate insulating film 9 is formed along the surface of the n-type source region 7, the bottom and the side walls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000 °C in an oxygen atmosphere. Also, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as High Temperature Oxide (HTO).

[0076] When formed by thermal oxidation, the interface state density at the interface between the gate insulating film 9 and the semiconductor portion may be reduced by heat treatment (Post Oxidation Anneal (POA) treatment). When the gate insulating film 9 is formed by a deposition method such as HTO, post deposition anneal (PDA) may be performed for reducing leakage current and improving relative permittivity.

[0077] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 18. The polycrystalline silicon layer is patterned by photolithography and left inside the trench 18 to form the gate electrode 10.

[0078] Next, for example, a ring glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, thereby forming an interlayer insulating film (not shown). Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film. The interlayer insulating film and the gate insulating film 9 are patterned by photolithography to form a contact hole exposing the n + -type source region 7. When a p + -type contact region is formed, contact holes exposing the n + -type source region 7 and the n + -type source region 7 are formed. Thereafter, a heat treatment (reflow) is performed to planarize the interlayer insulating film.

[0079] Next, a conductive film serving as an ohmic electrode (not shown) is provided in the contact hole and on the interlayer insulating film. This conductive film is selectively removed to leave the ohmic electrode only in the contact hole, and the n + -type source region 7 is brought into contact with the ohmic electrode. When a p + -type contact region is formed, the n + -type source region 7 and the p + -type contact region are brought into contact with the ohmic electrode. Next, the ohmic electrodes other than those in the contact holes are selectively removed.

[0080] Next, for example, by sputtering, an electrode pad serving as a source electrode pad (not shown) is deposited on the ohmic electrode on the front surface of the silicon carbide semiconductor substrate and on the upper portion of the interlayer insulating film.

[0081] Next, a back surface electrode (not shown) such as nickel is provided on the second main surface of the n + -type semiconductor substrate 1. Thereafter, a heat treatment is performed in an inert gas atmosphere at about 1000 °C to +A back surface electrode that makes an ohmic contact with the type semiconductor substrate 1 is formed. When the trench 18 is not formed, an n-type well region is formed in a part of the surface region of the p-type base region 6, the front surface side of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 9, and the p-type base region 6 and each region formed on the surface of the p-type base region 6 are covered with the gate insulating film 9. On the gate insulating film 9, a polycrystalline silicon layer is formed as a gate electrode 10, the polycrystalline silicon layer is patterned and selectively removed, and the polycrystalline silicon layer is left on the portion sandwiched between the n + type source region 7 and the n-type well region, and an interlayer insulating film is formed so as to cover the gate electrode 10.

[0082] In the above-described epitaxial growth and ion implantation, as the n-type impurity (n-type dopant), for example, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc. that become n-type with respect to silicon carbide may be used. As the p-type impurity (p-type dopant), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc. that become p-type with respect to silicon carbide may be used. In this way, the silicon carbide semiconductor device shown in FIGS. 1 to 2(c) is completed.

[0083] As described above, according to the first embodiment, since the p-type column region in the terminal region second parallel pn structure is separated from the n + type region (channel stopper), the amount of p-type impurity in the terminal region second parallel pn structure is made less than the amount of p-type impurity in the active region parallel pn structure and the terminal region first parallel pn structure. As a result, it is possible to prevent the electric field from concentrating on the portion where the channel stopper and the p-type column region overlap in the state where the neutral region remains in the p-column of the edge terminal region and the voltage is low, relax the electric field near the channel stopper, and prevent the breakdown voltage from decreasing in the edge terminal region.

[0084] (Embodiment 2) FIG. 7 is a plan view showing the structure of the superjunction semiconductor device according to Embodiment 2. Further, FIG. 8 is a cross-sectional view of FIG. 7 showing the structure of the superjunction semiconductor device according to Embodiment 2. FIG. 8(a) is a cross-sectional view taken along the line Y-Y' of FIG. 7. Further, FIG. 8(b) is a cross-sectional view taken along the line X-X' of FIG. 7. Further, FIG. 8(c) is a cross-sectional view taken along the line X1-X1' of FIG. 7.

[0085] As shown in FIG. 7, in Embodiment 2, in the longitudinal direction (x direction) of the p-type column region 3, which is orthogonal to the direction in which the p-type column region 3 and the n-type column region 4 are arranged, the width w of the p-type column region 3 becomes narrower as it approaches the outer periphery. As a result, the impurity amount of the p-type column region 3 in the edge termination region 31 is reduced on the drain potential side (the n-type region 22 side that functions as a channel stopper). For this reason, similar to Embodiment 1, in a state where a neutral region (a region at the source potential) remains in the edge termination region 31 and the voltage is low, it is possible to prevent the electric field from concentrating at the overlapping portion of the channel stopper (n-type region 22) and the p-type column region 3, relax the electric field near the channel stopper (n-type region 22), and prevent the breakdown voltage from decreasing in the edge termination region 31. + Similar to Embodiment 1, in a state where a neutral region (a region at the source potential) remains in the edge termination region 31 and the voltage is low, it is possible to prevent the electric field from concentrating at the overlapping portion of the channel stopper (n-type region 22) and the p-type column region 3, relax the electric field near the channel stopper (n-type region 22), and prevent the breakdown voltage from decreasing in the edge termination region 31. + Similar to Embodiment 1, in a state where a neutral region (a region at the source potential) remains in the edge termination region 31 and the voltage is low, it is possible to prevent the electric field from concentrating at the overlapping portion of the channel stopper (n-type region 22) and the p-type column region 3, relax the electric field near the channel stopper (n-type region 22), and prevent the breakdown voltage from decreasing in the edge termination region 31. + Similar to Embodiment 1, in a state where a neutral region (a region at the source potential) remains in the edge termination region 31 and the voltage is low, it is possible to prevent the electric field from concentrating at the overlapping portion of the channel stopper (n-type region 22) and the p-type column region 3, relax the electric field near the channel stopper (n-type region 22), and prevent the breakdown voltage from decreasing in the edge termination region 31.

[0086] FIG. 9 is a plan view of a simulation of the edge termination region in the superjunction semiconductor device according to Embodiment 2. FIG. 9(a) is a plan view showing the spread of the depletion layer in the simulation of the low voltage (Vds1) in the edge termination region. FIG. 9(b) is a cross-sectional view taken along the line X-X' of FIG. 9(a). As shown in FIGS. 9(a) and 9(b), since the impurity amount at the end of the p-type column region 3 is small, at Vds1, the depletion layer 32 extending from the junction between the p-type column region 3 and the n-type column region 4 is already connected to the depletion layer 32 extending from the junction between the channel stopper and the p-type column region 3.

[0087] FIG. 10 is a plan view simulating an edge termination region in the superjunction semiconductor device according to Embodiment 2. FIG. 10(a) is a plan view showing the spread of the depletion layer in the simulation of the intermediate voltage (Vds2) in the edge termination region. FIG. 10(b) is a cross-sectional view taken along line X-X' of FIG. 10(a). As shown in FIGS. 10(a) and 10(b), when Vds is further increased, the end of the depletion layer 32 moves away from the channel stopper, so that the electric field strength between the neutral region 33 at the source potential and the channel stopper at the drain potential does not increase, and breakdown does not occur at a low voltage.

[0088] FIG. 11 is a diagram simulating the structure of the edge termination region of the superjunction semiconductor device according to Embodiment 2. FIG. 11(a) is a plan view showing the spread of the depletion layer in the simulation of the high voltage (Vds3) in the edge termination region. FIG. 11(b) is a cross-sectional view taken along line X-X' of FIG. 11(a). As shown in FIGS. 11(a) and 11(b), when the voltage is increased from Vds2 to Vds3, the neutral region 33 rapidly retreats due to the SJ effect.

[0089] (Method for manufacturing a superjunction semiconductor device according to Embodiment 2) The manufacturing method of the superjunction semiconductor device 40 according to Embodiment 2 can be manufactured by forming the p-type column region 3 in the lower region of the n-type region 22 that functions as a channel stopper and narrowing the width of the p-type column region 3 as it approaches the outer periphery in the longitudinal direction of the p-type column region 3 in the manufacturing method of the superjunction semiconductor device 40 according to Embodiment 1. + type region 22 up to the lower region and narrowing the width of the p-type column region 3 as it approaches the outer periphery in the longitudinal direction of the p-type column region 3.

[0090] As described above, according to Embodiment 2, in the longitudinal direction of the p-type column region, the width of the p-type column region becomes narrower as it approaches the outer periphery. Thereby, the amount of p-type impurities in the second parallel pn structure in the termination region is made less than the amount of p-type impurities in the active region parallel pn structure and the first parallel pn structure in the termination region. For this reason, the same effects as those of Embodiment 1 can be obtained.

[0091] (Embodiment 3) FIG. 12 is a plan view showing the structure of the superjunction semiconductor device according to Embodiment 3. FIG. 13 is a cross-sectional view showing the structure of the superjunction semiconductor device according to Embodiment 3. FIG. 13(a) is a Y-Y' cross-sectional view of FIG. 12. FIG. 13(b) is an X-X' cross-sectional view of FIG. 12. FIG. 13(c) is an X1-X1' cross-sectional view of FIG. 12.

[0092] As shown in FIG. 12, in Embodiment 3, in the longitudinal direction of the p-type column region 3, the p-type column region 3 in the terminal region second parallel pn structure 19c is separated from the n-type region 22 that functions as a channel stopper, and in the longitudinal direction of the p-type column region 3, the width w of the p-type column region 3 becomes narrower as it approaches the outer periphery. That is, it has both the features of Embodiment 1 and the features of Embodiment 2. + As a result, similar to Embodiment 1 and Embodiment 2, in a state where a neutral region (a region at the source potential) remains in the edge termination region 31 and the voltage is low, it is possible to prevent the electric field from concentrating in the overlapping portion of the channel stopper (n-type region 22) and the p-type column region 3, relax the electric field near the channel stopper (n-type region 22), and prevent a decrease in the breakdown voltage in the edge termination region 31.

[0093] (Method for manufacturing a superjunction semiconductor device according to Embodiment 3) + The manufacturing method of the superjunction semiconductor device 40 according to Embodiment 3 can be manufactured by forming the p-type column region 3 to be separated from the n-type region 22 that functions as a channel stopper in the longitudinal direction of the p-type column region 3 and narrowing the width of the p-type column region 3 as it approaches the outer periphery in the longitudinal direction of the p-type column region 3 in the manufacturing method of the superjunction semiconductor device 40 according to Embodiment 1. + As described above, according to Embodiment 3, in the longitudinal direction of the p-type column region, the p-type column region in the terminal region second parallel pn structure functions as a channel stopper n

[0094] (Method for manufacturing a superjunction semiconductor device according to Embodiment 3) The manufacturing method of the superjunction semiconductor device 40 according to Embodiment 3 is the manufacturing method of the superjunction semiconductor device 40 according to Embodiment 1, in which, in the longitudinal direction of the p-type column region 3, the p-type column region 3 is formed to be separated from the n-type region 22 that functions as a channel stopper, and the width of the p-type column region 3 is made narrower as it approaches the outer periphery in the longitudinal direction of the p-type column region 3. + As described above, according to Embodiment 3, in the longitudinal direction of the p-type column region, the p-type column region in the terminal region second parallel pn structure functions as a channel stopper n

[0095] As described above, according to Embodiment 3, in the longitudinal direction of the p-type column region, the p-type column region in the terminal region second parallel pn structure functions as a channel stopper n +It is separated from the type region, and in the longitudinal direction of the p-type column region, the width of the p-type column region becomes narrower as it approaches the outer periphery. As a result, the amount of p-type impurities in the terminal region second parallel pn structure is made less than the amount of p-type impurities in the active region parallel pn structure and the terminal region first parallel pn structure. For this reason, the same effects as those in Embodiment 1 and Embodiment 2 can be obtained.

[0096] (Embodiment 4) Since the plan view showing the structure of the superjunction semiconductor device according to Embodiment 4 is the same as FIG. 12, the description thereof is omitted. FIG. 14 is a cross-sectional view showing the structure of the superjunction semiconductor device according to Embodiment 4. FIG. 14(a) is a Y-Y' cross-sectional view of FIG. 12. FIG. 14(b) is an X-X' cross-sectional view of FIG. 12. FIG. 14(c) is an X1-X1' cross-sectional view of FIG. 12.

[0097] As shown in FIGS. 14(a) to 14(c), in Embodiment 4, the p-type column region 3 and the n-type column region 4 have a so-called semi-SJ structure that does not reach the n + type semiconductor substrate 1. For this reason, an n-type drift layer 2 exists between the parallel pn structure 19 and the n + type semiconductor substrate 1. Also in Embodiment 4, as in Embodiment 3, in the longitudinal direction of the p-type column region 3, the p-type column region 3 in the terminal region second parallel pn structure 19c is separated from the n + type region 22 that functions as a channel stopper, and in the longitudinal direction of the p-type column region 3, the width of the p-type column region 3 is made narrower as it approaches the outer periphery.

[0098] As a result, as in Embodiment 3, it is possible to prevent the electric field from concentrating at the overlapping portion of the channel stopper and the p-type column region 3 in the state where a neutral region (region at the source potential) remains in the edge termination region 31 with a low voltage, relax the electric field near the channel stopper, and prevent a decrease in the breakdown voltage in the edge termination region 31.

[0099] (Manufacturing method of the superjunction semiconductor device according to Embodiment 4) The manufacturing method of the superjunction semiconductor device 40 according to Embodiment 4 is the manufacturing method of the superjunction semiconductor device 40 according to Embodiment 3, in which the p-type column region 3 and the n-type column region 4 are formed so as not to reach the n + type semiconductor substrate 1.

[0100] As described above, according to Embodiment 4, the p-type column region and the n-type column region do not reach the n + type semiconductor substrate 1. Even with this SJ structure of this shape, the same effects as in Embodiment 3 can be obtained.

[0101] Also, with the same structure as the conventional superjunction semiconductor device, the impurity concentration of the p-type column region 3 of the terminal region second parallel pn structure 19c may be decreased as it approaches the outer periphery in the longitudinal direction (x direction) of the p-type column region 3. Thereby, the amount of impurities in the p-type column region 3 of the edge terminal region 31 is reduced on the drain potential side (channel stopper side).

[0102] Also in this case, the same effects as those of the above-described Embodiments 1 to 4 can be obtained. Further, in the above-described Embodiments 1 to 4, the impurity concentration of the p-type column region 3 may be decreased as it approaches the outer periphery.

[0103] (Embodiment 5) FIG. 15 is a top view showing an end portion in the longitudinal direction of a p-type column region set for simulation in the same manner as in FIGS. 3 to 5 and FIGS. 9 to 11, which is a superjunction semiconductor device according to Embodiment 5. In Embodiment 5, in the region S where the parallel pn structure 19 is in contact with the n-type region 22 in the longitudinal direction (x direction) of the n-type column region 4 and the p-type column region 3, it is n + rich. That is, in the region S, the product of the width of the n-type column region 4 and the impurity concentration of the n-type column region 4 is larger than the product of the width of the p-type column region 3 and the impurity concentration of the p-type column region 3.

[0104] For example, as shown in Fig. 15(a), with the impurity concentration of the n-type column region 4 being the same as that of the p-type column region 3, the width W2 of the p-type column region 3 may be made narrower than the width W1 of the n-type column region 4 in the vicinity of the region S where the parallel pn structure 19 is in contact with the n + type region 22. Also, as shown in Fig. 15(b), with the impurity concentration of the n-type column region 4 being the same as that of the p-type column region 3, the width W2 of the p-type column region 3 may be monotonically decreased as it approaches the region S where the parallel pn structure 19 is in contact with the n + type region 22. Further, with the width W2 of the p-type column region 3 being the same as the width W1 of the n-type column region 4, the impurity concentration of the n-type column region 4 may be made higher than that of the p-type column region 3. Also, at the location where the p-type column region 3 near the surface is in contact with the high-concentration n + type region 22, since the electric field particularly concentrates, only near the surface of the region S where the n + type region 22 is in contact, it may be n-rich.

[0105] Also, in Embodiment 5, as shown in Fig. 15(c), the p-type column region 3 of the parallel pn structure 19 may be provided at a distance L from the n + type region 22 in the longitudinal direction of the p-type column region 3. In this case, in the vicinity of the n + type region 22 of the edge termination region 31, the farther the distance L, the more n-rich it becomes. By separating this distance L, at the longitudinal end of the p-type column region 3 of the parallel pn structure 19, it can be made p-rich in the same way as the active region. In this case, without changing the respective widths and impurity concentrations in the longitudinal directions of the p-type column region 3 and the n-type column region 4, it can be made the same as the active region.

[0106] Therefore, as shown in Fig. 15(c), the p-type column region 3 of the parallel pn structure 19 is separated by a distance L from the n +When separated from the p-type region 22 by a distance L, the impurity concentration of the n-type column region 4 and the impurity concentration of the p-type column region 3 may be made the same, and the width W2 of the p-type column region 3 may be made the same as or wider than the width W1 of the n-type column region 4 throughout the longitudinal direction of the p-type column region 3. Also, with the width W2 of the p-type column region 3 and the width W1 of the n-type column region 4 made the same, the impurity concentration of the n-type column region 4 may be made the same as or lower than the impurity concentration of the p-type column region 3. Also, since the electric field particularly concentrates at the location where the p-type column region 3 near the surface is in contact with the high-concentration n + type region 22, the p-type column region 3 may be provided separately from the n + type region 22 by a distance L only near the surface.

[0107] Here, FIG. 16 is a graph showing the breakdown voltage reduction at high temperature in the case of the structure of FIG. 15(c) for a 1200 V-class SJ-SiCMOSFET. In FIG. 16, the vertical axis represents the drain-source current I DS and the unit is A. The horizontal axis represents the drain-source voltage V DS and the unit is V. In FIG. 16, for a semi-SJ structure SiCMOSFET with a cell pitch of 5 μm, with V GS set to 0 V, the breakdown voltage reduction at room temperature (RT) and high temperature (175°C) is shown when the parallel pn structure 19 is made n-rich or p-rich.

[0108] FIG. 16(a) shows the case of 50% p-rich, FIG. 16(b) shows the case of 30% p-rich, FIG. 16(c) shows the case of 10% n-rich, and FIG. 16(d) shows the case of 50% n-rich. Here, 50% p-rich means that the product of the width of the p-type column region 3 and the impurity concentration of the p-type column region 3 is 50% more, that is, 1.5 times, the product of the width of the n-type column region 4 and the impurity concentration of the n-type column region 4. The same applies to 30% p-rich, 10% n-rich, and 50% n-rich.

[0109] As shown in Fig. 16(a), when it is 50% p-rich, at high temperature (175 °C), the breakdown voltage decreases by 58% compared to room temperature (RT). As shown in Fig. 16(b), when it is 30% p-rich, at high temperature (175 °C), the breakdown voltage decreases by 26% compared to room temperature (RT). On the other hand, as shown in Fig. 16(c), when it is 10% n-rich, and as shown in Fig. 16(d), when it is 50% n-rich, it can be seen that there is no decrease in the breakdown voltage even at high temperature (175 °C).

[0110] Therefore, in Embodiment 5, at the location where the p-type column region 3 is in contact with the high-concentration n + type region 22, in order to prevent the electric field from concentrating at high temperature, as shown in Figs. 15(a) and 15(b), in the longitudinal direction of the n-type column region 4 and the p-type column region 3, in the region S in contact with the n + type region 22, it is made n-rich. Thereby, deep electron traps and deep hole traps generated by Al ion implantation are reduced, the detrapping of majority carriers at high temperature is reduced, and the shrinkage of the depletion layer is suppressed. For this reason, by making the intersecting portion of the n + type region 22 that functions as a channel stopper and the p-type column region 3 n-rich, a decrease in the breakdown voltage at high temperature (175 °C) can be suppressed. The formation of the p-type column region 3 and the high-concentration n + type region 22 is a separate process, and there are variations in the formation position due to the mask alignment between the end of the p-type column region 3 and the high-concentration n + type region 22. In the longitudinal direction of the n-type column region 4 and the p-type column region 3, in the structure in contact with the n + type region 22, even if the contact position is shifted due to manufacturing variations, since it is the portion that is made n-rich by changing the widths of the n-type column region 4 and the p-type column region 3, it has no influence on the suppression of the breakdown voltage decrease, and since only the widths of the n-type column region 4 and the p-type column region 3 are changed, the degrees of freedom in design and manufacturing are high.

[0111] Also, as shown in Fig. 15(c), by separating the p-type column region 3 of the parallel pn structure 19 by a distance L in the longitudinal direction of the p-type column region 3 from the n + type region 22, from the p-type column region 3 and the high-concentration n+ The n-type region 22 is in contact with the n-type region 22, and the n-type region 22 is in contact with the n-type region 22. + This can prevent breakdown in the vicinity of the n-type region 22. When the active region has a p-rich structure in order to increase the avalanche resistance, the widths of the p-type column region 3 and the n-type column region 4 in the active region do not need to be changed up to the ends, so that the parallel pn structure can be formed with high precision.

[0112] Figure 17 shows the Vds and C of a full SJ-SiC MOSFET with a breakdown voltage of 3,300 V. OSS In FIG. 17, the vertical axis represents the output capacitance C OSS The horizontal axis indicates the drain-source voltage Vds, and the unit is F. In Fig. 17, the relationship between Vds and C when the temperature of the SJ-SiC MOSFET is changed is shown. OSS FIG. 17(a) shows the relationship between the temperature and the operating frequency of the SJ-SiC MOSFET, where FIG. 17(a) shows the case of -55°C, FIG. 17(b) shows the case of 25°C, and FIG. 17(c) shows the case of 140°C. FIG. 17 shows the cases where the operating frequencies of the SJ-SiC MOSFET are 1 MHz, 100 kHz, 10 kHz, and 1 kHz.

[0113] FIG. 17 shows the impurity concentration of the p-type column region 3 as 6×10 16 / cm 3 , the impurity concentration of the n-type column region 4 is set to 3×10 16 / cm 3 The calculation is based on the assumption that the width of the p-type column region 3 is 1.5 μm, the width of the n-type column region 4 is 3.5 μm, and the activation rate of the impurities implanted into the p-type column region 3 is 70%. Here, the activation rate is defined as the value obtained by dividing the integral concentration obtained by integrating the true doping concentration over the region of the p-type column region 3 for the electrically activated true doping concentration distribution by the implantation dose. The true doping concentration can be obtained by well-known CV (capacitance-applied voltage) measurement.

[0114] As shown in Figure 17, at low temperatures (-55°C) and room temperatures (25°C), the C OSS At high temperatures (140°C), the COSS are the same. This is because when there are deep levels, it cannot follow high frequencies and the capacitance appears small. When the frequency is low, even deep traps (levels) can be followed, so the capacitance appears large. Also, when the temperature is increased, the carrier response improves, so the capacitance appears large at both high and low frequencies. Thus, when the temperature rises or the frequency decreases, the capacitance increases. An increase in capacitance means that the depletion layer shrinks. From this result as well, as shown in FIG. 15, it is advisable to make the intersection of the n + -type region 22 functioning as a channel stopper and the p-type column region 3 n-rich.

[0115] FIG. 18 is a graph showing the relationship between the width of the p-type column region and the depletion voltage in an SJ-SiCMOSFET with a breakdown voltage of 3300 V class. In FIG. 18, the vertical axis represents the depletion voltage and the unit is V. The horizontal axis represents the width of the p-type column region 3 and the unit is μm. FIG. 18 shows the cases where the activation rate of aluminum implanted in the p-type column region 3 is 70%, 90%, and 100%. The case where the activation rate is 100% is when formed by epitaxial growth, and the activation rates of 70% and 90% show the lower limit and upper limit when formed by ion implantation. The configuration of the SJ-SiCMOSFET in FIG. 18 is the same as the configuration of the SJ-SiCMOSFET in FIG. 17.

[0116] As shown in FIG. 18, as the width of the p-type column region 3 increases, that is, as it becomes p-rich, the depletion voltage increases, and as the activation rate increases, the depletion voltage increases. Therefore, in order to prevent breakdown in the vicinity of the n + -type region 22 which is a channel stopper at high temperatures, the distance L between the p-type column region 3 and the n + -type region 22 needs to be determined considering the activation rate.

[0117] FIG. 19 is a graph showing the doping density dependence of the breakdown electric field. In FIG. 19, the vertical axis represents the breakdown electric field and the unit is V / cm. The horizontal axis represents the doping density and the unit is / cm 3is shown. In FIG. 19, for Si, 3C-SiC, 4H-SiC, and 6H-SiC, it shows how much they break down. From FIG. 19, in 4H-SiC, when the impurity concentration (doping density) of the p-type column region 3 is 6×10 16 / cm 3 , the breakdown electric field is 3×10 6 V / cm.

[0118] FIG. 20 is a graph showing the relationship between the distance between the p-type column region and the n + -type region and the breakdown voltage when the Al activation rate is 70% (the lower limit value when formed by ion implantation). In FIG. 20, the vertical axis represents the breakdown voltage, and the unit is V. The horizontal axis represents the distance L between the p-type column region 3 and the n + -type region 22, and the unit is μm. FIG. 20 is the result of calculation with the structure of the SJ-SiCMOSFET the same as that in FIG. 18. In FIG. 20, when the breakdown electric field Emax is 3×10 6 V / cm, and since the breakdown electric field Emax in the horizontal direction may be 0.8 times that in the vertical direction, the cases of the breakdown electric field Emax×0.9 and Emax×0.8 are also calculated. Here, the horizontal direction and the vertical direction are the directions with respect to the C-axis of the silicon carbide semiconductor substrate. In general planar-type Si surfaces, C surfaces, or trench-type m surfaces and a surfaces of MOSFETs or IGBTs, the depth direction is approximately the C-axis direction, and the longitudinal direction of the p-type column region 3 is perpendicular to the C-axis. Therefore, the breakdown electric field Emax determines the magnitude of the distance L using the Emax in the horizontal direction. In FIG. 20, when the width of the p-type column region 3 is increased from 1.5 μm by +30% and +50% to be p-rich, the depletion voltage of the p-type column region 3 is also shown by a straight line.

[0119] As shown in FIG. 20, when the impurity concentration of the p-type column region 3 is 6×10 16 / cm 3 and the Al activation rate is 70%, even in the case of Emax×0.8, when the distance L between the p-type column region 3 and the n + -type region 22 is 0 μm, the p-type column region 3 is depleted, so the n +It does not break down in the p-type region 22. Therefore, when the Al activation rate exceeds 70%, the distance L between the p-type column region 3 and the n + type region 22 is set to be greater than 0 μm.

[0120] Figure 21 is a graph showing the relationship between the distance between the p-type column region and the n + type region and the breakdown voltage when the Al activation rate is 90% (the upper limit value when formed by ion implantation). In Figure 21, the vertical axis represents the breakdown voltage, and the unit is V. The horizontal axis represents the distance L between the p-type column region 3 and the n + type region 22, and the unit is μm. Figure 21 is the result calculated with the same configuration as Figure 20.

[0121] As shown in Figure 21, when the impurity concentration of the p-type column region 3 is 6×10 16 / cm 3 , in the case of an Al activation rate of 90% and in the case of the breakdown electric field Emax, when the width of the p-type column region 3 is +30%, if the distance L between the p-type column region 3 and the n + type region 22 is 0.1 μm or less, breakdown occurs in the vicinity of the n + type region 22. Therefore, it is preferable that the distance L between the p-type column region 3 and the n + type region 22 is greater than 0.1 μm.

[0122] Also, in the case of the breakdown electric field Emax, if the distance L between the p-type column region 3 and the n + type region 22 is 0.4 μm or less when the width of the p-type column region 3 is +50%, breakdown occurs in the vicinity of the n + type region 22. Also, when the lateral Emax is smaller than the longitudinal Emax, that is, in the case of Emax×0.8, the required distance further increases.

[0123] Figure 22 shows the p-type column region and the n +It is a graph showing the relationship between the distance from the p-type region and the breakdown voltage. 100% Al activation rate is, for example, the case where the p-type column region 3 is formed by epitaxial growth. In FIG. 22, the vertical axis represents the breakdown voltage, and the unit is V. The horizontal axis represents the distance L between the p-type column region 3 and the n + type region 22, and the unit is μm. FIG. 22 is the result calculated with the same configuration as FIG. 20.

[0124] As shown in FIG. 22, when the impurity concentration of the p-type column region 3 is 6×10 16 / cm 3 , in the case of 100% Al activation rate and in the case of the breakdown electric field Emax, when the width of the p-type column region 3 is +30%, if the distance L between the p-type column region 3 and the n + type region 22 is 0.4 μm or less, breakdown occurs near the n + type region 22. Therefore, it is preferable that the distance L between the p-type column region 3 and the n + type region 22 is greater than 0.4 μm.

[0125] Also, in the case of the breakdown electric field Emax, when the width of the p-type column region 3 is +50%, if the distance L between the p-type column region 3 and the n + type region 22 is 1.0 μm or less, breakdown occurs near the n + type region 22. Therefore, it is preferable that the distance L between the p-type column region 3 and the n + type region 22 is greater than 1.0 μm. Also, when the lateral Emax is smaller than the longitudinal Emax, that is, in the case of Emax×0.8, the required distance further increases.

[0126] FIG. 23 is a top view showing the configuration near the p-type column region and the n + type region, which is an enlarged view of one of the four corners in a plan view of the planar structure of the superjunction semiconductor device according to Embodiment 5. The n + type region 22 is provided so as to surround the active region 30, and is composed of a straight portion and a curved portion at the corner. As in the region indicated by the dotted line pointed to by S1 in FIG. 23, in the longitudinal direction of the p-type column region 3, the distance L1 at which the p-type column region 3 and the n + type region 22 are separated is the n+ It is preferably uniform in the straight portion of the n-type region 22. Also, n + The distance L2 at which the p-type column region 3 and the n + type region 22 are separated at the corner portion of the type region 22 is preferably the same as or longer than the distance L1 in the straight portion.

[0127] Also, like in the region of the dotted line indicated by S2 in FIG. 23, the longitudinal end of the p-type column region 3 is n + At the corner portion of the n-type region 22, n + type region 22 is inclined according to the curvature of the n-type region 22. Thereby, also at the corner portion, the distance at which the p-type column region 3 and the n + type region 22 are separated becomes uniform.

[0128] (Method for manufacturing a superjunction semiconductor device according to Embodiment 5) The method for manufacturing the superjunction semiconductor device 40 according to Embodiment 5 is the method for manufacturing the superjunction semiconductor device 40 according to Embodiment 1, in which, in the longitudinal direction of the p-type column region 3, the width of the p-type column region 3 is narrowed, or the p-type column region 3 is n + type region 22 so as not to reach, it can be manufactured.

[0129] As described above, according to Embodiment 5, in the longitudinal direction of the n-type column region and the p-type column region, n + type region, the region in contact with the n-type region is n-rich. Thereby, deep electron traps and deep hole traps generated by Al ion implantation are reduced, the detrapping of majority carriers at high temperatures is reduced, and the shrinkage of the depletion layer is suppressed. For this reason, by making the intersecting portion of the n + type region that functions as a channel stopper and the p-type column region n-rich, a decrease in breakdown voltage at high temperature (175 ° C) can be suppressed. Also, by separating the p-type column region of the parallel pn structure by a distance L from the n + type region in the longitudinal direction of the p-type column region, the portion where the p-type column region and the high-concentration n + type region are in contact is eliminated, and at high temperatures, the n +It is possible to prevent breakdown in the vicinity of the type region.

[0130] In the above, in the present invention, the case where a MOS gate structure is formed on the first main surface of a silicon carbide substrate made of silicon carbide has been described as an example. However, the present invention is not limited to this, and various changes such as the plane orientation of the substrate main surface can be made. Further, in the present invention, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention also holds true when the first conductivity type is p-type and the second conductivity type is n-type. Further, the present invention is applicable not only to a semiconductor device having a trench structure in which a channel is formed perpendicular to the substrate surface, but also to a planar structure in which a channel is formed parallel to the substrate surface. Further, in each of the above-described embodiments, the case where silicon carbide is used as a wide bandgap semiconductor has been described as an example. However, the same effects can be obtained when using a wide bandgap semiconductor other than silicon carbide such as gallium nitride (GaN), and silicon or the like other than the wide bandgap semiconductor. Further, in the present invention, the example in which the trench 18 has a structure parallel to the longitudinal direction of the p-type column region 3 and the n-type column region 4 has been described. However, the same effect can be obtained even when the trench 18 has a structure perpendicular to the longitudinal direction of the p-type column region 3 and the n-type column region 4.

Industrial Applicability

[0131] As described above, the superjunction semiconductor device according to the present invention is useful for a high withstand voltage semiconductor device used in a power conversion device, a power supply device such as various industrial machines, and the like.

Explanation of Reference Numerals

[0132] 1, 101 n + -type semiconductor substrate 2, 102 n-type drift layer 2a Lower n-type drift layer 2b Upper n-type drift layer 3, 103 p-type column region 3a Lower p-type column region 3b Upper p-type column region 4, 104 n-type column region 6, 106 p-type base region 7, 107 n + Type source region 9, 109 Gate insulating film 10, 110 Gate electrode 14, 114 First p + Type base region 15, 115 Second p + Type base region 18, 118 Trench 19, 119 Parallel pn structure 19a Active region parallel pn structure 19b Terminal region first parallel pn structure 19c Terminal region second parallel pn structure 20, 120 First JTE region 21, 121 Second JTE region 22, 122 n + Type region 30, 130 Active region 31, 131 Edge termination region 32, 132 Depletion layer 33, 133 Neutral region 34 Mask for ion implantation 40, 140 SJ-MOSFET

Claims

1. A superjunction semiconductor device having an active region through which current flows and a termination structure portion disposed outside the active region and having a breakdown voltage structure formed therein, wherein the active region and the termination structure portion include a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on a front surface of a semiconductor substrate of the first conductivity type, and a parallel pn structure in which stripe-shaped first columns of the first conductivity type and stripe-shaped second columns of a second conductivity type provided on a surface of the first semiconductor layer are repeatedly arranged alternately in a direction parallel to the front surface, and the termination structure portion includes a channel stopper disposed so as to surround the parallel pn structure in a plan view, the second column of the parallel pn structure is provided at a distance from the channel stopper in a longitudinal direction of the second column, at an end portion in the longitudinal direction of the second column of the parallel pn structure, a product of a width of the second column and an impurity concentration of the second column is the same as or greater than a product of a width of the first column and an impurity concentration of the first column, in the longitudinal direction of the second column, the second column and the channel stopper are separated by 0.1 μm or more, and the second column is doped with an impurity of the second conductivity type, and an activation rate of the doped impurity is greater than 70% and less than or equal to 90%.

2. A superjunction semiconductor device having an active region through which current flows and a termination structure portion disposed outside the active region and having a breakdown voltage structure formed therein, wherein the active region and the termination structure portion include a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on a front surface of a semiconductor substrate of the first conductivity type, and a parallel pn structure in which stripe-shaped first columns of the first conductivity type and stripe-shaped second columns of a second conductivity type provided on a surface of the first semiconductor layer are repeatedly arranged alternately in a direction parallel to the front surface, and the termination structure portion includes a channel stopper disposed so as to surround the parallel pn structure in a plan view, the second column of the parallel pn structure is provided at a distance from the channel stopper in a longitudinal direction of the second column, at an end portion in the longitudinal direction of the second column of the parallel pn structure, a product of a width of the second column and an impurity concentration of the second column is greater than a product of a width of the first column and an impurity concentration of the first column, and a width of the second column is +50% or less with respect to a width of the first column. A superjunction semiconductor device, wherein in the longitudinal direction of the second column, the second column and the channel stopper are separated by 0.4 μm or more.

3. In the longitudinal direction of the second column of the parallel pn structure, the distance between the second column and the channel stopper, which is directly connected to the surface electrode potential, is uniform in the straight portion of the channel stopper, and at the corner portion of the channel stopper, it is the same as or longer than the distance of the straight portion. The superjunction semiconductor device according to claim 1 or 2, characterized in that.

4. Each of the longitudinal ends of the second column of the parallel pn structure is inclined in accordance with the curvature of the channel stopper at the corner portion of the channel stopper. The superjunction semiconductor device according to any one of claims 1 to 3, characterized in that.

5. The active region is A second semiconductor layer of a second conductivity type provided on the surface side of the parallel pn structure, A first semiconductor region of a first conductivity type selectively provided on the surface layer of the second semiconductor layer, A gate insulating film provided on the surface side of the second semiconductor layer and in contact with the second semiconductor layer, A gate electrode provided on the surface side opposite to the surface of the gate insulating film in contact with the second semiconductor layer, The superjunction semiconductor device according to any one of claims 1 to 4, characterized in that it comprises.

6. The first column and the second column of the parallel pn structure do not reach the semiconductor substrate. The superjunction semiconductor device according to any one of claims 1 to 5, characterized in that.

7. The semiconductor substrate is made of a wide bandgap semiconductor. The superjunction semiconductor device according to any one of claims 1 to 6, characterized in that.

8. The channel stopper is of a first conductivity type. The superjunction semiconductor device according to any one of claims 1 to 7, characterized in that.

9. The semiconductor substrate is a silicon carbide semiconductor, The first conductivity type is an n-type formed by adding nitrogen to the silicon carbide semiconductor, The second conductivity type is a p-type formed by adding aluminum to the silicon carbide semiconductor. The superjunction semiconductor device according to any one of claims 1 to 8, characterized in that.

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