Field effect transistor
The field-effect transistor design addresses high resistance and instability by using a pillar region with distinct p-type impurity concentrations to stabilize the electric field relaxation region's potential, reducing leakage current and improving operational stability and breakdown voltage.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-01-09
- Publication Date
- 2026-04-20
AI Technical Summary
The existing field-effect transistor design has high electrical resistance and instability in the connection path between the electric field relaxation region and the source electrode, leading to potential fluctuations and increased likelihood of leakage current due to high p-type impurity concentration in the body region.
The design incorporates a semiconductor substrate with a trench-type gate electrode and a pillar region that includes a contact region with high p-type impurity concentration and a connection region with lower p-type impurity concentration, connected directly to the electric field relaxation region, eliminating the low p-type impurity concentration body region and reducing crystal defects.
This configuration lowers the electrical resistance and stabilizes the potential of the electric field relaxation region, reducing leakage current and enhancing the transistor's operational stability and breakdown voltage characteristics.
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
Technical Field
[0001] The technology disclosed in this specification relates to a field effect transistor and the manufacturing method thereof and is concerned with it.
[0002] A field effect transistor having a trench-type gate electrode and an electric field relaxation region for relaxing the electric field at the lower end of the trench is known. For example, Patent Document 1 discloses a field effect transistor having an electric field relaxation region in contact with the lower end of a trench. Incidentally, the electric field relaxation region may be arranged at a position away from the lower end of the trench. When the field effect transistor is turned off, the depletion layer spreads from the electric field relaxation region to its surroundings, thereby relaxing the electric field at the lower end of the trench.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] The field-effect transistor described in Patent Document 1 has a contact region, a body region (also called a base region), and a connection region. The contact region has a high p-type impurity concentration and is in contact with the source electrode. The body region is located below the contact region. Since the body region is the region where the channel is formed when the field-effect transistor is turned on, the p-type impurity concentration in the body region is low. The connection region is located below the body region and connects the body region and the field relaxation region. The connection region has a higher p-type impurity concentration than the body region. The field relaxation region is connected to the source electrode via the connection region, the body region, and the contact region. Because the p-type impurity concentration in the body region is low, the electrical resistance of the body region is high. Since the body region with high electrical resistance is located between the connection region and the contact region, the electrical resistance of the path connecting the field relaxation region to the source electrode is high. Therefore, the potential of the field relaxation region is unstable. Also, the contact region penetrates the body region. Contact area By forming a deep contact region, the electrical resistance of the connection path between the electric field relaxation region and the source electrode can be reduced. However, forming a deep contact region with a high p-type impurity concentration increases crystal defects in the semiconductor substrate, making it easier for leakage current to occur. This specification proposes a technique for suitably reducing the electrical resistance of the connection path between the electric field relaxation region and the source electrode. [Means for solving the problem]
[0005] The field-effect transistor disclosed herein comprises a semiconductor substrate having a trench on its upper surface, a gate insulating film and a gate electrode disposed within the trench, and a source electrode in contact with the upper surface of the semiconductor substrate. The semiconductor substrate has a source region, a body region, a lower n-type region, a field relaxation region, and a pillar region. The source region is an n-type region in contact with the source electrode and the gate insulating film. The body region is a p-type region in contact with the gate insulating film below the source region. The lower n-type region is an n-type region in contact with the body region from below, in contact with the gate insulating film below the body region, and distributed below the lower end of the trench. The field relaxation region is a p-type region located in a depth range including the lower end of the trench, or in a depth range below the lower end of the trench, and in contact with the lower n-type region. The pillar region is a p-type region extending along the depth direction from a position in contact with the source electrode to a position in contact with the field relaxation region. The pillar region has a contact region and a connection region. The contact region is located in contact with the source electrode and is a p-type region having a higher p-type impurity concentration than the body region. The connection region extends from the lower end of the contact region to a position in contact with the electric field relaxation region and is a p-type region having a lower p-type impurity concentration than the contact region and a higher p-type impurity concentration than the body region. The boundary between the contact region and the connection region is located above the lower end of the body region.
[0006] In this field-effect transistor, there is no body region with a low p-type impurity concentration between the contact region and the connection region; the contact region and the connection region are in contact. Therefore, the field relaxation region is connected to the source electrode via the connection region and the contact region. As a result, the electrical resistance of the path connecting the field relaxation region to the source electrode is low, and the potential of the field relaxation region is stable. Furthermore, since the boundary between the contact region and the connection region is located above the lower end of the body region, the contact region with a high p-type impurity concentration is located within a shallow range near the top surface of the semiconductor substrate. As a result, there are fewer crystal defects in the semiconductor substrate, and leakage current is less likely to occur. Thus, this configuration allows for a favorable reduction in the electrical resistance of the path connecting the field relaxation region to the source electrode. [Brief explanation of the drawing]
[0007] [Figure 1] A cross-sectional perspective view of the field-effect transistor of Example 1. [Figure 2] A cross-sectional view of the field-effect transistor of Example 1 along the xz plane. [Figure 3] A plan view showing the arrangement of the trench, pillar region, and field relaxation region when the field-effect transistor of Example 1 is viewed from above. [Figure 4] A graph showing the p-type impurity concentration distribution at the center line CL. [Figure 5] Diagram illustrating the manufacturing method of the field-effect transistor in Example 1. [Figure 6] Diagram illustrating the manufacturing method of the field-effect transistor in Example 1. [Figure 7] Diagram illustrating the manufacturing method of the field-effect transistor in Example 1. [Figure 8] Diagram illustrating the manufacturing method of the field-effect transistor in Example 1. [Figure 9] Cross-sectional view of the field-effect transistor of Example 2 along the xz plane. [Figure 10] A cross-sectional view of the field-effect transistor of Example 3 along the xz plane. [Figure 11] A cross-sectional view of the field-effect transistor of Example 4 along the xz plane. [Figure 12] A cross-sectional perspective view of the field-effect transistor of Example 5. [Figure 13] A plan view showing the arrangement of the trench, pillar region, and field relaxation region when the field-effect transistor of Example 5 is viewed from above. [Figure 14] A cross-sectional perspective view of the field-effect transistor of Example 6. [Figure 15] A plan view showing the arrangement of the trench, pillar region, and field relaxation region when the field-effect transistor of Example 6 is viewed from above. [Figure 16] A cross-sectional view of the field-effect transistor of Example 7 along the xz plane. [Modes for carrying out the invention]
[0008] The field-effect transistor 10 of Embodiment 1 shown in Figures 1 and 2 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductor materials (for example, Si, GaN, Ga2O3, etc.). Hereinafter, the thickness direction of the semiconductor substrate 12 will be referred to as the z direction, the direction parallel to the upper surface 12a of the semiconductor substrate 12 will be referred to as the x direction, and the direction parallel to the upper surface 12a and perpendicular to the x direction will be referred to as the y direction.
[0009] Multiple trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. On the upper surface 12a, each trench 14 extends linearly in the y direction. Each trench 14 is spaced apart in the x direction. A gate insulating film 16 and a gate electrode 18 are provided within each trench 14. The gate insulating film 16 covers the inner surface of each trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of the gate electrode 18 is covered by an interlayer insulating film 20. As shown in Figure 1, near the upper surface 12a of the semiconductor substrate 12, the semiconductor region is divided into multiple regions by the trenches 14. Hereinafter, each semiconductor region divided by the trenches 14 (i.e., the semiconductor region sandwiched between the trenches 14) will be referred to as a divided region 60.
[0010] The field effect transistor 10 has a source electrode 22 and a drain electrode 24. The source electrode 22 covers the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is insulated from each gate electrode 18 by the interlayer insulating film 20. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.
[0011] The semiconductor substrate 12 has a source region 40, a body region 42, a lower n-type region 44, a plurality of pillar regions 50, and a plurality of electric field relaxation regions 56.
[0012] The source region 40 is an n-type region and has a high n-type impurity concentration. The source region 40 is provided within the partition region 60. The source region 40 is provided in a range including the upper surface 12a and makes an ohmic contact with the source electrode 22. The source region 40 is in contact with the gate insulating film 16 on the side surface of the trench 14.
[0013] The body region 42 is a p-type region and has a low p-type impurity concentration. The body region 42 is provided within the partition region 60. The body region 42 is disposed below the source region 40 and contacts the source region 40 from below. The body region 42 is in contact with the gate insulating film 16 on the side surface of the trench 14 below the source region 40.
[0014] The lower n-type region 44 is disposed below the body region 42. The lower n-type region 44 extends from the position contacting the body region 42 to the lower surface 12b of the semiconductor substrate 12. The lower n-type region 44 has a current dispersion region 45, a JFET region 46, a drift region 47, and a drain region 48.
[0015] The current dispersion region 45 has a medium n-type impurity concentration. The current dispersion region 45 is provided within the partition region 60. The current dispersion region 45 is disposed below the body region 42 and contacts the body region 42 from below. The current dispersion region 45 is in contact with the gate insulating film 16 on the side surface of the trench 14 below the body region 42. The current distribution region 45 corresponds to the first n-type region.
[0016] The JFET region 46 is an n-type region having a lower n-type impurity concentration than the current-dispersion region 45. The JFET region 46 is distributed from within each compartment region 60 to the region below each compartment region 60. The JFET region 46 is located below the current-dispersion region 45 and is in contact with the current-dispersion region 45 from below. The JFET region 46 is in contact with the gate insulating film 16 below the current-dispersion region 45. The JFET region 46 corresponds to the 2n-type region.
[0017] The drift region 47 is an n-type region having a lower n-type impurity concentration than the JFET region 46. The drift region 47 is located below the JFET region 46 and is in contact with the JFET region 46 from below.
[0018] The drain region 48 is an n-type region having a higher n-type impurity concentration than the current dispersion region 45. The drain region 48 is located below the drift region 47 and is in contact with the drift region 47 from below. The drain region 48 is in ohmic contact with the drain electrode 24 at its lower surface 12b.
[0019] Each field relaxation region 56 is a p-type region and is located within a depth range below the lower end of the trench 14. Each field relaxation region 56 is located within the JFET region 46 and is in contact with the JFET region 46. Each field relaxation region 56 is located at the bottom of each compartment region 60 (more specifically, at the bottom center in the x-direction of each compartment region 60). The width of the field relaxation region 56 in the x-direction is wider than the width of the pillar region 50 in the x-direction. Figure 3 shows the arrangement of the trench 14, pillar region 50 and field relaxation region 56 when the semiconductor substrate 12 is viewed from above. Note that in Figure 3, the pillar region 50 overlaps with the field relaxation region 56. As shown in Figures 1 and 3, each field relaxation region 56 extends linearly in the y-direction.
[0020] The pillar regions 50 are p-type regions and are located within each partition region 60. Each pillar region 50 is located in the center of each partition region 60 in the x-direction. Each pillar region 50 extends along the z-direction from a position in contact with the source electrode 22 to a position in contact with the field relaxation region 56. Each pillar region 50 penetrates the source region 40 and the body region 42. As shown in Figures 1 and 3, each pillar region 50 extends linearly in the y-direction. Each pillar region 50 has a contact region 52 and a connection region 54.
[0021] The contact region 52 is the upper part of the pillar region 50 and has a high concentration of p-type impurities. The contact region 52 extends along the z-direction from the position in contact with the source electrode 22 to the depth range of the body region 42. The depth range of the body region 42 refers to the depth range between the upper and lower ends of the body region 42. In other words, the contact region 52 penetrates the source region 40. The concentration of p-type impurities in the contact region 52 is higher than the concentration of n-type impurities in the source region 40.
[0022] The connection region 54 is the lower part of the pillar region 50 and has a p-type impurity concentration that is lower than the contact region 52 but higher than the body region. The p-type impurity concentration in the connection region 54 is higher than the n-type impurity concentration in the current dispersion region 45. The connection region 54 extends along the z-direction from a position touching the lower end of the contact region 52 to the electric field relaxation region 56. The boundary between the contact region 52 and the connection region 54 is located within the depth range of the body region 42.
[0023] Graph G3 in Figure 4 shows the distribution of the p-type impurity concentration D at the center line CL (see Figure 2) in the x-direction of the pillar region 50. Figure 4 shows the distribution of p-type impurity concentration along the path from the center position CP to the upper surface 12a (i.e., the source electrode 22) in the z-direction of the electric field relaxation region 56. Note that the vertical axis in Figure 4 is displayed on a logarithmic scale. As shown in Figure 4, at every position along the path from the center position CP to the source electrode 22, the p-type impurity concentration is higher than the p-type impurity concentration Dc at the center position CP. Therefore, the electrical resistance is low throughout the entire path from the electric field relaxation region 56 to the source electrode 22.
[0024] Next, the operation of the field-effect transistor 10 will be described. When the field-effect transistor 10 is in use, a higher potential is applied to the drain electrode 24 than to the source electrode 22. When a potential greater than or equal to the gate threshold is applied to the gate electrode 18, a channel is formed in the body region 42 within the range adjacent to the gate insulating film 16, and the source region 40 is connected to the current dispersion region 45 by the channel. Then, electrons flow from the source electrode 22 to the drain electrode 24 via the source region 40, channel, current dispersion region 45, JFET region 46, drift region 47, and drain region 48. Since the current dispersion region 45, which has a relatively high n-type impurity concentration, is provided below the body region 42, electrons that flow from the channel into the current dispersion region 45 easily diffuse in the x direction within the current dispersion region 45. Therefore, electrons can flow dispersedly within the lower n-type region 44. This reduces the on-resistance of the field-effect transistor 10.
[0025] When the potential of the gate electrode 18 is reduced to a value lower than the gate threshold, the channel disappears and the field-effect transistor 10 turns off. Then, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the lower n-type region 44, and a depletion layer spreads to the current dispersion region 45, the JFET region 46, and the drift region 47. In addition, since the field relaxation region 56 is connected to the source electrode 22 by the pillar region 50, when the field-effect transistor 10 turns off, a reverse voltage is also applied to the pn junction at the interface between the field relaxation region 56 and the JFET region 46. As a result, a depletion layer spreads from the field relaxation region 56 to the JFET region 46. The depletion layer spreading from the field relaxation region 56 to the JFET region 46 suppresses electric field concentration at the lower end of each trench 14. Therefore, this field-effect transistor has high breakdown voltage characteristics.
[0026] Furthermore, in this field-effect transistor 10, the field relaxation region 56 is connected to the source electrode 22 by a pillar region 50 with a high p-type impurity concentration. In other words, there is no region with a low p-type impurity concentration on the path from the field relaxation region 56 to the source electrode 22. Therefore, the electrical resistance of the path from the field relaxation region 56 to the source electrode 22 is low. Consequently, during the operation of the field-effect transistor 10, the potential of the field relaxation region 56 stabilizes at approximately the same potential as that of the source electrode 22. In other words, during the operation of the field-effect transistor 10, the potential of the field relaxation region 56 is unlikely to fluctuate. Consequently, the width of the depletion layer extending from the field relaxation region 56 to the JFET region 46 can be changed with a fast response speed to the operation of the field-effect transistor 10.
[0027] Next, a method for manufacturing the field-effect transistor 10 will be described. First, a semiconductor substrate 12 having a lower n-type region 44, a body region 42, and an electric field relaxation region 56 is prepared, as shown in Figure 5. At this stage, the trench 14 and pillar region 50 are not provided in the semiconductor substrate 12. Each region shown in Figure 5 may be formed by epitaxial growth or by ion implantation.
[0028] Next, as shown in Figure 6, a mask 90 having an opening 92 is formed on the upper surface 12a of the semiconductor substrate 12. The opening 92 is positioned above the area where the pillar region 50 is to be formed. Next, p-type impurities are ion-implanted into the semiconductor substrate 12 through the mask 90. Here, p-type impurities are implanted at a high concentration in a shallow area near the upper surface 12a. More specifically, p-type impurities are implanted at a high concentration in an area shallower than the lower end of the body region 42. This forms the contact region 52. Next, as shown in Figure 7, p-type impurities are implanted into the semiconductor substrate 12 through the same mask 90 as in Figure 6. Here, p-type impurities are implanted at a lower concentration than in the contact region 52 in the area between the contact region 52 and the electric field relaxation region 56 (i.e., a deeper position when viewed from the upper surface 12a). Also, here, p-type impurities are implanted at a higher concentration than the n-type impurity concentration in the current dispersion region 45. This forms a connection region 54 below the contact region 52. As a result, the pillar region 50 is formed.
[0029] Graph G1 in Figure 4 shows the concentration distribution of p-type impurities implanted in the ion implantation process shown in Figures 6 and 7. In graph G1, the concentration distribution of p-type impurities implanted during the ion implantation process that forms the connection region 54 in Figure 7 corresponds to the first concentration distribution. Furthermore, graph G2 in Figure 4 shows the p-type impurity concentration distribution within the electric field relaxation region 56 before the ion implantation process in Figures 6 and 7. This corresponds to the second concentration distribution.The distribution shown in graph G3 is formed by adding graphs G1 and G2. As shown in graph G1, the p-type impurities implanted in the ion implantation process are distributed such that the concentration of p-type impurities decreases towards the lower end of the implantation range in portion 54x. Also, as shown in graph G2, before the ion implantation process, the electric field relaxation region 56 has a portion 56x at its upper end where the concentration of p-type impurities decreases towards the upper end. Since portions 54x and 56x overlap, graphs G1 and G2 intersect. The p-type impurity concentration Dx1 at the intersection of graphs G1 and G2 is higher than half the p-type impurity concentration Dc at the center position CP of the electric field relaxation region 56. Therefore, in graph G3, which is the sum of graphs G1 and G2, the p-type impurity concentration Dx2 at the intersection is higher than the p-type impurity concentration Dc at the center position CP. As a result, as shown in graph G3, the concentration of p-type impurities is higher throughout the entire path from the center position CP to the source electrode 22.
[0030] Next, as shown in Figure 8, the mask 90 is removed and n-type impurities are ion-implanted into a shallow region near the upper surface 12a to form the source region 40. Here, n-type impurities are implanted into a region shallower than the lower end of the contact region 52 at a concentration lower than the p-type impurity concentration of the contact region 52 and higher than the p-type impurity concentration of the body region 42. As a result, the shallow region of the body region 42 becomes n-type and forms the source region 40, while the contact region 52 remains without becoming n-type. Therefore, the boundary between the contact region 52 and the connection region 54 is located within a depth range that is below the source region 40 and above the lower end of the body region 42.
[0031] Subsequently, the field-effect transistor 10 shown in Figures 1-3 is completed by forming the trench 14, gate electrode 18, source electrode 22, drain electrode 24, etc.
[0032] In the above manufacturing method, p-type impurities are injected into the semiconductor substrate 12 at a high concentration during the process of forming the contact region 52, so that high-density crystal defects are formed around the contact region 52. Since the contact region 52 is formed in a shallow region near the upper surface 12a, high-density crystal defects are not formed at deeper locations. For this reason, leakage current is less likely to occur in field-effect transistors manufactured by this method.
[0033] Furthermore, in the field-effect transistor 10 manufactured by the above manufacturing method, since the body region 42 is not interposed between the contact region 52 and the connection region 54, the electrical resistance between the field relaxation region 56 and the source electrode 22 is low. Therefore, the potential of the field relaxation region 56 can be stabilized. In particular, since the p-type impurity concentration is higher than the p-type impurity concentration Dc at the center CP of the field relaxation region 56 throughout the entire path from the center CP to the source electrode 22, the potential of the field relaxation region 56 can be stabilized even further.
[0034] Furthermore, in the above manufacturing method, the contact region 52 and the connection region 54 are formed by ion implantation via a common mask 90, so the contact region 52 and the connection region 54 can be formed efficiently. In the above embodiment, the contact region 52 was formed before the connection region 54, but the contact region 52 may be formed after the connection region 54.
[0035] In the manufacturing method of Embodiment 1 described above, the electric field relaxation region 56 was formed before the pillar region 50, but the electric field relaxation region 56 may be formed after the pillar region 50.
[0036] Furthermore, in the above-described embodiment 1, the lower n-type region 44 had a current distribution region 45. However, as shown in Figure 9, the lower n-type region 44 may not have a current distribution region 45, and the JFET region 46 may be in contact with the body region 42.
[0037] Furthermore, in the above-described embodiment 1, the electric field relaxation region 56 was located below the lower end of the trench 14. However, as shown in Figure 10, the electric field relaxation region 56 may be located within a depth range that includes the lower end of the trench 14.
[0038] Furthermore, in the above-described embodiment 1, the interface between the contact region 52 and the connection region 54 was located within the depth range of the body region 42. However, as shown in Figure 11, the interface between the contact region 52 and the connection region 54 may also be located within the depth range of the source region 40.
[0039] Furthermore, in the above-described embodiment 1, the electric field relaxation region 56 was not in contact with the trench 14. However, as shown in Figures 12 and 13, the electric field relaxation region 56 may be in contact with the lower end of the trench 14. In this case, as shown in Figure 12, the pillar region 50 may extend linearly along the x-direction (i.e., the direction intersecting the trench 14). Even in this configuration, since the pillar region 50 is arranged within each partition region 60, the potential of each electric field relaxation region 56 can be stabilized.
[0040] Furthermore, in the above-described embodiment 1, the trenches 14 extended in a straight line. However, as shown in Figures 14 and 15, the trenches 14 may extend in a grid pattern. Multiple rectangular partition regions 60 are formed on the upper surface 12a of the semiconductor substrate 12. In this case, for example, a pillar region 50 can be provided in the center of each partition region 60. In this configuration as well, since the pillar region 50 is located within each partition region 60, the potential of each electric field relaxation region 56 can be stabilized.
[0041] Furthermore, as shown in Figure 16, the connection region 54 may penetrate the electric field relaxation region 56. However, as shown in Figures 1 and 2, if the connection region 54 does not penetrate the electric field relaxation region 56, it is easier to reduce electric field concentration around the electric field relaxation region 56.
[0042] The components of the technology disclosed herein are listed below. (Composition 1) It is a field-effect transistor, A semiconductor substrate having a trench on its upper surface, The gate insulating film and gate electrode disposed within the trench, Source electrode in contact with the upper surface of the semiconductor substrate, It has, The aforementioned semiconductor substrate The source electrode and the n-type source region in contact with the gate insulating film, A p-shaped body region in contact with the gate insulating film on the lower side of the source region, A lower n-type region is in contact with the body region from below, is in contact with the gate insulating film on the lower side of the body region, and is distributed below the lower end of the trench, A p-type electric field relaxation region is located within a depth range including the lower end of the trench, or within a depth range below the lower end of the trench, and is in contact with the lower n-type region. A p-shaped pillar region extending along the depth direction from a position in contact with the source electrode to a position in contact with the electric field relaxation region, It has, The aforementioned pillar region is A p-type contact region is provided at a position in contact with the source electrode and has a higher p-type impurity concentration than the body region, A p-type connection region extending from the lower end of the contact region to a position in contact with the electric field relaxation region, having a p-type impurity concentration lower than that of the contact region and higher than that of the body region, It has, The boundary between the contact area and the connection area is located above the lower end of the body area. Field-effect transistor. (Configuration 2) In at least some cross-sections, the width of the electric field relaxation region is wider than the width of the pillar region. On the center line in the width direction of the pillar region, the p-type impurity concentration on the path from the center position in the depth direction of the electric field relaxation region to the source electrode is higher than the p-type impurity concentration at the center position. A field-effect transistor as described in Configuration 1. (Composition 3) A plurality of trenches are provided on the upper surface of the semiconductor substrate, Each of the semiconductor regions demarcated by the trench is provided with the pillar region. A field-effect transistor as described in configuration 1 or 2. (Composition 4) A field-effect transistor according to any one of configurations 1 to 3, wherein the connection region does not penetrate the field relaxation region. (Composition 5) The aforementioned lower n-type region is A first n-type region that is in contact with the body region from below, A second n-type region is in contact with the first n-type region from below, and has a lower n-type impurity concentration than the first n-type region. It has, A field-effect transistor according to any one of configurations 1 to 4, wherein the p-type impurity concentration in the connection region is higher than the n-type impurity concentration in the first n-type region. (Composition 6) A field-effect transistor according to any one of configurations 1 to 5, wherein within the depth range of the source region, the p-type impurity concentration of the pillar region is higher than the n-type impurity concentration of the source region. (Composition 7) A method for manufacturing a field-effect transistor according to any one of the configurations 1 to 6, A contact region formation step in which the contact region is formed by injecting p-type impurities into the semiconductor substrate via a mask, A connection region formation step in which the connection region is formed by injecting p-type impurities into the semiconductor substrate via the same mask as the contact region formation step, A manufacturing method having (Composition 8) In the first concentration distribution, which is the concentration distribution of p-type impurities injected in the connection region formation step, the portion where the concentration decreases towards the bottom overlaps with the portion in the second concentration distribution, which is the concentration distribution of p-type impurities within the electric field relaxation region, where the concentration decreases towards the top. The p-type impurity concentration at the intersection where the first concentration distribution and the second concentration distribution intersect is higher than half the p-type impurity concentration at the center position in the depth direction of the electric field relaxation region. The manufacturing method described in component 7.
[0043] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]
[0044] 14: Trench 16: Gate insulating film 18: Guard gate 22: Source electrode 40: Source area 42: Body area 44: Lower n-type region 50: Pillar area 52: Contact area 54: Connection area 56: Electric field relaxation region
Claims
1. A field effect transistor, comprising: a semiconductor substrate having a trench formed on its upper surface; a gate insulating film and a gate electrode disposed in the trench; a source electrode in contact with the upper surface of the semiconductor substrate; wherein the semiconductor substrate includes an n-type source region in contact with the source electrode and the gate insulating film; a p-type body region in contact with the gate insulating film below the source region; a lower n-type region in contact with the body region from below, in contact with the gate insulating film below the body region, and distributed below the lower end of the trench; a p-type electric field relaxation region disposed within a depth range including the lower end of the trench or within a depth range below the lower end of the trench, and in contact with the lower n-type region; a p-type pillar region extending along the depth direction from a position in contact with the source electrode to a position in contact with the electric field relaxation region; wherein the pillar region includes a p-type contact region provided at a position in contact with the source electrode and having a p-type impurity concentration higher than that of the body region; a p-type connection region extending from the lower end of the contact region to a position in contact with the electric field relaxation region, having a p-type impurity concentration lower than that of the contact region and higher than that of the body region; wherein a boundary between the contact region and the connection region is located above the lower end of the body region; a field effect transistor.
2. In at least a part of a cross section, a width of the electric field relaxation region is wider than a width of the pillar region, and on a center line in a width direction of the pillar region, a p-type impurity concentration on a path from a center position in a depth direction of the electric field relaxation region to the source electrode is higher than a p-type impurity concentration at the center position, the field effect transistor according to Claim 1.
3. a plurality of the trenches are formed on the upper surface of the semiconductor substrate, and the pillar region is provided in each of semiconductor regions partitioned by the trenches, the field effect transistor according to Claim 1 or 2.
4. the field effect transistor according to Claim 1 or 2, wherein the connection region does not penetrate the electric field relaxation region.
5. the lower n-type region includes a first n-type region in contact with the body region from below, and a second n-type region in contact with the first n-type region from below and having an n-type impurity concentration lower than that of the first n-type region, wherein The field-effect transistor according to claim 1 or 2, wherein the p-type impurity concentration in the connection region is higher than the n-type impurity concentration in the first n-type region.
6. The field-effect transistor according to claim 1 or 2, wherein the p-type impurity concentration in the pillar region is higher than the n-type impurity concentration in the source region within the depth range of the source region.
7. A method for manufacturing a field-effect transistor according to claim 1 or 2, comprising: a contact region forming step of forming the contact region by implanting p-type impurities into the semiconductor substrate through a mask; a connection region forming step of forming the connection region by implanting p-type impurities into the semiconductor substrate through the mask common to the contact region forming step; A manufacturing method having the above steps.
8. In a first concentration distribution which is the concentration distribution of the p-type impurities implanted in the connection region forming step, a portion where the concentration decreases toward the lower side overlaps with a portion where the concentration decreases toward the upper side in a second concentration distribution which is the concentration distribution of the p-type impurities in the electric field relaxation region, and the p-type impurity concentration at an intersection where the first concentration distribution and the second concentration distribution intersect is higher than half of the p-type impurity concentration at the central position in the depth direction of the electric field relaxation region. The manufacturing method according to claim 7.
Citation Information
Patent Citations
Silicon carbide semiconductor device, and method of manufacturing the same
JP2019003966A