Inverter circuit, semiconductor device

Abstract

To provide a semiconductor device having a circuit with reduced area, and a semiconductor device having a circuit enabling reduction of power source voltage fluctuation.SOLUTION: A semiconductor device 500 includes a first transistor 491, a second transistor 490, a first power supply wiring 480, and a second power supply wiring 482, the second transistor and the first transistor are stacked, the second power supply wiring and the first power supply wiring are laminated, the second power supply wiring and the first power supply wiring are at least partially overlapped with each other, the second power supply wiring and the first power supply wiring are arranged approximately in parallel, the source electrode 476a of the first transistor is electrically connected to the first power supply wiring, the source electrode of the second transistor is electrically connected to the second power supply wiring, the source electrode 416a of the second power supply wiring, the second transistor is an n-channel type and its channel formation region is formed of an oxide semiconductor, and the first transistor is a p-channel type and its channel formation region is formed of silicon.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. In particular, the term "composition of matter" refers to a process, manufacture, or composition of matter. The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, The present invention relates to a memory device or a processor, or a semiconductor device, a display device, or a light-emitting device. , a lighting device, a power storage device, a memory device, or a processor. DEVICE, DISPLAY DEVICE, LIGHT-EMITTING DEVICE, ILLUMINATION DEVICE, POWER STORAGE DEVICE, MEMORY DEVICE, OR PROCESSOR DRIVE METHOD - Patent application Regarding.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Memory devices, display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits Electronic devices and the like may include semiconductor devices. [Background technology]

[0003] A transistor in which the channel formation region is made of semiconductor silicon (Si) (hereinafter referred to as a Si transistor) These transistors are widely used in electronic devices such as integrated circuits and image display devices. The integrated circuit is configured with n-channel Si transistors and p-channel Si transistors. The cells (logic cells) are made up of wiring, such as inverter circuits, NAND circuits, and flip-flops. The building blocks of the LSI are the 3-D CMOS transistors, which are sometimes called standard cells (see Non-Patent Document 1). ).

[0004] On the other hand, when the channel formation region is made of oxide such as In-Ga-Zn oxide (In-Ga-Zn-O), A transistor made of an oxide semiconductor (OS) (hereinafter referred to as an OS transistor) is known. Since the oxide semiconductor has a larger bandgap than silicon, it is known that a transistor made of the oxide semiconductor has an extremely low off-current. For example, in Patent Document 1, a semiconductor device capable of retaining data even after power-off is described by using an OS transistor in a memory cell.

[0005] In recent years, with the improvement in performance, miniaturization, or weight reduction of electronic devices, the demand for circuits in which semiconductor elements such as miniaturized transistors are integrated at high density has been increasing.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non - Patent Documents

[0007]

Non - Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention has at least one of the following problems. To provide a semiconductor device (cell) having a circuit with a reduced area in which a plurality of transistors are arranged and wired, to provide a circuit having a plurality of transistors arranged and wired and capable of improving the operating speed. ​​​​​ Providing a semiconductor device (cell), a circuit having a plurality of transistors arranged and wired, and capable of reducing power consumption Providing a semiconductor device (cell) having a circuit capable of reducing power consumption, the circuit having a plurality of transistors arranged and wired Providing a semiconductor device (cell) having a circuit capable of reducing fluctuations in power supply voltage, the circuit having a plurality of transistors arranged and wired Providing a semiconductor device (cell) having a plurality of transistors arranged and wired, and being small-sized Providing a semiconductor device having a plurality of transistors arranged and wired, and capable of improving processing speed Providing a semiconductor device having a plurality of transistors arranged and wired, and capable of reducing power consumption Providing a semiconductor device having a plurality of transistors arranged and wired, and capable of reducing cost Providing a semiconductor device having a plurality of transistors arranged and wired, or providing a novel semiconductor device or, providing a novel semiconductor device

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] (1) One aspect of the present invention includes a first transistor, a second transistor, a first conductor, and a second conductor. The second transistor and the first transistor are stacked. A first power supply voltage is supplied to the first conductor, and a second power supply voltage is supplied to the second conductor. The first conductor has a first region, and the second conductor has a second region. The first region and the second region are one layer or a plurality of layers layers layers, and the first region and the second region are electrically connected to each other layers, and the first region and the second region are electrically connected to each other Overlap through the insulator of the layer and extend in parallel, and the source electrode or drain of the first transistor The electrode is electrically connected to the first conductor, and the source electrode or drain of the second transistor The electrode is electrically connected to the second conductor, and the second transistor is an n-channel type The channel formation region of the second transistor is formed of an oxide semiconductor, and the first transistor The channel formation region of the p-channel type transistor is formed of silicon It is a semiconductor device formed.

[0011] (2) Alternatively, one aspect of the present invention has an input terminal and an output terminal, and the width of the first conductor and the width of the second conductor are each wider than the width of the conductor connected to the input terminal and wider than the width of the conductor connected to the output terminal. It is a semiconductor device according to the aspect of (1). The width of the second conductor is wider than the width of the conductor connected to the input terminal and wider than the width of the conductor connected to the output terminal. It is a semiconductor device according to the aspect of (1). Connected semiconductor device according to aspect (1).

[0012] (3) Alternatively, one aspect of the present invention includes a first insulator having a first opening, a second insulator having a second opening, a third conductor, and a fourth conductor. In the first opening, the source electrode or drain electrode of the first transistor and the first conductor are directly connected via the third conductor. In the second opening, the source electrode or drain electrode of the second transistor and the second conductor are directly connected via the fourth conductor. It is a semiconductor device according to any one of aspects (1) or (2). A second insulator having a second opening, a third conductor, and a fourth conductor. In the first opening, the source electrode or drain electrode of the first transistor and the first conductor are directly connected via the third conductor. The source electrode or drain electrode of the first transistor and the first conductor are directly connected via the third conductor. In the second opening, the source electrode or drain electrode of the second transistor and the second conductor are directly connected via the fourth conductor. The source electrode or drain electrode of the second transistor and the second conductor are directly connected via the fourth conductor. It is a semiconductor device according to any one of aspects (1) or (2). Connected semiconductor device according to any one of aspects (1) or (2). It is a semiconductor device according to any one of aspects (1) or (2).

[0013] (4) Alternatively, one aspect of the present invention is between the first conductor and the first transistor, and between the second conductor and the second transistor, and does not have a transistor. It is a semiconductor device according to any one of aspects (1) to (3). Between the conductor and the second transistor, it is a semiconductor device according to any one of aspects (1) to (3) that does not have a transistor. It is a semiconductor device according to any one of aspects (1) to (3).

[0014] (5) Alternatively, in one aspect of the present invention, there is no conductor between the first region and the second region (1 ) and is a semiconductor device according to any one of aspects (1) to (4).

[0015] (6) Alternatively, in one aspect of the present invention, the first conductor and the second conductor are formed of conductors of adjacent layers, and it is a semiconductor device according to any one of aspects (1) to (5).

[0016] (7) Alternatively, in one aspect of the present invention, the channel formation region of the first transistor, the first conductor, the second conductor, and the channel formation region of the second transistor are stacked in this order and are a semiconductor device according to any one of aspects (1) to (6 ).

[0017] (8) Alternatively, in one aspect of the present invention, the channel formation region of the first transistor, the first conductor, the channel formation region of the second transistor, and the second conductor are stacked in this order and are a semiconductor device according to any one of aspects (1) to (6 ).

[0018] (9) Alternatively, in one aspect of the present invention, the direction in which the source electrode, gate electrode, and drain electrode of the first transistor are arranged is parallel or anti-parallel to the direction in which the source electrode, gate electrode, and drain electrode of the second transistor are arranged, and the gate electrode of the first transistor and the gate electrode of the second transistor are electrically connected, and it is a semiconductor device according to any one of aspects (1) to (8).

[0019] (10) Alternatively, in one aspect of the present invention, the direction in which the current flows through the first transistor and the direction in which the current flows through the second transistor are parallel or anti-parallel, and the gate electrode of the first transistor and the gate electrode of the second transistor are electrically connected, and it is a semiconductor device according to any one of aspects (1) to (9). ​​​​​​​ A semiconductor device according to any one of the aspects.

[0020] (11) Alternatively, one aspect of the present invention is an acid for forming a channel formation region of a second transistor The oxide semiconductor has a plurality of c-axis oriented crystal portions, and the region where a diffraction pattern indicating a c-axis oriented crystal is observed occupies 90% or more in a certain range. Any one of (1) to (10) A semiconductor device according to any one of the aspects. A semiconductor device according to any one of the aspects.

[0021] (12) Alternatively, one aspect of the present invention is a memory device having a memory cell array including a semiconductor device according to any one of the aspects (1) to (11). A storage device having a memory cell array including a semiconductor device according to any one of the aspects (1) to (11).

[0022] (13) Alternatively, one aspect of the present invention is an RFID tag having a semiconductor device according to any one of the aspects (1) to (11) and an antenna. An RFID tag having a semiconductor device according to any one of the aspects (1) to (11) and an antenna.

[0023] (14) Alternatively, one aspect of the present invention is an electronic device having a semiconductor device according to any one of the aspects (1) to (11) and a printed wiring board. An electronic device having a semiconductor device according to any one of the aspects (1) to (11) and a printed wiring board.

Advantages of the Invention

[0024] It is possible to provide a semiconductor device having a circuit with a reduced area in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of improving the operating speed in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of reducing power consumption in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of reducing fluctuations in power supply voltage in which transistors are arranged and wired. Or, a novel semiconductor It is possible to provide a semiconductor device having a circuit with a reduced area in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of improving the operating speed in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of reducing power consumption in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of reducing fluctuations in power supply voltage in which transistors are arranged and wired. Or, a novel semiconductor It is possible to provide a semiconductor device having a circuit capable of improving the operating speed in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of reducing power consumption in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of reducing fluctuations in power supply voltage in which transistors are arranged and wired. Or, a novel semiconductor It is possible to provide a semiconductor device having a circuit capable of reducing power consumption in which transistors are arranged and wired. Or, it is possible to provide a semiconductor device having a circuit capable of reducing fluctuations in power supply voltage in which transistors are arranged and wired. Or, a novel semiconductor It is possible to provide a semiconductor device having a circuit capable of reducing fluctuations in power supply voltage in which transistors are arranged and wired. Or, a novel semiconductor It is possible to provide a semiconductor device having a circuit capable of reducing fluctuations in power supply voltage in which transistors are arranged and wired. Or, a novel semiconductor A body device can be provided. Note that the description of these effects does not prevent the existence of other effects. That is, one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0025]

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Embodiments for Carrying Out the Invention

[0026] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not to be construed as being limited to the description of the embodiments shown below alone. In describing the configuration of the invention with reference to the drawings, the same reference numerals are used in common among different drawings. When referring to similar things, the hatch pattern is the same and may not be particularly labeled with reference numerals.

[0027] In the figures, the size, film (layer) thickness, or region may be exaggerated for clarity purposes.

[0028] Also, voltage often indicates the potential difference between a certain potential and a reference potential (e.g., ground potential (GND) or source potential ). Therefore, it is possible to interchangeably refer to voltage as potential .

[0029] The ordinal numbers attached as first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, "first" can be replaced with "second" or "third", etc. It can be described by appropriately replacing it as needed. Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

[0030] Even when it is described as "semiconductor", for example, when the conductivity is sufficiently low, it may have the characteristics of an "insulator". Also, the boundary between "semiconductor" and "insulator" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification may be convertible to "insulator". Similarly, the "insulator" described in this specification may be convertible to "semiconductor". When described as "semiconductor", for example, when the conductivity is sufficiently high, it may have the characteristics of a "conductor". Also, the boundary between "semiconductor" and "conductor" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification may be convertible to "conductor". Similarly, the "conductor" described in this specification may be convertible to "semiconductor". Note that the impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, DOS (Density of State) may be formed in the semiconductor, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example

[0031]

[0032] ​​​​​​​​​​​​​, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, for example, oxygen vacancies may be formed due to the incorporation of impurities such as hydrogen. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 1 5 elements, etc., excluding oxygen and hydrogen.

[0033] Note that in the embodiments shown below, unless otherwise specified, as the insulator, for example, an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium , hafnium, or tantalum may be used in a single layer or in a stacked layer. Alternatively, a resin may be used as the insulator. For example, a resin containing polyimide, polyamide, a cryl, silicone, etc. may be used. By using a resin, it may not be necessary to perform a planarization process on the upper surface of the insulator. In addition, since the resin can form a thick film in a short time, productivity can be improved. As the insulator, preferably an insulator containing aluminum oxide, silicon oxynitride, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used in a single layer or in a stacked layer.

[0034] Also, in the embodiments shown below, unless otherwise specified, as the conductor, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, A conductor containing one or more of ruthenium, silver, indium, tin, tantalum, or tungsten may be used in a single layer or in a stacked layer. For example, it may be an alloy film or a compound film, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese , a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, etc. may be used .

[0035] In this specification, when it is described that A has a region with a concentration B, for example, when the entire depth direction in a certain region of A is the concentration B, when the average value in the depth direction in a certain region of A is the concentration B, when the median value in the depth direction in a certain region of A is the concentration B, when the maximum value in the depth direction in a certain region of A is the concentration B, when the minimum value in the depth direction in a certain region of A is the concentration B, when the convergence value in the depth direction in a certain region of A is the concentration B, when the region where a reliable value of A itself can be obtained in the measurement is the concentration B, etc. are included . .

[0036] Also, in this specification, when it is described that A has a region with a size B, a length B, a thickness B, a width B, or a distance B, for example, when the entire region of A in a certain region is the size B, the length B, the thickness B, the width B, or the distance B, when the average value in a certain region of A is the size B, the length B, the thickness B, the width B, or the distance B, when the median value in a certain region of A is the size B, the length B, the thickness B, the width B, or the distance B, when the maximum value in a certain region of A is the size B, the length B the thickness B, the width B, or the distance B, when the minimum value in a certain region of A is the size B, the length B, the thickness B, the width B, or the distance B, when the convergence value in a certain region of A is the size B, the length B, the thickness B, the width B, or the distance B, ​When it is B, the thickness B, the width B, or the distance B, a region where a reliable value of A itself can be obtained in measurement includes cases where the region is the size B, the length B, the thickness B, the width B, or the distance B, etc.

[0037] Note that the channel length means, for example, in the top view of a transistor, the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that the channel width means, for example, the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor,

[0038] the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, in the region where the channel is actually formed, the cha

[0039] ​​​​​The channel width (hereinafter referred to as the effective channel width) may differ from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible . For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor . In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view . For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor . In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view . For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor . In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view

[0040] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement . For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known . Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width . For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known

[0041] Note that the functions of the "source" and "drain" of the transistor may be interchanged when different polarities of transistors are adopted or when the direction of the current changes in the circuit operation . Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable . Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable . Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable

[0042] Note that in this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less . Therefore, the case of -5° or more and 5° or less is also included. Also, " "Vertical" refers to a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case where the angle is 85° or more and 95° or less is also included.

[0043] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0044] A configuration example of a semiconductor device in which transistors are arranged and wired will be described with reference to FIG. 1. will be described.

[0045] FIG. 1 is a schematic diagram of a semiconductor device 500 in which transistors 490 and 491 are arranged and wired. The semiconductor device 500 includes a transistor 491, a conductor 480 that functions as a wiring, a transistor 490, and a conductor 482 that functions as a wiring. The semiconductor device 500 may have a transistor formed simultaneously with the transistor 490. The transistor and the transistor 490 have a channel formation region formed of the same semiconductor material. The semiconductor device 500 may have a transistor formed simultaneously with the transistor 491. The transistor and the transistor 491 have a channel formation region formed of the same semiconductor material. The transistors 490 and 491 are stacked. The conductor 480 has a function of supplying a high power supply voltage (VDD) (hereinafter also referred to as a high power supply wiring). The conductor 482 has a function of supplying a low power supply voltage (VSS) (hereinafter also referred to as a low power supply wiring). The conductor 482 and the conductor 480 are stacked. The transistor 491 can be, for example, a p-channel type transistor with a high switching speed. For example, the switching speed of the transistor 491 is The semiconductor device 500 may have a transistor formed simultaneously with the transistor 490. The transistor and the transistor 490 have a channel formation region formed of the same semiconductor material. The semiconductor device 500 may have a transistor formed simultaneously with the transistor 491. The transistor and the transistor 491 have a channel formation region formed of the same semiconductor material. The transistors 490 and 491 are stacked. The conductor 480 has a function of supplying a high power supply voltage (VDD) (hereinafter also referred to as a high power supply wiring). The conductor 482 has a function of supplying a low power supply voltage (VSS) (hereinafter also referred to as a low power supply wiring). The conductor 482 and the conductor 480 are stacked. The conductor 482 has a function of supplying a low power supply voltage (VSS) (hereinafter also referred to as a low power supply wiring). The conductor 482 and the conductor 480 are stacked.

[0046] The transistor 491 can be, for example, a p-channel type transistor with a high switching speed. For example, the switching speed of the transistor 491 is Less than 10 ns, preferably less than 1 ns, more preferably less than 0.1 ns. As an example a p-channel Si transistor can be used as transistor 491. The transistor 490 can be, for example, an n-channel transistor with a high switching speed. For example, the switching speed of transistor 490 is less than 10 ns, preferably less than 1 ns, more preferably less than 0.1 ns. As an example, a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region can be used as transistor 490 (hereinafter also referred to as a transistor using an oxide semiconductor).

[0047] Note that the switching speed of a transistor represents the speed at which a single transistor changes from a non-conducting state to a conducting state. This can be interpreted as the speed corresponding to the time during which the charge corresponding to the increment of the drain current of the transistor is accumulated in the gate capacitance when the gate voltage changes. Alternatively, the switching speed of a transistor may represent the speed corresponding to the maximum frequency (cutoff frequency) at which the current gain becomes 1 or more when the transistor is used as an amplifier.

[0048] The semiconductor device 500 can function as a circuit by arranging and wiring transistor 491 and / or a transistor formed simultaneously with transistor 491, and transistor 490 and / or a transistor formed simultaneously with transistor 490. The semiconductor device 500 can supply power to the transistors. It has power supply wiring. The semiconductor device 500 is, for example, a component of various electronic circuits and It may be a unit that becomes. Such a unit is a standard cell, a logic cell, or simply It is called a cell.

[0049] The transistors and power supply wiring of the semiconductor device 500 are arranged closely. Also, the power The wiring is preferably arranged regularly at the end of the cell area. Thereby, the electronic circuit can be Made smaller.

[0050] The semiconductor device 500 (cell) includes an inverter circuit, a NAND circuit, an AND circuit, a NOR Circuit, OR circuit, buffer, level shifter, XOR circuit, XNOR circuit, AND-NOR Circuit, OR-NAND circuit, AND-OR-INV circuit, OR-AND-INV circuit, a Analog switch, flip-flop, settable flip-flop, resetable f Lip flop, set and resetable flip-flop, adder, half adder, m Multiplexer, demultiplexer, register, scan register, retention register Isolator, decoder, etc. are included.

[0051] In particular, by arranging and wiring p-channel transistors and n-channel transistors, A complementary metal oxide semiconductor (CMOS) circuit can be configured. By configuring a CMOS circuit, The power consumption of the electronic circuit can be reduced. By configuring.

[0052] As an electronic circuit in which the semiconductor device 500 (cell) is used, a CPU, a GPU (Graph ICS Processing Unit), DSP (Digital Signal Processor), MCU (Microcontroller Unit), RF- ID (Radio Frequency Identification), custom L SI, etc. In these electronic circuits, a plurality of cells are arranged in a plurality of rows, and the input / output terminals of the cells are connected by wiring so as to function as an electronic circuit. The low-power wiring (conductor 482) is connected to the source electrode (or source region) of the transistor 490. Or, the source electrode (or source region) of the transistor 490 is connected to the low-power wiring (conductor 482) via a transistor formed simultaneously with the transistor 490. The high-power wiring (conductor 480) is connected to the source electrode (or source region) of the transistor 491. Or, the source electrode (or source region) of the transistor 491 is connected to the high-power wiring (conductor 480) via a transistor formed simultaneously with the transistor 491. The low-power wiring (conductor 482) and the high-power wiring (conductor 480) are arranged substantially in parallel and overlap each other. The output signal OUT is output from one or a plurality of the drain electrodes (or drain regions) of the transistor 490, the drain electrodes (or drain regions) of the transistors formed simultaneously with the transistor 490, the drain electrodes (or drain regions) of the transistor 491, or the drain electrodes (or drain regions) of the transistors formed simultaneously with the transistor 491. The input signal IN is applied to the gate electrode of the transistor 490, or the transistor

[0053] The low-power wiring (conductor 482) is connected to the source electrode (or source region) of the transistor 490. Or, the source electrode (or source region) of the transistor 490 is connected to the low-power wiring (conductor 482) via a transistor formed simultaneously with the transistor 490. The high-power wiring (conductor 480) is connected to the source electrode (or source region) of the transistor 491. Or, the source electrode (or source region) of the transistor 491 is connected to the high-power wiring (conductor 480) via a transistor formed simultaneously with the transistor 491. The low-power wiring (conductor 482) and the high-power wiring (conductor (480) are arranged substantially in parallel and overlap each other. The output signal OUT is output from one or a plurality of the drain electrodes (or drain regions) of the transistor 490, the drain electrodes (or drain regions) of the transistors formed simultaneously with the transistor 490, the drain electrodes (or drain regions) of the transistor 491, or the drain electrodes (or drain regions) of the transistors formed simultaneously with the transistor 491. The input signal IN is applied to the gate electrode of the transistor 490, or the transistor The low-power wiring (conductor 482) and the high-power wiring (conductor (480) are arranged substantially in parallel and overlap each other. The output signal OUT is output from one or a plurality of the drain electrodes (or drain regions) of the transistor 490, the drain electrodes (or drain regions) of the transistors formed simultaneously with the transistor 490, the drain electrodes (or drain regions) of the transistor 491, or the drain electrodes (or drain regions) of the transistors formed simultaneously with the transistor 491. The input signal IN is applied to the gate electrode of the transistor 490, or the transistor formed simultaneously with the transistor 490, the drain electrode (or drain region) of the transistor 491, or the drain electrode (or drain region) of the transistor formed simultaneously with the transistor 491. The input signal IN is applied to the gate electrode of the transistor 490, or the transistor 491, or the transistor formed simultaneously with the transistor 491. formed simultaneously with the transistor 491. The input signal IN is applied to the gate electrode of the transistor 490, or the transistor formed simultaneously with the transistor 490, the drain electrode (or drain region) of the transistor 491, or the drain electrode (or drain region) of the transistor formed simultaneously with the transistor 491. The input signal IN is applied to the gate electrode of the transistor 490, or the transistor The gate electrode of the transistor formed at the same time as the transistor 490, the gate of the transistor 491 Electrode or one of the gate electrodes of a transistor formed at the same time as the transistor 491 One or more inputs are made.

[0054] The low power wiring (conductor 482) and the high power wiring (conductor 480) are overlapped with each other in a generally parallel manner. By being arranged in such a manner, the wiring has a large parasitic capacitance (also called wiring capacitance). As a result, by using this wiring as a power supply wiring, voltage fluctuations due to power supply noise can be reduced. The circuit is capable of suppressing the power supply voltage fluctuation and is resistant to power supply noise. In addition, in a semiconductor device to which the semiconductor device 500 (cell) is applied, In order to reduce fluctuations in the power supply voltage, a capacitive element may be intentionally provided in the power supply wiring. The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) have a large wiring capacitance. This allows the size of such a capacitance element to be reduced, which in turn allows the semiconductor device to be miniaturized. In addition, the low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) By arranging the wirings so as to overlap each other, the area occupied by the wirings can be reduced, and The area of the semiconductor device 500 (cell) can be reduced.

[0055] The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) are adjacent to each other in the vertical direction. It is preferable to use conductors for lines. It is preferable to use conductors for wiring adjacent to each other in the vertical direction. Therefore, the distance between the wires is small and the wires have a large capacitance. It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. , it becomes possible to miniaturize the semiconductor device to which the semiconductor device 500 (cell) is applied.

[0056] Note that the conductor A for wiring and the conductor B for wiring being adjacent in the vertical direction means, for example, when the semiconductor device has n layers of conductors for wiring in order from the substrate side, the conductor A for wiring is the conductor for the i-th layer of wiring, and the conductor B for wiring is the conductor for the (i + 1)-th layer of wiring (i is an integer of 1 or more and (n - 1) or less).

[0057] Alternatively, it is preferable to use conductors of adjacent layers for the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480). Alternatively, in the semiconductor device 500 (cell), it is preferable that there is no conductor overlapping these between the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480). 482) and the high-power supply wiring (conductor 480). It is preferable not to have conductors overlapping these between the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480).

[0058] The transistor 490 and the transistor 491 are arranged so as to overlap each other. As a result , the area of the semiconductor device 500 (cell) can be reduced.

[0059] That the transistor 490 and the transistor 491 overlap each other means that at least a part of the gate electrode, drain electrode (or drain region), or source electrode (or source region) of the transistor 490 overlaps with a part of the gate electrode, drain electrode (or drain region), or source electrode (or source region) of the transistor 491. Or, a region including the gate electrode, drain electrode (or drain region), and source electrode (or source region) of the transistor 490 overlaps with a region including the gate electrode, drain electrode (or drain region), and source electrode (or source region) of the transistor 491. and a region including a source electrode (or a source region) overlap at least partially. That is, it means that a region including components of the transistor 490 and a region including components of the transistor 491 overlap at least partially.

[0060] The transistor 490 and the transistor 491 are arranged to overlap each other, and the direction in which current flows in the transistor 490 and the direction in which current flows in the transistor 491 are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of the transistor 490 are arranged and the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491 are arranged are generally parallel. As a result, when connecting the gate electrode of the transistor 490 and the gate electrode of the transistor 491, the transistor 490 and the transistor 491 can be arranged in a narrow region including the connection portion of the gate electrodes, and the area of the semiconductor device 500 (cell) can be reduced.

[0061] Also, by stacking the transistor 491 or a transistor of the same type as the transistor 491 and the transistor 490 or a transistor of the same type as the transistor 490, the area can be reduced compared to the case where they are not stacked, so the wiring length for connecting between the transistors can be shortened. As a result, the parasitic capacitance associated with the signal wiring can be reduced. As a result, the operating speed of the semiconductor device 500 (cell) can be improved.

[0062] The transistor 490 is located above the transistor 491. The conductor 482 is located above the conductor 480. The conductor 482 is located above the transistor 491. ​​​​​​​​​​​​​

[0063] Note that when part A is above part B, it means that part A is located farther from the substrate side than part B. Or it means that part A is formed after part B. The part includes regions, conductors, insulators, transistors, electrodes, etc. In particular, when the semiconductor device has conductors for wiring in n layers in order from the substrate side, when part A is below conductor C, it means that part A is located between the conductor for wiring in the i-th layer and the conductor for wiring in the (i + 1)-th layer, and conductor C uses conductors for wiring from the (i + 1)-th layer to the n-th layer. When part A is above conductor C, it means that part A is located between the conductor for wiring in the i-th layer and the conductor for wiring in the (i + 1)-th layer, and conductor C uses conductors for wiring from the first layer to the i-th layer.

[0064] The transistors and power supply wiring of the semiconductor device 500 (cell) are arranged closely. Thereby, the electronic circuit can be made smaller. The area occupied by the semiconductor device 500 (cell) (also called the cell area) may be a rectangle with a height Hcell and a width Wcell. By the way, for the wiring connecting a plurality of cells, it is preferable to use at least a wiring (conductor) extending in the height direction and a wiring (conductor) extending in the width direction, which are substantially perpendicular to each other. If the pitch of the wiring extending in the height direction is Px and the pitch of the wiring extending in the width direction is Py, the cell may have a cell area where the height Hcell of the cell is an integer multiple of Py and the width Wcell of the cell is an integer multiple of Px. By doing so, the connection between cells can be performed efficiently.

[0065] FIG. 39 is an example of a top view of an inverter circuit cell. A detailed description of the top view will be given later. Here, the cell area will be described. In FIG. 39, for ease of understanding, a part of the insulator is shown with some omitted. The cell shown in FIG. 39 has a transistor 490, a transistor 491, a conductor 480, and a conductor 482. Transistor 490 and transistor 4 91 overlap. Also, conductor 480 and conductor 482 overlap. The height of the cell is 6*Py, and the width is 4*Px.

[0066] The semiconductor device 500 (cell) described above can reduce the cell area. For example , in the case of an inverter circuit, the height of the cell can be preferably set to WW + WT + 5*Py or less, more preferably, WW + WT + 4*Py or less. Here, WW is the power line width , and WT is the maximum channel width among the channel widths of the plurality of transistors included in the semiconductor device 500 (cell). Also, the width of the cell can be set to 5*Px or less, more preferably, 4*Px or less . Also, in the case of a small inverter, the height of the cell can be set to 6*Py or less . Also, for example, in the case of a 2-input NAND circuit, the height of the cell can be preferably set to WW + WT + 7*Py or less, more preferably, WW + WT + 5*Py or less . Also, the width of the cell can be preferably set to 5*Px or less, more preferably, 4*Px or less .

[0067] Also, it is preferable that the heights of the plurality of cells are the same. By doing so, the height of the cell is used as the row height, and by arranging the plurality of cells in a plurality of rows, efficient placement and wiring can be performed.

[0068] In order to closely arrange the transistor and the power supply wiring of the semiconductor device 500 (cell), When the source electrode or drain electrode of the transistor 490 and the conductor (482) that functions as a power supply wiring are electrically connected, it is preferable that the electrode and the conductor are directly connected through a conductor (also called a via) provided in an opening provided in an insulator. Alternatively, it is preferable to connect through a via and a conductor sandwiched between the vias. When the source electrode or drain electrode of the transistor 491 and the conductor (48 0) that functions as a power supply wiring are electrically connected, it is preferable that the electrode and the conductor are directly connected through a conductor provided in an opening provided in an insulator. Alternatively, it is preferable to connect through a via and a conductor sandwiched between the vias. When the source electrode or drain electrode of the transistor 491 and the conductor (48 0) that functions as a power supply wiring are electrically connected, it is preferable that the electrode and the conductor are directly connected through a conductor provided in an opening provided in an insulator. Alternatively, it is preferable to connect through a via and a conductor sandwiched between the vias.

[0069] In order to closely arrange the transistor and the power supply wiring of the semiconductor device 500 (cell), The semiconductor device 500 (cell) preferably has no transistors between the transistor 490 and the conductor ( 482) that functions as a power supply wiring, and between the transistor 491 and the conductor (480) that functions as a power supply wiring.

[0070] In order to closely arrange the transistor and the power supply wiring of the semiconductor device 500 (cell) and also efficiently arrange a plurality of cells, the power supply wiring is preferably regularly arranged at the end of the cell area. In particular, in the semiconductor device (cell) according to one aspect of the present invention, the power supply wiring may be arranged only at the end of one side of the cell area. The cell area may be reduced compared to the case where the power supply wiring is arranged at the ends of both sides of the cell area. In some cases, the cell area can be reduced. When compared with the case where the power supply wiring is arranged at the ends of both sides of the cell area, the cell area may be reduced.

[0071] A configuration example of a semiconductor device in which transistors are arranged and wired will be described with reference to FIG. 31. This is done. The schematic diagram of the semiconductor device shown in FIG. 31 shows the semiconductor device 500 (cell) shown in FIG. 1 having the transistor 491, the high - power supply wiring (conductor 480), the transistor 490, and the low - power supply wiring (conductor 482), and schematically represents the positional relationship among them.

[0072] In FIG. 31(A), the semiconductor device 500 (cell) has the transistor 491, the high - power supply wiring (conductor 480), the low - power supply wiring (conductor 482), and the transistor 490 stacked in this order. In other words, the high - power supply wiring (conductor 480) is arranged above the transistor 491, the low - power supply wiring (conductor 482) is arranged above and overlaps the high - power supply wiring (conductor 480), and the transistor 490 is arranged above the low - power supply wiring (conductor 482).

[0073] With such a configuration, the low - power supply wiring (conductor 482) and the high - power supply wiring (conductor 48 0) are located close to each other in the vertical direction, so they have a large wiring capacitance. As a result, a circuit that is strong against power supply noises and can reduce fluctuations in the power supply voltage can be realized. Also, it becomes possible to miniaturize the semiconductor device to which the semiconductor device 500 (cell) is applied.

[0074] In FIG. 31(B), the semiconductor device 500 (cell) has the transistor 491, the high - power supply wiring (conductor 480), the transistor 490, and the low - power supply wiring (conductor 482) stacked in this order. In other words, the high - power supply wiring (conductor 480) is arranged above the transistor 491, the transistor 490 is arranged above the high - power supply wiring (conductor 480), and the low - power supply wiring (conductor 482) is arranged above the transistor 490.

[0075] In the semiconductor device 500 (cell), the source electrode (or source region) or drain electrode (or drain region) of the transistor 490 may be configured to be connected only to a conductor above the transistor 490. In that case, the conductor is used for the connection wiring between the transistors within the semiconductor device 500 (cell). Therefore, it may be difficult to use the conductor as the connection wiring between a plurality of semiconductor devices 500 (cells). This is because, in the connection between a plurality of semiconductor devices 500 (cells), the wiring positions are irregular, and if there are scattered unusable regions, the wiring that has to detour increases. Even in such a case, with almost no increase in area, the conductor can be used as a power supply wiring. This is because the power supply wiring is regularly arranged at the end of the semiconductor device 500 (cell) region. In such a case, the stacked power supply wiring (conductor 482) and the connection wiring between the transistors within the semiconductor device 500 (cell) can be formed of conductors on the same layer, and the manufacturing cost can be kept low. With reference to FIGS. 2 to 4 and FIG. 19, a more specific device structure of the semiconductor device 500 (cell) in FIG. 1 will be described. The semiconductor device 501 (cell) shown in FIG. 2 corresponds to the semiconductor device 500 (cell) shown in FIG. 1 and is a semiconductor device (cell) in which the transistors 490 and 491 are arranged and wired.

[0076] FIG. 2 is a schematic diagram showing an example of the configuration of the semiconductor device 501 (cell). In FIGS. 2 and 3, for ease of understanding, a part such as an insulator is omitted, and components formed on the same layer are also shown with some omissions.

[0077] FIG. 2 is a schematic diagram showing an example of the configuration of the semiconductor device 501 (cell). Note that in FIGS. 2 and 3, for ease of understanding, a part such as an insulator is omitted, and components formed on the same layer ​The conductors and the like are given the same hatching pattern.

[0078] FIG. 3 is a top view showing an example of the configuration of the semiconductor device 501 (cell). In FIG. 3(A), a top view of a region including the transistor 491 and the conductor 480 in the semiconductor device 501 (cell) is shown, and in FIG. 3(B), a top view of a region including the transistor 490 and the conductors 482 and 484 in the semiconductor device 501 (cell) is shown.

[0079] FIG. 4 is a cross-sectional view showing an example of the configuration of the semiconductor device 501 (cell). On the left side of FIG. 4, a cross-sectional view taken along the dashed-dotted line A1 - A2 in FIGS. 3(A) and 3(B) is shown, and on the right side of the same figure a cross-section taken along the dashed-dotted line B1 - B2 in FIGS. 3(A) and 3(B) is shown.

[0080] The semiconductor device 501 (cell) has the transistor 491 and the transistor 490, and constitutes the CMOS inverter circuit shown in FIG. 1 9. In the CMOS inverter circuit, the output signal OUT is the inverted signal of the input signal IN. As an example, for the transistor 491, a p-channel transistor with a fast switching speed can be used. In the present embodiment, it will be described assuming that a p-channel Si transistor is used. As an example, an n-channel transistor with a fast switching speed can be used as the transistor 490. In the present embodiment, it will be described assuming that a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region is used as the transistor 490.

[0081] The semiconductor device 501 (cell) includes the transistor 491, the conductor 480, and the transistor It has 490, a conductor 482, conductors 424a and 424b. Transistor 4 90 and transistor 491 are stacked. Conductor 482 and conductor 480 are stacked . Transistor 491 has region 476a, region 476b, and conductor 454. The transistor 490 has conductors 416a, 416b, and conductor 404.

[0082] The semiconductor device 501 (cell) has a conductor 484. Transistor 490 has a conductor 413.

[0083] Conductor 482 functions as a wiring (low-power supply wiring) for supplying a low power supply voltage (VSS). Conductor 480 functions as a wiring (high-power supply wiring) for supplying a high power supply voltage (VDD). Regions 476a and 476b function as one and the other of the source electrode ( or source region) and the drain electrode (or drain region) of transistor 491 . Conductor 454 functions as the gate electrode of transistor 491. Conductors 416a and 416b function as one and the other of the source electrode (or source region) and the drain electrode (or drain region) of transistor 490. Conductor 404 functions as the gate electrode of transistor 490.

[0084] Conductor 413 functions as the gate electrode of transistor 490. Conductor 48 4 functions as a wiring for supplying a voltage to the gate electrode of transistor 490.

[0085] Note that both conductor 413 and conductor 404 are gate electrodes of transistor 490 and It has the functions described above, and the potentials applied to each of them may be different. For example, By applying a negative or positive gate voltage to the conductor 413, the threshold voltage of the transistor 490 may be adjusted.

[0086] The high - power supply wiring (conductor 480) is electrically connected to the source region (region 476a) of the transistor 491. The low - power supply wiring (conductor 482) is electrically connected to the source electrode (conductor 416a) of the transistor 490. The high - power supply wiring (conductor 480) and the low - power supply wiring (conductor 482) are arranged overlapping each other substantially in parallel. The gate electrode (conductor 404) of the transistor 490 and the gate electrode (conductor 454) of the transistor 491 are electrically connected. The drain electrode (conductor 416b) of the transistor 490 and the drain region (region 476b) of the transistor 491 are electrically connected. The output signal OUT is output to the outside from the conductor 424a located above the conductor 416b, which is connected to the drain electrode (conductor 416b) of the transistor 490 and the drain region (region 476b) of the transistor 491. The input signal IN is input from the outside through the conductor 424b located above the conductor 404, which is connected to the gate electrode (conductor 404) of the transistor 490 and the gate electrode (conductor 454) of the transistor 491. The gate electrode (conductor 413) of the transistor 490 is electrically connected to the wiring (conductor 484) that supplies the gate voltage. The wiring (conductor 484) that supplies the gate voltage and the low - power supply wiring (conductor 482) are arranged overlapping each other substantially in parallel.

[0087] The gate electrode (conductor 413) of the transistor 490 is electrically connected to the wiring (conductor 484) that supplies the gate voltage. The wiring (conductor 484) that supplies the gate voltage and the low - power supply wiring (conductor 482) are arranged overlapping each other substantially in parallel.

[0088] ​​The low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) are arranged such that they overlap each other substantially in parallel, and as a result, the wiring has a large parasitic capacitance (also referred to as wiring capacitance). Consequently, by using such wiring as a power supply wiring, voltage fluctuations can be reduced with respect to power supply noise, and a circuit that is resistant to power supply noise and can reduce fluctuations in the power supply voltage can be realized. In addition, in a semiconductor device to which the semiconductor device 501 (cell) is applied, a capacitance element may be intentionally provided in the power supply wiring in order to reduce fluctuations in the power supply voltage. Since the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) have a large wiring capacitance, such a capacitance element can be made smaller. As a result, it becomes possible to miniaturize the semiconductor device to which the semiconductor device 501 (cell) is applied. In addition, since the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) are arranged so as to overlap each other, the occupied area of the wiring can be reduced, and the area of the semiconductor device to which the semiconductor device 501 (cell) is applied can be reduced. As the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482), conductors for wiring adjacent to each other in the vertical direction can be used. By using conductors for wiring adjacent to each other in the vertical direction, the distance between the wirings becomes smaller, and the wiring has a large wiring capacitance. As a result, a circuit that is resistant to power supply noise and can reduce fluctuations in the power supply voltage can be realized. In addition, it becomes possible to miniaturize the semiconductor device to which the semiconductor device 501 (cell) is applied. Alternatively, the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) are conductors in adjacent layers.

[0089]

[0090] It is preferable to use an electric body. Alternatively, it is preferable not to have a conductor between the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480). It is preferable not to have a conductor between them.

[0091] Transistors 490 and 491 are arranged to overlap each other. As a result , the area of the semiconductor device 501 (cell) can be reduced.

[0092] Transistors 490 and 491 are arranged to overlap each other, and the direction in which current flows in transistor 490 and the direction in which current flows in transistor 491 are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490 are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491 are arranged are generally parallel. As a result, the drain electrode of transistor 490 and the drain electrode of transistor 491 can be arranged close to each other, and the gate electrode of transistor 490 and the gate electrode of transistor 491 can be arranged close to each other. By arranging them in this way, when connecting the drain electrode of transistor 490 and the drain electrode of transistor 491 and connecting the gate electrode of transistor 490 and the gate electrode of transistor 491, the area of the connection region can be reduced, and the area of the semiconductor device 501 (cell) can be reduced. By arranging them in this way, the drain electrode of transistor 490 and the drain electrode of transistor 491 are connected, and the gate electrode of transistor 490 and the gate electrode of transistor 491 are connected, the area of the connection region can be reduced, and the area of the semiconductor device 501 (cell) can be reduced.

[0093] The direction in which current flows in transistor 490 (or the direction in which the source electrode, gate electrode, and drain electrode of transistor 490 are arranged) and the extending direction of the low-power supply wiring (conductor 482) are generally parallel. In this case, the source electrode and drain of transistor 490 electrode Even if the electrodes are arranged in a swapped manner, the source electrode and the low-power supply wiring (conductor 482) can be connected by a short wiring, which is preferable. The direction in which current flows in the transistor 491 (or the arrangement direction of the source electrode, gate electrode, and drain electrode of the transistor 491 direction) and the extending direction of the high-power supply wiring (conductor 480) are substantially parallel. In this case, regardless of whether the source electrode of the transistor 491 is located on either side of the gate electrode, it can be connected to the high-power supply wiring (conductor 480) by a short wiring, which is preferable.

[0094] Note that the direction in which current flows in the transistor 490 (or the arrangement direction of the source electrode, gate electrode, and drain electrode of the transistor 490) and the extending direction of the low-power supply wiring (conductor 48 2) may be substantially perpendicular. When the source electrode of the transistor 490 is connected to the low-power supply wiring (conductor 482), it is possible to arrange the source electrode so as to overlap with the low-power supply wiring, which is preferable because the area can be reduced. The direction in which current flows in the transistor 491 (or the arrangement direction of the source electrode, gate electrode, and drain electrode of the transistor 491) and the extending direction of the high-power supply wiring (conductor 480) may be substantially perpendicular. When the source electrode of the transistor 491 is connected to the high-power supply wiring (conductor 480), it is possible to arrange the source electrode so as to overlap with the high-power supply wiring, which is preferable because the area can be reduced. Note that when the input / output terminals are connected to adjacent cells or proximate cells, the output terminal of the output signal OUT is connected to the drain electrode of the transistor 490 without passing through the conductor 424a.

[0095] In addition, when the input / output terminals are connected to adjacent cells or proximate cells, the output terminal of the output signal OUT is connected to the drain electrode of the transistor 490 without passing through the conductor 424a. ​The drain region (region 476b) of the conductor 416b) or the transistor 491 may be directly connected to the input terminal of an adjacent cell or a neighboring cell. Also, the input terminal of the input signal IN may be directly connected to the output terminal of an adjacent cell or a neighboring cell without passing through the conductor 424b, to the gate electrode (conductor 404) of the transistor 490 or to the gate electrode (conductor 454) of the transistor 491. In FIG. 2, the semiconductor device 501 (cell) has a transistor 491, a high power supply wiring (conductor 480), a low power supply wiring (conductor 482), a conductor 484, and a transistor 490 stacked in this order. In other words, the high power supply wiring (conductor 480) is disposed above the transistor 491, the low power supply wiring (conductor 482) is disposed and overlaps above the high power supply wiring (conductor 480), the conductor 484 is disposed and overlaps above the low power supply wiring (conductor 482), and the transistor 490 is disposed above the conductor 484. Since the source electrode (or source region) of the transistor 491 is connected to the high power supply wiring (conductor 480), it is easier and preferable to connect than the case where the source electrode (or source region) of the transistor 491 is connected to the low power supply wiring (conductor 482) disposed above the high power supply wiring (conductor 480). Since the source electrode (or source region) of the transistor 490 is connected to the low power supply wiring (conductor 482), it is easier and preferable to connect than the case where the source electrode (or source region) of the transistor 490 is connected to the high power supply wiring (conductor 480) disposed below the low power supply wiring (conductor 482).

[0096]

[0097]

[0098] ​​​​​​​​​​​​​​​Also, in the semiconductor device 501 (cell), the wiring widths of the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482) are preferably wider than the wiring width of the gate electrode (conductor 454) of the transistor 491, the gate electrode (conductor 404) of the transistor 490, or the signal wiring for transferring input / output signals. Alternatively, the wiring widths of the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482) are preferably wider than the width of the wiring (conductor) connected to the input terminal and the width of the wiring (conductor) connected to the output terminal. This is because the power supply wiring often conducts more current than the signal wiring, and it is preferable to make the wiring resistance lower than that of the signal wiring. Also, in the semiconductor device 501 (cell), the width of the region where the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482) overlap is preferably wider than the wiring width of the gate electrode (conductor 454) of the transistor 491, the gate electrode (conductor 404) of the transistor 490, or the signal wiring for transferring input / output signals. Alternatively, the width of the region where the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482) overlap is preferably wider than the width of the wiring (conductor) connected to the input terminal and the width of the wiring (conductor) connected to the output terminal. The cross-sectional view of the semiconductor device shown in FIG. 4 will be used for a more detailed explanation. The semiconductor device 501 (cell) shown in FIG. 4 includes a transistor 491, an insulator 442 on the transistor 491, and a transistor 490 on the insulator 442. Note that the insulator 442 is preferably an insulator having a function of blocking oxygen and hydrogen.

[0099]

[0100]

[0101]

[0102]

[0100]

[0101]

[0102]

[0102]

[0102] Transistor 491 includes an insulator 462 on a semiconductor substrate 400, a conductor 454 on the insulator 462, an insulator 470 in contact with a side surface of the conductor 454, regions 476a and 476b that are regions not overlapping with the conductor 454 and the insulator 470 in the semiconductor substrate 400, and a region 474 that is a region overlapping with the insulator 470. The semiconductor substrate 400 may be made of, for example, a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, or gallium oxide. Note that the semiconductor substrate 400 may be made of an amorphous semiconductor or a crystalline semiconductor, and examples of the crystalline semiconductor include a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. The insulator 462 functions as a gate insulator of the transistor 491. The conductor 454 functions as a gate electrode of the transistor 491. The insulator 470 functions as a sidewall insulator (also referred to as a sidewall) of the conductor 454. The regions 476a and 476b function as a source region or a drain region of the transistor 491. The region 474 functions as a lightly doped drain (LDD) region of the transistor 491. Note that the region 474 can be formed by impurity addition using the conductor 454 as a mask. Then, the insulator 470 is formed, and the regions 476a and 476b can be formed by impurity implantation using the conductor 454 and the insulator 470 as masks.

[0103] The semiconductor substrate 400 may be made of, for example, a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, or gallium oxide. Note that the semiconductor substrate 400 may be made of an amorphous semiconductor or a crystalline semiconductor, and examples of the crystalline semiconductor include a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. The semiconductor substrate 400 may be made of, for example, a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, or gallium oxide. Note that the semiconductor substrate 400 may be made of an amorphous semiconductor or a crystalline semiconductor, and examples of the crystalline semiconductor include a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. The semiconductor substrate 400 may be made of, for example, a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, or gallium oxide. Note that the semiconductor substrate 400 may be made of an amorphous semiconductor or a crystalline semiconductor, and examples of the crystalline semiconductor include a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. The semiconductor substrate 400 may be made of, for example, a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, or gallium oxide. Note that the semiconductor substrate 400 may be made of an amorphous semiconductor or a crystalline semiconductor, and examples of the crystalline semiconductor include a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. The semiconductor substrate 400 may be made of, for example, a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, or gallium oxide. Note that the semiconductor substrate 400 may be made of an amorphous semiconductor or a crystalline semiconductor, and examples of the crystalline semiconductor include a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor.

[0104] The insulator 462 functions as a gate insulator of the transistor 491. The conductor 454 functions as a gate electrode of the transistor 491. The insulator 470 functions as a sidewall insulator (also referred to as a sidewall) of the conductor 454. The regions 476a and 476b function as a source region or a drain region of the transistor 491. The region 474 functions as a lightly doped drain (LDD) region of the transistor 491. The semiconductor substrate 400 may be made of, for example, a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, zinc oxide, or gallium oxide. Note that the semiconductor substrate 400 may be made of an amorphous semiconductor or a crystalline semiconductor, and examples of the crystalline semiconductor include a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor. The insulator 462 functions as a gate insulator of the transistor 491. The conductor 454 functions as a gate electrode of the transistor 491. The insulator 470 functions as a sidewall insulator (also referred to as a sidewall) of the conductor 454. The regions 476a and 476b function as a source region or a drain region of the transistor 491. The region 474 functions as a lightly doped drain (LDD) region of the transistor 491. The insulator 462 functions as a gate insulator of the transistor 491. The conductor 454 functions as a gate electrode of the transistor 491. The insulator 470 functions as a sidewall insulator (also referred to as a sidewall) of the conductor 454. The regions 476a and 476b function as a source region or a drain region of the transistor 491. The region 474 functions as a lightly doped drain (LDD) region of the transistor 491. The insulator 462 functions as a gate insulator of the transistor 491. The conductor 454 functions as a gate electrode of the transistor 491. The insulator 470 functions as a sidewall insulator (also referred to as a sidewall) of the conductor 454. The regions 476a and 476b function as a source region or a drain region of the transistor 491. The region 474 functions as a lightly doped drain (LDD) region of the transistor 491. The insulator 462 functions as a gate insulator of the transistor 491. The conductor 454 functions as a gate electrode of the transistor 491. The insulator 470 functions as a sidewall insulator (also referred to as a sidewall) of the conductor 454. The regions 476a and 476b function as a source region or a drain region of the transistor 491. The region 474 functions as a lightly doped drain (LDD) region of the transistor 491.

[0105] Note that the region 474 can be formed by impurity addition using the conductor 454 as a mask. Then, the insulator 470 is formed, and the regions 476a and 476b can be formed by impurity implantation using the conductor 454 and the insulator 470 as masks. Note that the region 474 can be formed by impurity addition using the conductor 454 as a mask. Then, the insulator 470 is formed, and the regions 476a and 476b can be formed by impurity implantation using the conductor 454 and the insulator 470 as masks. Note that the region 474 can be formed by impurity addition using the conductor 454 as a mask. Then, the insulator 470 is formed, and the regions 476a and 476b can be formed by impurity implantation using the conductor 454 and the insulator 470 as masks. When regions 474 and regions 476a, 476b are formed by adding the same type of impurity Region 474 becomes a region with a lower impurity concentration than regions 476a and 476b.

[0106] By having region 474, transistor 491 can suppress the short-channel effect. Therefore, it can be seen that it is a structure suitable for miniaturization.

[0107] Transistor 491 is separated from other transistors provided on semiconductor substrate 400 by insulator 4 60 or the like. In FIG. 4, an example in which insulator 460 is formed by a technique called STI (Shallow Trench Isolation) is shown, but it is not limited to this. For example, instead of insulator 460, an insulator formed by the LOCOS (Local Oxidation ation of Silicon) method may be used to separate the transistors.

[0108] Transistor 490 includes conductor 413, insulator 402 on conductor 413, semiconductor 406a on insulator 4 02, semiconductor 406b on semiconductor 406a, semiconductor 406c in contact with the side surface of semiconductor 406a, as well as the upper and side surfaces of semiconductor 406b, conductors 416a and 4 16b in contact with the upper and side surfaces of semiconductor 406a, the side surface of semiconductor 406a, the upper and side surfaces of semiconductor 406b, the upper and side surfaces of conductor 416a, and the upper and side surfaces of conductor 416b, and insulator 412 on semiconductor 406c, and conductor 404 on insulator 412. Here, conductor 413 is regarded as part of transistor 490, but it is not limited to this. For example, conductor 413 may be an independent component from transistor 490. ​​​​​

[0109] Conductor 413 functions as the gate electrode of transistor 490. Also, the insulator 402 functions as the gate insulator of transistor 490. Also, conductors 4 16a and 416b function as the source and drain electrodes of transistor 490. Also, insulator 412 functions as the gate insulator of transistor 490. Also, conductor 404 functions as the gate electrode of transistor 490. It has.

[0110] As shown in FIG. 4, conductors 416a and 416b are in contact with the side surface of semiconductor 406b. Also, conductor 404 has a structure that electrically surrounds the channel width direction of semiconductor 406b, and has a structure that surrounds semiconductor 406b not only on the upper surface but also on the side surface. Such a transistor structure is called a surrounded channel (s-channel) structure. channel) structure. Conductor 404 preferably has a structure that extends to below semiconductor 406b. .

[0111] By adopting the s-channel structure for the transistor structure, it becomes easier to control the channel formation region by the gate electric field with respect to the side surface of semiconductor 406b. When conductor 404 has a structure that extends to below semiconductor 406b, the controllability is further improved. As a result, the subthreshold swing value (also referred to as the S value) of transistor 490 can be made small, and the current in the off state of transistor 490 can be made small. By adopting such a structure, good electrical characteristics can be obtained even in a fine transistor. It can be done.

[0112] By adopting such a structure, good electrical characteristics can be obtained even in a fine transistor. This is achieved. With the miniaturization of transistors, a semiconductor device having such transistors can be made into a highly integrated , highly dense semiconductor device. Also, since the capacitance parasitic on the transistor decreases, good switching characteristics can be obtained. For example, the transistor 490 has a channel length preferably of 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, and the transistor 490 has a channel width preferably of 4 0 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less.

[0113] When the transistor 490 has an s-channel structure, a channel may be formed in the entire (bulk) semiconductor 406b. Therefore, the thicker the semiconductor 406b, the larger the channel formation region becomes. For example, a semiconductor 406b having a thickness in the region of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example , a semiconductor 406b having a thickness in the region of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less may be used. With such a structure, in an s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased.

[0114] Also, at least a part (or all) of the conductor 416a (and / or the conductor 416b) is in contact with at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the semiconductor 406b. The contacting semiconductor 406b In some cases, hydrogen may enter the oxygen-deficient sites to form donor levels, resulting in an n-channel type conductive region. The state where hydrogen enters the oxygen-deficient sites may be denoted as VH. O As a result, a good on-current can be obtained when a current flows through the n-channel type conductive region.

[0115] Also, as the oxide semiconductor, it is preferable to use CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) which will be described later. CAAC-OS is one of the oxide semiconductors having a plurality of crystal parts oriented along the c-axis. In particular, it is preferable to increase the CAAC ratio which will be described later. The CAAC ratio is the ratio of the region where the diffraction pattern of CAAC-OS in a certain range is observed. By increasing the CAAC ratio, for example, the number of defects can be reduced. Also, for example, carrier scattering can be reduced. Moreover, CAAC-OS with few impurities can be realized, and for example, extremely low off-current characteristics can be realized. For example, in the case of high-quality CAAC-OS, the CAAC ratio is 50% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more and 100% or less.

[0116] Also, it is effective to reduce the impurity concentration in the semiconductor 406b and make the oxide semiconductor intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor is less than 1×10 / cm 17 3 , preferably less than 1×10 15 / cm 3 , and more preferably less than 1×10 / cm 13 ​​​​​​​ / cm 3 It means being less than. In an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component become impurities. For example , hydrogen and nitrogen contribute to the formation of donor levels in the oxide semiconductor, increasing the carrier density . Also, silicon forms impurity levels in the oxide semiconductor . .

[0117] A transistor using a substantially intrinsic oxide semiconductor has a low carrier density in the channel formation region, so it rarely has electrical characteristics with a negative threshold voltage. Also , a transistor using the oxide semiconductor has few carrier traps in the oxide semiconductor , so the variation in electrical characteristics is small, and it becomes a highly reliable transistor. Also, a transistor using the oxide semiconductor can make the off-current extremely low . .

[0118] For example, when a transistor using an oxide semiconductor is in the off state, the drain current is 1×10 A or less at room temperature (about 25°C), preferably 1×10 -18 A or less, more preferably 1×10 -21 A or less, or 1×10 A or less at 85°C, preferably 1 -24 ×10 -15 A or less, more preferably 1×10 ×10 -18 A or less, and even more preferably 1×10 -21 A or less. Note , when the transistor is in the off state, in the case of an n-channel transistor, it means a state where the gate voltage is less than the threshold voltage. Specifically, if the gate voltage is 1 V or more, 2 V or more, or 3 V or more less than the threshold voltage, the transistor is in the off state . .

[0119] Also, when the transistor 490 is an accumulation type with electrons as majority carriers, the semiconductor 40 An electric field extending from the region in contact with the source electrode and drain electrode of 6b to the channel is shielded over a short distance Therefore, even if the transistor has a short channel, it is easy to control carriers by the gate electric field easily.

[0120] Also, by forming the transistor on the insulating surface, unlike the case where the semiconductor substrate is used as the channel formation region as it is, parasitic capacitance is not formed between the gate electrode and the semiconductor substrate Therefore, it becomes easier to control carriers by the gate electric field.

[0121] By adopting such a structure, good electrical characteristics can be obtained. Specifically, excellent subthreshold characteristics, an extremely small off-current, and good on-current can be obtained. Also, good switching characteristics can be obtained.

[0122] The above-described three-layer structure is an example. For example, a two-layer structure without the semiconductor 406a or the semiconductor 406c may be used. Or, a four-layer structure having any one of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406, and the semiconductor 406c above or below the semiconductor 406a, or above or below the semiconductor 406c may be used. Or, the semiconductor 406 may have an n-layer structure (n is an integer of 5 or more) including any one of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406, and the semiconductor 406c at two or more locations among above the semiconductor 406a, below the semiconductor 406a, above the semiconductor 406c, and below the semiconductor 406c.

[0123] Note that the insulator 402 is preferably an insulator containing excess oxygen.

[0124] ​​​​​​​​​For example, an insulator containing excess oxygen is an insulator having a function of releasing oxygen by heat treatment. For example, silicon oxide containing excess oxygen is silicon oxide that can release oxygen by heat treatment or the like. Therefore, the insulator 402 is an insulator through which oxygen can move in the film. That is, the insulator 402 may be an insulator having oxygen permeability. For example, the insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a. An insulator containing excess oxygen may have a function of reducing oxygen deficiency in the semiconductor 406b. Oxygen deficiency in the semiconductor 406b forms DOS and becomes a hole trap or the like. Also, when hydrogen enters the site of oxygen deficiency, electrons as carriers can be generated. Therefore, by reducing oxygen deficiency in the semiconductor 406b, stable electrical characteristics can be imparted to the transistor 490. That is, the insulator 402 may be an insulator having oxygen permeability. For example, the insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a. For example, the insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a.

[0125] An insulator containing excess oxygen may have a function of reducing oxygen deficiency in the semiconductor 406b. Oxygen deficiency in the semiconductor 406b forms DOS and becomes a hole trap or the like. Also, when hydrogen enters the site of oxygen deficiency, electrons as carriers can be generated. Therefore, by reducing oxygen deficiency in the semiconductor 406b, stable electrical characteristics can be imparted to the transistor 490. That is, the insulator 402 may be an insulator having oxygen permeability. For example, the insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a. For example, the insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a.

[0126] The insulator 442 shown in FIG. 4 or the like is provided between the transistor 491 and the transistor 490. As the insulator 442, for example, an oxide containing aluminum, such as aluminum oxide, is used. The insulator 442 is an insulator that blocks oxygen and hydrogen, but aluminum oxide having a density of less than 3.2 g / cm is preferable because it has a particularly high function of blocking hydrogen. Or, aluminum oxide having low crystallinity is preferable because it has a particularly high function of blocking hydrogen. The insulator 442 is an insulator that blocks oxygen and hydrogen, but aluminum oxide having a density of less than 3.2 g / cm is preferable because it has a particularly high function of blocking hydrogen. Or, aluminum oxide having low crystallinity is preferable because it has a particularly high function of blocking hydrogen. 3 is preferable because it has a particularly high function of blocking hydrogen. Or, aluminum oxide having low crystallinity is preferable because it has a particularly high function of blocking hydrogen. is preferable because it has a particularly high function of blocking hydrogen. Or, aluminum oxide having low crystallinity is preferable because it has a particularly high function of blocking hydrogen. is preferable because it has a particularly high function of blocking hydrogen. Or, aluminum oxide having low crystallinity is preferable because it has a particularly high function of blocking hydrogen.

[0127] For example, when the transistor 491 is a transistor using silicon, supplying hydrogen from the outside can reduce the dangling bonds of silicon, so the transistor For example, when the transistor 491 is a transistor using silicon, supplying hydrogen from the outside can reduce the dangling bonds of silicon, so the transistor The electrical characteristics of the transistor may be improved. The supply of hydrogen may be performed, for example, by heat treatment in an atmosphere containing hydrogen. Alternatively, for example, an insulator containing hydrogen may be disposed near the transistor 491, and the hydrogen may be diffused by performing heat treatment to supply the hydrogen to the transistor 4 91. Specifically, it is preferable that the insulator 464 on the transistor 491 is an insulator containing hydrogen. Note that the insulator 464 may have a single-layer structure or a stacked structure. For example, a stacked structure having silicon oxynitride or silicon oxide and silicon oxynitride or silicon nitride may be used for the insulator 464. The insulator containing hydrogen may release hydrogen (in terms of the number of hydrogen atoms) of, for example, 1×10 atoms / cm or more, 1×1

[0128] 0 atoms / cm 18 or more, or 1×10 3 atoms / cm 0 19 or more in the surface temperature range of 100°C or higher and 700°C or lower, or 10 3 0°C or higher and 500°C or lower as analyzed by TDS. 20 atoms / cm 3 Note that the hydrogen diffused from the insulator 464 may reach near the transistor 490 through the conductor 471 provided at the opening of the insulator 464, the conductor 480 on the insulator 464, the conductor 482 on the conductor 480, etc. However, since the insulator 442 has a function of blocking hydrogen, the amount of hydrogen reaching the transistor 490 is small. Hydrogen may become a carrier trap or a carrier generation source in the oxide semiconductor and deteriorate the electrical characteristics of the transistor 490.

[0129] Therefore, blocking hydrogen by the insulator 442 is semi- ​​​​​It has important significance for enhancing the performance and reliability of the conductor device.

[0130] On the other hand, for example, by supplying oxygen from the outside to the transistor 490, the oxygen deficiency of the oxide semiconductor can be reduced, so the electrical characteristics of the transistor may be improved. . The supply of oxygen may be performed, for example, by heat treatment in an atmosphere containing oxygen. Also or, for example, an insulator containing excess oxygen (oxygen) may be disposed near the transistor 490, and by performing heat treatment, the oxygen may be diffused and supplied to the transistor 490. Here, the insulator 402 of the transistor 490 uses an insulator containing excess oxygen.

[0131] The diffused oxygen may reach the transistor 491 through each layer, but since the insulator 442 has a function of blocking oxygen, the oxygen reaching the transistor 491 is small. When the transistor 491 is a transistor using silicon, oxygen mixing into the silicon may reduce the crystallinity of the silicon or be a factor that hinders the movement of carriers. Therefore, the fact that the insulator 442 blocks oxygen has important significance for enhancing the performance and reliability of the semiconductor device. It has important significance for enhancing the performance and reliability of the semiconductor device.

[0132] Also, in FIG. 4 and the like, it is preferable that the semiconductor device has an insulator 408 on the transistor 490. The insulator 408 has a function of blocking oxygen and hydrogen. The insulator 4 08 refers to, for example, the description of the insulator 442. Or, the insulator 408 is, for example has higher characteristics of blocking oxygen and hydrogen than the semiconductor 406a and / or the semiconductor 406c.

[0133] By having the insulator 408 in the semiconductor device, outward diffusion of oxygen from the transistor 490 can be suppressed. Therefore, oxygen can be effectively supplied to the transistor 490 with respect to the amount of excess oxygen (oxygen) contained in the insulator 402 or the like. Further, the insulator 408 blocks impurities containing hydrogen mixed from a layer provided above the insulator 408 or the outside of the semiconductor device, so that deterioration of the electrical characteristics of the transistor 490 due to the mixing of impurities can be suppressed. For convenience, the insulator 442 and / or the insulator 408 have been described separately from the transistor 490, but it may be a part of the transistor 490. In the cross-sectional view shown in FIG. 4, the semiconductor device 501 (cell) has conductors for a plurality of layers of wiring connected to the transistor 490 and the transistor 491. The first layer conductor is located on the insulator 464 provided on the transistor 491 and includes a high power supply wiring (conductor 480). The transistor 491 and the first layer conductor may be connected via a conductor 471 (also called a via) provided in an opening provided in the insulator 464. The second layer conductor is located on the insulator 465 provided on the first layer conductor and includes a low power supply wiring (conductor 482). The first layer conductor and the second layer conductor may be connected via a conductor 472 (also called a via) provided in an opening provided in the insulator 465. The third layer conductor is located on the insulator 466 provided on the second layer conductor and includes a wiring (conductor 484) for supplying a gate voltage. The second layer conductor and the third layer conductor are provided in the insulator 466. Connected via a conductor 473 (also called a via) provided in the opening. Note that, for convenience, the insulator 442 and / or the insulator 408 have been described separately from the transistor 490, but it may be a part of the transistor 490.

[0134] For convenience, the insulator 442 and / or the insulator 408 have been described separately from the transistor 490, but it may be a part of the transistor 490.

[0135] In the cross-sectional view shown in FIG. 4, the semiconductor device 501 (cell) has conductors for a plurality of layers of wiring connected to the transistor 490 and the transistor 491. The first layer conductor is located on the insulator 464 provided on the transistor 491 and includes a high power supply wiring (conductor 480). The transistor 491 and the first layer conductor may be connected via a conductor 471 (also called a via) provided in an opening provided in the insulator 464. The second layer conductor is located on the insulator 465 provided on the first layer conductor and includes a low power supply wiring (conductor 482). The first layer conductor and the second layer conductor may be connected via a conductor 472 (also called a via) provided in an opening provided in the insulator 465. The third layer conductor is located on the insulator 466 provided on the second layer conductor and includes a wiring (conductor 484) for supplying a gate voltage. The second layer conductor and the third layer conductor are provided in the insulator 466. Connected via a conductor 473 (also called a via) provided in the opening. It may be connected via a conductor 473 (also called a via) provided in the formed opening. An insulator 442 is located on an insulator 467 provided on the conductor of the third layer, and the insulator 442 has a conductor 413 and a transistor 490 located thereon. The conductor of the fourth layer is the transis tor 490 provided on an insulator 408 and located on an insulator 468, and includes conductors 424a , 424b. The conductor of the third layer and the conductor of the fourth layer are provided in openings provided in the insulators 408, 468 with a conductor 475 (also called a via) and may be connected via the drain electrode (conductor 416b) of the transistor 490. An insulator may be further provided on the conductor of the fourth layer. On the insulator, one or more layers of conductors and insulators may be provided. Those conductors can be used as wiring for connection between a plurality of semiconductor devices (cells), etc. In the configuration example shown in FIG. 4, three layers of conductors are provided between the transistor 490 and the transistor 491, but the structure of the semiconductor device (cell) according to one aspect of the present invention is not limited to this. One to ten layers of conductors may be provided between the transistor 490 and the trans istor 491. In the configuration example shown in FIG. 4, although three layers of conductors are provided between the transistor 490 and the transistor 491, the structure of the semiconductor device (cell) according to one aspect of the present invention is not limited to this. One to ten layers of conductors may be provided between the transistor 490 and the transistor 491. 490 and the transistor 491, but the structure of the semiconductor device (cell) according to one aspect of the present invention is not limited to this. One to ten layers of conductors may be provided between the transistor 490 and the trans istor 491. It should be noted that the structure of the transistor 491 is not limited to the structure shown in FIG. 4. For example, like the transistor 491 shown in FIG. 5, a structure having a convex portion (also called a protrusion, fin, etc.) on the semiconductor substrate 400

[0136] may be used. The structure of the transistor 491 shown in FIG. 5 can increase the effective channel width for the same occupied area compared to the structure of the transistor 491 shown in FIG. 4. Therefore, the current of the transistor 491 during conduction can be increased broadly. be called.) may be used. The structure of the transistor 491 shown in FIG. 5 can increase the effective channel width for the same occupied area compared to the structure of the transistor 491 shown in FIG. 4. Therefore, the current of the transistor 491 during conduction can be increased broadly. broadly. This can be achieved. Further, the conductor 454 surrounds the convex portion of the semiconductor substrate 400 in the channel width direction and has a structure that makes it easier to control the channel formation region by the gate electric field . As a result, the short-channel effect can be suppressed, and it can be seen that the structure is suitable for miniaturization .

[0137] Alternatively, for example, as in the transistor 491 shown in FIG. 6, a structure in which an insulator region 452 is provided in the semiconductor substrate 400 may be employed. By adopting the structure of the transistor 491 shown in FIG. 6 , the transistors operating individually can be more reliably separated, and the leakage current can be suppressed . Also, the parasitic capacitance formed between the substrate and the leakage current to the substrate can be suppressed . As a result, the leakage current of the transistor 491 can be reduced . Also, high-speed operation and low-power operation of the transistor 491 become possible .

[0138] The p-channel type Si transistor described above can obtain a good switching speed . For example, the switching speed of the transistor is less than 10 ns, preferably less than 1 ns , more preferably less than 0.1 ns. Also, the transistor including the above-described oxide semiconductor in the channel formation region can obtain a good switching speed . For example, the switching speed of the transistor is less than 10 ns, preferably less than 1 ns, more preferably 0 .1 ns or less. By using the above-described p-channel type Si transistor for the transistor 491 and using the transistor including the above-described oxide semiconductor in the channel formation region for the transistor 490 , the semiconductor device (cell) according to one aspect of the present invention can improve the operating speed . For example, an inverter which is a semiconductor device (cell) according to one aspect of the present invention ​ The delay time of the 2-input NAND circuit is less than 10 ns, preferably less than 1 ns, more preferably less than 0.1 ns.

[0139] In addition, since the off-current of the transistor using the oxide semiconductor is extremely small, it is possible to provide a semiconductor device with a small static leakage current (or DC leakage current). In particular, during the period when the input signal is low or at a low power supply voltage, even if the input signal is input to the gate electrode of the transistor using the oxide semiconductor, the transistor using the oxide semiconductor will be in the off state, and the leakage current through the transistor using the oxide semiconductor can be made extremely small. As a result, it is possible to provide a semiconductor device capable of reducing power consumption.

[0140] Also, it is preferable to use only p-channel Si transistors for the transistor 491 or the transistors formed simultaneously with the transistor 491. As a result, in the manufacturing process of the Si transistor, there is no need to manufacture an n-channel Si transistor, and the manufacturing cost can be kept low. In particular, in the case of a fine transistor, the manufacturing processes of the n-channel Si transistor and the p-channel Si transistor are optimized differently, so the effect of reducing the manufacturing cost by not manufacturing the n-channel Si transistor is significant. Also, when manufacturing only p-channel Si transistors, as the plane orientation of the silicon substrate surface, a plane orientation that is convenient for p-channel transistors, for example, a plane orientation capable of obtaining high mobility, can be selected. For example, the plane orientation of the silicon substrate can be the Si(110) plane.

[0141] (Embodiment 2) A semiconductor device which is one form of the present invention is not limited to the structure shown in FIGS. 4 to 6. In this embodiment, an example of a semiconductor device which is one form of the present invention will be described using FIGS. 7 to 9. The semiconductor device 502 (cell) shown in FIG. 7 corresponds to the semiconductor device 500 (cell) shown in FIG. 1 and is a cell in which the transistors 490 and 491 are arranged and wired.

[0142] FIG. 7 is a schematic diagram showing an example of the configuration of the semiconductor device 502 (cell). Note that in FIGS. 7 and 8, for ease of understanding, some parts such as insulators are omitted, and conductors formed in the same layer etc. are given the same hatching pattern.

[0143] FIG. 8 is a top view showing an example of the configuration of the semiconductor device 502 (cell). In FIG. 8(A), a top view of a region of the semiconductor device 502 including the transistor 491 and the conductor 480 is shown, and in FIG. 8(B), a top view of a region of the semiconductor device 502 including the transistor 490 and the conductor 482 is shown.

[0144] FIG. 9 is a cross-sectional view showing an example of the configuration of the semiconductor device 502 (cell). On the left side of FIG. 9, a cross-sectional view taken along the dashed line A1 - A2 in FIGS. 8(A) and 8(B) is shown, and on the right side of the same figure a cross-section taken along the dashed line B1 - B2 in FIGS. 8(A) and 8(B) is shown.

[0145] In FIG. 7, in the semiconductor device 502 (cell), the transistor 491, the high - power supply wiring (conductor 480), the low - power supply wiring (conductor 482), and the transistor 490 are stacked in this order. In other words, the high - power supply wiring (conductor 480) is arranged above the transistor 491 , a low power supply wiring (conductor 482) is disposed above and overlaps with a high power supply wiring (conductor 480), and a transistor 490 is disposed above the low power supply wiring (conductor 482).

[0146] Since the source electrode (or source region) of the transistor 491 is connected to the high power supply wiring (conductor 48 0), it is easier and more preferable to connect the source electrode (or source region) of the transistor 491 to the low power supply wiring (conductor 482) disposed above the high power supply wiring (conductor 480). Since the source electrode (or source region) of the transistor 490 is connected to the low power supply wiring (conductor 482), it is easier and more preferable to connect the source electrode (or source region) of the transistor 490 to the high power supply wiring (conductor 480) disposed below the low power supply wiring (conductor 482) than in the case where they are connected.

[0147] Also, in the semiconductor device 502 (cell), the wiring widths of the high power supply wiring (conductor 480) and the low power supply wiring (conductor 482) are preferably wider than the wiring width of the gate electrode (conductor 45 4) of the transistor 491, the gate electrode (conductor 404) of the transistor 490, or the wiring width of the signal wiring that transfers the input / output signal. Alternatively, the wiring widths of the high power supply wiring (conductor 480) and the low power supply wiring (conductor 482) are preferably wider than the width of the wiring (conductor) connected to the input terminal and the width of the wiring (conductor) connected to the output terminal. This is because the power supply wiring often conducts more current than the signal wiring, and it is preferable to make the wiring resistance lower than that of the signal wiring.

[0148] In FIGS. 2 to 6, the transistor 490 has a conductor 413 having the function of the gate electrode. Examples have been shown, but the structure of the semiconductor device according to one aspect of the present invention is not limited to this. FIG. 7 As shown in FIGS. 7 to 9, the transistor 490 may not have the conductor 413. Also the semiconductor device 502 (cell) may not have the conductor 484 that supplies voltage to the conductor 413. By having such a structure, the conductor layer for forming the conductor 484 becomes unnecessary, and the manufacturing cost can be suppressed.

[0149] In FIGS. 2 to 6, an example in which the gate electrode (conductor 404) of the transistor 490 and the gate electrode (conductor 454) of the transistor 491 are connected via the conductor 424b located above the conductor 404 has been shown, but the structure of the semiconductor device (cell) according to one aspect of the present invention is not limited to this. As shown in FIGS. 7 to 9, the conductor 404 and the conductor 454 may be connected via only the conductor located between the conductor 404 and the conductor 454 without passing through the conductor 424b. By having such a structure, the region for connecting the gate electrode of the transistor 490 and the gate electrode of the transistor 491 can be made smaller. As a result, the semiconductor device 502 (cell) can be made smaller.

[0150] (Embodiment 3) The semiconductor device which is one form of the present invention is not limited to the structure shown in FIGS. 4 to 6. In this embodiment, an example of the semiconductor device which is one form of the present invention will be described using FIGS. 10 to 12. The semiconductor device 503 (cell) shown in FIG. 10 corresponds to the semiconductor device 500 (cell) shown in FIG. 1 and is a cell in which the transistors 490 and 491 are arranged and wired.

[0151] ​​​​​​​​​​FIG. 10 is a schematic diagram showing an example of the configuration of the semiconductor device 503 (cell). Note that FIG. 10 and FIG. 11 are shown with some parts such as insulators omitted for easy understanding, and conductors formed in the same layer are given the same hatching pattern.

[0152] FIG. 11 is a top view showing an example of the configuration of the semiconductor device 503 (cell). In FIG. 11(A) a top view of the region of the semiconductor device 503 including the transistor 491 and the conductor 480 is shown, and in FIG. 11(B) a top view of the region of the semiconductor device 503 (cell) including the transistor 490 and the conductor 482 is shown.

[0153] FIG. 12 is a cross-sectional view showing an example of the configuration of the semiconductor device 503 (cell). On the left side of FIG. 12 a cross-sectional view cut along the dashed line A1 - A2 in FIGS. 11(A) and 11(B) is shown, and on the right side of the figure, a cross-section cut along the dashed line B1 - B2 in FIGS. 11(A) and 11(B) is shown.

[0154] In FIG. 10, the semiconductor device 503 (cell) has the transistor 491, the high - power supply wiring (conductor 480), the low - power supply wiring (conductor 482), and the transistor 490 stacked in this order. In other words, the high - power supply wiring (conductor 480) is disposed above the transistor 491, the low - power supply wiring (conductor 482) is disposed above and overlaps the high - power supply wiring (conductor 480), and the transistor 490 is disposed above the low - power supply wiring (conductor 482). The source electrode (or source region) of the transistor 491 is connected to the high - power supply wiring (conductor

[0155] 480), so the source electrode (or source region) of the transistor 491 is at a high electrical potential, and the source electrode (or source region) of the transistor 491 is connected to the high - power supply wiring (conductor A connection is easier and more preferable than a case where it is connected to a low-power supply wiring (conductor 482) arranged above the source wiring (conductor 480). Since the source electrode (or source region) of the transistor 490 is connected to the low-power supply wiring (conductor 482), a connection is easier and more preferable than a case where the source electrode (or source region) of the transistor 490 is connected to a high-power supply wiring (conductor 480) arranged below the low-power supply wiring (conductor 482). Also, in the semiconductor device 503 (cell), the wiring widths of the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482) are preferably wider than the wiring width of the gate electrode (conductor 454) of the transistor 491, the gate electrode (conductor 404) of the transistor 490, or a signal wiring that transfers an input / output signal. Alternatively, the wiring widths of the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482) are preferably wider than the width of a wiring (conductor) connected to an input terminal and the width of a wiring (conductor) connected to an output terminal. This is because the power supply wiring often conducts more current than the signal wiring, and it is preferable to make the wiring resistance lower than that of the signal wiring. In FIGS. 2 to 6, an example is shown in which the transistor 490 has a gate electrode (conductor 413), and a gate voltage can be applied independently to the gate electrode (conductor 413) and the gate electrode (conductor 404). However, the structure of the semiconductor device (cell) according to one aspect of the present invention is not limited to this. As shown in FIGS. 10 to 12, the same potential may be applied by electrically connecting the gate electrode (conductor 413) and the gate electrode (conductor 404). In this case, an effective

[0156]

[0157] ​​​​​​​​​​​​​​Since the channel width can be increased, the current at the time of conduction of the transistor 490 can be increased. Further, even in a region where the electric field by the gate electrode (conductor 404) hardly reaches, since the electric field by the gate electrode (conductor 413) reaches, the subthreshold swing value (also referred to as S value) of the transistor 490 can be decreased, and the current in the off state of the transistor 490 can be decreased.

[0158] (Embodiment 4) The cross-sectional structure of the semiconductor device which is one form of the present invention is not limited to the structure shown in FIGS. 4 to 6. In the present embodiment, an example of the cross-sectional structure of the semiconductor device which is one form of the present invention will be described using FIGS. 13 to 15. The semiconductor device 504 (cell) shown in FIG. 13 corresponds to the semiconductor device 500 (cell) shown in FIG. 1, and is a cell in which the transistors 490 and 491 are arranged and wired.

[0159] FIG. 13 is a schematic diagram showing an example of the configuration of the semiconductor device 504 (cell). In FIGS. 13 and 14, for easy understanding, a part such as an insulator is omitted, and conductors formed in the same layer etc. are given the same hatching pattern.

[0160] FIG. 14 is a top view showing an example of the configuration of the semiconductor device 504 (cell). In FIG. 14(A) is shown a top view of a region including the transistor 491 and the conductor 480 in the semiconductor device 504, and in FIG. 14(B) is shown a top view of a region including the transistor 490, the conductor 4 82, and the conductor 484 in the semiconductor device 504.

[0161] FIG. 15 is a cross-sectional view showing an example of the configuration of the semiconductor device 504 (cell). The left side of FIG. 15 shows a cross-sectional view taken along the chain-dotted line A1-A2 in FIGS. 14(A) and 14(B), on the right side of the figure, shows a cross-section taken along the chain-dotted line B1-B2 in FIGS. 14(A) and 14(B) .

[0162] In FIG. 13, the semiconductor device 504 (cell) includes a transistor 491, a high-power wiring (conductor 480), a conductor 484, a transistor 490, and a low-power wiring (conductor 482), which are stacked in this order. In other words, the high-power wiring (conductor 480) is disposed above the transistor 491, the conductor 484 is disposed above the high-power wiring (conductor 480) and overlaps it, the transistor 490 is disposed above the conductor 484, and the low-power wiring (conductor 482) is disposed above the transistor 490 .

[0163] Since the source electrode (or source region) of the transistor 491 is connected to the high-power wiring (conductor 480), it is easier and more preferable to connect the source electrode (or source region) of the transistor 491 to the low-power wiring (conductor 482) disposed above the high-power wiring (conductor 480) than in the case where they are not connected. Since the source electrode (or source region) of the transistor 490 is connected to the low-power wiring (conductor 482), it is easier and more preferable to connect the source electrode (or source region) of the transistor 490 to the high-power wiring (conductor 480) disposed below the low-power wiring (conductor 482) than in the case where they are not connected.

[0164] Also, in the semiconductor device 504 (cell), the wiring widths of the high-power wiring (conductor 480) and the low-power wiring (conductor 482) are each the gate electrode (conductor 45) of the transistor 491 ​​​​​4), the gate electrode of the transistor 490 (conductor 404), or the input / output signal transfer is preferably wider than the wiring width of the signal wiring. Alternatively, the wiring widths of the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482) are each preferably wider than the width of the wiring (conductor) connected to the input terminal and the width of the wiring (conductor) connected to the output terminal. Since the power supply wiring often conducts more current than the signal wiring, it is preferable to make the wiring resistance lower than that of the signal wiring for this reason.

[0165] In FIGS. 2 to 6, an example is shown in which the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) use adjacent conductors, but the structure of the semiconductor device (cell) according to one aspect of the present invention is not limited to this. As shown in FIGS. 13 to 15, a conductor 484 may be provided between the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) so as to overlap with the low-power supply wiring (conductor 482). Since the conductor 482 and the conductor 484 overlap each other and are arranged, there is a parasitic capacitance between the wirings. Also, a conductor 484 may be provided between the low-power supply wiring (conductor 482 ) and the high-power supply wiring (conductor 480) so as to overlap with the high-power supply wiring (conductor 480). Since the conductor 480 and the conductor 484 overlap each other and are arranged, there is a parasitic capacitance between the wirings. Due to these parasitic capacitances, it is possible to realize a circuit that is resistant to power supply noise and can reduce fluctuations in the power supply voltage . Note that the potential of the conductor 484 preferably does not change frequently. Alternatively, the conductor 48 4 preferably has a function as a power supply wiring. With such a configuration, an event in which the potential of the conductor 480 or the conductor 482 is changed due to the fluctuation of the conductor 484 can be prevented. . 4 preferably has a function as a power supply wiring. By adopting such a configuration, an event in which the potential of the conductor 480 or the conductor 482 is changed due to the fluctuation of the conductor 484 can be prevented. It can be reduced.

[0166] In the configuration example shown in FIGS. 13 to 15, the conductor 484 serves as a wiring for applying a gate voltage. It has the function of. The gate voltage can be utilized to control the threshold voltage of the transistor 490. The gate voltage may always be constant. In that case, the conductor 484 has the function of a power supply wiring. Also, the gate voltage may be switched in value between the period when the semiconductor device 504 (cell) is operating and the period when it is not operating. Such switching is not performed frequently, and the conductor 484 becomes a wiring whose potential does not change frequently.

[0167] Also, in FIGS. 2 to 6, the low - power supply wiring (conductor 482) and the conductors 424a, 424b were provided as conductors in separate layers, but the structure of the semiconductor device (cell) according to one aspect of the present invention is not limited to this. As shown in FIGS. 13 to 15, the conductor 482 and the conductors 424 a, 424b may be made of conductors in the same layer. As a result, the manufacturing cost may be reduced due to the reduction of the area and the number of conductor layers.

[0168] Note that the output signal OUT is output to the outside from the conductor 425a located above the conductor 416b, which is connected to the drain electrode (conductor 416b) of the transistor 490 and the drain region (region 476b) of the transistor 491. The conductor 425a is connected to the conductor 424a via the conductor 477. The input signal IN is input from the outside from the conductor 425b located above the conductor 404, which is connected to the gate electrode (conductor 404) of the transistor 490 and the gate electrode (conductor 454) of the transistor 491. Note that the conductor The body 425b is connected to the conductor 424b via the conductor 478. The conductors 477, 47 8 are provided in the opening of the insulator 469.

[0169] (Embodiment 5) An example of the configuration of a semiconductor device (cell) according to one aspect of the present invention will be described with reference to FIGS. 16 to 18, FIG. 20, and FIG. 32.

[0170] FIG. 32 is a schematic diagram of a semiconductor device in which the transistors 490a, 490b, 491a, and 491b are arranged and wired.

[0171] The semiconductor device 510 (cell) includes the transistors 491a, 491b, 490a, 490b, a conductor 480 that functions as a wiring, and a conductor 482 that functions as a wiring, and constitutes a 2-input NAND circuit having a CMOS configuration shown in FIG. 20. In the 2-input NAND circuit having a CMOS configuration, the output signal Z becomes low only when both of the two input signals A and B are high. The transistors 490a, 490b, 491a, and 491b are stacked. The conductor 482 has a function of supplying a low power supply voltage (VSS). The conductor 480 has a function of supplying a high power supply voltage (VDD). The conductor 482 and the conductor 480 are stacked. The output signal Z is output from the drain electrodes of the transistor 490b, the transistor 491a, and the transistor 4 91b. One of the input signals A is input to the gate electrodes of the transistor 490a and the transistor 491a. The other input signal B is input to the gate electrodes of the transistor 490b and the transistor 491b. 91b. 91b. gate electrode of the transistor 490a and the gate electrode of the transistor 491a. The other input signal B is, input to the gate electrode of the transistor 490b and the gate electrode of the transistor 491b. It is.

[0172] As an example, the transistors 491a and 491b can be p-channel transistors with a fast switching speed. For example, the switching speed of the transistor can be less than 10 ns, preferably less than 1 ns, and more preferably less than 0.1 ns. For example, a p-channel Si transistor can be used as the transistors 491a and 491b. The transistors 490a and 490b can be n-channel transistors with a fast switching speed as an example. For example, the switching speed of the transistor can be less than 10 ns, preferably less than 1 ns, and more preferably less than 0.1 ns. For example, a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region can be used as the transistors 490a and 490b. For example, the switching speed of the transistor can be less than 10 ns, preferably less than 1 ns, and more preferably less than 0.1 ns. For example, a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region can be used as the transistors 490a and 490b. The low-power supply wiring (conductor 482) is electrically connected to the source electrode of the transistor 490a. The low-power supply wiring (conductor 482) is electrically connected to the source electrode of the transistor 490b via the transistor 490a.

[0173] The high-power supply wiring (conductor 480) is electrically connected to the source electrodes of the transistors 491a and 491b. The gate electrode of the transistor 490a and the gate electrode of the transistor 491a are electrically connected. The gate electrode of the transistor 490b and the gate electrode of the transistor 491b are electrically connected. The drain electrode of the transistor 490b is electrically connected to the drain electrodes of the transistors 491a and 491b. The drain electrode of the transistor 490b is electrically connected to the drain electrodes of the transistors 491a and 491b. The drain electrode of the transistor 490b is electrically connected to the drain electrodes of the transistors 491a and 491b. The drain electrode of the transistor 490b is electrically connected to the drain electrodes of the transistors 491a and 491b. The drain electrode of the transistor 490b is electrically connected to the drain electrodes of the transistors 491a and 491b. The drain electrode of the transistor 490a and the source electrode of the transistor 490b are electrically connected. The drain electrode of the transistor 491a and the drain electrode of the transistor 491b are electrically connected. The low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) are generally arranged in parallel and overlap each other.

[0174] The low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) are generally arranged in parallel and overlap each other, so that the wiring has a large parasitic capacitance (also referred to as wiring capacitance). As a result, by using such wiring as a power supply wiring, voltage fluctuations can be reduced with respect to power supply noise, and a circuit that is resistant to power supply noise and can reduce fluctuations in the power supply voltage can be realized. Further, in a semiconductor device applying the semiconductor device 510 (cell), in order to reduce fluctuations in the power supply voltage, a capacitive element may be intentionally provided in the power supply wiring. Since the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) have a large wiring capacitance, such a capacitive element can be made smaller. As a result, the semiconductor device applying the semiconductor device 510 (cell) can be miniaturized. Further, since the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480) are arranged to overlap each other, the occupied area of the wiring can be reduced, and the area of the semiconductor device 510 (cell) can be reduced.

[0175] It is preferable to use conductors for adjacent wiring in the vertical direction for the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480). By using conductors for adjacent wiring in the vertical direction, the distance between the wirings becomes small, and the wiring has a large wiring capacitance. As a result, the power supply noise​ It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. Also it is possible to miniaturize the semiconductor device applying the semiconductor device 510 (cell).

[0176] Alternatively, it is preferable to use conductors in adjacent layers for the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480). Alternatively, it is preferable that there is no conductor between the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480). Alternatively, it is preferable to use conductors in adjacent layers for the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480). Alternatively, it is preferable that there is no conductor between the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480). Alternatively, it is preferable that there is no conductor between the low-power supply wiring (conductor 482) and the high-power supply wiring (conductor 480).

[0177] Transistor 490a and transistor 491a are arranged to overlap each other. Transistor 490b and transistor 491b are arranged to overlap each other. As a result it is possible to reduce the area of the semiconductor device 510 (cell). it is possible to reduce the area of the semiconductor device 510 (cell).

[0178] Transistor 490a and transistor 491a are arranged to overlap each other, and the direction in which current flows in transistor 490a and the direction in which current flows in transistor 491a are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490a are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491a are arranged are generally parallel. Transistor 490b and transistor 491b are arranged to overlap each other, and the direction in which current flows in transistor 490b and the direction in which current flows in transistor 491b are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490a are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491a are arranged are generally parallel. Transistor 490 b and transistor 491b are arranged to overlap each other, and the direction in which current flows in transistor 490b and the direction in which current flows in transistor 491b are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490a are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491a are arranged are generally parallel. Transistor 490 b and transistor 491b are arranged to overlap each other, and the direction in which current flows in transistor 490b and the direction in which current flows in transistor 491b are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490a are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491a are arranged are generally parallel. Transistor 490 b and transistor 491b are arranged to overlap each other, and the direction in which current flows in transistor 490b and the direction in which current flows in transistor 491b are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490a are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491a are arranged are generally parallel. Transistor 490 b and transistor 491b are arranged to overlap each other, and the direction in which current flows in transistor 490b and the direction in which current flows in transistor 491b are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490a are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491a are arranged are generally parallel. As a result, transistor 490a and transistor The transistor 491a can be connected in a small area including the connection part of the gate electrode. The transistor 490b and the transistor 491b can be connected in a narrow area, including the connection part of the gate electrode. As a result, the (cell) area of the semiconductor device 510 can be reduced.

[0179] In FIG. 32A, a semiconductor device 510 (cell) includes transistors 491a and 491b. b, the high power supply wiring (conductor 480), the low power supply wiring (conductor 482), and the transistor 49 In other words, transistors 491a and 491b are stacked in order. A high power supply wiring (conductor 480) is arranged above the The low power supply wiring (conductor 482) is arranged and overlaps the low power supply wiring (conductor 482). Transistors 490a and 490b are disposed in the same region.

[0180] With this configuration, the low power supply wiring (conductor 482) and the high power supply wiring (conductor 48 0) is located close to the top and bottom, and therefore has a large wiring capacitance. It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. It is possible to miniaturize a semiconductor device to which the semiconductor device 510 (cell) is applied.

[0181] In FIG. 32B, a semiconductor device 510 (cell) is provided on a semiconductor substrate. On a semiconductor substrate, transistors 491a and 491b, a high power supply wiring (conductor 480), The transistors 490a and 490b and the low power supply wiring (conductor 482) are arranged in this order. In this case, a high power supply wiring (conductor 480) is disposed above transistors 491a and 491b. Transistors 490a and 490b are disposed above the high power supply wiring (conductor 480). A low-power supply wiring (conductor 482) is disposed above the transistors 490a and 490b.

[0182] In the semiconductor device 510 (cell), the source electrodes or drain electrodes of the transistors 490a and 490b may be connected to other transistors within the semiconductor device 510 (cell) via a conductor above the transistors 490a and 490b. In that case, if the conductor used as a connection wiring between the conductor and a plurality of cells is formed in the same layer, the area required for the wiring may become large. This is because, in the connection between a plurality of cells, since the wiring positions are irregular and there are scattered unusable regions, the wiring that has to detour increases. Even in such a case, if the conductor and the conductor used as a power supply wiring are formed in the same layer, there may be almost no increase in area. This is because the power supply wiring is regularly arranged at the end of the cell region. As a result, the manufacturing cost may be reduced due to the reduction in area and the reduction in the number of conductor layers.

[0183] The semiconductor device 510 (cell) described above can reduce the cell area. For example, in the case of a 2-input NAND circuit, the height of the cell can be preferably set to WW + WT + 7 * Py or less, more preferably, WW + WT + 5 * Py or less. Also, the width of the cell can be preferably set to 5 * Px or less, more preferably, 4 * Px or less. Here, WW is the power line width, and WT is the maximum channel width among the channel widths of the plurality of transistors included in the semiconductor device 510 (cell).

[0184] Also, it is preferable that the heights of the plurality of cells are the same. By doing so, the height of the cell can be ​​​​​​​​​Set the row height and arrange multiple cells in multiple rows to perform efficient placement and wiring. This can be achieved.

[0185] To closely arrange the transistors and power supply wiring of the semiconductor device 510 (cell), when the source electrode of transistor 490a and / or the source electrode of transistor 490b is electrically connected to a conductor (482) functioning as a power supply wiring, the electrode and the conductor are preferably directly connected via a conductor (also called a via) provided in an opening provided in an insulator. Alternatively, the source electrode of transistor 490a and / or the source electrode of transistor 490b and a conductor (482 ) functioning as a power supply wiring are preferably connected via a via and a conductor sandwiched between the vias. The source electrode of transistor 491a and / or the source electrode of transistor 491b and a conductor (480) functioning as a power supply wiring are electrically connected. In this case, the electrode and the conductor are preferably directly connected via a conductor provided in an opening provided in an insulator. Alternatively, the source electrode of transistor 491a and / or the source electrode of transistor 4 91b and a conductor (480) functioning as a power supply wiring are preferably connected via a via and a conductor sandwiched between the vias.

[0186] To closely arrange the transistors and power supply wiring of the semiconductor device 510 (cell), the semiconductor device 510 (cell) has no transistors between transistor 490a and transistor 490b and a conductor 480 functioning as a power supply wiring, and between transistor 491a and transistor 4 91b and a conductor 482 functioning as a power supply wiring. ​ is preferable.

[0187] The transistor included in the semiconductor device 510 (cell) and the power supply wiring are arranged closely, and in order to arrange a plurality of cells efficiently, the power supply wiring is preferably arranged regularly at the end of the cell area. In particular, in the semiconductor device (cell) according to one aspect of the present invention, the power supply wiring may be arranged only at one end of the cell area. There may be a case where the cell area can be made smaller as compared with the case where the power supply wiring is arranged at both ends of the cell area. In particular, in the semiconductor device (cell) according to one aspect of the present invention, the power supply wiring may be arranged only at one end of the cell area. There may be a case where the cell area can be made smaller as compared with the case where the power supply wiring is arranged at both ends of the cell area. In particular, in the semiconductor device (cell) according to one aspect of the present invention, the power supply wiring may be arranged only at one end of the cell area. There may be a case where the cell area can be made smaller as compared with the case where the power supply wiring is arranged at both ends of the cell area. In particular, in the semiconductor device (cell) according to one aspect of the present invention, the power supply wiring may be arranged only at one end of the cell area. There may be a case where the cell area can be made smaller as compared with the case where the power supply wiring is arranged at both ends of the cell area.

[0188] FIG. 16 is a schematic diagram showing an example of the configuration of the semiconductor device 511 (cell). The semiconductor device 511 (cell) shown in FIG. 16 corresponds to the semiconductor device 510 (cell) shown in FIG. 32, and is a cell in which transistors 490a, 490b, 491a, and 491b are arranged and wired. In FIGS. 16 and 17, for ease of understanding, a part such as an insulator is omitted, and the same wiring pattern is attached to conductors formed in the same layer. FIG. 16 is a schematic diagram showing an example of the configuration of the semiconductor device 511 (cell). The semiconductor device 511 (cell) shown in FIG. 16 corresponds to the semiconductor device 510 (cell) shown in FIG. 32, and is a cell in which transistors 490a, 490b, 491a, and 491b are arranged and wired. In FIGS. 16 and 17, for ease of understanding, a part such as an insulator is omitted, and the same wiring pattern is attached to conductors formed in the same layer. FIG. 16 is a schematic diagram showing an example of the configuration of the semiconductor device 511 (cell). The semiconductor device 511 (cell) shown in FIG. 16 corresponds to the semiconductor device 510 (cell) shown in FIG. 32, and is a cell in which transistors 490a, 490b, 491a, and 491b are arranged and wired. In FIGS. 16 and 17, for ease of understanding, a part such as an insulator is omitted, and the same wiring pattern is attached to conductors formed in the same layer. FIG. 16 is a schematic diagram showing an example of the configuration of the semiconductor device 511 (cell). The semiconductor device 511 (cell) shown in FIG. 16 corresponds to the semiconductor device 510 (cell) shown in FIG. 32, and is a cell in which transistors 490a, 490b, 491a, and 491b are arranged and wired. In FIGS. 16 and 17, for ease of understanding, a part such as an insulator is omitted, and the same wiring pattern is attached to conductors formed in the same layer. FIG. 16 is a schematic diagram showing an example of the configuration of the semiconductor device 511 (cell). The semiconductor device 511 (cell) shown in FIG. 16 corresponds to the semiconductor device 510 (cell) shown in FIG. 32, and is a cell in which transistors 490a, 490b, 491a, and 491b are arranged and wired. In FIGS. 16 and 17, for ease of understanding, a part such as an insulator is omitted, and the same wiring pattern is attached to conductors formed in the same layer. FIG. 16 is a schematic diagram showing an example of the configuration of the semiconductor device 511 (cell). The semiconductor device 511 (cell) shown in FIG. 16 corresponds to the semiconductor device 510 (cell) shown in FIG. 32, and is a cell in which transistors 490a, 490b, 491a, and 491b are arranged and wired. In FIGS. 16 and 17, for ease of understanding, a part such as an insulator is omitted, and the same wiring pattern is attached to conductors formed in the same layer.

[0189] FIG. 17 is a top view showing an example of the configuration of the semiconductor device 511 (cell). In FIG. 17(A), a top view of a region including transistors 491a and 491b and conductor 480 in the semiconductor device 511 is shown, and in FIG. 17(B), a top view of a region including transistors 490a and 490b and conductor 482 in the semiconductor device 511 (cell) is shown. FIG. 17 is a top view showing an example of the configuration of the semiconductor device 511 (cell). In FIG. 17(A), a top view of a region including transistors 491a and 491b and conductor 480 in the semiconductor device 511 is shown, and in FIG. 17(B), a top view of a region including transistors 490a and 490b and conductor 482 in the semiconductor device 511 (cell) is shown. FIG. 17 is a top view showing an example of the configuration of the semiconductor device 511 (cell). In FIG. 17(A), a top view of a region including transistors 491a and 491b and conductor 480 in the semiconductor device 511 is shown, and in FIG. 17(B), a top view of a region including transistors 490a and 490b and conductor 482 in the semiconductor device 511 (cell) is shown. FIG. 17 is a top view showing an example of the configuration of the semiconductor device 511 (cell). In FIG. 17(A), a top view of a region including transistors 491a and 491b and conductor 480 in the semiconductor device 511 is shown, and in FIG. 17(B), a top view of a region including transistors 490a and 490b and conductor 482 in the semiconductor device 511 (cell) is shown.

[0190] FIG. 18 is a cross-sectional view showing an example of the configuration of the semiconductor device 511 (cell). On the left side of FIG. 18, a cross-sectional view taken along the dashed line A1 - A2 in FIGS. 17(A) and 17(B) is shown. FIG. 18 is a cross-sectional view showing an example of the configuration of the semiconductor device 511 (cell). On the left side of FIG. 18, a cross-sectional view taken along the dashed line A1 - A2 in FIGS. 17(A) and 17(B) is shown. On the right side of the figure, a cross-section taken along the dashed line B1 - B2 in FIGS. 17(A) and 17(B) is shown.

[0191] The semiconductor device 511 (cell) shown in FIG. 16 has a transistor 491a, a transistor 49 1b, a conductor 480, a transistor 490a, a transistor 490b, and a conductor 482. The transistors 490a and 490b are stacked on the transistors 491a and 491b. The conductors 482 and 480 are stacked. The transistor 491a has regions 476a, 476b, and a conductor 454a. The transistor 491b has regions 476b, 476c, and a conductor 454b. The transistor 4 90a has conductors 416a, 416b, and 404a. The transistor 490b has conductors 416b, 416c, and 404b.

[0192] The regions 476a and 476b function as one and the other of the source electrode (or source region) and the drain electrode (or drain region) of the transistor 491a. The conductor 454a functions as the gate electrode of the transistor 491a. The region 4 76b and 476c function as one and the other of the source electrode (or source region) and the drain electrode (or drain region) of the transistor 491b. The conductor 454b functions as the gate electrode of the transistor 491b. The conductors 416a and 416b function as one and the other of the source electrode (or source region) and the drain electrode (or drain region) of the transistor 490a. The conductor 404 a functions as the gate electrode of the transistor 490a. The conductors 416b and 416c function as one and the other of the source electrode (or source region) and the drain electrode (or drain region) of the transistor 490b. The conductor 404b functions as the gate electrode of the transistor 490b. 416c functions as one and the other of the source electrode (or source region) and the drain electrode (or drain region) of the transistor 490b. The conductor 404b functions as the gate electrode of the transistor 490b.

[0193] The high power supply wiring (conductor 480) and the low power supply wiring (conductor 482) are arranged overlapping each other substantially in parallel. The output signal is output to the outside from the conductor 424a located above the conductor 416c, which is connected to the drain electrode (conductor 416c ) of the transistor 490b, the drain region (region 476a) of the transistor 491a, and the drain region (region 476c) of the transistor 491b. One of the input signals is input from the outside to the conductor 424b located above the conductor 404a, which is connected to the gate electrode (conductor 404a) of the transistor 490a and the gate electrode (conductor 454a) of the transistor 491a. The other input signal is input from the outside to the conductor 424c located above the conductor 404b, which is connected to the gate electrode (conductor 404b) of the transistor 490b and the gate electrode (conductor 454b) of the transistor 491b. (conductor 454b) of the transistor 491b. Since the low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) are arranged overlapping each other substantially in parallel, the wiring has a large parasitic capacitance (also referred to as wiring capacitance). As a result,

[0194] by using the wiring as a power supply wiring, voltage fluctuations can be reduced with respect to power supply noise, and a circuit that is resistant to power supply noise and can reduce fluctuations in the power supply voltage can be realized. Further, in a semiconductor device to which the semiconductor device 511 (cell) is applied, ​​​​In order to reduce fluctuations in the power supply voltage, a capacitive element may be intentionally provided in the power supply wiring. Since the low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) have a large wiring capacitance, such a capacitive element can be made smaller. As a result, it becomes possible to miniaturize the semiconductor device incorporating the semiconductor device 511 (cell). Also, since the low power supply wiring (conductor 4 82) and the high power supply wiring (conductor 480) are arranged so as to overlap each other, the occupied area of the wiring can be reduced, and the area of the semiconductor device 511 (cell) can be reduced.

[0195] The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) can use conductors for adjacent wiring in the vertical direction. By using conductors for adjacent wiring in the vertical direction, the distance between the wirings is reduced, and the wiring has a large wiring capacitance. As a result, it is possible to realize a circuit that is resistant to power supply noise and can reduce fluctuations in the power supply voltage. Also, it becomes possible to miniaturize the semiconductor device incorporating the semiconductor device 511 (cell).

[0196] Alternatively, it is preferable to use conductors in adjacent layers for the low power supply wiring (conductor 482) and the high power supply wiring (conductor 480). Alternatively, it is preferable that there is no conductor between the low power supply wiring (conductor 482) and the high power supply wiring (conductor 480).

[0197] The transistor 490a and the transistor 491a are arranged so as to overlap each other. The transistor 490b and the transistor 491b are arranged so as to overlap each other. As a result, the area of the semiconductor device 510 (cell) can be reduced.

[0198] Transistors 490a and 491a are arranged to overlap each other, and the direction in which current flows in transistor 490a and the direction in which current flows in transistor 491a are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490a are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491a are arranged are generally parallel. Transistors 490b and 491b are arranged to overlap each other, and the direction in which current flows in transistor 490b and the direction in which current flows in transistor 491b are generally parallel or anti-parallel. Alternatively, the direction in which the source electrode, gate electrode, and drain electrode of transistor 490b are arranged and the direction in which the source electrode, gate electrode, and drain electrode of transistor 491b are arranged are generally parallel. By arranging them in such a manner, the drain electrode of transistor 490a and the drain electrode of transistor 491a can be arranged close to each other, and the gate electrode of transistor 490a and the gate electrode of transistor 491a can be arranged close to each other. Also, the drain electrode of transistor 490b and the drain electrode of transistor 491b can be arranged close to each other, and the gate electrode of transistor 490b and the gate electrode of transistor 491b can be arranged close to each other. As a result, when connecting the gate electrode of transistor 490a and the gate electrode of transistor 491a, connecting the drain electrode of transistor 490b and the drain electrode of transistor 491b, and connecting the gate electrode of transistor 490b and the gate electrode of transistor 491b, the area of the connection region can be reduced. The direction in which current flows in transistor 490a and the direction in which current flows in transistor 491a are generally parallel or anti-parallel. Alternatively, the source electrode of transistor 490a, the gate electrode, and the direction in which the drain electrodes are arranged and the source electrode of transistor 491a, the gate electrode, and the direction in which the drain electrodes are arranged are generally parallel. Transistor 490b and transistor 491b are arranged to overlap each other, and the current flowing in transistor 490b and the direction in which current flows in transistor 491b are generally parallel or anti-parallel. Alternatively, the source electrode of transistor 490b, the gate electrode, and the drain electrode arrangement direction and the source electrode of transistor 491b, the gate electrode, and the drain electrode arrangement direction are generally parallel. By arranging them in this way, the drain electrode of transistor 4 90a and the drain electrode of transistor 491a can be arranged close to each other, and the gate electrode of transistor 490a and the gate of transistor 491a electrodes can be arranged close to each other. Also, the drain of transistor 490b electrode and the drain electrode of transistor 491b can be arranged close to each other, and the gate electrode of transistor 490b and the gate electrode of transistor 491b can be arranged close to each other. As a result, the gate electrode of transistor 490a and the gate of transistor 4 91a electrodes are connected, the drain electrode of transistor 490b and the drain of transistor 4 91b electrodes are connected, and the gate electrode of transistor 490b and the gate electrode of transistor 491b are connected, the area of the connection region is reduced. It is possible to reduce the area of the semiconductor device 510 (cell).

[0199] In the transistor 490a, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 490a are arranged) and the extending direction of the low - power supply wiring (conductor 482) are substantially parallel. In this case, regardless of whether the source electrode of the transistor 490a is located on either side of the gate electrode, it can be connected to the low - power supply wiring (conductor 482) by a short wiring, which is preferable. ) In the transistor 491a, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491a are arranged) and the extending direction of the high - power supply wiring (conductor 480) are substantially parallel. In this case, regardless of whether the source electrode of the transistor 491a is located on either side of the gate electrode, it can be connected to the high - power supply wiring (conductor 480) by a short wiring, which is preferable. In the transistor 490b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 490b are arranged) and the extending direction of the low - power supply wiring (conductor 482) are substantially parallel. In this case, regardless of whether the source electrode of the transistor 490b is located on either side of the gate electrode, it can be connected to the low - power supply wiring (conductor 482) by a short wiring, which is preferable. In the transistor 491b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491b are arranged) and the extending direction of the high - power supply wiring (conductor 480) are substantially parallel. In this case, regardless of whether the source electrode of the transistor 491b is located on either side of the gate electrode, it can be connected to the high - power supply wiring (conductor 480) by a short wiring, which is preferable. In the transistor 491b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491b are arranged) and the extending direction of the high - power supply wiring (conductor 480) are substantially parallel. In this case, regardless of whether the source electrode of the transistor 491b is located on either side of the gate electrode, it can be connected to the high - power supply wiring (conductor 480) by a short wiring, which is preferable. ​​​​​​​

[0200] The direction in which current flows in the transistor 490a (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 490a are arranged) and the extending direction of the low-power supply wiring (conductor 482) may be substantially perpendicular. When the source electrode of the transistor 490a is connected to the low-power supply wiring (conductor 482), it is possible to arrange the source electrode so as to overlap with the low-power supply wiring, and since the area can be reduced, it is preferable. In the transistor 491a, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491a are arranged) and the extending direction of the high-power supply wiring (conductor 480) may be substantially perpendicular. When the source electrode of the transistor 491a is connected to the high-power supply wiring (conductor 480), it is possible to arrange the source electrode so as to overlap with the high-power supply wiring, and since the area can be reduced, it is preferable. In the transistor 490b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 490b are arranged) and the extending direction of the low-power supply wiring (conductor 482) may be substantially perpendicular. When the source electrode of the transistor 490b is connected to the low-power supply wiring (conductor 482), it is possible to arrange the source electrode so as to overlap with the low-power supply wiring, and since the area can be reduced, it is preferable. In the transistor 491b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491b are arranged) and the extending direction of the high-power supply wiring (conductor 480) may be substantially perpendicular. When the source electrode of the transistor 491b is connected to the high-power supply wiring (conductor 480), it is possible to arrange the source electrode so as to overlap with the high-power supply wiring, and since the area can be reduced, it is preferable. When the source electrode of the transistor 491b is connected to the high-power supply wiring (conductor 480), it is possible to arrange the source electrode so as to overlap with the high-power supply wiring, and since the area can be reduced, it is preferable. In the transistor 490b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 490b are arranged) and the extending direction of the low-power supply wiring (conductor 482) may be substantially perpendicular. When the source electrode of the transistor 490b is connected to the low-power supply wiring (conductor 482), it is possible to arrange the source electrode so as to overlap with the low-power supply wiring, and since the area can be reduced, it is preferable. In the transistor 491b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491b are arranged) and the extending direction of the high-power supply wiring (conductor 480) may be substantially perpendicular. When the source electrode of the transistor 490b is connected to the low-power supply wiring (conductor 482), it is possible to arrange the source electrode so as to overlap with the low-power supply wiring, and since the area can be reduced, it is preferable. In the transistor 491b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491b are arranged) and the extending direction of the high-power supply wiring (conductor 480) may be substantially perpendicular. When the source electrode of the transistor 491b is connected to the high-power supply wiring (conductor 480), it is possible to arrange the source electrode so as to overlap with the high-power supply wiring, and since the area can be reduced, it is preferable. In the transistor 491b, the direction in which current flows (or the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491b are arranged) and the extending direction of the high-power supply wiring (conductor 480) may be substantially perpendicular. When the source electrode of the transistor 491b is connected to the high-power supply wiring (conductor 480), it is possible to arrange the source electrode so as to overlap with the high-power supply wiring, and since the area can be reduced, it is preferable. When the source electrode of the transistor 491b is connected to the high-power supply wiring (conductor 480), it is possible to arrange the source electrode so as to overlap with the high-power supply wiring, and since the area can be reduced, it is preferable. When the source electrode of the transistor 491b is connected to the high-power supply wiring (conductor 480), it is possible to arrange the source electrode so as to overlap with the high-power supply wiring, and since the area can be reduced, it is preferable. It is preferable because it is capable and the area can be reduced.

[0201] The direction in which current flows in transistor 490a (or the direction in which the source electrode, gate electrode, and drain electrode of transistor 490a are arranged) and the direction in which current flows in transistor 490b (or the direction in which the source electrode, gate electrode, and drain electrode of transistor 490b are arranged) may be substantially parallel or antiparallel. By aligning the directions of the transistors, when arranging and wiring the transistors to form a circuit, a regular arrangement can be achieved. By performing a regular arrangement, for example, the height direction of the semiconductor device (cell) can be aligned, and a plurality of cells can be arranged efficiently. Also, by aligning the directions of the transistors, the variation in the electrical characteristics of the transistors may be reduced.

[0202] When the input / output terminals are connected to adjacent cells or nearby cells, the output terminal from which the output signal OUT is output may be directly connected to the drain electrode (conductor 416c) of transistor 490b, the drain electrode or drain region (region 476a) of transistor 491a, or the drain electrode or drain region (region 476c) of transistor 491b without passing through conductor 424a, to the input / output terminals of adjacent cells or nearby cells. One of the input terminals to which the input signal IN is input may be directly connected to the gate electrode (conductor 404a) of transistor 490a or the gate electrode (conductor 454a) of transistor 491a without passing through conductor 424b, to the input / output terminals of adjacent cells or nearby cells. The other of the input terminals to which the input signal IN is input may be directly connected to the gate electrode (conductor 404a) of transistor 490a or the gate electrode (conductor 454a) of transistor 491a without passing through conductor 424c, to the input / output terminals of adjacent cells or nearby cells. ​​​​​​​​​​​​​​​​The gate electrode of the STA 490b (conductor 404b) and the gate electrode of the transistor 491b (conductor 454b) can be directly connected to the input / output terminals of adjacent cells or neighboring cells as well.

[0203] In FIG. 16, the semiconductor device 511 (cell) includes transistors 491a and 491b, a high power supply wiring (conductor 480), a low power supply wiring (conductor 482), and transistors 490a and 490b are stacked in this order. In other words, the high power supply wiring (conductor 480) is arranged above the transistors 491a and 491b, and the low power supply wiring (conductor 482) is arranged and overlaps above the high power supply wiring (conductor 480), and the transistors 490a and 490b are arranged above the low power supply wiring (conductor 482).

[0204] The source electrodes (or source regions) of the transistors 491a and 491b are connected to the high power supply wiring (conductor 480). Therefore, it is easier and more preferable to connect the source electrodes (or source regions) of the transistors 491a and 491b to the low power supply wiring (conductor 482) arranged above the high power supply wiring (conductor 480) than when they are connected to the low power supply wiring (conductor 482). The source electrode (or source region) of the transistor 490a is connected to the low power supply wiring (conductor 482). Therefore, it is easier and more preferable to connect the source electrode (or source region) of the transistor 490a to the low power supply wiring (conductor 482) than when it is connected to the high power supply wiring (conductor 480) arranged below the low power supply wiring (conductor 482). preferable.

[0205] Also, in the semiconductor device 511 (cell), the wiring widths of the high power supply wiring (conductor 480) and the low power supply wiring (conductor 482) are each the gate electrode of the transistor 491 (conductor 45 4), the gate electrode of the transistor 490 (conductor 404), or the input / output signal transfer is preferably wider than the wiring width of the signal wiring. Alternatively, the high-power supply wiring (conductor 480) and the low-power supply wiring (conductor 482) each preferably have a wiring width wider than the width of the wiring (conductor) connected to the input terminal and the width of the wiring (conductor) connected to the output terminal. This is because the power supply wiring often conducts more current than the signal wiring, and it is preferable to make the wiring resistance lower than that of the signal wiring .

[0206] Note that the semiconductor device shown in FIG. 18 has the same cross-sectional structure as the semiconductor device shown in FIG. 5. Therefore, for the semiconductor device shown in FIG. 18, the description of the transistor shown in FIG. 5 can be referred to as appropriate .

[0207] Note that this embodiment can be appropriately combined with other embodiments shown in this specification .

[0208] (Embodiment 6) The transistor 490 can have various structures. In this embodiment, for ease of understanding , only the transistor 490 and the region in its vicinity are extracted and shown in FIGS. 33 and 34 .

[0209] FIG. 33(A) is an example of a top view of the transistor 490. An example of a cross-sectional view cut along the dashed-dotted line E1 - E2 and the dashed-dotted line E3 - E4 in FIG. 33(A) is shown in FIG. 33(B). Note that in FIG. 33(A), for ease of understanding, some parts such as insulators are omitted and shown

[0210] In FIG. 4 etc., conductors 416a and conductors that function as the source electrode and the drain electrode An example where the body 416b is in contact with the upper surface and side surface of the semiconductor 406b, the upper surface of the insulator 402, etc. is shown. However, the structure of the transistor according to one aspect of the present invention is not limited to this. For example, in FIG. 3 As shown in FIG. 3, a structure in which the conductor 416a and the conductor 416b are in contact with only the upper surface of the semiconductor 406b may be used.

[0211] In the transistor shown in FIG. 33, the conductor 416a and the conductor 416b do not contact the side surface of the semiconductor 406 b. Therefore, an electric field applied from the conductor 404 having a function as a gate electrode toward the side surface of the semiconductor 406b is less likely to be shielded by the conductor 416a and the conductor 416b. Also, the conductor 416a and the conductor 416b do not contact the upper surface of the insulator 4 02. Therefore, excess oxygen (oxygen) released from the insulator 402 is not consumed to oxidize 41 6a and the conductor 416b. Therefore, the excess oxygen (oxygen) released from the insulator 402 can be efficiently utilized to reduce the oxygen deficiency of the semiconductor 406b . That is, the transistor having the structure shown in FIG. 33 has excellent electrical characteristics such as high on-current, high field-effect mobility, low subthreshold swing value, and high reliability . That is, the transistor having the structure shown in FIG. 33 is a transistor with excellent electrical characteristics such as high on-current, high field-effect mobility, low subthreshold swing value, and high reliability.

[0212] FIG. 34(A) is an example of a top view of the transistor 490. An example of a cross-sectional view cut along the dashed-dotted line G1-G2 and the dashed-dotted line G3-G4 in FIG. 34(A) is shown in FIG. 34(B). Also, in FIG. 34(A), for ease of understanding, a part such as an insulator is shown with omission.

[0213] The transistor 490 shown in FIGS. 34(A) and 34(B) is a conductor on the insulator 442 The body 413, the insulator 402 having convex portions on the insulator 442 and on the conductor 413, and the insulation The semiconductor 406a on the convex portion of the insulator 402, the semiconductor 406b on the semiconductor 406a, and the semiconductor 4 The semiconductor 406c on 06b, the semiconductors 406a, 406b, and 406c Contacting and spaced-apart conductors 416a and 416b, and the semiconductor 406c The insulator 412 on the semiconductor 406c, on the conductor 416a, and on the conductor 416b, and the conductor on the insulator 412 The body 404, on the conductor 416a, on the conductor 416b, on the insulator 412, and on the conductor 404 The insulator 408, and the insulator 468 on the insulator 408.

[0214] Note that the insulator 412 contacts at least the side surface of the semiconductor 406b in the G3-G4 cross-section. Also, the conductor 404 faces at least the upper surface and the side surface of the semiconductor 406b through the insulator 412 in the G3-G4 cross-section. Also, the conductor 413 faces the lower surface of the semiconductor 406b through the insulator 402. Also, the insulator 402 may not have a convex portion. Also, the semiconductor 406c may not be provided. Also, the insulator 408 may not be provided.

[0215] The transistor 490 shown in FIG. 34 is only different in some structures from the transistor 490 shown in FIG. 4. Specifically, the structures of the semiconductors 406a, 4 The structures of the conductors 406b and 406c of the transistor 490 shown in FIG. 4 are only different from the structures of the semiconductors 406a, 406b, and 406c of the transistor 490 shown in FIG. 34. Therefore, for the transistor shown in FIG. 34, the description of the transistor shown in FIG. 4 can be appropriately referred to as needed. ​

[0216] In addition, in this embodiment, as an example, the transistor 490 can use an oxide semiconductor in a channel or the like, but one aspect of the embodiment of the present invention is not limited to this. For example, the transistor 490 may be formed of a material having Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc. in a channel, in the vicinity thereof, a source region, a drain region, etc., depending on circumstances or according to the situation.

[0217] For example, in this specification and the like, transistors such as the transistor 490 and the transistor 491 can be formed using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, there are a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI (Silicon on insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. As an example of the glass substrate, there are barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate, the laminated film, the base film, etc. include the following. For example, plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Or, as an example, there are synthetic resins such as acrylic. Or ​​​​​​​​​​​​​​​, As an example, there are polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride, etc. Or, as an example, there are polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, or papers, etc. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate, etc., there are fewer fluctuations in characteristics, size, or shape, etc., and a transistor with high current capacity and small size can be manufactured. When a circuit is configured with such a transistor, power consumption reduction of the circuit or high integration of the circuit can be achieved.

[0218] Also, a flexible substrate may be used as the substrate, and a transistor may be formed directly on the flexible substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer is separated from the substrate after partially or completely completing a semiconductor device thereon, and can be used for transfer to another substrate. At that time, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. Incidentally, for the above-mentioned release layer, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, or a configuration in which an organic resin film such as polyimide is formed on the substrate can be used.

[0219] That is, a transistor may be formed using a certain substrate, and then the transistor may be transposed to another substrate and the transistor may be arranged on another substrate. As an example of the substrate to which the transistor is transposed, in addition to the substrate on which the above-mentioned transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp), synthetic fiber (nylon, polyurethane, polyester) or or include regenerated fibers (such as acetate, cupra, rayon, regenerated polyester), there are leather substrates, rubber substrates, etc. By using these substrates, transistors with good characteristics can be formed, transistors with low power consumption can be formed, devices that are not easily damaged can be manufactured, heat resistance can be imparted, weight reduction, or thinning can be achieved.

[0220] (Embodiment 7) Hereinafter, the structure of an oxide semiconductor applicable to semiconductor 406a, semiconductor 406b, semiconductor 406c, etc. will be described. In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

[0221] Oxide semiconductors are roughly classified into non-single crystal oxide semiconductors and single crystal oxide semiconductors. Non-single crystal oxide semiconductors refer to CAAC-OS (C Axis Aligned Crystal line Oxide Semiconductor), polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, etc.

[0222] First, CAAC-OS will be described.

[0223] CAAC-OS is one of the oxide semiconductors having a plurality of crystal parts oriented along the c-axis.

[0224] When CAAC-OS is observed by a transmission electron microscope (TEM: Transmission Electron Microscope), clear boundaries between crystal parts, that is, grain boundaries (also referred to as grain boundaries) cannot be confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries.

[0225] The CAAC-OS is observed by TEM from a direction approximately parallel to the sample surface (cross-sectional TEM observation ). As a result, in the crystal part, it can be confirmed that the metal atoms are arranged in layers. The metal atoms in each layer have a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS and are arranged parallel to the formed surface or the upper surface of the CAAC-OS.

[0226] On the other hand, when the CAAC-OS is observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM observation), it can be confirmed that in the crystal part, the metal atoms are arranged in a triangular or hexagonal shape. However, between different crystal parts, the arrangement of the metal atoms is not necessarily regularly arranged.

[0227] Fig. 35(a) is a cross-sectional TEM image of the CAAC-OS. Fig. 35(b) is a cross-sectional TEM image obtained by further magnifying Fig. 3 5(a), and the atomic arrangement is emphasized for easy understanding displayed.

[0228] Fig. 35(c) is a local Fourier transform image of the region (diameter approximately 4 nm) enclosed by a circle between A - O - A' in Fig. 35(a). From Fig. 35(c), c-axis orientation can be confirmed in each region. Also, since the direction of the c-axis is different between the A - O interval and the O - A' interval, it is suggested that they are different grains . Also, it can be seen that between A - O, the angle of the c-axis changes continuously little by little, such as 14.3°, 16. 6°, 26.4°. Similarly, between O - A ', it can be seen that the angle of the c-axis changes continuously little by little, such as -18.3°, -17.6°, -15.9° .

[0229] In addition, when electron diffraction is performed on the CAAC-OS, spots (bright spots) indicating orientation are observed​ is measured. For example, when electron diffraction (also referred to as nano-beam electron diffraction) using an electron beam of, for example, 1 nm or more and 30 nm or less is performed on the upper surface of CAAC-OS, spots are observed (see Fig. 36(A)). (See Fig. 36(A).)

[0230] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystalline part of CAAC-OS has orientation. It can be seen that the crystalline part of CAAC-OS has orientation.

[0231] Most of the crystalline parts contained in CAAC-OS are sized to fit within a cube with a side length of less than 100 nm. Therefore, the crystalline parts contained in CAAC-OS also include cases where they are sized to fit within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. However, when a plurality of crystalline parts contained in CAAC-OS are connected, a single large crystal region may be formed. For example, in a planar TEM image, a crystal region of 2500 nm or more, 5 μm or more or 1000 μm 2 or more may be observed. 2 or more or 1000 μm 2 or more may be observed.

[0232] When structural analysis is performed on CAAC-OS using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the out-of-plane method analysis of CAAC-OS having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. When structural analysis is performed on CAAC-OS using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the out-of-plane method analysis of CAAC-OS having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. In the out-of-plane method analysis of CAAC-OS having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. In the out-of-plane method analysis of CAAC-OS having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0233] On the other hand, for CAAC-OS, when X-rays are incident from a direction substantially perpendicular to the c-axis, in-pl In the analysis by the XRD method, a peak may appear near 2θ = 56°. This peak is attributed to the (110) plane of the InGaZnO₄ crystal. For a single crystal oxide semiconductor of InGaZnO₄, if 2θ is fixed near 56° and the sample is rotated while performing analysis (φ scan) with the normal vector of the sample surface as the axis (φ axis), six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of CAAC-OS, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°.

[0234] From the above, in CAAC-OS, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the layered arranged metal atoms confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

[0235] Note that the crystal part is formed when CAAC-OS is deposited or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of CAAC-OS. Therefore, for example, when the shape of CAAC-OS is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of CAAC-OS.

[0236] Also, in CAAC-OS, the distribution of the c-axis oriented crystal parts does not have to be uniform. For example, when the crystal part of CAAC-OS is formed by crystal growth from near the upper surface of CAAC-OS, the region near the upper surface has a higher proportion of c-axis oriented crystal parts than the region near the formed surface. The combination may be high. Also, in the CAAC-OS to which impurities are added, the region where the impurities are added is altered, and regions with different ratios of partially c-axis oriented crystal parts may be formed. There is also a case where the region where impurities are added is altered, and regions with different ratios of partially c-axis oriented crystal parts are formed. There is also a case where the region where impurities are added is altered, and regions with different ratios of partially c-axis oriented crystal parts are formed.

[0237] In addition, in the analysis of CAAC-OS having InGaZnO4 crystals by the out-of-plane method, in addition to the peak near 2θ = 31°, a peak may also appear near 2θ = 36°. The peak near 2θ = 36° indicates that a part of the CAAC-OS contains crystals without c-axis orientation. It is preferable that the CAAC-OS shows a peak near 2θ = 31° and does not show a peak near 2θ = 36°. The peak near 2θ = 31° indicates that a part of the CAAC-OS contains crystals without c-axis orientation. It is preferable that the CAAC-OS shows a peak near 2θ = 31° and does not show a peak near 2θ = 36°. The peak near 2θ = 31° indicates that a part of the CAAC-OS contains crystals without c-axis orientation. It is preferable that the CAAC-OS shows a peak near 2θ = 31° and does not show a peak near 2θ = 36°.

[0238] CAAC-OS is an oxide semiconductor with a low impurity concentration. Impurities are elements other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, CAAC-OS is an oxide semiconductor with a low impurity concentration. Impurities are elements other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, CAAC-OS is an oxide semiconductor with a low impurity concentration. Impurities are elements other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, CAAC-OS is an oxide semiconductor with a low impurity concentration. Impurities are elements other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, CAAC-OS is an oxide semiconductor with a low impurity concentration. Impurities are elements other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, CAAC-OS is an oxide semiconductor with a low impurity concentration. Impurities are elements other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, CAAC-OS is an oxide semiconductor with a low impurity concentration. Impurities are elements other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, CAAC-OS is an oxide semiconductor with a low impurity concentration. Impurities are elements other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor,

[0239] CAAC-OS is an oxide semiconductor with a low density of defect levels. For example, oxygen vacancies in an oxide semiconductor may become carrier traps or may become carrier generation sources by capturing hydrogen. CAAC-OS is an oxide semiconductor with a low density of defect levels. For example, oxygen vacancies in an oxide semiconductor may become carrier traps or may become carrier generation sources by capturing hydrogen. CAAC-OS is an oxide semiconductor with a low density of defect levels. For example, oxygen vacancies in an oxide semiconductor may become carrier traps or may become carrier generation sources by capturing hydrogen.

[0240] A semiconductor oxide having a low impurity concentration and a low density of defect levels (low oxygen deficiency) is called highly pure intrinsic or substantially highly pure intrinsic. Since a semiconductor oxide that is highly pure intrinsic or substantially highly pure intrinsic has few carrier generation sources, the carrier density can be lowered. Therefore, a transistor using the semiconductor oxide has electrical characteristics (also called normal ions) in which the threshold voltage rarely becomes negative. In addition, a semiconductor oxide that is highly pure intrinsic or substantially highly pure intrinsic has few carrier traps. Therefore, a transistor using the semiconductor oxide has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the semiconductor oxide takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using a semiconductor oxide having a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. .

[0241] In addition, a transistor using CAAC-OS has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0242] Next, a microcrystalline semiconductor oxide will be described.

[0243] In an observation image obtained by TEM, a crystal part may not be clearly confirmed in a microcrystalline semiconductor oxide. The crystal part contained in the microcrystalline semiconductor oxide often has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals having a size of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less are called nanocrystals (nc: nanocrystal). A semiconductor oxide having nanocrystals is referred to as nc-OS (nanocrys tal). is called a "talline Oxide Semiconductor". Also, nc-OS may not clearly show grain boundaries in an observation image by TEM, for example.

[0244] nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS has no regularity in crystal orientation between different crystal parts. Therefore, no orientation is observed in the whole layer. Accordingly nc-OS may not be distinguishable from an amorphous oxide semiconductor depending on the analysis method. For example, when performing structural analysis on nc-OS using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron diffraction (also referred to as limited-field electron diffraction) on nc-OS using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on nc-OS using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. Also, when performing nano-beam electron diffraction on nc-OS, a region with high brightness may be observed in a circular (ring-shaped) manner. Also, when performing nano-beam electron diffraction on nc-OS, a plurality of spots may be observed within the ring-shaped region (see Fig. 36(B)). (see Fig. 36(B)). When performing nano-beam electron diffraction on nc-OS using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. Also, when performing nano-beam electron diffraction on nc-OS, a region with high brightness may be observed in a circular (ring-shaped) manner. Also, when performing nano-beam electron diffraction on nc-OS, a plurality of spots may be observed within the ring-shaped region (see Fig. 36(B)). (see Fig. 36(B)). (see Fig. 36(B)).

[0245] nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. Therefore , the density of defect levels in nc-OS is lower than that in an amorphous oxide semiconductor. However, nc-O In S, no regularity is observed in the crystal orientation among different crystal parts. Therefore, nc-OS is CA The density of defect levels becomes higher compared with AC-OS.

[0246] Therefore, the carrier density of nc-OS may be higher than that of CAAC-OS. . An oxide semiconductor with a high carrier density may have a high electron mobility. Therefore, nc -OS transistors may have a high field-effect mobility. Also, since nc- OS has a higher density of defect levels than CAAC-OS, there may be more carrier traps. Therefore, transistors using nc-OS have larger fluctuations in electrical characteristics and lower reliability compared to transistors using CAAC-OS. However Since nc-OS can be formed even when it contains relatively many impurities, it is easier to form than CA AC-OS and may be suitably used depending on the application. Therefore, a semiconductor device having a transistor using nc-OS may be manufactured with high productivity.

[0247] Note that the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a microcrystalline oxide semiconductor, and CAAC -OS.

[0248] As described above, CAAC-OS has an advantage that the carrier mobility is less likely to decrease because the scattering of carriers caused by crystal grain boundaries is small compared with polycrystals and microcrystals. Also, C AAC-OS is an oxide semiconductor with a low density of defect levels and few carrier traps. Therefore, transistors using CAAC-OS are excellent transistors with small fluctuations in electrical characteristics and high reliability. ​​​​

[0249] When an oxide semiconductor has a plurality of structures, structural analysis may be possible by using nano-beam electron diffraction. There may be cases where it is possible.

[0250] Fig. 36(C) shows a transmission electron diffraction measurement apparatus having an electron gun chamber 10, an optical system 12 below the electron gun chamber 10, a sample chamber 14 below the optical system 12, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, a camera 18 installed in the observation chamber 20, and a film chamber 22 below the observation chamber 20. The camera 18 is installed facing inside the observation chamber 20. Note that the film chamber 22 may not be provided. Note that the film chamber 22 may not be provided. It does not have to have a film chamber 22.

[0251] Further, Fig. 36(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Fig. 36(C). Inside the transmission electron diffraction measurement apparatus, electrons 24 emitted from an electron gun installed in the electron gun chamber 10 are irradiated onto a substance 28 disposed in the sample chamber 14 via the optical system 12. The electrons that have passed through the substance 28 enter a fluorescent plate 32 installed inside the observation chamber 20 via the optical system 16. In the fluorescent plate 32, a transmission electron diffraction pattern can be measured by a pattern appearing according to the intensity of the incident electrons. can be measured.

[0252] The camera 18 is installed facing the fluorescent plate 32 and can photograph the pattern that appears on the fluorescent plate 32. The angle formed by the straight line passing through the center of the lens of the camera 18 and the center of the fluorescent plate 32 and the upper surface of the fluorescent plate 32 is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance, and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance, If so, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera 18 may be installed in the film chamber 22. For example, the camera 18 may be installed in the film chamber 22 so as to face the incident direction of the electrons 24. In this case, a transmission electron diffraction pattern with little distortion can be photographed from the back surface of the fluorescent plate 32.

[0253] A holder for fixing the substance 28, which is the sample, is installed in the sample chamber 14. The holder has a structure that allows electrons passing through the substance 28 to pass through. The holder may have, for example, a function of moving the substance 28 in the X-axis, Y-axis, Z-axis, etc. The moving function of the holder may have, for example, an accuracy of moving in a range of 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less, etc. These ranges may be set to an optimal range depending on the structure of the substance 28.

[0254] Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measuring apparatus will be described.

[0255] For example, as shown in FIG. 36(D), by changing (scanning) the irradiation position of the electrons 24, which are nanobeams in the substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 28 is CAAC-OS, a diffraction pattern as shown in FIG. 36(A) is observed. Or, if the substance 28 is nc-OS, a ring-shaped diffraction pattern with bright spots as shown in FIG. 36(B) is observed.

[0256] The diffraction pattern typically observed in CAAC-OS, as shown in Fig. 36(A), i.e., the diffraction pattern indicating the c-axis orientation, is called the diffraction pattern of the CAAC structure. As shown in Fig. 36(A), in the diffraction pattern of CAAC-OS, for example, spots located at the vertices of a hexagon can be identified. In CAAC-OS, by scanning the irradiation position, it can be seen that the orientation of this hexagon is not uniform and rotates little by little. Also, the rotation angle has a certain range.

[0257] Alternatively, in the diffraction pattern of CAAC-OS, by scanning the irradiation position, it can be seen that it rotates little by little around the c-axis. This can also be said to be that, for example, the plane formed by the a-axis and the b-axis rotates.

[0258] However, even if the substance 28 is CAAC-OS, a diffraction pattern similar to that of nc-OS, etc. may be observed partially. Therefore, the quality of CAAC-OS may be represented by the ratio of the area where the diffraction pattern of CAAC-OS is observed within a certain range (CAAC ratio, also referred to as the CAAC conversion rate). For example, for high-quality CAAC- OS, the CAAC ratio is 50% or more, preferably 80% or more, more preferably 9 0% or more, and even more preferably 95% or more and 100% or less. Note that the ratio of the area where a diffraction pattern different from that of CAAC-OS is observed within a certain range is referred to as the non-CAAC ratio or non-CAAC conversion rate.

[0259] Hereinafter, the method for evaluating the CAAC ratio of CAAC-OS will be described. Randomly select measurement points, obtain a transmission electron diffraction pattern, and for the total number of measurement points, ​The ratio of the number of measurement points at which the line is observed is calculated. Here, the number of measurement points is preferably 50 or more. A score of 100 or more is preferable.

[0260] As a method for randomly selecting measurement points, for example, the irradiation position is scanned linearly and the measurement points are selected at regular intervals. The diffraction pattern can be obtained at each time. This is preferable because it allows one to confirm the boundaries between regions having a structure and other regions.

[0261] As an example, a CAAC-OS film just after deposition (denoted as "as-sputtered") is The CAAC-OS samples were also heat-treated at 450°C in an oxygen-containing atmosphere. Samples were prepared, and the top surface of each sample was scanned to obtain a transmission electron diffraction pattern. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / sec for 60 sec. The CAAC ratio was derived by converting the captured diffraction pattern into still images every 0.5 seconds. The electron beam used was a nano-beam electron beam with a probe diameter of 1 nm. The measurements were performed on six samples. The CAAC ratio was calculated by the average value of the six samples. was used.

[0262] The CAAC ratio in each sample is shown in Fig. 37(A). The AC ratio was 75.7% (non-CAAC ratio was 24.3%). The CAAC rate in CAAC-OS after surgery was 85.3% (non-CAAC rate was 14.7%). It can be seen that the CAAC ratio is higher after the 450°C heat treatment than immediately after the film formation. By heat treatment at high temperatures (e.g., 400°C or higher), the non-CAAC ratio is reduced. It can be seen that (the CAAC ratio increases). Also, even in the heat treatment below 500 °C, it can be seen that CAAC-OS having a high CAAC ratio is obtained.

[0263] Here, most of the diffraction patterns different from that of CAAC-OS were the same diffraction pat terns as those of nc-OS. Also, in the measurement region, the amorphous oxide semiconductor could not be confirmed. Therefore, it is suggested that by the heat treatment, the regions having the same structure as nc-OS are rearranged under the influence of the structure of the adjacent regions and

[0264] become CAAC. Figs. 37(B) and 37(C) are plan-view TEM images of CAAC-OS immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 37(B) with Fig. 37(C), it can be seen that the film quality of CAAC-OS after heat treatment at 450 °C is more homogeneous. That is, it can be

[0265] seen that the film quality of CAAC-OS is improved by heat treatment at a high temperature. When such a measurement method is used, structural analysis of an oxide semiconductor having a

[0266] plurality of structures may be possible. Here, consider the case where when nano-beam electron diffraction is performed, CAAC-OS has a region having a structure other than the CAAC structure partially, for example, a region where a diffraction pattern of an nc structure is observed, or a region where a diffraction pattern of a spinel-type crystal structure is observed. In such a case, at the boundary between the region Therefore, there is a concern that the impurity concentration of CAAC-OS may increase.

[0267] In particular, the region having a structure other than the CAAC structure is a region having a spinel type crystal structure. In this case, between the area with CAAC structure and the area with non-CAAC structure In addition, at the boundary, the carrier scattering occurs. In addition, when forming a conductive film on the CAAC-OS, The elements of the conductive film, such as metal elements, have a region with a CAAC structure and a region with a spinel crystal structure. In addition, the crystal structure of the spinel type may be diffused to the boundary of the region having the spinel type crystal structure. In a film that is subject to this, the impurity concentration in the film, for example the hydrogen concentration, may increase. It is possible that impurities such as hydrogen are trapped. In particular, it is more preferable that the crystal structure does not contain any or only a small amount of spinel type crystal structure.

[0268] Consider the case where the oxide semiconductor contains an indium oxide semiconductor, an element M, and zinc. Here, the element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements that can be used for element M include boron, silicon, titanium, iron, and nickel. Nickel, Germanium, Yttrium, Zirconium, Molybdenum, Lanthanum, Cerium , neodymium, hafnium, tantalum, tungsten, etc. However, as the element M, In some cases, a combination of two or more of the above elements may be used. A preferable range of the ratio of the number of atoms of element M and zinc, x:y:z, will be described below.

[0269] In an oxide containing indium, element M, and zinc, InMO3(ZnO) m (m is a natural number), a homologous phase (homologous series) represented by is known to exist. Here As an example, consider the case where element M is Ga.

[0270] For example, as a compound having a spinel-type crystal structure, a compound represented by ZnM2 O4 such as ZnGa2O4 is known. Also, in the composition near ZnGa2O4, that is, Zn x Ga y O z where x, y, and z have values close to (x, y, z) = (0, 1, 2) In this case, a spinel-type crystal structure is likely to form or coexist. Here, the oxide semiconductor is preferably CAAC-OS. Also, CAAC-OS preferably does not contain a spinel-type crystal structure. Also, in order to increase the carrier mobility, it is preferable to increase the content ratio of In. In an oxide semiconductor containing indium, element M, and zinc, mainly the s orbitals of heavy metals contribute to carrier conduction. By increasing the content ratio of indium, more s orbitals overlap. Therefore, an oxide with a higher indium content has a higher mobility compared to an oxide with a lower indium content. Therefore, by using an oxide with a high indium content in the oxide semiconductor, the carrier mobility can be increased . For example, it is preferable to increase the atomic ratio of indium compared to other metal elements in order to increase the carrier mobility. For example, when the atomic ratio of indium, element M, and zinc in the oxide semiconductor is represented as x:y:z, x is preferably 1.75 times or more of y .

[0271] For example, it is preferable because the carrier mobility can be increased by increasing the atomic ratio of indium. For example, when the atomic ratio of indium, element M, and zinc in the oxide semiconductor is represented as x:y:z, x is preferably 1.75 times or more of y and preferably.

[0272] In addition, in order to further increase the CAAC ratio of the oxide semiconductor, it is preferable to increase the atomic ratio of zinc compared to other metal elements. For example, by setting the atomic ratio of In-Ga-Zn oxide within the range where a solid solution region can be obtained, the CAAC ratio may be further increased. When increasing the ratio of the number of atoms of zinc to the sum of the number of atoms of indium and gallium, the range where a solid solution region can be obtained tends to become wider. Therefore, by increasing the atomic ratio of zinc to the sum of the number of atoms of indium and gallium, the CAAC ratio of the oxide semiconductor may be further increased. For example, when the ratio of the number of atoms of indium, element M, and zinc in the oxide semiconductor is represented as x:y:z, it is preferable that z is 0.5 times or more of x + y. On the other hand, in order to increase the atomic ratio of indium and increase the carrier mobility, it is preferable that z is 2 times or less of x + y. As a result, the ratio at which a spinel-type crystal structure is observed in nano-beam electron diffraction can be eliminated or extremely reduced. Therefore, excellent CAAC-OS can be obtained. In addition, since carrier scattering etc. at the boundary between the CAAC structure and the spinel-type crystal structure can be reduced, when the oxide semiconductor is used for a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized. As a result, an oxide semiconductor with a high CAAC ratio can be realized. That is, high-quality CAAC-OS can be realized. In addition, in the region where a spinel-type crystal structure is observed,

[0273]

[0274] ​​​​​​​​​​It is possible to realize CAAC-OS with no or extremely little domain. For example, for a good quality CAAC-OS, the CAAC ratio is 50% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more and 100% or less.

[0275] In addition, when forming a film of an oxide semiconductor by sputtering, a film with an atomic ratio different from that of the target may be formed. In particular, for zinc, the atomic ratio of the film may be smaller than that of the target. Specifically, the atomic ratio of zinc contained in the target may be 40 atomic% or more and about 90 atomic% or less.

[0276] Therefore, the atomic ratio of the target preferably has a higher atomic ratio of zinc than the oxide semiconductor obtained by the sputtering method.

[0277] Note that the oxide semiconductor may be a laminate of a plurality of films. Also, the CAA C ratios of the respective plurality of films may be different. Further, among the plurality of laminated films, at least one layer of the film preferably has, for example, a CAAC ratio as high as 90%, more preferably 95% or more, and even more preferably 9 7% or more and 100% or less.

[0278] The above is the structure of the oxide semiconductor applicable to the semiconductor 406a, semiconductor 406b, semiconductor 406c, etc.

[0279] Next, other elements of the semiconductor applicable to the semiconductor 406a, semiconductor 406b, semiconductor 406c, etc. will be described.

[0280] The oxide semiconductor applicable to the semiconductor 406b is, for example, an oxide semiconductor containing indium. ​​​​​That is. When the semiconductor 406b contains indium, for example, the carrier mobility (electron mobility ) becomes high. Also, the semiconductor 406b preferably contains the element M. The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other applicable elements for M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like. However, in some cases, a plurality of the aforementioned elements may be combined as the element M. The element M is, for example, an element having a high binding energy with oxygen. For example, it is an element having a higher binding energy with oxygen than indium. Or, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. Also, the semiconductor 406b preferably contains zinc. The oxide semiconductor may be more likely to crystallize when it contains zinc.

[0281] For the semiconductor 406b, for example, an oxide having a large energy gap is used. The energy gap of the semiconductor 40 6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2. 8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3.5 eV or less.

[0282] The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c preferably contain at least indium. When the semiconductor 406a is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is less than 50 atomic% and M is 5 0 atomic% or more, more preferably In is less than 25 atomic% and M is 75 at omic%. It shall be omic% or more. When the semiconductor 406b is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is 25 atomic% or more and M is less than 75 atomic%, more preferably In is 34 atomic% or more and M is less than 66 atomic%. When the semiconductor 406c is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is less than 50 atomi c% and M is 50 atomic% or more, more preferably In is less than 25 atomic% and M is 75 atomic% or more. Note that the semiconductor 406c may use the same kind of oxide as the semiconductor 406a.

[0283] The semiconductor 406b uses an oxide with a larger electron affinity than the semiconductor 406a and the semiconductor 406c. For example, as the semiconductor 406b, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than those of the semiconductor 406a and the semiconductor 406c is used. Note that the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band.

[0284] Note that indium gallium oxide has a small electron affinity and high oxygen blocking property. Therefore, it is preferable that the semiconductor 406c contains indium gallium oxide. The gallium atomic ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, more preferably 90% or more.

[0285] At this time, when an electric field is applied to the gate electrode, the semiconductor 406a, the semiconductor 406b, the semiconductor ​​​​Among 406c, a channel is formed in the semiconductor 406b with a large electron affinity. Therefore, the field-effect mobility of the transistor can be increased. Here, since the semiconductor 406b and the semiconductor 406c have common constituent elements, almost no interface scattering occurs.

[0286] Here, there may be a mixed region between the semiconductor 406a and the semiconductor 406b, and between the semiconductor 406b and the semiconductor 406 c. Also, there may be a mixed region between the semiconductor 406b and the semiconductor 406c. The mixed region has a low interface level density. Therefore, the laminate of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c has a band structure in which energy changes continuously (also called a continuous junction) near each interface. Note that FIG. 38(A) is a cross-sectional view in which the semiconductor 406a, the semiconductor 406b and the semiconductor 406c are laminated in this order. FIG. 38(B) shows the energy (Ec) of the lower end of the conduction band corresponding to the dashed line P1-P2 in FIG. 38( A), and shows the case where the electron affinity of the semiconductor 406c is larger than that of the semiconductor 4 06a. Also, FIG. 38(C) shows the case where the electron affinity of the semiconductor 406c is smaller than that of the semiconductor 406a. At this time, electrons mainly move not in the semiconductor 406a and the semiconductor 406c but in the semiconductor 406 b. As described above, by reducing the interface level density at the interface between the semiconductor 406a and the semiconductor 406b and the interface level density at the interface between the semiconductor 406b and the semiconductor 406c , the movement of electrons in the semiconductor 406b is less inhibited, and the on-current of the transistor 490 can be increased.

[0287]

[0288] ​​​​​For example, semiconductor 406a and semiconductor 406c are oxide semiconductors containing one or more elements other than oxygen that constitute semiconductor 406b. Since semiconductor 406a and semiconductor 406c are composed of one or more elements other than oxygen that constitute semiconductor 406b, interface levels are less likely to be formed at the interface between semiconductor 406a and semiconductor 406b and at the interface between semiconductor 406b and semiconductor 406c.

[0289] It is preferable that semiconductor 406a, semiconductor 406b, and semiconductor 406c do not contain or contain little spinel-type crystal structure. Also, semiconductor 406a, semiconductor 406b, and semiconductor 406c are preferably CAAC-OS.

[0290] For example, by using CAAC-OS having a plurality of c-axis oriented crystal parts as semiconductor 406a, semiconductor 406b laminated thereon can form a region having a good c-axis orientation even in the vicinity of the interface with semiconductor 406a.

[0291] Also, by increasing the CAAC ratio of CAAC-OS, for example, the number of defects can be further reduced. Also, for example, the area having a spinel-type structure can be reduced. Also, for example, carrier scattering can be reduced. Also, for example, a film with a high blocking ability against impurities can be obtained. Therefore, by increasing the CAAC ratio of semiconductor 406a and semiconductor 406c, a good interface can be formed with semiconductor 406b in which a channel is formed, and carrier scattering can be suppressed to a small level. Also, the incorporation of impurities into semiconductor 406b can be suppressed, and the impurity concentration of semiconductor 406b can be reduced.

[0292] Even when the density of defect levels in the region where the channel is formed is high, the movement of electrons is inhibited. This occurs.

[0293] For example, when the semiconductor 406b has oxygen vacancies (also denoted as V O ).), hydrogen may enter the sites of the oxygen vacancies to form donor levels. In the following, the state where hydrogen enters the sites of the oxygen vacancies may be denoted as V H. V H scatters electrons, O which becomes a factor in reducing the on-current of the transistor 490. Note that the sites of oxygen vacancies are more stable when oxygen enters rather than hydrogen. Therefore, reducing the oxygen vacancies in the semiconductor 406b O may increase the on-current of the transistor 490 in some cases. To reduce the oxygen vacancies in the semiconductor 406b, for example, there is a method of moving the excess oxygen contained in the insulator 402 to the semiconductor 406b through the semiconductor 406a. In this case the semiconductor 406a is preferably a layer having oxygen permeability (a layer that allows oxygen to pass through or permeate). Oxygen is released from the insulator 402 by heat treatment or the like and taken into the semiconductor 406a. Note that oxygen may exist freely between the atoms in the semiconductor 406a or may exist in combination with other oxygen

[0294] etc. The lower the density of the semiconductor 406a, that is, the more interstitial spaces between the atoms, the higher the oxygen permeability. For example, also, when the semiconductor 406a has a layered crystal structure and the movement of oxygen across the layers is unlikely to occur, the semiconductor 406a is preferably a layer with moderately low crystallinity. This is preferred.

[0295] Oxygen is released from the insulator 402 by heat treatment or the like and taken into the semiconductor 406a. Oxygen may exist freely between the atoms in the semiconductor 406a or may exist in combination with other oxygen etc. The lower the density of the semiconductor 406a, that is, the more interstitial spaces between the atoms, the higher the oxygen permeability. For example, also, when the semiconductor 406a has a layered crystal structure and the movement of oxygen across the layers is unlikely to occur, the semiconductor 406a is preferably a layer with moderately low crystallinity. This is preferred. For example, also, when the semiconductor 406a has a layered crystal structure and the movement of oxygen across the layers is unlikely to occur, the semiconductor 406a is preferably a layer with moderately low crystallinity.

[0296] ​In order for the excess oxygen (oxygen) released from the insulator 402 to reach the semiconductor 406b the semiconductor 406a preferably has a crystallinity that allows the excess oxygen (oxygen) to permeate. For example when the semiconductor 406a is CAAC-OS, if the entire layer becomes CAAC, the excess oxygen (oxygen) cannot permeate, so it is preferable to have a structure with gaps in part . For example, the CAAC ratio of the semiconductor 406a may be less than 100%, preferably less than 98%, more preferably less than 95%, and even more preferably less than 90%. However, in order to reduce the interface state density between the semiconductor 4 06a and the semiconductor 406b, the CA AC ratio of the semiconductor 406a may be 10% or more, preferably 20% or more, more preferably 50%, and even more preferably 70% or more.

[0297] Also, in order to increase the on-current of the transistor 490, the thickness of the semiconductor 406c is preferably as small as possible. For example less than 10 nm, preferably 5 nm or less, and more preferably a semiconductor 406c having a region of 3 nm or less may be used. On the other hand, the semiconductor 406c has a function of blocking elements other than oxygen (hydrogen, silicon, etc.) that constitute the adjacent insulator from entering the semiconductor 406b where the channel is formed . Therefore, the semiconductor 406c preferably has a certain thickness. For example a semiconductor 406c having a region with a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more may be used . Also, the semiconductor 406c preferably has a property of blocking oxygen in order to suppress the outward diffusion of oxygen released from the insulator 402 etc . .

[0298] In addition, to increase reliability, semiconductor 406a is thick and semiconductor 406c is thin which is preferable. For example, semiconductor 406a having a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 n m or more, and even more preferably 60 nm or more may be used . By increasing the thickness of semiconductor 406a, the distance from the interface between the adjacent insulator and semiconductor 406a to semiconductor 406b where a channel is formed can be increased. However, since the productivity of the semiconductor device may decrease, for example, semiconductor 406a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used . For example, between semiconductor 406b and semiconductor 406a, for example, in secondary ion mass spectrometry ( SIMS: Secondary Ion Mass Spectrometry), there is a region having a silicon concentration of less than 1×10

[0299] atoms / cm ², preferably less than 5×10 atoms / cm 19 ², and more preferably less than 2×10 3 atoms / cm 18 ² 3 . Also, between semiconductor 406b and semiconductor 406c, in SIMS, there is a region having a silicon concentration of less than 1×1 0 19 atoms / cm ², preferably less than 5×10 0 3 atoms / cm 18 ², and more preferably less than 2×10 3 atoms / cm 18 ² . Also, in order to reduce the hydrogen concentration of semiconductor 406b, semiconductor 406a and semiconductor 40 3 atoms / cm 20 ²

[0300] 6c It is preferable to reduce the hydrogen concentration of 6c. The semiconductors 406a and 406c have a region with a hydrogen concentration of 2×10 atoms / cm 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, and even more preferably 5×10 18 atoms / cm 3 or less. Also, to reduce the nitrogen concentration of the semiconductor 406b, it is preferable to reduce the nitrogen concentration of the semiconductors 406a and 406c. The semiconductors 406a and 406c have a region with a nitrogen concentration of less than 5×10 atoms / cm atoms / cm 0 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, and even more preferably 5×10 17 ato ms / cm 3 or less.

[0301] The above are the structures and other elements of oxide semiconductors applicable to the semiconductors 406a, 406b, 406c, etc. By applying the oxide semiconductor as described above to the semiconductors 406a, semiconductors 406b, 406c, etc., the transistor 490 can obtain good electrical characteristics. For example, good switching speed can be obtained. For example, the switching speed of the transistor 490 is less than 10 ns, preferably less than 1 ns, more preferably less than 0.1 ns. Furthermore, as the transistor 490, good switching characteristics can be obtained. characteristics can be obtained. For example, good switching speed can be obtained. For example, the switching speed of the transistor 490 is less than 10 ns, preferably less than 1 ns, more preferably By using a p-channel type Si transistor having speed, one aspect of the present invention The semiconductor device (cell) can improve the operating speed. For example, the p-channel type S The switching speed of the i transistor is less than 10 ns, preferably less than 1 ns, more preferably less than 0.1 ns. Also, for example, the delay time of an inverter or a NAND circuit which is a semiconductor device (cell) according to one aspect of the present invention is less than 10 ns, preferably less than 1 ns, more preferably less than 0.1 ns.

[0302] (Embodiment 8) An example of the configuration of a semiconductor device using the semiconductor device (cell) according to one aspect of the present invention will be described with reference to FIG. 21.

[0303] The semiconductor device 300 shown in FIG. 21 includes a CPU core 301, a power management unit 321, and a peripheral circuit 322. The power management unit 321 includes a power controller 302 and a power switch 303. The peripheral circuit 322 includes a cache 304 having a cache memory, a bus interface (BUS I / F) 305 , and a debug interface (Debug I / F) 306. The CPU core 3 01 includes a data bus 323, a control device 307, a PC (program counter) 308, a pi pline register 309, a pipeline register 310, an ALU (Arithmetic logic unit) 311, and a register file 312. The data exchange between the CPU core 3 01 and the peripheral circuit 322 such as the cache 304 is performed via the data bus 32 3.

[0304] ​A semiconductor device (cell) according to one aspect of the present invention can be applied to many logic circuits, including a power controller 302 and a control device 3 07. In particular, it can be applied to all logic circuits that can be configured using standard cells. As a result, a small semiconductor device 300 can be provided. Also, a semiconductor device 300 capable of reducing power consumption can be provided. Further, a semiconductor device 300 capable of improving the operating speed can be provided. Also

[0305] a semiconductor device 300 capable of reducing fluctuations in the power supply voltage can be provided. In a semiconductor device (cell) according to one aspect of the present invention, a p-channel Si transistor and the oxide semiconductor (preferably an oxide containing In, Ga, and Zn) described in the previous embodiment are used in the channel formation region. By applying the semiconductor device (cell) to the semiconductor device 300 a small semiconductor device 300 can be provided. Also, a semiconductor device 300 capable of reducing power consumption can be provided. Further, a semiconductor device 300 capable of improving the operating speed can be provided. In particular, by using only p-channel type Si transistors, the manufacturing cost can be kept low.

[0306]

[0307] The control device 307 has the function of decoding and executing instructions included in a program such as an input application by comprehensively controlling the operations of the PC 308, pipeline registers 309, 310, ALU 311, register file 312, cache 304, bus interface 305, debug interface 306, and power controller 302. 310, ALU 311, register file 312, cache 304, bus interface 305, debug interface 306, and power controller 302 to comprehensively control the operations of the PC 308, pipeline registers 309, 310, ALU 311, register file 312, cache 304, bus interface 305, debug interface 306, and power controller 302. By comprehensively controlling the operations of the PC 308, pipeline registers 309, 310, ALU 311, register file 312, cache 304, bus interface 305, debug interface 306, and power controller 302, the control device 307 has the function of decoding and executing instructions included in a program such as an input application.

[0307] ​​​The ALU 311 has the function of performing various arithmetic operations such as addition, subtraction, multiplication, division, and logical operations.

[0308] The cache 304 has the function of temporarily storing frequently used data. C 308 is a register that has the function of storing the address of the next instruction to be executed. Note that , although not shown in FIG. 21, the cache 304 is provided with a cache controller for controlling the operation of the cache memory.

[0309] The pipeline register 309 is a register that has the function of temporarily storing instruction data.

[0310] The register file 312 has a plurality of registers including general-purpose registers, and can store data read from the main memory, or data obtained as a result of the arithmetic processing of the ALU 311, etc.

[0311] The pipeline register 310 is a register that has the function of temporarily storing data used for the arithmetic processing of the ALU 311, or data obtained as a result of the arithmetic processing of the A LU 311.

[0312] The bus interface 305 has the function of serving as a data path between the semiconductor device 300 and various devices outside the semiconductor device 300. The debug interface 3 06 has the function of serving as a signal path for inputting instructions for controlling debugging into the semiconductor device 300.

[0313] The power switch 303 has the function of controlling the supply of the power voltage to various circuits other than the power controller 302 of the semiconductor device 300. The above various circuits include several ​ Each belongs to the word main, and various circuits belonging to the same power domain are powered The presence or absence of the supply of the power supply voltage is controlled by the power switch 303. Also, the power controller 302 has a function of controlling the operation of the power switch 303.

[0314] The semiconductor device 300 having the above configuration can perform power gating. An example will be given to explain the flow of the operation of power gating.

[0315] First, the CPU core 301 sets the timing to stop the supply of the power supply voltage in the register of the power controller 302. Next, a command to start power gating is sent from the CPU core 301 to the power controller 3 02. Next, various registers and caches 304 included in the semiconductor device 300 start saving data. Next, the semiconductor The supply of the power supply voltage to various circuits other than the power controller 302 included in the device 300 is Stopped by the power switch 303. Next, when an interrupt signal is input to the power controller 302 The supply of the power supply voltage to various circuits included in the semiconductor device 300 is started . Note that a counter is provided in the power controller 302, and the timing at which the supply of the power supply voltage is started is Determined using the counter regardless of the input of the interrupt signal. It may be done. Next, various registers and caches 304 start restoring data. Next Then, the execution of the instruction in the control device 307 is resumed. Then, the execution of the instruction in the control device 307 is resumed.

[0316] Such power gating can be performed in the entire processor, or in one Or a plurality of logic circuits constituting the processor. Also, even for a short time, the supply of power It can be stopped. Therefore, power consumption can be reduced with a fine granularity spatially or temporally.

[0317] When performing power gating, it is preferable that the information held by the CPU core 301 and the peripheral circuit 322 can be saved in a short period of time. By doing so, the power can be turned on and off in a short period of time, and the power saving effect is enhanced.

[0318] In order to save the information held by the CPU core 301 and the peripheral circuit 322 in a short period of time, it is preferable that a flip-flop circuit can save data in the circuit (referred to as a backup-capable flip-flop circuit). Also, it is preferable that an SRAM cell can save data in the cell (referred to as a backup-capable SRAM cell). The backup-capable flip-flop circuit and SRAM cell preferably have a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region. As a result, since the transistor has a low off-current, the backup-capable flip-flop circuit and SRAM cell can hold information without power supply for a long period of time. Also, since the transistor has a high switching speed, the backup-capable flip-flop circuit and SRAM cell may be capable of short-term data saving and restoration.

[0319] Examples of the backup-capable flip-flop circuit and the backup-capable SRAM cell will be described with reference to FIGS. 22 and 23.

[0320] The semiconductor device 200 shown in FIG. 22 is an example of a backup-capable flip-flop circuit. ​​​​​​​​​​​​​Yes. The semiconductor device 200 includes a first memory circuit 201, a second memory circuit 202, and a third memory circuit 203, and a read circuit 204. A potential difference between a potential V1 and a potential V2 is supplied as a power supply voltage to the semiconductor device 200. One of the potential V1 and the potential V2 is at a high level and the other is at a low level. Hereinafter, a configuration example of the semiconductor device 200 will be described by taking the case where the potential V1 is at a low level and the potential V2 is at a high level as an example.

[0321] The first memory circuit 201 has a function of holding data when a signal D including data is input during a period when a power supply voltage is supplied to the semiconductor device 200. Then, during a period when a power supply voltage is supplied to the semiconductor device 200, a signal Q including the held data is output from the first memory circuit 201. On the other hand, the first memory circuit 201 cannot hold data during a period when a power supply voltage is not supplied to the semiconductor device 200. That is, the first memory circuit 201 can be called a volatile memory circuit.

[0322] The second memory circuit 202 has a function of reading and storing (or saving) the data held in the first memory circuit 201. The third memory circuit 203 has a function of reading and storing (or saving) the data held in the second memory circuit 202. The read circuit 204 has a function of reading the data held in the second memory circuit 202 or the third memory circuit 203 and storing (or restoring) it in the first memory circuit 201.

[0323] In particular, the third memory circuit 203 stores data during a period when a power supply voltage is not supplied to the semiconductor device 200. ​​​​​​​​​However, it has a function of reading and storing (or avoiding) the data held in the second memory circuit 202. to avoid).

[0324] As shown in FIG. 22, the second memory circuit 202 includes a transistor 212 and a capacitor element 219. The third memory circuit 203 includes a transistor 213, a transistor 215, and a capacitor element 220. The read circuit 204 includes a transistor 210, a transistor 21 8, a transistor 209, and a transistor 217.

[0325] The transistor 212 has a function of charging and discharging the capacitor element 219 with an electric charge corresponding to the data held in the first memory circuit 201. The transistor 212 can charge and discharge the capacitor element 219 with an electric charge corresponding to the data held in the first memory circuit 2 01 at high speed. Specifically, it is desirable that the transistor 212 includes crystalline silicon (preferably polycrystalline silicon, more preferably single-crystalline silicon) in the channel formation region. It is desirable.

[0326] The transistor 213 is selected to be in a conductive state or a non-conductive state according to the electric charge held in the capacitor element 219. When the transistor 213 is in a conductive state, the transistor 215 has a function of charging and discharging the capacitor element 220 with an electric charge corresponding to the potential of the wiring 244. It is desirable that the transistor 215 has an extremely small off-current. Specifically, it is desirable that the transistor 215 includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region. It is desirable.

[0327] Specifically explaining the connection relationship of each element, the source and drain of the transistor 212 One side is connected to the first memory circuit 201. The source and drain of the transistor 212 The other side of the in is connected to one electrode of the capacitive element 219, the gate of the transistor 213, and the tran The gate of the transistor 218. The other electrode of the capacitive element 219 is connected to the wiring 242 is connected. One of the source and drain of the transistor 213 is connected to the wiring 244 is connected. The other of the source and drain of the transistor 213 is connected to one of the source and drain of the transistor 215. The source and drain of the transistor 215 The other is connected to one electrode of the capacitive element 220 and the gate of the transistor 210 is connected. The other electrode of the capacitive element 220 is connected to the wiring 243. One of the source and drain of the transistor 21 0 is connected to the wiring 241. One of the source and drain of the transistor 210 The other is connected to one of the source and drain of the transistor 218 is connected. The other of the source and drain of the transistor 218 is connected to the source of the transistor 209 and one of the drains. The source and drain of the transistor 209 The other is connected to one of the source and drain of the transistor 217 and the first memory circuit 201 is connected. The other of the source and drain of the transistor 217 is connected to the wiring 240 is connected. Also, in FIG. 22, the gate of the transistor 209 is connected to the gate of the transistor 2 17, but the gate of the transistor 209 does not necessarily have to be connected to the gate of the transistor 217.

[0328] The transistor exemplified in the previous embodiment can be applied to the transistor 215 Since the off-current of the transistor 215 is small, the semiconductor device 200 can retain information without power supply for a long time. Since the switching characteristics of the transistor 215 are good, the semiconductor device 200 can perform high-speed backup and recovery.

[0329] The semiconductor device 100 shown in FIG. 23 is an example of a backup-capable SRAM cell. The semiconductor device 100 includes transistors M101, M102, Mos1, Mos2, inverters INV101, INV102, and capacitors C101, C102. The semiconductor device 100 is connected to wirings WL, BL, BLB, and BRL. Also, a low power supply voltage (VSS) or the like is supplied to the semiconductor device 100 as a power supply voltage.

[0330] The inverters INV101 and INV102 have their input nodes and output nodes connected to each other, forming an inverter loop circuit. The gate of the transistor M101 and the gate of the transistor M102 are connected to the wiring WL. The transistor M101 functions as a switch connecting between the wiring BL and the input node of the inverter INV101, and the transistor M102 functions as a switch connecting between the wiring BLB and the input node of the inverter INV102.

[0331] The wiring WL functions as a write / read word line, and a selection signal ( WLE) for the memory cell is input from a word line driver circuit. The wirings BL and BLB function as bit lines for sending data signals D and DB. The data signal DB is a signal obtained by inverting the logical value of the data signal D. The data signals D and DB are supplied from a bit line driver circuit. Also, ​​​​​​​The wirings BL and BLB are also wirings that send data read from the semiconductor device 100 to the output circuit. There is.

[0332] The semiconductor device 100 corresponds to a circuit provided with a pair of memory circuits in a volatile memory circuit having an inverter INV101, an inverter INV102, transistors M101, and transistors M102. The pair of memory circuits includes a memory circuit having transistors Mos1 and capacitor C101 (hereinafter referred to as memory circuit (Mos1, C101)), and a memory circuit having transistors Mos2 and capacitor C102 (hereinafter referred to as memory circuit (Mos2, C102)). The memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) are circuits for backing up the data of the volatile memory circuit by storing the potentials held at nodes NET1 and NET2, respectively. These memory circuits write data by charging or discharging capacitors C101 and C102 by turning transistors Mos1 and Mos2 on, and hold the data without power supply by turning them off and holding the charges accumulated in the capacitors. A circuit provided with a pair of memory circuits is provided in a volatile memory circuit having an inverter INV101, an inverter INV102, transistors M101, and transistors M102. The pair of memory circuits includes a memory circuit having transistors Mos1 and capacitor C101 (hereinafter referred to as memory circuit (Mos1, C101)), and a memory circuit having transistors Mos2 and capacitor C102 (hereinafter referred to as memory circuit (Mos2, C102)). The memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) are circuits for backing up the data of the volatile memory circuit by storing the potentials held at nodes NET1 and NET2, respectively. These memory circuits write data by charging or discharging capacitors C101 and C102 by turning transistors Mos1 and Mos2 on, and hold the data without power supply by turning them off and holding the charges accumulated in the capacitors. That is, a pair of memory circuits. The pair of memory circuits includes a memory circuit having transistors Mos1 and capacitor C101 (hereinafter referred to as memory circuit (Mos1, C101)), and a memory circuit having transistors Mos2 and capacitor C102 (hereinafter referred to as memory circuit (Mos2, C102)). The memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) are circuits for backing up the data of the volatile memory circuit by storing the potentials held at nodes NET1 and NET2, respectively. These memory circuits write data by charging or discharging capacitors C101 and C102 by turning transistors Mos1 and Mos2 on, and hold the data without power supply by turning them off and holding the charges accumulated in the capacitors. 01 (hereinafter referred to as memory circuit (Mos1, C101)). A memory circuit having transistors Mos2 and capacitor C102 (hereinafter referred to as memory circuit (Mos2, C102)). The memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) are circuits for backing up the data of the volatile memory circuit by storing the potentials held at nodes NET1 and NET2, respectively. These memory circuits write data by charging or discharging capacitors C101 and C102 by turning transistors Mos1 and Mos2 on, and hold the data without power supply by turning them off and holding the charges accumulated in the capacitors. A memory circuit having transistors Mos2 and capacitor C102 (hereinafter referred to as memory circuit (Mos2, C102)). The memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) are circuits for backing up the data of the volatile memory circuit by storing the potentials held at nodes NET1 and NET2, respectively. These memory circuits write data by charging or discharging capacitors C101 and C102 by turning transistors Mos1 and Mos2 on, and hold the data without power supply by turning them off and holding the charges accumulated in the capacitors. 02). The memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) are circuits for backing up the data of the volatile memory circuit by storing the potentials held at nodes NET1 and NET2, respectively. These memory circuits write data by charging or discharging capacitors C101 and C102 by turning transistors Mos1 and Mos2 on, and hold the data without power supply by turning them off and holding the charges accumulated in the capacitors. The memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) are circuits for backing up the data of the volatile memory circuit by storing the potentials held at nodes NET1 and NET2, respectively. These memory circuits write data by charging or discharging capacitors C101 and C102 by turning transistors Mos1 and Mos2 on, and hold the data without power supply by turning them off and holding the charges accumulated in the capacitors. By storing the potentials held at nodes NET1 and NET2, respectively, they are circuits for backing up the data of the volatile memory circuit. These memory circuits write data by charging or discharging capacitors C101 and C102 by turning transistors Mos1 and Mos2 on, and hold the data without power supply by turning them off and holding the charges accumulated in the capacitors. These memory circuits charge or discharge capacitors C101 and C102 by turning transistors Mos1 and Mos2 on to write data, and turn them off to hold the charges accumulated in the capacitors, thereby holding the data without power supply. These memory circuits charge or discharge capacitors C101 and C102 by turning transistors Mos1 and Mos2 on to write data, and turn them off to hold the charges accumulated in the capacitors, thereby holding the data without power supply. These memory circuits charge or discharge capacitors C101 and C102 by turning transistors Mos1 and Mos2 on to write data, and turn them off to hold the charges accumulated in the capacitors, thereby holding the data without power supply. That is, without power supply.

[0333] Data recovery is also performed by turning transistors Mos1 and Mos2 on. With the power supply to inverters INV101 and INV102 stopped, transistors Mos1 and Mos2 are turned on to connect node FN1 to node NET1 and share charges at nodes FN1 and NET1, and then node FN2 is connected to node NET2 and charges are shared at nodes FN2 and NET2. Then, With the power supply to inverters INV101 and INV102 stopped, transistors Mos1 and Mos2 are turned on to connect node FN1 to node NET1 and share charges at nodes FN1 and NET1, and then node FN2 is connected to node NET2 and charges are shared at nodes FN2 and NET2. Then, Transistors Mos1 and Mos2 are turned on to connect node FN1 to node NET1 and share charges at nodes FN1 and NET1, and then node FN2 is connected to node NET2 and charges are shared at nodes FN2 and NET2. Then, Transistors Mos1 and Mos2 are turned on to connect node FN1 to node NET1 and share charges at nodes FN1 and NET1, and then node FN2 is connected to node NET2 and charges are shared at nodes FN2 and NET2. Then, Node FN2 is connected to node NET2 and charges are shared at nodes FN2 and NET2. Then, inverter INV10 1. By supplying power to INV102, data is fed back to the inverter loop circuit according to the potentials of node NET1 and node NET2. Then, transistors Mos1 and Mos2 are turned off. The gates of transistors Mos1 and Mos2 are connected to wiring BRL. A signal OSG is input to wiring BRL. The signal OSG drives a pair of memory circuits (memory circuit (Mos1, C101), memory circuit (Mos2, C102)) to perform backup or recovery.

[0334] The gates of transistors Mos1 and Mos2 are connected to wiring BRL. A signal OSG is input to wiring BRL. The signal OSG drives a pair of memory circuits (memory circuit (Mos1, C101), memory circuit (Mos2, C102)) to perform backup or recovery. L. A signal OSG is input to wiring BRL. The signal OSG drives a pair of memory circuits (memory circuit (Mos1, C101), memory circuit (Mos2, C102)) to perform backup or recovery. 1, C101), memory circuit (Mos2, C102)) to perform backup or recovery.

[0335] Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described.

[0336] The memory circuits (Mos1, C101), (Mos2, C102) hold the potentials of nodes FN1 and FN2 by accumulating charges in capacitors C101 and C102. By turning on transistors Mos1 and Mos2, node NET1 and node FN1 are connected, and the potential held at node NET1 is applied to node FN1. Also, by turning on transistor Mos2, node NET2 and node FN2 are connected, and the potential held at node NET2 is applied to node FN2. Then, by turning off transistors Mos1 and Mos2, nodes FN1 and FN2 become electrically floating, and the charges accumulated in capacitors C101 and C102 are held, and the memory circuit enters the data holding state. Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described. Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described. Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described. Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described. Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described. Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described. Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described. Hereinafter, the configuration and operation of the memory circuit (Mos1, C101) and the memory circuit (Mos2, C102) will be described.

[0337] For example, when node FN1 is at the H level, charge leaks from C101 and gradually ​​​There is a risk that the voltage will drop. Transistors Mos1 and Mos2 preferably contain an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region. As a result, the leakage current (off-current) flowing between the source and drain in the off state is extremely small, so fluctuations in the voltage of node FN1 are suppressed. That is, the memory circuit (Mos1, C101) can be operated as a non-volatile memory circuit or a memory circuit that can hold data for a long time without power supply. Similarly, the memory circuit (Mos2, C102), and these memory circuits can be used as backup memory circuits for a volatile memory circuit having inverters INV101, INV102, transistor M101, and transistor M102.

[0338] The transistors exemplified in the previous embodiments can be applied to transistors Mos1 and Mos2. Since the off-currents of transistors Mos1 and Mos2 are small, semiconductor device 100 can hold information without power supply for a long time. Since the switching characteristics of transistors Mos1 and Mos2 are good, semiconductor device 100 can perform high-speed backup and recovery.

[0339] A semiconductor device (cell) according to an aspect of the present invention and a backup flip-flop circuit or SRAM cell using a transistor containing an oxide semiconductor exemplified in the previous embodiments can be applied to semiconductor device 300. As a result, it becomes possible to turn the power on and off in a short period, and a semiconductor device with lower power consumption can be provided.

[0340] Also, a semiconductor device (cell) according to an aspect of the present invention and the oxide semiconductor exemplified in the previous embodiment A backup-capable flip-flop circuit and an SRAM cell using a transistor including an oxide semiconductor in a channel formation region can be applied to the semiconductor device 300. As a result, The manufacturing cost can be suppressed. In particular, all n-channel transistors used in the flip-flop circuit and the SRAM cell may be replaced with transistors including the oxide semiconductor exemplified in the previous embodiment in a channel formation region. By considering the Si transistor as a p-channel type, the manufacturing cost can be kept low. Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like. Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like. Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like. Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like.

[0341] Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like. aphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Proces sor), an MCU (Microcontroller Unit), an RF-ID (Rad io Frequency Identification), a custom LSI, and the like. Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like.

[0342] (Embodiment 9) In this embodiment, a usage example of the semiconductor device (cell) according to an aspect of the present invention will be described. Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like.

[0343] FIG. 24(A) shows a perspective view of a part inside a package using a lead frame type interposer. The package shown in FIG. 24(A) is a chip 751 to which a semiconductor device (cell) according to an aspect of the present invention is applied, and is wire-bonded to the interposer Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like. Note that the semiconductor device (cell) according to an aspect of the present invention can be applied not only to a CPU but also to a GPU (Graphics Processing Unit), a PLD (Programmable Logic Device), a DSP (Digital Signal Processor), an MCU (Microcontroller Unit), an RF-ID (Radio Frequency Identification), a custom LSI, and the like. It is connected to a terminal 752 on 750. The terminal 752 is disposed on the surface where the chip 751 of the interposer 750 is mounted. And the chip 751 may be encapsulated by a molding resin 753, but it is encapsulated in a state where a part of each terminal 752 is exposed to be.

[0344] The configuration of a module of an electronic device (mobile phone) in which the package is mounted on a circuit board is shown in FIG. 24(B). The module of the mobile phone shown in FIG. 24(B) has a printed wiring board 7 61, a package 762, and a battery 764 mounted thereon. Also, a printed wiring board 761 is mounted on a panel 760 provided with a display element by an FPC 763 and is.

[0345] (Embodiment 10) An example of the configuration of a semiconductor device using a semiconductor device (cell) according to an aspect of the present invention will be described with reference to FIGS. 26 to 29.

[0346] FIG. 26 shows an example of the configuration of a semiconductor device. The semiconductor device 600 shown in FIG. 26 is an example of a semiconductor device that can function as a storage device. The semiconductor device 600 includes a memory cell array 610, a row decoder 621, a word line driver circuit 622, a bit line driver circuit 630, an output circuit 640, and a control logic circuit 660.

[0347] The bit line driver circuit 630 includes a column decoder 631, a precharge circuit 632, a sense amplifier 633, and a write circuit 634. The precharge circuit 632 has a function of precharging the wiring BL and BLB, and the voltages of the wiring BL and the wiring BLB in the same column are ​​​The sense amplifier 633 has a function of equalizing the data read from the wirings BL and BLB. The amplified data signals D and DB are output to the output circuit 640. The digital data signal RDATA is outputted to the outside of the semiconductor device 600 via the GND terminal 614.

[0348] The semiconductor device 600 also receives a low power supply voltage VSS as an external power supply voltage, A high power supply voltage VDD for the circuit section 601 other than the array, a high power supply voltage VDD for the memory cell array 610 A pressure VIL is supplied.

[0349] The semiconductor device 600 also includes control signals CE, WE, and RE, an address signal ADDR, The data signal WDATA is input from the outside. The WDATA is input to a write circuit 634.

[0350] The control logic circuit 660 receives control signals (CE, WE, RE ) to generate control signals for the row decoder 621 and the column decoder 631. The signal CE is a chip enable signal, and the control signal WE is a write enable signal. The control signal RE is a read enable signal. The signals processed by 0 are not limited to these, and other control signals can be input as necessary. Just put in the effort.

[0351] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as necessary.

[0352] The semiconductor device (cell) according to one embodiment of the present invention includes a row decoder 621, a word line driver circuit 622, bit line driver circuit 630, output circuit 640, control logic circuit It can be applied to 660. In particular, it can be configured using standard cells. It can be applied to all logic circuits. As a result, a small semiconductor device 600 can be provided. Moreover, a semiconductor device 600 capable of reducing power consumption can be provided. Also, a semiconductor device 600 capable of improving the operation speed can be provided.

[0353] In the semiconductor device (cell) according to one aspect of the present invention, a p-channel type Si transistor and a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) described in the previous embodiment in the channel formation region are used, and by applying them to the semiconductor device 600, a small semiconductor device 600 can be provided. Moreover, a semiconductor device 600 capable of reducing power consumption can be provided. Also, a semiconductor device 600 capable of improving the operation speed can be provided. In particular, by using only p-channel type Si transistors, the manufacturing cost can be kept low.

[0354] Note that for the memory cell array 610, a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) described in the previous embodiment in the channel formation region may be used. An example of such a memory cell will be described below with reference to FIGS. 27 to 29.

[0355] FIG. 27 is a circuit diagram showing an example of the configuration of a memory cell. The memory cell 103 has a transistor Mos3 and a capacitor C103. The node FN3 is a data holding part, and the terminal of the capacitor C103 is connected thereto. The transistor Mos3 functions as a switch connecting the node FN3 and the wiring BL, and its gate is connected to the wiring WL. The wiring To WL, signal OSG is input as a signal for selecting a memory cell.

[0356] FIG. 28 is a circuit diagram showing an example of the configuration of a memory cell. Memory cell 104 has transistor Mos4, transistor M104, and capacitor C104. Node FN 4 is a data holding part, and transistor Mos4 functions as a switch connecting node FN4 and wiring BL, and its gate is connected to wiring WL. Signal OSG is input to wiring WL. Capacitor C104 connects between wiring WLC and node FN4. Wiring WLC is a wiring for supplying a constant voltage to the terminals of C104 during write and read operations. Transistor M104 is a p-channel type transistor, and its gate is connected to node FN4, its source is connected to wiring SL, and its drain is connected to wiring BL. With a constant voltage applied to wirings WLC and SL, transistor Mos4 is turned on to connect node FN4 to wiring BL, thereby writing data. For reading data, a constant voltage is applied to wirings BL, WLC, and SL. Depending on the voltage of node FN4, the value of the current flowing between the source and drain of transistor M104 varies. Due to the source-drain current of transistor M104, wiring BL is charged or discharged, so the data value held in memory cell 104 can be read by detecting the voltage of wiring BL.

[0357] Note that transistor M104 can be an n-channel type transistor. The voltage applied to wirings (BL, SL, WLC) is determined according to the conductivity type of transistor M104.

[0358]

[0359] ​​​​​​​​ Figure 29 is a circuit diagram showing an example of the configuration of a memory cell. Memory cell 105 includes a transistor Mos5, a transistor M105, a transistor M106, and a capacitor C10 5. Node FN5 is a data holding section, and transistor Mos5 functions as a switch connecting node FN5 to wiring BL, and its gate is connected to wiring WL. A signal OSG is input to wiring WL. One terminal of wiring BL and capacitor C105 is connected by transistors M105 and M106. The gate of transistor M105 is connected to wiring RWL, and the gate of transistor M106 is connected to node FN5. Also, the other terminal of capacitor C105 is connected to node FN5.

[0360] Writing of data is performed by turning on transistor Mos5 and connecting node FN4 to wiring B L. Reading of data is performed by turning on transistor M105. Depending on the voltage of node FN5, the value of the current flowing between the source and drain of transistor M106 varies. Due to the source-drain current of transistor M106, wiring BL is charged or discharged, so the data value held in memory cell 105 can be read by detecting the voltage of wiring BL.

[0361] Note that transistors M105 and M106 can be p-channel type transistors. The voltages applied to wiring RWL and capacitor C105 may be determined according to the conductivity type of transistors M105 and M106.

[0362] In the configuration examples of the memory cells shown in FIGS. 27 to 29, transistors Mos3 and Mo It is desirable that S4 and Mos5 include an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region. As a result, since the leakage current (off-current) flowing between the source and drain of the transistor in the off state is extremely small, fluctuations in the voltages of nodes FN3, FN4, and FN5 can be suppressed. That is, the circuits including Mos3 and C103, the circuits including Mos4 and C104, and the circuits including Mos3 and C103 can each operate as a non-volatile memory circuit or a memory circuit capable of retaining data for a long time without power supply.

[0363] By applying the semiconductor device (cell) according to one aspect of the present invention and the memory cell using the transistor including the oxide semiconductor exemplified in the previous embodiment in the channel formation region to the semiconductor device 600, a semiconductor device 600 having a non-volatile memory circuit or a memory circuit capable of retaining data for a long time without power supply can be provided. Further, a semiconductor device 600 that can be miniaturized, has low power consumption, can operate at high speed, or can reduce fluctuations in the power supply voltage can be provided.

[0364] Also, the semiconductor device (cell) according to one aspect of the present invention and the memory cell using the transistor including the oxide semiconductor exemplified in the previous embodiment in the channel formation region can be applied to the semiconductor device 600. Therefore, it is possible to suppress the manufacturing cost. In particular, all the n-type transistors used in the memory cell may be formed using the transistors including the oxide semiconductor exemplified in the previous embodiment in the channel formation region. By using only p-channel type Si transistors, the manufacturing cost can be kept low. ​​​​​​​​​​​​​​​​

[0365] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. .

[0366] (Embodiment 11) An example of the configuration of an apparatus using a semiconductor device (cell) according to one aspect of the present invention will be described with reference to FIG. 25. while using it.

[0367] The semiconductor device 800 shown in FIG. 25 is an example of the configuration of an RFID tag. In this embodiment, the RFID tag has a memory circuit inside, stores necessary information in the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Due to such characteristics, the RFID tag can be used in an individual authentication system that identifies an article by reading the individual information of the article or the like.

[0368] The semiconductor device 800 shown in FIG. 25 includes an antenna 804, a rectifier circuit 805, a constant voltage circuit 80 6, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. .

[0369] The antenna 804 is for transmitting and receiving a radio signal 803 between the antenna 802 connected to the communicator 801. Also, the rectifier circuit 805 generates an input potential. Specifically, it generates an input AC signal by receiving a radio signal with the antenna 804, rectifies the input power signal, for example, half-wave double voltage rectifies it, and the rectified signal is smoothed by a capacitive element provided at the subsequent stage of the rectifier circuit 805. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit that limits the amplitude of the input AC signal. of the rectifier circuit 805. or the output side. When the amplitude is large and the internally generated voltage is large, it controls so that electric power equal to or more than a certain amount of electric power is not input to the subsequent circuit. It is a circuit for such control.

[0370] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. In addition, the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit generates a reset signal for the logic circuit 809 by utilizing the rise of the stable power supply voltage. The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. Also, the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit generates a reset signal for the logic circuit 809 by utilizing the rise of the stable power supply voltage. The reset signal generation circuit generates a reset signal for the logic circuit 809 by utilizing the rise of the stable power supply voltage. The reset signal generation circuit generates a reset signal for the logic circuit 809 by utilizing the rise of the stable power supply voltage.

[0371] The demodulation circuit 807 demodulates by envelope-detecting the input AC signal and generates a demodulated signal. Also, the modulation circuit 808 performs modulation according to the data output from the antenna 804. The demodulation circuit 807 demodulates by envelope-detecting the input AC signal and generates a demodulated signal. Also, the modulation circuit 808 performs modulation according to the data output from the antenna 804. The modulation circuit 808 performs modulation according to the data output from the antenna 804.

[0372] The logic circuit 809 decodes and processes the demodulated signal. The memory circuit 810 holds the input information and has a loader, a column decoder, a memory area, etc. Also, the ROM 811 stores a unique number (ID), etc., and outputs according to the process. The logic circuit 809 decodes and processes the demodulated signal. The memory circuit 810 holds the input information and has a loader, a column decoder, a memory area, etc. Also, the ROM 811 stores a unique number (ID), etc., and outputs according to the process. The ROM 811 stores a unique number (ID), etc., and outputs according to the process.

[0373] Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communicate by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, a radio wave method in which communication is performed using radio waves, etc. The semiconductor device 800 shown in this embodiment can be used in any of these methods. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communicate by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, a radio wave method in which communication is performed using radio waves, etc. The semiconductor device 800 shown in this embodiment can be used in any of these methods. The semiconductor device 800 shown in this embodiment can be used in any of these methods. The semiconductor device 800 shown in this embodiment can be used in any of these methods.

[0374] In addition, each of the above circuits can be appropriately selected and discarded as necessary.

[0375] The semiconductor device (cell) according to one aspect of the present invention can be applied to the logic circuit 809, the memory circuit 810, the ROM 811, etc. In particular, it can be configured using standard cells. The semiconductor device (cell) according to one aspect of the present invention can be applied to the logic circuit 809, the memory circuit 810, the ROM 811, etc. In particular, it can be configured using standard cells. It can be applied to all logic circuits. As a result, a small semiconductor device 800 can be provided. In addition, a semiconductor device 800 capable of reducing power consumption can be provided. Also, a semiconductor device 800 capable of improving the operating speed can be provided.

[0376] A p-channel Si transistor and a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) described in the previous embodiment in a channel formation region are used. By applying a semiconductor device (cell) according to one aspect of the present invention to the semiconductor device 800, a small semiconductor device 800 can be provided. In addition, a semiconductor device 800 capable of reducing power consumption can be provided. In addition, a semiconductor device 800 capable of improving the operating speed can be provided. In particular, by using only p-channel Si transistors, the manufacturing cost can be kept low.

[0377] Note that the memory circuit 810 can use the memory circuit described in the previous embodiment. In addition, for the element exhibiting a rectifying action included in the demodulation circuit 807, a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) described in the previous embodiment in a channel formation region may be used. Since the transistor has a low off-current, the reverse current of the element exhibiting a rectifying action can be suppressed to be small. As a result, excellent rectification efficiency can be realized.

[0378] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0379] (Embodiment 12) A semiconductor device (cell) according to one aspect of the present invention can be used in a display device, a personal computer, an image playback device equipped with a recording medium (typically a device having a display capable of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying its image). Additionally, as electronic devices that can use the semiconductor device (cell) according to one aspect of the present invention, there are mobile phones, game machines including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (such as car audio and digital audio players), copiers, facsimiles, printers, printer copiers, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 30. FIG. 30(A) is a portable game machine and has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that the portable game machine shown in FIG. 30(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this. FIG. 30(B) is a portable data terminal and has a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection unit 915. and can be used. Other electronic devices that can use the semiconductor device (cell) according to one aspect of the present invention include mobile phones, game machines including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (such as car audio and digital audio players), copiers, facsimiles, printers, printer copiers, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 30. Mobile phones, game machines including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (such as car audio and digital audio players), copiers, facsimiles, printers, printer copiers, automated teller machines (ATMs), vending machines, and the like. FIG. 30(A) shows a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Although the portable game machine shown in FIG. 30(A) has two display units 903 and a display unit 904, the number of display units of the portable game machine is not limited to this. FIG. 30(B) shows a portable data terminal, which has a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection unit 915.

[0380] FIG. 30(A) is a portable game machine, having a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, etc. Note that the portable game machine shown in FIG. 30(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this. FIG. 30(A) is a portable game machine, having a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, etc. Although the portable game machine shown in FIG. 30(A) has two display units 903 and a display unit 904, the number of display units of the portable game machine is not limited to this. FIG. 30(B) is a portable data terminal, having a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, operation keys 916, etc.

[0381] FIG. 30(B) is a portable data terminal, having a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection unit 915. and the angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915 There is. It is also possible to adopt a configuration in which the video on the first display unit 913 is switched according to the angle between the first housing 911 and the second housing 912 at the connecting portion 915. Further, at least one of the first display unit 9 13 and the second display unit 914 may be a display device to which a function as a position input device is added. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device.

[0382] FIG. 30(C) is a notebook personal computer, and includes a housing 921, a display unit 922, a keyboard 923, a pointing device 924, and the like.

[0383] FIG. 30(D) is an electric refrigerator-freezer, and includes a housing 931, a refrigerator door 932, a freezer door 9 33, and the like.

[0384] FIG. 30(E) is a video camera, and includes a first housing 941, a second housing 942, a display unit 943 , operation keys 944, a lens 945, a connecting portion 946, and the like. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display unit 943 is provided on the second housing 942. The first housing 941 and the second housing 942 are connected by the connecting portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. It is also possible to adopt a configuration in which the video on the display unit 943 is switched according to the angle between the first housing 941 and the second housing 942 at the connecting portion 946. 942. ​​​​​​

[0385] Figure 30(F) is a normal automobile, which has a vehicle body 951, wheels 952, a dashboard 953, lights 954, etc.

[0386] By using the semiconductor device (cell) according to one aspect of the present invention in these electronic devices, miniaturization of the electronic devices, increase in the operating speed, reduction in power consumption, and / or reduction in fluctuations in the power supply voltage can be achieved. In particular, by using only p-channel type Si transistors, the manufacturing cost can be kept low. As a result, small-sized electronic devices can be provided. Also, by using the semiconductor device (cell) according to one aspect of the present invention, an electronic device with reduced power consumption can be provided. Also, an electronic device capable of high-speed operation can be provided. Also, an electronic device that operates more stably can be provided.

[0387] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0388] Note that the content described in one embodiment (even a part of the content) can be applied to, combined with, or replaced with the content described in another part (even a part of the content) in that embodiment, and / or the content described in one or more other embodiments (even a part of the content).

[0389] Note that the content described in the embodiments refers to the content described using various figures in each embodiment, or the content described using the text described in the specification.

[0390] Note that the figure (even a part of it) described in one embodiment can be applied to, combined with, or replaced with ​​, another figure (which may be a part) described in the embodiment, and / or, a figure (which may be a part) described in one or more other embodiments can be combined to form even more figures. By combining with the figure (which may be a part) described in one or more other embodiments, even more figures can be constructed.

Description of Reference Numerals

[0391] 10 Electron gun chamber 11 Memory circuit 12 Optical system 14 Sample chamber 16 Optical system 18 Camera 20 Observation chamber 22 Film chamber 24 Electron 28 Substance 32 Fluorescent plate 100 Semiconductor device 101 INV 102 INV 103 Memory cell 104 Memory cell 105 Memory cell 200 Semiconductor device 201 Memory circuit 202 Memory circuit 203 Memory circuit 204 Circuit 209 Transistor 210 Transistor 212 Transistor 213 Transistor 215 Transistor 217 Transistor 218 Transistor 219 Capacitor element 220 Capacitor element 240 Wiring 241 Wiring 242 Wiring 243 Wiring 244 Wiring 300 Semiconductor device 301 CPU core 302 Power controller 303 Power Switch 304 Cache 305 Bus Interface 306 Debug Interface 307 Control Device 308 PC 309 Pipeline Register 310 Pipeline Register 311 ALU 312 Register File 321 Power Management Unit 322 Peripheral Circuit 323 Data Bus 400 Semiconductor Substrate 402 Insulator 404 Conductor 404a Conductor 404b Conductor 406 Semiconductor 406a Semiconductor 406b Semiconductor 406c Semiconductor 408 Insulator 412 Insulator 413 Conductor 416a Conductor 416b Conductor 416c Conductor 424a Conductor 424b Conductor 424c Conductor 425a Conductor 425b Conductor 442 Insulator 452 Insulator Region 454 Conductor 454a Conductor 454b Conductor 460 Insulator 462 Insulator 464 Insulator 465 Insulator 466 Insulator 467 Insulator 468 Insulator 470 Insulator 471 Conductor 472 Conductor 473 Conductor 474 Region 476a Region 476b Region 476c Region 480 Conductor 482 Conductor 484 Conductor 490 Transistor 490a Transistor 490b Transistor 491 Transistor 491a Transistor 491b Transistor 492 Transistor 500 Semiconductor Device 501 Semiconductor Device 502 Semiconductor Device 503 Semiconductor Device 504 Semiconductor Device 510 Semiconductor Device 511 Semiconductor Device 600 Semiconductor Device 601 Circuit Section 610 Memory Cell Array 621 Loader Decoder 622 Word Line Driver Circuit 630 Bit Line Driver Circuit 631 Column Decoder 632 Precharge Circuit 633 Sense Amplifier 634 Circuit 640 Output Circuit 660 Control Logic Circuit 750 Interposer 751 Chip 752 Terminal 753 Mold Resin 760 Panel 761 Printed Wiring Board 762 Package 763 FPC 764 Battery 800 Semiconductor device 801 Communicator 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Memory circuit 811 ROM 901 Housing 902 Housing 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display unit 914 Display unit 915 Connection part 916 Operation key 921 Housing 922 Display unit 923 Keyboard 924 Pointing device 931 Housing 932 Door for refrigerator compartment 933 Door for freezer compartment 941 Housing 942 Housing 943 Display unit 944 Operation key 945 Lens 946 Connection part 951 Vehicle body 952 Wheel 953 Dashboard 954 Light

Claims

1. A semiconductor device comprising a first transistor, a second transistor, a first conductor, and a second conductor, wherein the second transistor and the first transistor are stacked, a first power supply voltage is supplied to the first conductor and a second power supply voltage is supplied to the second conductor, the first conductor has a first region and the second conductor has a second region, the first region and the second region overlap with each other via one or more layers of insulators and extend in parallel, one of a source electrode and a drain electrode of the first transistor is electrically connected to the first conductor, one of a source electrode and a drain electrode of the second transistor is electrically connected to the second conductor, the second transistor is an n-channel type and a channel formation region of the second transistor is formed of an oxide semiconductor, the first transistor is a p-channel type and a channel formation region of the first transistor is formed of silicon.

2. The semiconductor device according to claim 1, comprising an input terminal electrically connected to gate electrodes of the first transistor and the second transistor, and an output terminal electrically connected to the other of the source electrode and the drain electrode of the first transistor and the second transistor, wherein a width of the first conductor and a width of the second conductor are wider than a width of a conductor connected to the input terminal and larger than a width of a conductor connected to the output terminal.

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