Silicon-based josephson junctions for qubit devices

Abstract

To provide a qubit device which includes a Josephson junction including superconducting silicon material implemented in a vertical structure orientation, and a method for manufacturing the same.SOLUTION: A qubit device 100 includes a Josephson junction that includes a tunnel barrier 106 disposed between two vertically stacked superconducting silicon electrodes 102, 104.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present disclosure relates to one or more silicon-based Josephson junctions that can be incorporated into a qubit device, and more particularly to Josephson junctions including superconducting silicon materials that can be implemented in a vertical structure orientation.

Summary of the Invention

[0002] An overview is presented below that provides a basic understanding of one or more embodiments of the present invention. This overview is not intended to identify key or critical elements nor to define any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in an overview form as a prelude to a more detailed description that will be presented later. In one or more embodiments described herein, an apparatus or method or both related to a silicon-based Josephson junction for one or more qubit devices is described.

[0003] According to one embodiment, an apparatus is provided. The apparatus may comprise a Josephson junction including a tunnel barrier disposed between two vertically stacked superconducting silicon electrodes.

[0004] According to another embodiment, an apparatus is provided. The apparatus may comprise a Josephson junction including a dielectric tunnel barrier disposed between two superconducting silicon electrodes.

[0005] According to one embodiment, a method is provided. The method may include doping a portion of a silicon substrate to form a first superconducting electrode. The method may also include depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form a tunnel barrier. Further, the method may include doping a portion of the tunnel barrier to form a second superconducting electrode and forming a Josephson junction.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0007] The following detailed description is merely exemplary and is not intended to limit embodiments or the application or use of embodiments, either or both. Further, no intention is made to be bound by any representation or suggested information presented in the preceding background or summary sections or the detailed description of the invention section.

[0008] Hereinafter, one or more embodiments will be described with reference to the drawings, in which like reference numerals are used throughout to refer to like elements. In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that in various cases, one or more embodiments may be practiced without these specific details. Further, features shown in the drawings with like shading, cross-hatching, or coloring, or combinations thereof, may include a common composition and / or material, or both.

[0009] For the purpose of increasing the coherence time exhibited by a quantum computing device, Josephson junctions have been used to fabricate qubits (e.g., superconducting qubits). However, the theoretical coherence time associated with Josephson junctions is often shorter than that actually exhibited by the qubits. The material composition of the Josephson junction can affect the coherence time. For example, the type of superconducting material utilized, impurities within the superconducting material, or defects introduced by the manufacturing process with respect to the superconducting material, or combinations thereof, can have an adverse effect on the coherence time exhibited by the Josephson junction qubit. For example, an aluminum-based Josephson junction may exhibit a longer coherence time than a niobium-based Josephson junction, yet still be subject to decoherence caused by defects (e.g., aluminum oxide defects) that are commonly introduced during the manufacture and / or deposition of aluminum and / or aluminum derivatives, or both.

[0010] The various embodiments described herein may relate to an apparatus or method or both for manufacturing silicon-based Josephson junctions for incorporation within one or more qubit devices. For example, one or more embodiments may relate to Josephson junctions that include silicon materials that may be crystalline, such as doped superconducting silicon electrodes where single crystal undoped silicon acts as the junction. By using silicon materials, chemical purification, crystal growth, or defect control, or combinations thereof, may be achieved in the various embodiments described herein while implementing complementary metal oxide semiconductor (“CMOS”) technology. In one or more embodiments, the silicon-based Josephson junction may include a silicon dielectric material as a tunnel barrier to two superconducting silicon electrodes. Further, one or more embodiments may include orienting the silicon-based Josephson junction structure in a vertical orientation. Further, in various embodiments, electrical isolation of the Josephson junction may be achieved via intrinsic silicon, or incorporation of one or more isolation implants into the silicon, or both.

[0011] As described herein, the term "superconducting" can characterize materials that exhibit superconducting properties below the superconducting critical temperature. Further, as described herein, the term "deposition process" can denote any process of growing, coating, depositing, or transferring one or more first materials onto one or more second materials, or combinations thereof. Exemplary deposition processes can include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), atomic layer deposition ("ALD"), low pressure chemical vapor deposition ("LPCVD"), plasma enhanced chemical vapor deposition ("PECVD"), high density plasma chemical vapor deposition ("HDPCVD"), sub-atmospheric chemical vapor deposition ("SACVD"), rapid thermal chemical vapor deposition ("RTCVD"), in-situ radical assisted deposition, high temperature oxide deposition ("HTO"), low temperature oxide deposition ("LTO"), limited reaction processing CVD ("LRPCVD"), ultra-high vacuum chemical vapor deposition ("UHVCVD"), metal organic chemical vapor deposition ("MOCVD"), physical vapor deposition ("PVD"), chemical oxidation, sputtering, plating, evaporation, spin-on-coating, ion beam deposition, electron beam deposition, laser assisted deposition, or chemical solution deposition, or combinations thereof, etc.

[0012] As described herein, the term "epitaxial growth process" or "epitaxial growth process" or both may refer to any process of growing an epitaxial material (e.g., a crystalline semiconductor material) on the deposition surface of another semiconductor material, and the epitaxial material to be grown has substantially the same crystal characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants supplied by a source gas (e.g., a gas containing silicon or germanium or both) or a source liquid or both can be controlled, and the system parameters can be set, so that the deposited atoms move around on the surface and arrive at the deposition surface with sufficient energy to orient themselves with respect to the crystal structure of the atoms on the deposition surface. Therefore, the grown epitaxial material has substantially the same crystal characteristics as the deposition surface on which the epitaxial material is formed. For example, an epitaxially grown semiconductor material deposited on a crystal surface with a <100> orientation may have a <100> orientation. Exemplary epitaxial growth processes may include, but are not limited to, vapor phase epitaxy ("VPE"), molecular beam epitaxy ("MBE"), or liquid phase epitaxy ("LPE"), or combinations thereof.

[0013] As described herein, the term "etching process" or "removal process" or both may refer to any process of removing one or more first materials from one or more second materials. Exemplary etching processes or removal processes or both may include, but are not limited to, wet etching, dry etching (e.g., reactive ion etching ("RIE")), or chemical mechanical planarization ("CMP"), or combinations thereof.

[0014] As described herein, the term "laser doping process" can refer to one or more gas immersion laser doping techniques that can achieve a homogeneous doped layer of silicon where the active concentration and / or thickness varies, or both. The laser doping process can be carried out in an ultra-high vacuum ("UHV") chamber, and a precursor gas (e.g., boron trichloride) can be injected into the chamber and onto the surface of the silicon material (e.g., thereby saturating one or more chemisorption sites of the silicon material). Thereafter, a pulsed laser (e.g., a pulsed excimer XeCl laser) can be used to melt the silicon material in order to heat the silicon material over a defined duration. One or more dopants (e.g., boron, gallium, or germanium, or a combination thereof) from the precursor gas can diffuse into and be incorporated substitutionally into the silicon material. Thereby, a silicon-dopant (e.g., silicon-boron (Si:B), silicon-germanium (Si:Ge), or silicon-gallium (Si:Ga)) crystal can grow on the underlying silicon via one or more epitaxial growth processes.

[0015] FIG. 1A or FIG. 1B, or both, shows a diagram of an exemplary and non-limiting qubit device 100 that can include a first superconducting silicon electrode 102, a second superconducting silicon electrode 104, or a tunnel barrier 106, or a combination thereof, according to one or more embodiments described herein. FIG. 1A shows a cross-sectional view of the qubit device 100, and FIG. 1B shows a top view of the qubit device 100. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted.

[0016] As shown in FIG. 1A, a silicon-based Josephson junction can be disposed on a semiconductor substrate 108. Further, a first superconducting silicon electrode 102, a second superconducting silicon electrode 104, or a dielectric tunnel barrier 106, or a combination thereof, can be stacked on the semiconductor substrate 108 in a vertical orientation (e.g., along the "Y" axis). Further, at least a portion of the semiconductor substrate 108 and one or more isolation layers 110 can form an isolation region 112 (e.g., indicated by the bold dashed line) adjacent to the silicon-based Josephson junction. Further, the silicon-based Josephson junction can include a first metal contact 114 operably coupled to the first superconducting silicon electrode 102, or a second metal contact 116 operably coupled to the second superconducting silicon electrode 104, or both.

[0017] The semiconductor substrate 108 can be crystalline, quasi-crystalline, microcrystalline, or amorphous. The semiconductor substrate 108 can essentially (e.g., excluding foreign substances) include a single element (e.g., silicon or germanium) or a compound (e.g., aluminum oxide, silicon dioxide, gallium arsenide, silicon carbide, or silicon-germanium, or a combination thereof, etc.). The semiconductor substrate 110 can also have a plurality of material layers such as, but not limited to, a semiconductor-on-insulator substrate ("SeOI"), a silicon-on-insulator substrate ("SOI"), a germanium-on-insulator substrate ("GeOI"), or a silicon-germanium-on-insulator substrate ("SGOI"), or a combination thereof. Further, the semiconductor substrate 110 can also have other layers such as high dielectric constant oxides ("high-K oxides") or nitrides or both. In one or more embodiments, the semiconductor substrate 110 can be a silicon wafer. In various embodiments, the semiconductor substrate 110 can include single crystal silicon (Si), silicon-germanium (e.g., characterized by the chemical formula SiGe), or a group III-V semiconductor wafer or surface / active layer, or a combination thereof, etc.

[0018] In one or more embodiments, at least the upper end portion of the semiconductor substrate 108 can provide structural support for a silicon-based Josephson junction and / or a qubit device 100 (such as shown in FIG. 1A and / or FIG. 1B or both). In various embodiments, at least the upper end portion of the semiconductor substrate 108 can include intrinsic silicon. In some embodiments, at least the upper end portion of the semiconductor substrate 108 can include silicon germanium (SiGe).

[0019] The first superconducting silicon electrode 102 can include a laser-doped crystalline silicon material. For example, one or more dopants can be incorporated into a portion of the silicon material via one or more laser-doping processes to promote superconductivity. Exemplary dopants that can be included within the first superconducting silicon electrode 102 can include, but are not limited to, boron, gallium, or germanium, or combinations thereof. In one or more embodiments, the first superconducting silicon electrode 102 can have a dopant activation concentration in the range of, for example, from 4 atomic percent (At%) or more to 40 At% or less (for example, if the first superconducting electrode 102 includes a boron dopant, from at least 4 At% to 11 At%, or if the first superconducting electrode 102 includes a gallium dopant, from at least 10 At% to 40 At%, or both). In various embodiments, the critical temperature of the first superconducting electrode 102 can range from, for example, 500 millikelvin (mK) or more to 6 K or less (for example, if the first superconducting electrode 102 includes a boron dopant, from 500 mK to 600 mK, or if the first superconducting electrode 102 includes a gallium dopant, from 5 K to 6 K, or both).

[0020] Those skilled in the art will understand that the length of the first superconducting silicon electrode 102 (e.g., along the "X" axis) can vary depending on the function of the silicon-based Josephson junction, the structure of the qubit device 100, or both. For example, the length of the first superconducting silicon electrode 102 (e.g., along the "X" axis) can be 100 nanometers (nm) or more and several hundred microns or less (e.g., 500 nm to 1,000 nm). Similarly, the thickness of the first superconducting silicon electrode 102 (e.g., along the "Y" axis) can vary depending on the function of the silicon-based Josephson junction, the structure of the qubit device 100, or both. For example, the thickness of the first superconducting silicon electrode 102 (e.g., along the "Y" axis) can be 5 nm or more and 500 nm or less (e.g., 10 nm to 50 nm). Further, in one or more embodiments, the first superconducting silicon electrode 102 can be embedded in the semiconductor substrate 108 (e.g., as shown in FIG. 1A).

[0021] In one or more embodiments, the tunnel barrier 106, one or more isolation layers 110, or the first metal contact, or a combination thereof, can be disposed on (e.g., immediately on) the first superconducting silicon electrode 102. The tunnel barrier 106 is shown by a dashed line in FIG. 1A. In various embodiments, the tunnel barrier 106 can include a dielectric material to convert a silicon-based Josephson junction into a superconductor-insulator-superconductor (“SIS”) Josephson junction. For example, the tunnel barrier 106 can include an intrinsic silicon material. In one or more embodiments, the tunnel barrier 106 can include doped silicon to convert a silicon-based Josephson junction into a superconductor-normal-superconductor (“SNS”) Josephson junction. For example, one or more dopants that can be included within the tunnel barrier 106 can include, but are not limited to, phosphorus (P) or arsenic (As) or both. Those skilled in the art will understand that the length of the tunnel barrier 106 (e.g., along the “X” axis) can vary depending on the function of the silicon-based Josephson junction or the qubit device 100 or both. For example, the length of the tunnel barrier 106 (e.g., along the “X” axis) can be 30 nm or more and 1,000 nm or less (e.g., 100 nm to 300 nm). Similarly, the thickness of the tunnel barrier 106 (e.g., along the “Y” axis) can vary depending on the function of the silicon-based Josephson junction or the qubit device 100 or both. For example, the thickness of the tunnel barrier 106 (e.g., along the “Y” axis) can be 0.5 nm or more and 300 nm or less.

[0022] The second superconducting silicon electrode 104 can be disposed on the tunnel barrier 106 such that the tunnel barrier 106 is positioned between the first superconducting silicon electrode 102 and the second superconducting silicon electrode 104. In one or more embodiments, the second superconducting silicon electrode 104 can have the same or substantially the same composition as the first superconducting silicon electrode 102. Alternatively, in one or more embodiments, the second superconducting silicon electrode 104 can have a composition different from that of the first superconducting silicon electrode 102.

[0023] For example, the second superconducting silicon electrode 104 can include a laser-doped crystalline silicon material. For example, one or more dopants can be incorporated into a portion of the silicon material via one or more laser-doping processes to promote superconductivity. Exemplary dopants that can be included within the second superconducting silicon electrode 104 can include, but are not limited to, boron or gallium or combinations thereof. In one or more embodiments, the second superconducting silicon electrode 104 can have a dopant activation concentration in the range of, for example, from 4 At% to 40 At% (e.g., if the first superconducting electrode 102 includes a boron dopant, from at least 4 At% to 11 At%, or if the first superconducting electrode 102 includes a gallium dopant, from at least 10 At% to 40 At%, or both). In various embodiments, the critical temperature of the second superconducting silicon electrode 104 can range from, for example, 500 mK to 6 K (e.g., if the second superconducting electrode 104 includes a boron dopant, from 500 mK to 600 mK, or if the second superconducting electrode 104 includes a gallium dopant, from 5 K to 6 K, or both).

[0024] One of ordinary skill in the art will understand that the length of the second superconducting silicon electrode 104 (e.g., along the "X" axis) can vary depending on the function of the silicon-based Josephson junction or qubit device 100 or both. For example, the length of the second superconducting silicon electrode 104 (e.g., along the "X" axis) can be 10 nm or more and several hundred microns or less (e.g., 500 nm to 1,000 nm). Similarly, the thickness of the second superconducting silicon electrode 104 (e.g., along the "Y" axis) can vary depending on the function of the silicon-based Josephson junction or qubit device 100 or both. For example, the thickness of the second superconducting silicon electrode 104 (e.g., along the "Y" axis) can be 5 nm or more and 500 nm or less (e.g., 10 nm to 50 nm).

[0025] In one or more embodiments, one or more isolation layers 110 can be adjacent to the first superconducting silicon electrode 102, the tunnel barrier 106, or the second superconducting silicon electrode 104, or a combination thereof. The one or more isolation layers 110 can include one or more insulator materials and / or can electrically isolate the silicon-based Josephson junction from adjacent hardware and / or devices (e.g., an adjacent qubit device 100). In various embodiments, the one or more isolation layers 110 can include intrinsic silicon or can be deposited in the same manufacturing step as the tunnel barrier 106, or both. At least a portion of the one or more isolation layers 110 or the semiconductor substrate 108, or both, can define an isolation region 112 (e.g., shown by the thick dashed line in FIG. 1A). As shown in FIG. 1A, in one or more embodiments, the semiconductor substrate 108, the tunnel barrier 106, or the isolation layer 110, or a combination thereof, can include the same or substantially the same material (e.g., intrinsic silicon).

[0026] As shown in FIG. 1A, the first metal contact 114 or the second metal contact 116 or both can be adjacent to the isolation region 112 (e.g., at the upper end of the isolation region 112 when the first superconducting silicon electrode 102, the tunnel barrier 106, or the second superconducting silicon electrode 104 or a combination thereof is arranged in a stacked vertical orientation). The second metal contact 116 can be operably coupled (e.g., in direct contact) to the second superconducting silicon electrode 104. Further, the first metal contact 114 can extend through what would normally be a part of the isolation region 112 that is operably coupled to the first superconducting silicon electrode 102. The first metal contact 114 or the second metal contact 116 or both can include a conductive superconductor such as, but not limited to, aluminum (Al), niobium (Nb), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), vanadium (V), tin (Sb), or lead (Pb), or a combination thereof.

[0027] FIG. 1B shows a top view of the qubit device 100 shown in FIG. 1A and / or illustrates one or more exemplary arrangements and / or structural configurations of features of the qubit device 100 along the "Z" axis. FIGS. 1A or 1B or both show a qubit device comprising a single Josephson junction disposed on a semiconductor substrate 108, but the architecture of the qubit device 100 is not so limited. For example, a qubit device 100 comprising a plurality of Josephson junctions (e.g., a plurality of first superconducting silicon electrodes 102, tunnel barriers 106, or second superconducting silicon electrodes 104, or a combination thereof) is also envisioned. For example, one or more qubit devices 100 can include the features described herein (e.g., as shown in FIGS. 1A or 1B) and can comprise a plurality of Josephson junctions disposed adjacent to each other on the semiconductor substrate 108.

[0028] Figure 2 shows a diagram of an exemplary and non-limiting qubit device 100 during a first stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. During the first stage of manufacturing, one or more resist masks 202 may be deposited on the semiconductor substrate 108 via one or more deposition processes. The thickness of the resist mask 202 (e.g., along the "Y" axis) may vary, for example, in the range from 100 or more to 1,000 nm or less (e.g., from 100 nm to 300 nm). The exposed regions of the semiconductor substrate 108 (e.g., not covered by the resist mask 202) may define one or more boundaries of the silicon-based Josephson junctions.

[0029] Figure 3 shows a diagram of an exemplary and non-limiting qubit device 100 during a second stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. During the second stage of manufacturing, the first superconducting silicon electrode 102 may be formed, or the resist mask 202 may be removed, or both.

[0030] In one or more embodiments, one or more laser doping processes may be performed on an exposed (e.g., not covered by the resist mask 202) region of the semiconductor substrate 108 to form the first superconducting silicon electrode 102. For example, one or more laser doping processes may be performed on the exposed region to implant boron dopants and form the first superconducting silicon electrode 102. In one or more embodiments, the first superconducting silicon electrode 102 may be formed by etching a trench in an exposed region of the semiconductor substrate 108 (e.g., via one or more etching processes). Thereafter, an epitaxial silicon material such as an epitaxial silicon dopant material (e.g., Si:Ga, Si:Ge, or Ge, or a combination thereof) may be selectively deposited in the trench via one or more epitaxial growth processes. When the first superconducting silicon electrode 102 grows via one or more epitaxial growth processes, the thickness of the first superconducting silicon electrode 102 (e.g., along the "Y" axis) may be defined via one or more CMP processes. The resist mask 202 may be removed via one or more etching processes.

[0031] FIG. 4 shows a diagram of an exemplary and non-limiting qubit device 100 during a third stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. During the third stage of manufacturing, one or more silicon layers 402 may be deposited on the first superconducting electrode 102 and / or the semiconductor substrate 108 and / or both via one or more deposition processes and / or epitaxial growth processes and / or both. In one or more embodiments, one or more silicon layers 402 may be deposited at low temperature (e.g., by molecular beam epitaxy ("MBE"), e.g., at a temperature less than 500 degrees Celsius (°C)) via one or more epitaxial growth processes.

[0032] In one or more embodiments, one or more silicon layers 402 may then form the tunnel barrier 106 or one or more isolation layers 110 or both. Thereby, the thickness of the one or more silicon layers 402 (e.g., along the "Y" axis) can vary according to the desired thickness of the tunnel barrier 106, one or more isolation layers 110, or the second superconducting silicon electrode 104, or a combination thereof. For example, the thickness of the one or more silicon layers 402 (e.g., along the "Y" axis) can range from 5 nm or more to 500 nm or less (e.g., 20 nm to 50 nm).

[0033] FIG. 5A or FIG. 5B or both show diagrams of an exemplary and non-limiting qubit device 100 during a fourth stage of manufacturing according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 5A shows a cross-sectional view of the qubit device 100 during the fourth stage of manufacturing, or FIG. 5B shows a top view of the qubit device 100 during the fourth stage of manufacturing, or both. During the fourth stage of manufacturing, one or more resist masks 202 can be deposited on one or more silicon layers 402 via one or more deposition processes. The exposed regions (e.g., not covered by the resist mask 202) of the one or more silicon layers 402 can define one or more boundaries of the second superconducting silicon electrode 104.

[0034] FIG. 6A or FIG. 6B or both show diagrams of an exemplary and non-limiting qubit device 100 during a fifth stage of manufacturing according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 6A shows a cross-sectional view of the qubit device 100 during the fifth stage of manufacturing, or FIG. 6B shows a top view of the qubit device 100 during the fifth stage of manufacturing, or both. During the fifth stage of manufacturing, the second superconducting silicon electrode 104 can be formed.

[0035] In one or more embodiments, one or more laser doping processes may be performed on exposed regions (e.g., regions not covered by the resist mask 202) of one or more silicon layers 402 to form the second superconducting silicon electrode 104. For example, one or more laser doping processes may be performed on the exposed regions to implant dopants (e.g., boron) to form the second superconducting silicon electrode 104. In one or more embodiments, the second superconducting silicon electrode 104 may be formed by etching trenches in exposed regions of one or more silicon layers 402 (e.g., via one or more etching processes). Thereafter, an epitaxial silicon material such as an epitaxial silicon dopant material (e.g., Si:Ga, Si:Ge, or Ge, or a combination thereof) may be selectively deposited into the trenches via one or more epitaxial growth processes. When the second superconducting silicon electrode 104 grows via one or more epitaxial growth processes, the thickness of the second superconducting silicon electrode 104 (e.g., along the "Y" axis) may be defined via one or more CMP processes.

[0036] Thereby, the formation of the second superconducting silicon electrode 104 may define the tunnel barrier 106 or one or more separation layers 110 or both from the remaining portions of the one or more silicon layers 402. For example, the portion of the one or more silicon layers 402 remaining between the first superconducting silicon electrode 102 and the second superconducting silicon electrode 104 may be the tunnel barrier 106. For example, the tunnel barrier 106 may include intrinsic silicon (which may act as a dielectric, e.g., at a critical temperature of about 20 mK). Further, the portions of the one or more silicon layers 402 remaining adjacent to the second superconducting silicon electrode 104 and the tunnel barrier 106 may be one or more separation layers 110.

[0037] In one or more embodiments, the remaining portion of silicon layer 402 that can become tunnel barrier 106 can be doped (e.g., with P or As or both) to form a normal metal tunnel barrier 106. For example, the remaining portion of silicon layer 402 that can become tunnel barrier 106 can be doped prior to the epitaxial growth process that can form the second superconducting silicon electrode 104.

[0038] FIG. 7A or FIG. 7B or both show illustrative and non-limiting diagrams of quantum bit device 100 during a sixth stage of manufacturing, according to one or more embodiments described herein. For simplicity, repetitive descriptions of similar elements used in other embodiments described herein are omitted. FIG. 7A shows a cross-sectional view of quantum bit device 100 during the sixth stage of manufacturing, or FIG. 7B shows a top view of quantum bit device 100 during the sixth stage of manufacturing, or both. During the sixth stage of manufacturing, one or more resist masks 202 can be removed from one or more isolation layers 110 via one or more etching processes.

[0039] FIG. 8A or FIG. 8B or both show illustrative and non-limiting diagrams of quantum bit device 100 during a seventh stage of manufacturing, according to one or more embodiments described herein. For simplicity, repetitive descriptions of similar elements used in other embodiments described herein are omitted. FIG. 8A shows a cross-sectional view of quantum bit device 100 during the seventh stage of manufacturing, or FIG. 8B shows a top view of quantum bit device 100 during the seventh stage of manufacturing, or both.

[0040] During the seventh stage of manufacturing, one or more resist masks 202 may be deposited onto one or more isolation layers 110 or the second superconducting silicon electrode 104 or both via one or more deposition processes. As shown in FIG. 8A or FIG. 8B or both, the resist mask 202 may be deposited to leave a portion of one or more exposed isolation layers 110. Further, an exposed portion of one or more isolation layers 110 (e.g., a portion not covered by the resist mask 202) may be aligned with a portion of the first superconducting silicon electrode 102 along the "Y" axis (e.g., as shown in FIG. 8A).

[0041] FIG. 9A or FIG. 9B or both show diagrams of an exemplary and non-limiting qubit device 100 during the eighth stage of manufacturing according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 9A shows a cross-sectional view of the qubit device 100 during the eighth stage of manufacturing, or FIG. 9B shows a top view of the qubit device 100 during the eighth stage of manufacturing, or both.

[0042] During the eighth stage of manufacturing, an exposed portion of one or more isolation layers 110 may be etched away (e.g., via one or more etching processes such as RIE) to form contact holes 902 within the isolation layer 110 that may extend to the first superconducting silicon electrode 102. By etching the contact holes 902, a portion of the first superconducting silicon electrode 102 may be exposed (e.g., by removing at least a portion of the isolation layer 110 that previously covered the first superconducting silicon electrode 102), as shown in FIG. 9A or FIG. 9B or both. After etching the contact holes 902, one or more resist masks 202 may be removed (e.g., via one or more etching processes), or the exposed surface of the qubit device 100 may be cleaned (e.g., using DHF), or both.

[0043] FIG. 10A or FIG. 10B or both show a diagram of an exemplary and non-limiting qubit device 100 during the ninth stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 10A shows a cross-sectional view of the qubit device 100 during the ninth stage of manufacturing, or FIG. 10B shows a top view of the qubit device 100 during the ninth stage of manufacturing, or both.

[0044] During the ninth stage of manufacturing, one or more resist masks 202 are patterned over the second superconducting silicon electrode 104 or the isolation layer 110 or both (e.g., via one or more lift-off processes), facilitating the formation of one or more metal contacts for the qubit device 100 and / or the incorporation of one or more capacitors and / or resonators. As shown in FIG. 10A or FIG. 10B or both, at least a portion of the first superconducting silicon electrode 102 or the second superconducting silicon electrode or both may remain exposed (e.g., uncovered) by one or more resist masks 202 deposited during the ninth stage of manufacturing.

[0045] FIG. 11A or FIG. 11B or both show a diagram of an exemplary and non-limiting qubit device 100 during the tenth stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 11A shows a cross-sectional view of the qubit device 100 during the tenth stage of manufacturing, or FIG. 11B shows a top view of the qubit device 100 during the tenth stage of manufacturing, or both.

[0046] During the tenth stage of manufacturing, the conductive metal material 1102 can be deposited on the exposed surface of the qubit device 100 and / or one or more resist masks 202 (e.g., via one or more deposition processes). After depositing the conductive metal material 1102, the resist mask 202 and the portion of the conductive metal material 1102 disposed on the resist mask 202 are removed (e.g., via one or more etching processes), and the first metal contact 114 and / or the second metal contact 116 (e.g., as shown in FIG. 1A and / or FIG. 1B or both) can be formed. Thereby, the conductive metal material 1102 can be the same metal included in the first metal contact 114 and / or the second metal contact 116 or both. As shown in FIG. 11A, the conductive metal material can be deposited within the contact hole 902 such that the conductive metal material deposits on the first superconducting silicon electrode 102. Those skilled in the art will understand that the thickness of the conductive metal material 1102 (e.g., along the "Y" axis) can vary depending on the function of the qubit device 100 and / or the structural characteristics of the first metal contact 114 and / or the second metal contact 116.

[0047] FIG. 12A and / or FIG. 12B show a diagram of an exemplary and non-limiting qubit device 100 having a separation layer 110 that can include one or more isolation implants according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 12A shows a cross-sectional view of the qubit device 100 including the isolation implant, or FIG. 12B shows a top view of the qubit device 100 including the isolation implant, or both.

[0048] In one or more embodiments, one or more isolation implants may be incorporated into one or more portions of one or more silicon layers 402 or semiconductor substrate 108 or both, and one or more isolation layers 110 may be formed. Exemplary isolation implants may include, but are not limited to, carbon, oxygen, or nitrogen, or combinations thereof. For example, one or more isolation implants may be incorporated into portions of one or more silicon layers 402 or semiconductor substrate 108 or both using one or more plasma immersion processes. In one or more embodiments, one or more isolation implants may be carbon implants, and acetylene or benzene or combinations thereof may be used as a carbon source in one or more plasma immersion processes. One or more isolation implants may suppress the electrical conductivity of one or more isolation layers 110, thereby defining an isolation region 112. According to various embodiments described herein, a qubit device 100 comprising an isolation implant may comprise one or more silicon-based Josephson junctions arranged in a stacked vertical orientation. Further, the tunnel barrier 106 of a qubit device 100 comprising an isolation implant may include a dielectric material or a conventional metal material according to various embodiments described herein.

[0049] FIG. 13 shows a diagram of an exemplary and non-limiting qubit device 100 with one or more isolation implants during a first stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. During the first stage of manufacturing, a cap layer 1302 may be deposited (e.g., via one or more deposition processes) onto a multilayer structure comprising a semiconductor substrate 108, one or more superconducting silicon layers 1304, or a silicon barrier layer 1306, or a combination thereof. Exemplary materials that may be included within the cap layer 1302 may include, but are not limited to, silicon oxide, silicon nitride, silicon, or CVD carbon, or a combination thereof. Those skilled in the art will understand that the thickness of the cap layer 1302 (e.g., along the "Y" axis) may vary. For example, the thickness of the cap layer 1302 (e.g., along the "Y" axis) may be 5 nm or more and 500 nm or less (e.g., from 30 nm to 100 nm).

[0050] As shown in FIG. 13, a silicon barrier layer 1306 may be disposed between one superconducting silicon layer 1304 (e.g., disposed on a semiconductor substrate 108) and another superconducting silicon layer 1304 (e.g., disposed adjacent to the cap layer 1302). In one or more embodiments, the superconducting silicon layer 1304 may proceed to form the first superconducting silicon electrode 102 or the second superconducting silicon electrode 104 or both in subsequent manufacturing steps. Thus, the superconducting silicon layer 1304 may include the same material as the first superconducting silicon electrode 102 or the second superconducting silicon electrode 104 or both, according to various embodiments described herein. Further, in one or more embodiments, a multilayer structure may be formed via one or more laser doping processes, epitaxial growth processes, or etching processes according to one or more embodiments described herein (e.g., according to the features shown in FIGS. 2-7B).

[0051] FIG. 14A or FIG. 14B or both show an exemplary and non-limiting diagram of a qubit device 100 comprising one or more isolation implants during a second stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 14A shows a cross-sectional view of a qubit device 100 comprising one or more isolation implants during a second stage of manufacturing, or FIG. 14B shows a top view of a qubit device 100 comprising one or more isolation implants during a second stage of manufacturing, or both. During a second stage of manufacturing of the qubit device 100 comprising one or more isolation implants, one or more resist layers 202 may be deposited on the cap layer 1302 (e.g., via one or more deposition processes). In one or more embodiments, the one or more resist layers 202 may cover a portion of the cap layer 1302 that is to be aligned with a defined boundary of a silicon-based Josephson junction.

[0052] FIG. 15A or FIG. 15B or both show an exemplary and non-limiting diagram of a qubit device 100 comprising one or more isolation implants during a third stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 15A shows a cross-sectional view of a qubit device 100 comprising one or more isolation implants during a third stage of manufacturing, or FIG. 15B shows a top view of a qubit device 100 comprising one or more isolation implants during a third stage of manufacturing, or both. During a third stage of manufacturing of the qubit device 100 comprising one or more isolation implants, one or more of the exposed portions of the cap layer 1302 (e.g., portions not covered by one or more resist masks 202) may be removed via one or more etching processes (e.g., using diluted hydrofluoric acid (“DHF”) or oxygen plasma or both).

[0053] FIG. 16A or FIG. 16B or both show an exemplary and non - limiting diagram of a qubit device 100 comprising one or more isolation implants during a fourth stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 16A shows a cross - sectional view of a qubit device 100 comprising one or more isolation implants during a fourth stage of manufacturing, or FIG. 16B shows a top - view of a qubit device 100 comprising one or more isolation implants during a fourth stage of manufacturing, or both. During a fourth stage of manufacturing of a qubit device 100 comprising one or more isolation implants, one or more resist layers 202 may be removed via one or more etching processes, exposing the remaining portion of the cap layer 1302.

[0054] FIG. 17A or FIG. 17B or both show an exemplary and non - limiting diagram of a qubit device 100 comprising one or more isolation implants during a fifth stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 17A shows a cross - sectional view of a qubit device 100 comprising one or more isolation implants during a fifth stage of manufacturing, or FIG. 17B shows a top - view of a qubit device 100 comprising one or more isolation implants during a fifth stage of manufacturing, or both.

[0055] During a fifth stage of manufacturing the qubit device 100 comprising one or more isolation implants, a first plasma immersion 1702 may be performed on the cap layer 1302 or on one or both of one or more portions of a multilayer stack (e.g., comprising one or more superconducting silicon layers 1304 or silicon barrier layers 1306 or both) with one or more isolation implant sources. For example, if one or more of the isolation implants are carbon, the first plasma immersion 1702 may be performed on the cap layer 1302 or on one or both of one or more portions of the multilayer stack with one or more carbon sources such as acetylene or benzene or both. As shown in FIG. 17A or FIG. 17B or both, the cap layer 1302 or one or both of one or more portions of the multilayer stack may be saturated with an isolation implant source (e.g., a carbon source such as acetylene or benzene or both).

[0056] In various embodiments, one or more portions of the multilayer stack on which the first plasma immersion 1702 is performed may be the isolation region 112 of the qubit device 100. Thereby, the first plasma immersion 1702 may define one or more boundaries of one or more Josephson junctions included within the qubit device 100. For example, the first plasma immersion 1702 may define a structural boundary of the first superconducting silicon electrode 102 or the tunnel barrier 106 or both (e.g., as shown in FIG. 17A).

[0057] FIG. 18A or FIG. 18B or both show an exemplary and non - limiting diagram of a qubit device 100 comprising one or more isolation implants during a sixth stage of manufacturing according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 18A shows a cross - sectional view of a qubit device 100 comprising one or more isolation implants during a sixth stage of manufacturing, or FIG. 18B shows a top view of a qubit device 100 comprising one or more isolation implants during a sixth stage of manufacturing, or both.

[0058] During a sixth stage of manufacturing of a qubit device 100 comprising one or more isolation implants, a portion of the qubit device 100 saturated with an isolation implant source can be annealed (e.g., laser annealing), and the isolation implant can be implanted (e.g., and / or lattice damage can be reduced). For example, laser annealing can melt the silicon within the irradiation region, and the pulse time can be established based on how much silicon melting is desired. For example, in one or more embodiments, the isolation region 112 can be annealed (e.g., laser annealing), and one or more isolation layers 110 can be formed that can suppress the electrical conductivity within the isolation region 112. For example, in various embodiments, the isolation region 112 is saturated with a carbon source at a fifth stage and laser annealed at a sixth stage, such that one or more carbon isolation implants are implanted into the isolation region 112, and one or more isolation layers 110 can be formed. As shown in FIG. 18A or FIG. 18B or both, the cap layer 1302 can protect the superconducting silicon layer 1304, the tunnel barrier 106, or the first superconducting silicon electrode 102, or a combination thereof, from being implanted with the isolation implant during the sixth stage.

[0059] FIG. 19A or FIG. 19B or both show an exemplary and non-limiting diagram of a qubit device 100 comprising one or more isolation implants during a seventh stage of manufacture according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 19A shows a cross-sectional view of a qubit device 100 comprising one or more isolation implants during a seventh stage of manufacture, or FIG. 19B shows a top view of a qubit device 100 comprising one or more isolation implants during a seventh stage of manufacture, or both.

[0060] During a seventh stage of manufacture of a qubit device 100 comprising one or more isolation implants, one or more resist layers 202 may be deposited (e.g., via one or more deposition processes) on the cap layer 1302. In one or more embodiments, one or more resist layers 202 may cover a portion of the cap layer 1302 that is to be aligned with a defined boundary of the second superconducting silicon electrode 104.

[0061] FIG. 20A or FIG. 20B or both show an exemplary and non - limiting diagram of a qubit device 100 comprising one or more isolation implants during the eighth stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 20A shows a cross - sectional view of a qubit device 100 comprising one or more isolation implants during the eighth stage of manufacturing, or FIG. 20B shows a top - view of a qubit device 100 comprising one or more isolation implants during the eighth stage of manufacturing. During the eighth stage of manufacturing of the qubit device 100 comprising one or more isolation implants, one or more of the exposed portions of the cap layer 1302 (e.g., portions not covered by one or more resist masks 202) can be removed via one or more etching processes (e.g., using DHF). Thereafter, the remaining portions of the one or more resist masks 202 can be removed. Thereby, the remaining portion of the cap layer 1302 can be disposed over (e.g., along the "Y" axis) the location to be defined for the second superconducting silicon electrode 104.

[0062] FIG. 21A or FIG. 21B or both show an exemplary and non - limiting diagram of a qubit device 100 comprising one or more isolation implants during the ninth stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 21A shows a cross - sectional view of a qubit device 100 comprising one or more isolation implants during the ninth stage of manufacturing, or FIG. 21B shows a top - view of a qubit device 100 comprising one or more isolation implants during the ninth stage of manufacturing.

[0063] During the ninth stage of manufacturing the qubit device 100 with one or more isolation implants, a second plasma immersion 2102 may be performed on one or more portions of the cap layer 1302 or the remaining superconducting silicon layer 1304 or both, with one or more isolation implant sources. For example, if one or more of the isolation implants are carbon, the second plasma immersion 2102 may be performed on one or more portions of the cap layer 1302 or the superconducting silicon layer 1304 or both, with one or more carbon sources such as acetylene or benzene or both. As shown in FIG. 21A or FIG. 21B or both, one or more portions of the cap layer 1302 or the superconducting silicon layer 1304 or both may be saturated with an isolation implant source (e.g., a carbon source such as acetylene or benzene or both). In various embodiments, one or more portions of the superconducting silicon layer 1304 on which the second plasma immersion 2102 is performed may extend the isolation region 112 of the qubit device 100 (e.g., indicated by the bold dashed line in FIG. 21A). Thereby, the second plasma immersion 2102 may define one or more boundaries of the second superconducting silicon electrode 104 (e.g., as shown in FIG. 21A or FIG. 21B or both).

[0064] FIG. 22A or FIG. 22B or both show diagrams of an exemplary and non-limiting qubit device 100 with one or more isolation implants during the tenth stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 22A shows a cross-sectional view of a qubit device 100 with one or more isolation implants during the tenth stage of manufacturing, or FIG. 22B shows a top view of a qubit device 100 with one or more isolation implants during the tenth stage of manufacturing, or both may be the case.

[0065] During a tenth stage of manufacturing a qubit device 100 comprising one or more isolation implants, a portion of the qubit device 100 saturated with an isolation implant source is annealed (e.g., laser annealed), and the isolation implant can be implanted. For example, in one or more embodiments, the isolation region 112 is annealed (e.g., laser annealed), and one or more isolation layers 110 can be formed that can suppress the electrical conductivity within the isolation region 112. For example, in various embodiments, the isolation region 112 is saturated with a carbon source at a ninth stage and laser annealed at a tenth stage, such that one or more carbon isolation implants are implanted within the isolation region 112 and one or more isolation layers 110 can be extended. As shown in FIG. 22A or FIG. 22B or both, the cap layer 1302 can protect the second superconducting silicon electrode 104 from being implanted with an isolation implant during the tenth stage. Further, in one or more embodiments, the tunnel barrier 106 or the first superconducting silicon electrode 102 or both can remain unimplanted with an isolation implant during the tenth stage, controlling the depth of saturation of the isolation implant source (e.g., along the "Y" axis) during the ninth stage of manufacturing, and thereby the depth of isolation implant incorporation (e.g., along the "Y" axis) during the tenth stage of manufacturing.

[0066] FIG. 23A or FIG. 23B or both show diagrams of an exemplary and non-limiting qubit device 100 during an eleventh stage of manufacturing, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 23A shows a cross-sectional view of the qubit device 100 during the eleventh stage of manufacturing, or FIG. 23B shows a top view of the qubit device 100 during the eleventh stage of manufacturing, or both.

[0067] During the eleventh stage of manufacturing, one or more resist masks 202 may be deposited on one or more of the isolation layers 110 and / or the cap layer 1302 via one or more deposition processes. As shown in FIG. 23A and / or FIG. 23B, the resist mask 202 may be deposited to leave a portion of one or more of the exposed isolation layers 110. Further, an exposed portion of one or more of the isolation layers 110 (e.g., a portion not covered by the resist mask 202) may be aligned with a portion of the first superconducting silicon electrode 102 along the "Y" axis (as shown, for example, in FIG. 23A).

[0068] FIG. 24A and / or FIG. 24B show a diagram of an exemplary and non-limiting qubit device 100 during the twelfth stage of manufacturing according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 24A shows a cross-sectional view of the qubit device 100 during the twelfth stage of manufacturing, or FIG. 24B shows a top view of the qubit device 100 during the twelfth stage of manufacturing, or both.

[0069] During the twelfth stage of manufacturing, an exposed portion of one or more of the isolation layers 110 may be etched away (e.g., via one or more etching processes such as RIE) to form contact holes 902 within the isolation layer 110 that may extend to the first superconducting silicon electrode 102. By etching the contact holes 902, a portion of the first superconducting silicon electrode 102 may be exposed (e.g., by removing at least a portion of the isolation layer 110 and / or the tunnel barrier 106 that previously covered the first superconducting silicon electrode 102). After etching the contact holes 902, one or more resist masks 202 may be removed (e.g., via one or more etching processes), or the exposed surface of the qubit device 100 may be cleaned (e.g., using DHF), or both.

[0070] FIG. 25A or FIG. 25B or both show an exemplary and non - limiting diagram of the qubit device 100 during the 13th stage of manufacturing according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 25A shows a cross - sectional view of the qubit device 100 during the 13th stage of manufacturing, or FIG. 25B shows a top - view of the qubit device 100 during the 13th stage of manufacturing, or both. During the 13th stage of manufacturing, the cap layer 1302 may be etched away (e.g., via one or more etching processes such as RIE) to expose the second superconducting silicon electrode 104. Further, the exposed surface of the qubit device 100 may be cleaned (e.g., using DHF).

[0071] FIG. 26A or FIG. 26B or both show an exemplary and non - limiting diagram of the qubit device 100 during the 14th stage of manufacturing according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 26A shows a cross - sectional view of the qubit device 100 during the 14th stage of manufacturing, or FIG. 26B shows a top - view of the qubit device 100 during the 14th stage of manufacturing, or both.

[0072] During the fourteenth stage of fabrication, one or more resist masks 202 are patterned over (e.g., via one or more lift-off processes) the second superconducting silicon electrode 104 or the isolation layer 110 or both, facilitating the formation of one or more metal contacts for the qubit device 100 and / or the incorporation of one or more capacitors and / or resonators. As shown in FIG. 26A or FIG. 26B or both, at least a portion of the first superconducting silicon electrode 102 or the second superconducting silicon electrode or both may remain exposed (e.g., uncovered) by one or more resist masks 202.

[0073] FIG. 27A or FIG. 27B or both show diagrams of an exemplary and non-limiting qubit device 100 during the fifteenth stage of fabrication according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 27A shows a cross-sectional view of the qubit device 100 during the fifteenth stage of fabrication, or FIG. 27B shows a top view of the qubit device 100 during the fifteenth stage of fabrication, or both.

[0074] During the fifteenth stage of manufacturing, the conductive metal material 1102 can be deposited on the exposed surface of the qubit device 100 and / or one or more resist masks 202 (e.g., via one or more deposition processes). After depositing the conductive metal material 1102, the resist mask 202 and the portion of the conductive metal material 1102 disposed on the resist mask 202 are removed (e.g., via one or more etching processes), and the first metal contact 114 and / or the second metal contact 116 (e.g., as shown in FIG. 12A and / or FIG. 12B or both) can be formed. Thereby, the conductive metal material 1102 can be the same metal included in the first metal contact 114 and / or the second metal contact 116. As shown in FIG. 27A, the conductive metal material can be deposited within the contact hole 902 such that the conductive metal material is deposited on the first superconducting silicon electrode 102. Those skilled in the art will understand that the thickness of the conductive metal material 1102 (e.g., along the "Y" axis) can vary depending on the function of the qubit device 100 and / or the structural characteristics of the first metal contact 114 and / or the second metal contact 116.

[0075] FIG. 28 shows a flowchart of an exemplary and non-limiting method 2800 that can facilitate the manufacture of one or more qubit devices 100 comprising one or more silicon-based Josephson junctions, according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted.

[0076] At 2802, method 2800 may include doping a portion of semiconductor substrate 108 to form a first superconducting electrode (e.g., first superconducting silicon electrode 102). For example, the doping at 2802 may be performed according to at least a second stage of the fabrication shown in FIG. 3. For example, the first superconducting electrode may be the first superconducting silicon electrode 102, or the doping may include one or more laser-doping processes according to one or more embodiments described herein, or both.

[0077] At 2804, method 2800 may include depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form a tunnel barrier 106. For example, the deposition at 2804 may be performed according to at least a third stage of the fabrication shown in FIG. 4. For example, in one or more embodiments, the deposition at 2804 may grow a layer of native silicon that can act as a dielectric tunnel barrier 106 of a silicon-based Josephson junction during operation of qubit device 100 at a temperature near zero. In another example, the deposition at 2804 may further include doping one or more portions of the deposited silicon layer to form a normal-metal tunnel barrier 106 according to one or more embodiments described herein.

[0078] At 2806, method 2800 may include doping one or more portions of tunnel barrier 106 to form a second superconducting electrode (e.g., second superconducting silicon electrode 104) and forming a Josephson junction. For example, the doping at 2806 may be performed according to at least the fifth stage of the fabrication shown in at least FIG. 6A or FIG. 6B or both. For example, the second superconducting electrode may be the second superconducting silicon electrode 104, or the doping may include one or more laser doping processes according to one or more embodiments described herein, or both. In various embodiments, the Josephson junction formed by method 2800 may be a silicon-based Josephson junction comprising superconducting silicon electrodes. Further, the superconducting silicon electrodes may be stacked in a vertical orientation. Further, in one or more embodiments, tunnel barrier 106 may be a dielectric tunnel barrier comprising intrinsic silicon.

[0079] FIG. 29 shows a flow diagram of an exemplary and non-limiting method 2900 that may facilitate the fabrication of one or more qubit devices 100 comprising one or more silicon-based Josephson junctions electrically separated via one or more separation layers 110 that may include one or more isolation implants according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted.

[0080] At 2902, method 2900 may include doping a portion of semiconductor substrate 108 to form a first superconducting electrode (e.g., first superconducting silicon electrode 102). For example, the doping at 2902 may be performed according to at least the second stage of the fabrication shown in FIG. 3. For example, the first superconducting electrode may be the first superconducting silicon electrode 102, or the doping may include one or more laser doping processes according to one or more embodiments described herein, or both.

[0081] At 2904, method 2900 may include depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form the tunnel barrier 106. For example, the deposition at 2904 may be performed according to at least the third stage of the fabrication shown in FIG. 4. For example, in one or more embodiments, the deposition at 2904 may grow a layer of intrinsic silicon that can act as the dielectric tunnel barrier 106 of the silicon-based Josephson junction during operation of the qubit device 100 at a temperature near zero. In another example, the deposition at 2904 may further include doping one or more portions of the deposited silicon layer to form a normal metal tunnel barrier 106 according to one or more embodiments described herein.

[0082] At 2906, method 2900 may include doping one or more portions of the tunnel barrier 106 to form a second superconducting electrode (e.g., the second superconducting silicon electrode 104) and forming a Josephson junction. For example, the doping at 2806 may be performed according to at least the fifth stage of the fabrication shown in FIG. 6A or FIG. 6B or both. For example, the second superconducting electrode may be the second superconducting silicon electrode 104, or the doping may include one or more laser doping processes according to one or more embodiments described herein, or both. In various embodiments, the Josephson junction formed by method 2906 may be a multilayer stack structure such as the multilayer stack shown in FIG. 13, and one or more subsequent fabrication steps may further define one or more structural features of the Josephson junction, or electrically isolate the Josephson junction via incorporation of isolation implants, or both.

[0083] At 2908, method 2900 can include forming a separation region 112 from a Josephson junction through plasma immersion of one or more discrete implants into portions of a first superconducting electrode (e.g., first superconducting silicon electrode 102), a tunnel barrier 106, and a second superconducting electrode (e.g., second superconducting silicon electrode 104). For example, formation of the separation region at 2908 can be carried out according to the fifth through tenth stages of fabrication shown in FIGS. 17A through 22B. For example, formation of the separation region at 2908 can include one or more plasma immersion processes and / or annealing processes or both according to one or more embodiments described herein.

[0084] At 2910, method 2900 can include forming a contact hole 902 that can extend into a first superconducting electrode (e.g., first superconducting silicon electrode 102) within the separation region 112. For example, forming the contact hole 902 can be carried out according to the eleventh through twelfth stages of fabrication shown in FIGS. 23A through 24B.

[0085] At 2912, method 2900 can include depositing a first metal layer (e.g., conductive metal material 1102) within the contact hole 902 to form a first metal contact 114 operably coupled to a first superconducting electrode (e.g., first superconducting silicon electrode 102). For example, formation of the first metal contact 114 at 2912 can be carried out according to the fourteenth stage or the fifteenth stage or both of fabrication shown in FIGS. 26A - 27B or FIGS. 12A - 12B or both.

[0086] At 2914, method 2900 may include depositing a second metal layer (e.g., conductive metal material 1102) on a second superconducting electrode (e.g., second superconducting silicon electrode 104) to form a second metal contact 116 operably coupled to the second superconducting electrode (e.g., second superconducting silicon electrode 104). For example, the formation of the first metal contact 114 at 2914 may be performed according to the 14th or 15th or both of the manufacturing steps shown in FIGS. 26A - 27B or FIGS. 12A - 12B or both.

[0087] Furthermore, the term "or" shall mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X utilizes A or B" shall be taken to mean any of the natural inclusive permutations. That is, "X utilizes A or B" is satisfied under any of the above examples if X utilizes A, X utilizes B, or X utilizes both A and B. Additionally, the articles "a" and "an" used in this specification and the accompanying drawings shall generally be construed to mean "one or more" unless otherwise specified or it is clear from the context that the singular form is intended. In this specification, the term "example" or "exemplary" or both are used to mean serving as an example, instance, or illustration. To avoid doubt, the subject matter disclosed in this specification is not limited by such examples. Further, any aspect or design described in this specification as "example" or "exemplary" or both is not necessarily construed as more preferred or advantageous than other aspects or designs and does not mean excluding equivalent exemplary structures and techniques known to those skilled in the art.

[0088] Of course, in order to describe the present disclosure, it is not impossible to describe every conceivable combination of components, products, or methods, but those skilled in the art will understand that many other combinations and permutations of the present disclosure are possible. Further, to the extent that terms such as "comprising," "having," "owning," etc. are used in the detailed description, claims, appendices, and drawings, such terms shall be construed as being inclusive in the same manner as "comprising" when utilized as a transitional term in a claim. For the sake of illustration, descriptions of various embodiments have been presented, but the descriptions shall not be construed as being exhaustive or limited to the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected in order to best describe the principles of the embodiments, actual applications or technological improvements over the technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. Further, the present disclosure also discloses the following inventions. <Appendix 1> A Josephson junction including a tunnel barrier disposed between two vertically stacked superconducting silicon electrodes An apparatus comprising the same. <Appendix 2> The apparatus according to Appendix 1, wherein the two vertically stacked superconducting silicon electrodes include silicon doped with at least one dopant selected from the group consisting of boron, gallium, and germanium. <Appendix 3> The apparatus according to Appendix 2, wherein the at least one dopant is boron, and each of the two vertically stacked superconducting silicon electrodes includes boron in an amount greater than 4 atomic percent and not more than 11 atomic percent. <Appendix 4> A first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, A second metal contact operably coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, A separation layer, wherein the separation layer is disposed on the tunnel barrier so as to electrically separate the first metal contact from the second metal contact, and the separation layer includes carbon implantation in silicon, and The device according to any one of Appendices 1 to 3, further comprising <Appendix 5> A first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, and A second metal contact operably coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, and A separation layer, wherein the separation layer is disposed on the tunnel barrier so as to electrically separate the first metal contact from the second metal contact, and the separation layer includes intrinsic silicon, and The device according to any one of Appendices 1 to 4, further comprising <Appendix 6> The device according to any one of Appendices 1 to 5, wherein the tunnel barrier is doped with at least one dopant selected from the group consisting of phosphorus and arsenic. <Appendix 7> The device according to any one of Appendices 1 to 6, wherein the tunnel barrier includes intrinsic crystalline silicon. <Appendix 8> A Josephson junction including a dielectric tunnel barrier disposed between two superconducting silicon electrodes The device comprising <Appendix 9> The device according to Appendix 8, wherein the two superconducting silicon electrodes include silicon doped with at least one dopant selected from the group consisting of boron, germanium, and gallium. <Appendix 10> The device according to Appendix 9, wherein the at least one dopant is boron, and the two superconducting silicon electrodes each include boron greater than 4 atomic percent and boron less than or equal to 11 atomic percent. <Appendix 11> A first metal contact operably coupled to a first superconducting silicon electrode from the two superconducting silicon electrodes, A second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes, A separation layer, wherein the separation layer is disposed on the dielectric tunnel barrier so as to electrically separate the first metal contact from the second metal contact, and the separation layer includes carbon implantation in silicon, The device according to any one of Appendices 8 to 10, further comprising <Appendix 12> A first metal contact operably coupled to a first superconducting silicon electrode from the two superconducting silicon electrodes, A second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes, A separation layer, wherein the separation layer is disposed on the dielectric tunnel barrier so as to electrically separate the first metal contact from the second metal contact, and the separation layer includes intrinsic silicon, The device according to any one of Appendices 8 to 11, further comprising <Appendix 13> The device according to any one of Appendices 8 to 12, wherein the dielectric tunnel barrier includes intrinsic crystalline silicon. <Appendix 14> The device according to any one of Appendices 8 to 13, wherein the two superconducting silicon electrodes and the dielectric tunnel barrier are vertically stacked on a dielectric substrate. <Appendix 15> Doping a part of a silicon substrate to form a first superconducting electrode, Depositing a silicon layer on the first superconducting electrode through an epitaxial growth process to form a tunnel barrier, Doping a part of the tunnel barrier to form a second superconducting electrode and form a Josephson junction A method including <Appendix 16> The method according to appended claim 15, wherein the first dopant added by doping a part of the silicon substrate and the second dopant added by doping a part of the silicon layer are at least one member selected from the group consisting of boron, gallium, and germanium. <Appended claim 17> Forming a separation region from the Josephson junction through plasma immersion of the separation implant into parts of the first superconducting electrode, the tunnel barrier, and the second superconducting electrode The method according to appended claim 15 or 16, further comprising <Appended claim 18> Forming a contact hole extending to the first superconducting electrode within the separation region Depositing a first metal layer within the contact hole to form a first metal contact operably coupled to the first superconducting electrode Depositing a second metal layer on the second superconducting electrode to form a second metal contact operably coupled to the second superconducting electrode The method according to appended claim 17, further comprising <Appended claim 19> The method according to any one of appended claims 15 to 18, wherein the undoped portion of the silicon substrate and the undoped portion of the silicon layer define a separation region adjacent to the Josephson junction. <Appended claim 20> Forming a contact hole extending to the first superconducting electrode within the separation region Depositing a first metal layer within the contact hole to form a first metal contact operably coupled to the first superconducting electrode Depositing a second metal layer on the second superconducting electrode to form a second metal contact operably coupled to the second superconducting electrode The method according to appended claim 19, further comprising

Claims

1. Doping a part of a silicon substrate to form a first superconducting electrode; Depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form a tunnel barrier; Doping a part of the tunnel barrier by a laser doping process to form a second superconducting electrode and form a Josephson junction A method comprising the steps of.

2. The method according to claim 1, wherein the first dopant added by doping the part of the silicon substrate and the second dopant added by doping the part of the silicon layer are at least one member selected from the group consisting of boron, gallium, and germanium.

3. Further comprising forming a separation region from the Josephson junction through plasma immersion of a separation implant into portions of the first superconducting electrode, the tunnel barrier, and the second superconducting electrode The method according to claim 1 or 2.

4. Forming the separation region comprises: Forming a cap layer on a stack of the first superconducting electrode, the tunnel barrier, and the second superconducting electrode; Implanting a separation implant into portions of the first superconducting electrode, the tunnel barrier, and the second superconducting electrode exposed from the cap layer; Leaving a part of the cap layer aligned with a boundary to be defined for the second superconducting electrode and etching away the cap layer; Implanting a separation implant into a portion of the second superconducting electrode exposed from the part of the cap layer; Etching away the remaining part of the cap layer The method according to claim 3, comprising the steps of.

5. Forming a contact hole extending into the first superconducting electrode within the separation region; Depositing a first metal layer within the contact hole to form a first metal contact operably coupled to the first superconducting electrode; Depositing a second metal layer on the second superconducting electrode to form a second metal contact operably coupled to the second superconducting electrode The method according to claim 3, further comprising the steps of.

6. The method according to any one of claims 1 to 5, wherein undoped portions of the silicon substrate and the silicon layer define a separation region adjacent to the Josephson junction.

7. Forming a contact hole extending to the first superconducting electrode within the isolation region; Depositing a first metal layer within the contact hole to form a first metal contact operably coupled to the first superconducting electrode; Depositing a second metal layer on the second superconducting electrode to form a second metal contact operably coupled to the second superconducting electrode The method according to claim 6, further comprising.

8. The method according to any one of claims 1 to 7, wherein a first dopant added by doping a part of the silicon substrate and a second dopant added by doping a part of the silicon layer contain boron in an amount exceeding 4 atomic percent and not exceeding 11 atomic percent.

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