Semiconductor device

Abstract

To provide a semiconductor device having stable electric characteristic by the use of an oxide semiconductor film, in which the impurity element concentration in the oxide semiconductor film near a gate insulating film is reduced and the crystallinity of the oxide semiconductor film near the gate insulating film is improved.SOLUTION: In a semiconductor device, a transistor 150 comprises: a base insulation film 104; an oxide semiconductor film 106 formed on the base insulation film; a source electrode 108a and a drain electrode 108b formed on the oxide semiconductor film; a gate insulation film 110 formed on the oxide semiconductor film, the source electrode, and the drain electrode and including a silicon oxide; and a gate electrode 112 in contact with the gate insulation film and provided in a region overlapping at least the oxide semiconductor film. The oxide semiconductor film includes, from an interface with the gate insulation film toward the oxide semiconductor film, a region where a silicon concentration is less than or equal to 1.0 atom%, and includes at least a crystal part in the region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] A technique for constructing transistors using a semiconductor thin film formed on a substrate with an insulating surface. This technology is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). For example, semiconductors that can be used in transistors are widely used in electronic devices such as Silicon-based semiconductor materials are widely known as thin films, but other materials include oxide semiconductors. The body is attracting attention.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide containing zinc (Zn) has been disclosed (see Patent Document 1). (see).

[0005] Transistors using oxide semiconductors have higher performance than transistors using amorphous silicon. The transistor using this oxide semiconductor has higher on-state characteristics (such as on-state current) than the conventional transistor. In order to apply oxide semiconductors to high-performance devices, further improvements in their properties are required. The technology for crystallizing the oxide is being developed (see Patent Document 2). A technique for crystallizing a semiconductor by heat treatment has been disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-311342 [Summary of the Invention] [Problems to be Solved by the Invention]

[0007] In a transistor using an oxide semiconductor film, when a transistor having a top gate structure is formed, a gate insulating film is formed on the oxide semiconductor film. When forming the gate insulating film, the constituent elements of the gate insulating film may be mixed into the oxide semiconductor film that is the surface to be formed.

[0008] For example, after forming the oxide semiconductor film, when silicon oxide (SiO x = 2 or more) is formed as the gate insulating film using a sputtering method, silicon, which x、 is a constituent element of the silicon oxide, is implanted into the oxide semiconductor film together with the rare gas element (e.g., argon, etc.) used during sputtering, breaks the In-O bond in the oxide semiconductor film, and is taken in as an impurity element into the oxide semiconductor film. In particular, there is a risk that impurity elements will be taken in at a high concentration near the interface between the oxide semiconductor film and the gate insulating film. Since a channel region is formed near the interface between the oxide semiconductor film and the gate insulating film, if any impurity element such as silicon is taken in, the oxide semiconductor film will become highly resistive. As a result, the on current, which is one of the electrical characteristics of the transistor, will decrease. Thus,

[0009]

[0009] Further, when the oxide semiconductor film has a structure including a crystalline portion, if the constituent elements of the gate insulating film mix into the oxide semiconductor film, the bonds in the crystalline portion of the oxide semiconductor film are broken, and many amorphous regions are formed in the oxide semiconductor film near the gate insulating film. In view of such problems, one object is to reduce the concentration of impurity elements contained in the oxide semiconductor film near the gate insulating film. Another object is to improve the crystallinity of the oxide semiconductor film near the gate insulating film. Further, one object is to provide a semiconductor device having stable electrical characteristics by using the oxide semiconductor film.

[0010] [Means for Solving the Problems]

[0011] One aspect of the present invention disclosed herein includes a base insulating film, an oxide semiconductor film formed on the base insulating film, a source electrode and a drain electrode formed on the oxide semiconductor film, a gate insulating film containing silicon oxide formed on the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode provided in a region in contact with the gate insulating film and overlapping at least the oxide semiconductor film. The oxide semiconductor film has a region in which the silicon concentration is distributed at a concentration of 1.0 atomic % or less from the interface with the gate insulating film toward the oxide semiconductor film, and is a semiconductor device including at least a crystalline portion in the region.

[0012] Another aspect of the present invention disclosed herein includes a base insulating film, an oxide semiconductor film formed on the base insulating film, a gate insulating film containing silicon oxide formed on the oxide semiconductor film, and a gate electrode provided in a region in contact with the gate insulating film and overlapping at least the oxide semiconductor film. , an interlayer insulating film formed on the gate insulating film and the gate electrode, and formed on the interlayer insulating film , having at least a source electrode and a drain electrode that are electrically connected to the oxide semiconductor film The oxide semiconductor film has a region where the silicon concentration is distributed at a concentration of 1.0 atomic % or less from the interface with the gate insulating film toward the oxide semiconductor film, and at least within the region, a semi- conductor device including a crystal part.

[0013] In each of the above configurations, the region is preferably formed to be in contact with the gate insulating film and have a thickness of 5 nm or less. Further, the oxide semiconductor film preferably contains a crystal part also outside the region, and the crystal part preferably has its c-axis aligned in a direction perpendicular to the interface between the underlying insulating film and the oxide semiconductor film.

[0014] In each of the above configurations, the region preferably has a silicon concentration of 0.1 atomic % or less. Further, the region preferably has a carbon concentration of 1.0×10 20 atoms / cm 3 or less

[0015] By setting the oxide semiconductor film near the gate insulating film to the above-described silicon concentration or carbon concentration, it is possible to suppress the increase in the resistance of the oxide semiconductor film and improve the crystallinity. As a result, a semiconductor device having stable electrical characteristics can be obtained.

Advantages of the Invention

[0016] According to one aspect of the present invention disclosed, the concentration of impurity elements contained in the oxide semiconductor film near the gate insulating film can be reduced. Further, the crystallinity of the oxide semiconductor film near the gate insulating film can be improved. Also, a semiconductor device having stable electrical characteristics is provided. ​​​​​​​​​ It is possible to

Brief Description of the Drawings

[0017]

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Modes for Carrying Out the Invention

[0018] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that it can be variously modified in form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. 。 。

[0019] Note that the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. for the sake of simplicity of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. 。 。

[0020] In addition, the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components and are noted that they are not numerically limiting. 。

[0021] In addition, the terms "upper" and "lower" in this specification and the like do not limit that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", those including other components between the gate insulating layer and the gate electrode are not excluded. 。 。 。

[0022] Also, the terms "electrode" and "wiring" in this specification and the like do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. 。 。 。

[0023] Also, the functions of "source" and "drain" may be different when transistors of different polarities are employed. Or, it may be reversed when the direction of the current changes during circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" may be used interchangeably.

[0024] In addition, in this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

[0025] (Embodiment 1) In this embodiment, an example of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 and 2.

[0026] <Example Configuration of Semiconductor Device> FIGS. 1(A) and 1(B) show a plan view and a cross-sectional view of a transistor having a top gate structure as an example of a semiconductor device. FIG. 1(A) is a plan view, and FIG. 1(B) corresponds to a cross-sectional view taken along the broken line X1 - Y1 in FIG. 1( A). Note that in FIG. 1(A), some of the components of the transistor 150 (for example, the gate insulating film 11 0, etc.) are omitted to avoid complexity.

[0027] The transistor 150 shown in FIGS. 1(A) and 1(B) includes an underlying insulating film 104 on the substrate 102, and a region 106a and a region 106b formed on the underlying insulating film 104, and an acid ​​​​​​The oxide semiconductor film 106, the underlying insulating film 104, and the source electrode 108a and drain electrode 108b formed on the oxide semiconductor film 106, the oxide semiconductor film 106, the source electrode 1 08a, and the gate insulating film 110 formed on the drain electrode 108b, and the gate electrode 112 provided in a region in contact with the gate insulating film 110 and overlapping at least the oxide semiconductor film 106. Further, an interlayer insulating film 114 is formed on the transistor 150. Also, the thickness of the oxide semiconductor film 106 is greater than 5 nm and 200 nm or less, preferably 10 nm or more and 30 nm or less. Further, the oxide semiconductor film 106 preferably has a crystalline structure such as single crystal or

[0028] microcrystal. Also, as shown in FIG. 1(B), the oxide semiconductor film 106 preferably has a taper of 20° to 50° at the end. When the end of the oxide semiconductor film 106 is vertical, oxygen easily escapes from the end of the oxide semiconductor film 106 and oxygen deficiency easily occurs. However, by providing a taper at the end of the oxide semiconductor film

[0029] 106, the occurrence of oxygen deficiency can be suppressed, and the generation of leakage current of the transistor 150 can be reduced. Also, in the present embodiment, the oxide semiconductor film 106 is preferably a CAAC-OS (C Axially Aligned Crystalline Oxide Semiconductor) film. The CAAC-OS film will be described in detail in the manufacturing method of the transistor 150 described later. Also, the gate insulating film 110 contains an oxide containing silicon having sufficient breakdown voltage and insulation properties.

[0030] r) film. r) film.

[0031] ​It is preferable to use. When the gate insulating film 110 has a single-layer structure, for example, an insulating film such as oxidized silicon can be used.

[0032] Alternatively, the gate insulating film 110 may have a stacked structure. When the gate insulating film 110 has a stacked structure , for example, gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, yttrium oxide, lanthanum oxide or silicon oxynitride can be stacked on an oxide containing silicon. Also, on an oxide containing silicon, hafnium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-added hafnium silicate (HfSiO x N y (x>0, y>0)), hafnium al uminate (HfAl x O y (x>0, y>0)), etc. high-k materials can be stacked. That's fine.

[0033] Note that by using an oxide containing silicon as the gate insulating film 110, a part of oxygen can be desorbed by heating the insulating film, so oxygen can be supplied to the oxide semiconductor film 10 6, and oxygen vacancies in the oxide semiconductor film 106 can be filled. In particular, it is preferable that at least an amount of oxygen exceeding the stoichiometric composition is present in the gate insulating film 110 . For example, it is preferable to use a silicon oxide film represented by SiO 2+α (where α>0) as the gate insulating film 110. By using such a silicon oxide film as the gate insulating film 1 10, oxygen can be supplied to the oxide semiconductor film 106, and the oxidation can be achieved. The transistor characteristics of the transistor 150 using the oxide semiconductor film 106 can be improved. Yes.

[0034] However, when a silicon oxide film is used as the gate insulating film 110, silicon or the like, which is a constituent element of the gate insulating film 110, may be incorporated into the oxide semiconductor film 106 as an impurity. When silicon or the like, which is a constituent element of the gate insulating film 110, is incorporated into the oxide semiconductor film 106 as an impurity, it becomes a factor that affects the characteristics of the transistor. become.

[0035] Also, when the oxide semiconductor film 106 is a CAAC-OS film, silicon or the like, which is a constituent element of the gate insulating film 110, is mixed into the oxide semiconductor film 106, and the bonds of the crystal parts of the oxide semiconductor film 106 are broken. In the oxide semiconductor film 106 near the gate insulating film 110, an amorphous region is formed. In particular, impurities such as silicon are likely to be incorporated in the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110. Since the channel region of the transistor 150 is formed near the interface between the oxide semiconductor film 106 and the gate insulating film 110, if impurities such as silicon are incorporated near the interface between the oxide semiconductor film 106 and the gate insulating film 110, the electrical characteristics of the transistor 150 may vary. In the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110, an amorphous region is formed. A large number of regions are formed.

[0036] In particular, impurities such as silicon are likely to be incorporated in the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110. Since the channel region of the transistor 150 is formed near the interface between the oxide semiconductor film 106 and the gate insulating film 110, if impurities such as silicon are incorporated near the interface between the oxide semiconductor film 106 and the gate insulating film 110, the electrical characteristics of the transistor 150 may vary. In the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110, a channel region of the transistor 150 is formed. Therefore, when impurities such as silicon are incorporated near the interface between the oxide semiconductor film 106 and the gate insulating film 110, the electrical characteristics of the transistor 150 may vary. When impurities such as silicon are incorporated near the interface between the oxide semiconductor film 106 and the gate insulating film 110, the electrical characteristics of the transistor 150 may vary. There is a risk of causing fluctuations.

[0037] Here, when SiO2, which is silicon oxide, is added as an impurity to the oxide semiconductor film 106, the results of an investigation by classical molecular dynamics calculation on what structural changes occur will be described with reference to FIGS. 12 to 14. In order to perform the above calculation, classical molecular dynamics The results will be described with reference to FIGS. 12 to 14. For the above calculation, classical molecular As the sub-dynamics calculation software, SCIGRESS ME manufactured by Fujitsu Limited was used. In the classical molecular dynamics method, an empirical potential that characterizes the interatomic interaction is defined to evaluate the force acting on each atom. By numerically solving Newton's equations of motion, the motion (time evolution) of each atom can be deterministically traced.

[0038] The calculation model and calculation conditions are described below. In this calculation, the Born-May er-Huggins potential was used.

[0039] As the calculation model, a single crystal structure of InGaZnO4 consisting of 1680 atoms (see Fig. 12( A)) and a structure in which 20 atoms each of In, Ga, and Zn in InGaZnO4 consisting of 1680 atoms are replaced with silicon (Si) atoms (see Fig. 12(B)) were fabricated. In the silicon (Si) substitution model shown in Fig. 12(B), silicon (Si) is 3.5 7 atom% (2.34 wt%). Also, the density of the single crystal model shown in Fig. 12(A) is 6.36 g / cm and the density of the silicon (Si) substitution model shown in Fig. 12(B) 3 is 6.08 g / cm and 3 is 6.08 g / cm³.

[0040] For the calculation models shown in Fig. 12(A) and Fig. 12(B), at 1727 °C which is lower than the melting point of the single crystal of InGaZnO4 (estimated by classical molecular dynamics calculation to be about 2000 °C), at a constant pressure (1 atom), classical molecular dynamics calculations were performed for 150 psec (time step width 0.2 fsec × 750,000 steps) to perform structural relaxation. Also, the radial distribution function g(r) was obtained for these two structures. Note that the radial distribution function g(r) is the distance from a certain atom to another atom. ​It is a function that represents the probability density of the presence of other atoms at a position separated from the atom by a distance r. Atom As the correlation between the atoms disappears, g(r) approaches 1.

[0041] By performing classical molecular dynamics calculations for 150 psec on the above two calculation models The final structures obtained are shown in Fig. 13(A) and Fig. 13(B), respectively. Also, for each The radial distribution function g(r) in the structure is shown in Fig. 14.

[0042] The single crystal model shown in Fig. 13(A) is stable and maintains the crystal structure even in the final structure However, the silicon (Si) substitution model shown in Fig. 13(B) is unstable, and it can be confirmed that the crystal structure collapses over time and changes to an amorphous structure. Also, in Fig. 14 when comparing the radial distribution function g(r) of each structural model, in the single crystal model, there are peaks even at long distances which indicates the presence of long-range order. On the other hand, in the silicon (Si) substitution model it can be seen that the peak disappears near 0.6 nm, indicating the absence of long-range order.

[0043] These calculation results suggest that the inclusion of silicon (Si) in InGaZnO4 makes it easier for InGaZnO4 to become amorphous. Also, even when high-temperature heating is performed with silicon (Si) included in In GaZnO4, it was confirmed that InGaZnO 4 does not crystallize. 4 does not crystallize.

[0044] Next, regarding what structural changes occur when carbon atoms (C) are added to the oxide semiconductor film 106, the results of investigation by classical molecular dynamics calculations will be explained using Fig. 12(A), Fig 15, and Fig. 16. For performing the above calculations, a classical molecular dynamics calculation software was used. As software, SCIGRESS ME manufactured by Fujitsu Limited was used.

[0045] The calculation model and calculation conditions are described below. In this calculation, the Born-May er-Huggins potential was used. Also, the Lennard-Jones potential was used for the interatomic interaction with carbon atoms (C).

[0046] As the calculation model, a single crystal structure of InGaZnO4 consisting of 1680 atoms (see Fig. 12( A)), and a structure in which 20 atoms each of In, Ga, and Zn in InGaZnO4 consisting of 1680 atoms are replaced with carbon atoms (C), and 80 oxygen (O) atoms are replaced with carbon atoms (C) (see Fig. 15(A)) were fabricated. In the carbon (C) substitution model shown in Fig. 15(A), the carbon atoms (C) are 8.33 atom%. Also, the density of the single crystal model shown in Fig. 12(A) is 6.36 g / cm (see Fig. 15(A)), and the density of the carbon (C) substitution model shown in Fig. 15(A) is 5.89 g / cm (see Fig. 15(A)). The density of the single crystal model shown in Fig. 12(A) is 6.36 g / cm 3 while the density of the carbon (C) substitution model shown in Fig. 15(A) is 5.89 g / cm (see Fig. 15(A)). 3 (see Fig. 15(A)).

[0047] For the calculation models shown in Fig. 12(A) and Fig. 15(A), at 1727 °C, which is lower than the melting point of the single crystal of InGaZnO4 (estimated by classical molecular dynamics calculation to be about 2000 °C), at a constant pressure (1 atom), classical molecular dynamics calculation was performed for 150 psec (time step width 0.2 fsec × 750,000 steps) to perform structure relaxation. Also, the radial distribution function g(r) was obtained for these two structures. The radial distribution function g(r) is a function that represents the probability density of the presence of other atoms at a position r away from a certain atom. When the correlation between atoms disappears, g(r) approaches 1. The radial distribution function g(r) is a function that represents the probability density of the presence of other atoms at a position r away from a certain atom. When the correlation between atoms disappears, g(r) approaches 1. When the correlation between atoms disappears, g(r) approaches 1.

[0048] By performing classical molecular dynamics calculations for 150 psec on the above two calculation models The final structures obtained are shown in FIGS. 13(A) and 15(B), respectively. Also, the radial distribution function g(r) in each of the structures is shown in FIG. 16.

[0049] The single crystal model shown in FIG. 13(A) is stable and maintains its crystal structure even in the final structure However, the carbon (C) substitution model shown in FIG. 15(B) is unstable, and it can be confirmed that the crystal structure collapses over time and changes to an amorphous structure. Also, in FIG. 16, when comparing the radial distribution function g(r) of each structure model, in the single crystal model, there are peaks even at long distances, indicating long-range order. On the other hand, in the carbon (C) substitution model, the peak disappears near 0.7 nm, indicating no long-range order. These calculation results suggest that the inclusion of carbon (C) in InGaZnO4 makes it easier for InGaZnO4 to become amorphous. Also, it was confirmed that even when high-temperature heating is performed with carbon (C) included in InGaZnO4, InGaZnO4 does not crystallize.

[0050] Therefore, in the semiconductor device shown in this embodiment, impurities such as silicon incorporated near the interface between the gate insulating film 110 and the oxide semiconductor film 106 are suppressed. As a result, in the oxide semiconductor film 106, a region is formed in which the silicon concentration distributed from the interface with the gate insulating film 110 toward the oxide semiconductor film 106 is 1.0 atomic% or less. This region is indicated as region 106a in FIG. 1(B). Also, the silicon concentration included in region 106a

[0051] is more preferably 0.1 atomic% or less. Further, the region 106a exists in contact with the gate insulating film 11 0 with a thickness of 5 nm or less.

[0052] In FIG. 1(B), a region other than the region 106a of the oxide semiconductor film 106 is referred to as a region 1 06b.

[0053] When the gate insulating film 110 contains impurities such as carbon, this may also be incorporated as an impurity into the oxide semiconductor film 106 in the same manner as the above-mentioned silicon . Therefore, the carbon concentration contained in the region 106a is 1.0×10 20 atoms / cm 3 or less, more preferably or 1.0×10 19 atoms / cm 3 or less.

[0054] In order not to mix impurities such as silicon into the oxide semiconductor film 106, when forming the gate insulating film 110, it may be formed so as not to damage the oxide semiconductor film 106 . For example, when forming a silicon oxide film for the gate insulating film 110 by a sputtering method, the momentum of silicon, which is a constituent element of the gate insulating film 110, colliding with the oxide semiconductor film 106 may be weakened . Specifically, the film formation power during the formation of the gate insulating film 110 may be lowered, the film formation pressure during the formation of the gate insulating film 110 may be increased, or the distance between the target and the substrate (T-S distance) during the formation of the gate insulating film 110 may be increased, etc. However, the method for forming the gate insulating film 110 is not limited to this. For example, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, etc. can be used by the PE-CVD method. The PE-CVD method is preferable because it causes less damage to the oxide semiconductor film 106 serving as the base film than the sputtering method ​ is preferable.

[0055] In this way, by reducing the concentrations of impurities such as silicon and carbon incorporated into the region 106a of the oxide semiconductor film 106, fluctuations in the electrical characteristics of the transistor 150 can be suppressed. Further, when the oxide semiconductor film 106 is a CAAC-OS film, crystalline portions can be formed up to the vicinity of the interface with the gate insulating film 110. By manufacturing the transistor 150 using such an oxide semiconductor film 106, a semiconductor device having stable electrical characteristics can be obtained. Note that details of other components will be described with reference to FIG. 2 in the method for manufacturing the transistor 150 described later.

[0056]

[0057] <Method for Manufacturing Transistor 150> Hereinafter, an example of a method for manufacturing the transistor 150 shown in FIG. 1 according to the present embodiment will be described with reference to FIG. 2.

[0058] First, a substrate 102 is prepared. There is no major limitation on the substrate that can be used for the substrate 102, but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, single-crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium and the like, and SOI substrates can also be applied.

[0059] Further, a flexible substrate may be used as the substrate 102. When a flexible substrate is used, the flexible A transistor including an oxide semiconductor film 106 may be directly fabricated on a flexible substrate, or fabricated on another substrate and then peeled off and transferred onto the flexible substrate. Note that in order to peel off and transfer from the fabrication substrate to the flexible substrate, a release layer may be provided between the fabrication substrate and the transistor including the oxide semiconductor film 106. A transistor including an oxide semiconductor film 106 is fabricated on a substrate, and then peeled off and transferred onto the flexible substrate. For peeling off and transferring from the fabrication substrate to the flexible substrate, it is preferable to provide a release layer between the fabrication substrate and the transistor including the oxide semiconductor film 106.

[0060] Next, a base insulating film 104 is formed on the substrate 102 (see Fig. 2(A)). The base insulating film 104 has the effect of preventing the diffusion of impurity elements such as hydrogen and moisture from the substrate 102, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. In addition, another effect of the base insulating film 104 is that it can supply oxygen to the oxide semiconductor film 106 formed later. For example, when an insulating film containing an oxide is used as the base insulating film 104, a part of oxygen can be desorbed by heating the base insulating film 104, so that oxygen can be supplied to the oxide semiconductor film 106 to compensate for the oxygen deficiency in the oxide semiconductor film 106. In particular, it is preferable that at least an amount of oxygen exceeding the stoichiometric composition exists in the base insulating film 104. For example, it is preferable to use a silicon oxide film represented by SiO2 + α (where α > 0) as the base insulating film 104. By using such a silicon oxide film as the base insulating film 104, oxygen can be supplied to the oxide semiconductor film 106, and the transistor characteristics of the transistor 150 using the oxide semiconductor film 106 can be improved.

[0061] 2+α (where α > 0) is preferably used. By using such a silicon oxide film as the base insulating film 104, oxygen can be supplied to the oxide semiconductor film 106, and the transistor characteristics of the transistor 150 using the oxide semiconductor film 106 can be improved.

[0062] Also, before forming the base insulating film 104, plasma treatment or the like may be performed on the substrate 102. As the plasma treatment, for example, argon gas may be introduced to generate plasma. Reverse sputtering can be performed. Reverse sputtering is a method in which a voltage is applied using an RF power source to the substrate 102 side in an argon atmosphere to form plasma in the vicinity of the substrate 102 and modify the surface. It should be noted that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. When reverse sputtering is performed, powdery substances (also called particles, dust) adhering to the surface of the substrate 102 can be removed. Next, an oxide semiconductor film 106 is formed on the base insulating film 104 (see Fig. 2(A)). Also, the oxide semiconductor film 106 is preferably a CAAC-OS film. Note that the base insulating film 104 and the oxide semiconductor film 106 are preferably formed continuously without being exposed to the air. Here, a detailed description of the CAAC-OS film that can be used for the oxide semiconductor film 106 will be given below.

[0063]

[0064]

[0065] The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous material. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure with a crystal part in an amorphous phase. Note that the crystal part often has a size that can be accommodated within a cube with a side length of less than 100 nm. Also, in an observation image by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part contained in the CAAC-OS film is not clear. Also, by TEM, grain boundaries (grain boundaries) are not observed in the CAAC-OS film. ​​​​​(also referred to as Li) cannot be confirmed. Therefore, in the CAAC-OS film, the reduction in electron movement caused by grain boundaries is suppressed. The reduction in electron movement caused by grain boundaries is suppressed.

[0066] In the crystalline part contained in the CAAC-OS film, the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab-plane, it has a trigonal or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that between different crystalline parts, the directions of the a-axis and b-axis may be different. In this specification and the like, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of - 5° or more and 5° or less is also included. In the CAAC-OS film, the distribution of the crystalline part does not have to be uniform. For example, in the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of the crystalline part may be high in the vicinity of the surface. 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of - 5° or more and 5° or less is also included.

[0067] In the CAAC-OS film, the distribution of the crystalline part does not have to be uniform. For example, in the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of the crystalline part may be high in the vicinity of the surface. In the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of the crystalline part may be high in the vicinity of the surface. In the vicinity of the surface, the proportion of the crystalline part may be high.

[0068] Since the c-axis of the crystalline part contained in the CAAC-OS film is aligned in a direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Since the c-axis of the crystalline part contained in the CAAC-OS film is aligned in a direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystalline part is the same as the direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface when the CAAC-OS film is formed. The crystalline part is formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. Note that the direction of the c-axis of the crystalline part is the same as the direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface when the CAAC-OS film is formed. The crystalline part is formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. The crystalline part is formed by film formation or by performing a crystallization treatment such as heat treatment after film formation.

[0069] A transistor using a CAAC-OS film can reduce fluctuations in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light. Also, fluctuations and variations in the threshold value can be suppressed. Therefore, the transistor has high reliability.

[0070] In addition, in an oxide semiconductor having crystallinity, more bulk defects can be reduced. Furthermore, by enhancing the flatness of the surface of an oxide semiconductor film having crystallinity, a transistor having a top-gate structure using the oxide semiconductor can obtain a field-effect mobility higher than that of a transistor using an amorphous oxide semiconductor. To enhance the flatness of the surface of the oxide semiconductor film, it is preferable to form the oxide semiconductor on a flat surface. Specifically, it may be formed on a surface having an average surface roughness (Ra) of 0.15 nm or less, preferably 0.1 nm or less. To enhance the flatness of the surface of the oxide semiconductor film, it is preferable to form the oxide semiconductor on a flat surface. Specifically, it may be formed on a surface having an average surface roughness (Ra) of 0.15 nm or less, preferably 0.1 nm or less.

[0071] Note that Ra is an arithmetic mean roughness extended three-dimensionally so that it can be applied to a surface, and can be expressed as "a value obtained by averaging the absolute values of the deviations from the reference plane to the specified plane", and is defined by the following formula. Note that Ra is an arithmetic mean roughness extended three-dimensionally so that it can be applied to a surface, and can be expressed as "a value obtained by averaging the absolute values of the deviations from the reference plane to the specified plane", and is defined by the following formula.

[0072]

Equation

[0073] Here, the specified plane is the plane to be measured for roughness, and is defined as a rectangular area represented by four points of coordinates (x1, y1, f(x1, y1)), (x1, y2, f(x1, y2)), (x2, y1, f(x2, y1)), ( x2, y2, f(x2, y2)). Let the area of the rectangle obtained by projecting the specified plane onto the xy plane be S0, and the height of the reference plane (the average height of the specified plane) be Z0. R ​​​​a can be measured with an atomic force microscope (AFM). It is measurable.

[0074] In addition, as the oxide semiconductor used for the oxide semiconductor film 106, it is preferably contain at least indium ( In) or zinc (Zn). Particularly preferably contain In and Zn. In addition, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor film, as a stabilizer, it is preferably have gallium (Ga) in addition to them. Also, as a stabilizer, it is preferably have tin (Sn). Also, as a stabilizer, it preferably contains one or more selected from hafnium (Hf), zirconium (Zr), titanium (Ti), scandium (Sc ), yttrium (Y), lanthanoids (for example, cerium (Ce), neodymium (Nd) ), gadolinium (Gd)). Preferably.

[0075] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also denoted as IGZO ), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxide, In-Zr-Zn-based oxide, In-Ti-Zn-based oxide, In-Sc-Zn -based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide Substances, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides , In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides, I n-Sn-Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga- Zn-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, I n-Hf-Al-Zn-based oxides can be used.

[0076] Here, the In-Ga-Zn-based oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Also, metal elements other than In, Ga, and Zn may be contained.

[0077] Also, as the oxide semiconductor, InMO3(ZnO) m (m > 0 and m is not an integer ) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co, or the elements as the above stabilizer . Also, as the oxide semiconductor, In2SnO5(ZnO) (n > 0 and n is an integer n ) may be used.

[0078] For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1, In:Ga:Zn = 3:1:2, or In:Ga:Zn = 2:1:3 or oxides in the vicinity of their compositions may be used.

[0079] Also, in the film formation process of the oxide semiconductor film 106, hydrogen is added to the oxide semiconductor film 106, and also It is preferably free of water as much as possible. For example, in the film forming process of the oxide semiconductor film 106, as a pretreatment, the substrate 102 on which the underlying insulating film 104 is formed in the preheating chamber of the sputtering apparatus is preheated to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 102 and the underlying insulating film 104. Further, when forming the oxide semiconductor film 106, it is preferably performed in a film forming chamber (also referred to as a film forming chamber) from which residual moisture has been exhausted.

[0080] In order to remove moisture in the preheating chamber and the film forming chamber, it is preferable to use an adsorption type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump. Further, the exhaust means may be a turbo pump with a cold trap added thereto. The preheating chamber and the film forming chamber evacuated using a cryopump exhaust compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms), etc., so that the concentration of impurities such as hydrogen and moisture contained in the oxide semiconductor film 106 can be reduced.

[0081] In this embodiment, an In-Ga-Zn based oxide is formed as the oxide semiconductor film 106 by sputtering. Further, the oxide semiconductor film 106 can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen.

[0082] As a target for producing an In-Ga-Zn based oxide as the oxide semiconductor film 106 by sputtering, for example, a metal having an atomic ratio of In:Ga:Zn = 1:1:1 ​​​​​​​​Oxide target or metal oxide target with atomic ratio In:Ga:Zn=3:1:2 Alternatively, a metal oxide target with an atomic ratio of In:Ga:Zn=2:1:3 can be used. However, the target that can be used for the oxide semiconductor film 106 is one of these targets. There is no limitation on the material and composition ratio of the get.

[0083] In addition, when the oxide semiconductor film 106 is formed using the above-described metal oxide target, The composition of the target may differ from the composition of the thin film formed on the substrate. For example, A metal oxide target of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] was used. In this case, the composition ratio of the oxide semiconductor film 106, which is a thin film, is In, depending on the film formation conditions. The molar ratio of 2O3:Ga2O3:ZnO may be 1:1:0.6-0.8. This is because ZnO sublimes or In2O3 This is thought to be due to the different sputtering rates of the components Ga2O3 and ZnO.

[0084] Therefore, when it is desired to form a thin film having a desired composition ratio, a metal oxide target is first For example, the composition ratio of the oxide semiconductor film 106, which is a thin film, needs to be adjusted. In the case where the molar ratio is In2O3:Ga2O3:ZnO=1:1:1, The composition ratio of the metal oxide target was In2O3:Ga2O3:ZnO=1:1:1.5[ In other words, the ZnO content of the metal oxide target is increased in advance. However, the composition ratio of the target is not limited to the above values, and may vary depending on the film formation conditions and the formation The thickness of the thin film can be adjusted appropriately depending on the composition of the thin film to be formed. Increasing the content of O is preferable because it improves the crystallinity of the obtained thin film.

[0085] Further, the relative density of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the formed oxide semiconductor film 106 can be made into a dense film.

[0086] Also, as the sputtering gas used when forming the oxide semiconductor film 106, it is preferable to use a high-purity gas from which impurities such as hydrogen , water, hydroxyl groups, or hydrides have been removed.

[0087] When applying a CAAC-OS film as the oxide semiconductor film 106, there are three methods for forming the CAAC-OS film . The first is to form a crystal part in which the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed of the oxide semiconductor film by forming the oxide semiconductor film at a film formation temperature of 100°C or more and 450°C or less. The second is a method of forming a crystal part in which the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed of the oxide semiconductor film or the normal vector of the surface by performing a heat treatment at 200°C or more and 700°C or less after forming the oxide semiconductor film with a thin film thickness. The third is a method of forming a crystal part in which the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed of the oxide semiconductor film or the normal vector of the surface by forming the first layer of the oxide semiconductor film thinly, performing a heat treatment at 200°C or more and 700°C or less, and then forming the second layer of the oxide semiconductor film. After forming the first layer of the oxide semiconductor film thinly, perform a heat treatment at 200°C or more and 700°C or less, and then form the second layer of the oxide semiconductor film to form a crystal part in which the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed of the oxide semiconductor film or the normal vector of the surface.

[0088] Also, the CAAC-OS film is, for example, a target for sputtering an oxide semiconductor that is polycrystalline. ​​Use sputtering to form a film. When ions collide with the sputtering target used, the crystal regions contained in the sputtering target may split from the a-b plane and peel off as plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a-b plane. In this case, the plate-shaped sputtering particles reach the substrate while maintaining the crystalline state, enabling the formation of a CAAC-OS film.

[0089] Also, in order to form a CAAC-OS film, it is preferable to apply the following conditions.

[0090] By reducing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystalline state by impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber should be reduced. Also, the impurity concentration in the film formation gas should be reduced. Specifically, a film formation gas with a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0091] Also, by increasing the substrate heating temperature during film formation, migration of the sputtering particles occurs after reaching the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 150°C or higher and 500°C or lower for film formation. By increasing the substrate heating temperature during film formation, when plate-shaped sputtering particles reach the substrate, migration occurs on the substrate and the flat surface of the sputtering particles adheres to the substrate.

[0092] Also, it is preferable to increase the oxygen ratio in the film formation gas and optimize the power to reduce plasma damage during film formation. The oxygen ratio in the film formation gas is 30% by volume or higher, preferably 100 % by volume.

[0093] In addition, when forming a crystalline oxide semiconductor film (single crystal or microcrystal) other than the CAAC-OS film as the oxide semiconductor film 106, the film formation temperature is not particularly limited. Next, a conductive film to be used for the source electrode and the drain electrode (including wiring formed in the same layer) is formed on the underlying insulating film 104 and the oxide semiconductor film 106. As the conductive film to be used for the source electrode and the drain electrode, for example, a metal film containing an element selected from aluminum, chromium, copper, tantalum,

[0094] titanium, molybdenum, tungsten, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Further, a high melting point metal film such as titanium, molybdenum, tungsten or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) of these can be laminated on one or both of the lower side and the upper side of a metal film such as aluminum or copper. The structure may also be used. Further, the conductive film to be used for the source electrode and the drain electrode may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3-SnO2, abbreviated as ITO), indium zinc oxide (In2O3-ZnO) can be used. The conductive film to be used for the source electrode and the drain electrode can be formed into a single layer or a laminated layer using the above materials. The forming method is not particularly limited, and various film forming methods such as a vapor deposition method, a CVD method, a sputtering ring method, and a spin coating method can be used. Next, a resist mask is formed on the conductive film by a photolithography process, and selectively

[0095]

[0095]

[0095] Then, a resist mask is formed on the conductive film by a photolithography process, and selectively After performing etching to form the source electrode 108a and the drain electrode 108b, the resist mask is removed (see Fig. 2(B)). For the exposure in the photolithography process when forming the resist mask, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light.

[0096] Also, by the above process, depending on the interval width between the lower end portion of the adjacent source electrode 108a and the lower end portion of the drain electrode 108b on the oxide semiconductor film 106, the channel length L of the subsequently formed transistor 150 is determined. Therefore, for the case of performing exposure with a channel length L < 25 nm, for example, extreme ultraviolet light with an extremely short wavelength of several nm to several tens of nm can be used for the exposure when forming the resist mask in the photolithography process. Exposure with extreme ultraviolet light has high

[0097] resolution and a large depth of focus. Therefore, it is possible to miniaturize the channel length L of the subsequently formed transistor 150, and the operating speed of the circuit can be increased. Also, in order to reduce the number of photomasks and the number of processes used in the photolithography process, the etching process may be performed using a resist mask formed by a multi-tone mask, which is an exposure mask where the transmitted light has multiple intensities. The resist mask formed using the This enables the corresponding photolithography process to be reduced, thus simplifying the process.

[0098] Note that when etching the conductive film, it is desirable to optimize the etching conditions so that the oxide semiconductor film 106 is not etched and separated. However, it is difficult to obtain a condition where only the conductive film is etched and the oxide semiconductor film 106 is not etched at all. When etching the conductive film, only a part of the oxide semiconductor film 106 is etched. For example, 5% to 50% of the film thickness of the oxide semiconductor film 106 may be etched, resulting in an oxide semiconductor film 106 having a groove portion (recess). It is desired to optimize the etching conditions so as not to etch and separate the oxide semiconductor film 106 during the etching of the conductive film. However, it is difficult to obtain a condition where only the conductive film is etched and the oxide semiconductor film 106 is not etched at all. When etching the conductive film, only a part of the oxide semiconductor film 106 is etched. For example, 5% to 50% of the film thickness of the oxide semiconductor film 106 may be etched, resulting in an oxide semiconductor film 106 having a groove portion (recess). It is difficult to obtain a condition where only the conductive film is etched and the oxide semiconductor film 106 is not etched at all. When etching the conductive film, only a part of the oxide semiconductor film 106 is etched. For example, 5% to 50% of the film thickness of the oxide semiconductor film 106 may be etched, resulting in an oxide semiconductor film 106 having a groove portion (recess). When etching the conductive film, only a part of the oxide semiconductor film 106 is etched. For example, 5% to 50% of the film thickness of the oxide semiconductor film 106 may be etched, resulting in an oxide semiconductor film 106 having a groove portion (recess). When etching the conductive film, only a part of the oxide semiconductor film 106 is etched. For example, 5% to 50% of the film thickness of the oxide semiconductor film 106 may be etched, resulting in an oxide semiconductor film 106 having a groove portion (recess). When etching the conductive film, only a part of the oxide semiconductor film 106 is etched. For example, 5% to 50% of the film thickness of the oxide semiconductor film 106 may be etched, resulting in an oxide semiconductor film 106 having a groove portion (recess).

[0099] Next, a gate insulating film 110 is formed to cover the oxide semiconductor film 106, the source electrode 108a, and the drain electrode 108b. Here, the film thickness of the gate insulating film 110 can be, for example, 1 nm or more and 500 nm or less. Also, there is no particular limitation on the method for manufacturing the gate insulating film 110. For example, the gate insulating film 110 can be manufactured by appropriately using a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, an ALD method, or the like. Next, a gate insulating film 110 is formed to cover the oxide semiconductor film 106, the source electrode 108a, and the drain electrode 108b. Here, the film thickness of the gate insulating film 110 can be, for example, 1 nm or more and 500 nm or less. Also, there is no particular limitation on the method for manufacturing the gate insulating film 110. For example, the gate insulating film 110 can be manufactured by appropriately using a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, an ALD method, or the like. Next, a gate insulating film 110 is formed to cover the oxide semiconductor film 106, the source electrode 108a, and the drain electrode 108b. Here, the film thickness of the gate insulating film 110 can be, for example, 1 nm or more and 500 nm or less. Also, there is no particular limitation on the method for manufacturing the gate insulating film 110. For example, the gate insulating film 110 can be manufactured by appropriately using a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, an ALD method, or the like. Next, a gate insulating film 110 is formed to cover the oxide semiconductor film 106, the source electrode 108a, and the drain electrode 108b. Here, the film thickness of the gate insulating film 110 can be, for example, 1 nm or more and 500 nm or less. Also, there is no particular limitation on the method for manufacturing the gate insulating film 110. For example, the gate insulating film 110 can be manufactured by appropriately using a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, an ALD method, or the like. Next, a gate insulating film 110 is formed to cover the oxide semiconductor film 106, the source electrode 108a, and the drain electrode 108b. Here, the film thickness of the gate insulating film 110 can be, for example, 1 nm or more and 500 nm or less. Also, there is no particular limitation on the method for manufacturing the gate insulating film 110. For example, the gate insulating film 110 can be manufactured by appropriately using a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, an ALD method, or the like.

[0100] It is preferable to use an oxide insulating film having sufficient breakdown voltage and insulation properties for the gate insulating film 110. When the gate insulating film 110 has a single-layer structure, for example, an oxide containing silicon such as silicon oxide may be used. It is preferable to use an oxide insulating film having sufficient breakdown voltage and insulation properties for the gate insulating film 110. When the gate insulating film 110 has a single-layer structure, for example, an oxide containing silicon such as silicon oxide may be used. It is preferable to use an oxide insulating film having sufficient breakdown voltage and insulation properties for the gate insulating film 110. When the gate insulating film 110 has a single-layer structure, for example, an oxide containing silicon such as silicon oxide may be used.

[0101] Also, when forming the gate insulating film 110, impurities such as silicon are incorporated near the interface between the gate insulating film 110 and the oxide semiconductor film 106. As a result, a region 106a is formed near the interface between the oxide semiconductor film 106 and the gate insulating film 110, and the oxide outside the region 106a Also, when forming the gate insulating film 110, impurities such as silicon are incorporated near the interface between the gate insulating film 110 and the oxide semiconductor film 106. As a result, a region 106a is formed near the interface between the oxide semiconductor film 106 and the gate insulating film 110, and the oxide outside the region 106a Also, when forming the gate insulating film 110, impurities such as silicon are incorporated near the interface between the gate insulating film 110 and the oxide semiconductor film 106. As a result, a region 106a is formed near the interface between the oxide semiconductor film 106 and the gate insulating film 110, and the oxide outside the region 106a The oxide semiconductor film 106 becomes the region 106b.

[0102] The silicon concentration contained in the region 106a is 1.0 atomic % or less, more preferably, 0.1 atomic % or less. Further, the region 106a is in contact with the gate insulating film 110 and has a thickness of 5 nm or less.

[0103] Also, when the gate insulating film 110 contains impurities such as carbon, this is also incorporated as an impurity into the region 106a of the oxide semiconductor film 106 in the same manner as the above silicon. Therefore, the carbon concentration contained in the region 106a is 1.0×10 atoms / cm or less, more preferably 20 atoms / cm 3 or less. Preferably, it is 1.0×10 19 atoms / cm 3 or less.

[0104] Also, the gate insulating film 110 may have a stacked structure. When the gate insulating film 110 has a stacked structure, for example, gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, yttrium oxide, lanthanum oxide or silicon oxynitride may be stacked on an oxide containing silicon. Also, hafnium oxide, hafnium silicate (HfSi O (x>0, y>0)), hafnium silicate with nitrogen added (HfSiO N x O y (x>0, y>0)), hafnium al minate (HfAl x O y (x>0, y>0)) and other high-k materials may be stacked. That is, it is sufficient to stack x O y (x>0, y>0)) and other high-k materials. That's all right.

[0105] By using an oxide containing silicon as the gate insulating film 110, the insulating film is heated. Since part of oxygen can be released by heating, the oxide semiconductor film 106 can be desorbed with oxygen. In particular, oxygen vacancies in the oxide semiconductor film 106 can be compensated for by supplying oxygen to the gate electrode 104. It is preferable that the insulating film 110 contains oxygen in an amount exceeding the stoichiometric composition. For example, the gate insulating film 110 is made of SiO 2+α (where α>0) It is preferable to use a silicon film. By using the oxygen-containing oxide semiconductor film 106 as the oxygen supply source, oxygen can be supplied to the oxide semiconductor film 106. The transistor 150 using the conductive film 106 can have good transistor characteristics.

[0106] In addition, the gate insulating film 110 is formed by preventing impurities such as silicon from being mixed into the oxide semiconductor film 106. In order to prevent this, the oxide semiconductor film 106 is damaged when the gate insulating film 110 is formed. For example, the gate insulating film 110 may be formed by sputtering an oxide film. When forming a silicon film, silicon, which is a constituent element of the gate insulating film 110, is an oxide semiconductor. Specifically, the force of the collision with the film 106 may be weakened. The deposition power is lowered, the deposition pressure during deposition of the gate insulating film 110 is increased, or the gate insulating One method for this is to increase the distance between the target and the substrate (TS distance) when forming the film 110. However, the method for forming the gate insulating film 110 is not limited to this. For example, PE-CVD Depending on the method, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, etc. can be used. The PE-CVD method is more efficient than the sputtering method in that it can deposit an oxide semiconductor film 10 as a base film. It is preferable because it causes little damage to 6.

[0107] Next, a conductive film for forming a gate electrode (including wirings formed in the same layer as this) ) is formed on the gate insulating film 110. As the conductive film used for the gate electrode, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium and other metal materials, or alloy materials mainly composed of these can be used. As the conductive film used for the gate electrode, a conductive metal oxide may be used for formation. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (Zn O), indium tin oxide (In2O3 - SnO2, sometimes abbreviated as ITO), indium zinc oxide (In2O3 - ZnO), or those containing silicon or silicon oxide in these metal oxide materials can be used. The gate electrode can be formed as a single layer or laminated using the above materials. The formation method is not particularly limited either, and various film formation methods such as evaporation method, CVD method, sputtering method, spin coating method, etc. can be used .

[0108] Next, a resist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form the gate electrode 112, and then the resist mask is removed (see Fig. 2 (C)). Also, the resist mask for forming the gate electrode 112 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Note that the etching of the gate electrode 112 may be either dry etching or wet etching, or both may be used. Note that the gate electrode When the pole 112 is formed, the transistor 150 is formed.

[0109] Next, an interlayer insulating film 114 is formed on the gate insulating film 110 and the gate electrode 112 (see Fig. 2(D)).

[0110] As the interlayer insulating film 114, it is preferable to use an inorganic insulating film, such as a single layer or a laminate of an oxide insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, or a hafnium oxide film. Further, a single layer or a laminate of a nitride insulating film such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film may be further formed on the above-mentioned oxide insulating film. For example, a laminate of a silicon oxide film and an aluminum oxide film is formed in order from the gate electrode 112 side using a sputtering method. a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, or a hafnium oxide film. For example, a laminate of a silicon oxide film and an aluminum oxide film is formed in order from the gate electrode 112 side using a sputtering method. a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film. For example, a laminate of a silicon oxide film and an aluminum oxide film is formed in order from the gate electrode 112 side using a sputtering method. For example, a laminate of a silicon oxide film and an aluminum oxide film is formed in order from the gate electrode 112 side using a sputtering method. a laminate of a silicon oxide film and an aluminum oxide film is formed in order from the gate electrode 112 side using a sputtering method.

[0111] After forming the interlayer insulating film 114, it is preferable to perform heat treatment on the oxide semiconductor film 106. The temperature of the heat treatment is 300°C or higher and 700°C or lower, or lower than the distortion point of the substrate. The temperature of the heat treatment is 300°C or higher and 700°C or lower, or lower than the distortion point of the substrate.

[0112] The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.), but it is preferable that the atmosphere such as nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Further, the purity of nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.). The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.), but it is preferable that the atmosphere such as nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.), but it is preferable that the atmosphere such as nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.), but it is preferable that the atmosphere such as nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. 9%) or higher (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). is preferable.

[0113] By heat treatment after forming the oxide semiconductor film, one of the main component materials constituting the oxide semiconductor may simultaneously decrease. However, in this heat treatment, oxygen can be supplied to the oxide semiconductor film 106 from the underlying insulating film 104 or the gate insulating film 110 formed of an oxide containing silicon, so that the oxygen deficiency in the oxide semiconductor film 106 can be compensated.

[0114] By performing the heat treatment as described above, the oxide semiconductor film 106 can be purified to a high purity so that it contains as few impurities as possible other than its main components. In the highly purified oxide semiconductor film 10 6, the carriers derived from donors are extremely few (close to zero), and the carrier concentration is 1× 10 10 14 / cm 3 less than, preferably 1×10 12 / cm 3 less than, more preferably 1×1 0 11 / cm 3 less than. In this way, an i-type (intrinsic) oxide semiconductor film 10 6 can be formed.

[0115] The transistor 150 is formed in the above steps. In the transistor 150, the impurity concentration of silicon or the like incorporated into the region 106a of the oxide semiconductor film 106 is reduced. Also, when the oxide semiconductor film is a CAAC-OS film, a crystal part can be formed near the interface with the gate insulating film 110. Thereby, the transistor 150 can have stable electrical characteristics.

[0116] Further, a planarization insulating film may be provided on the interlayer insulating film 114. As the planarization insulating film Then, organic materials having heat resistance such as acrylic resins, polyimide resins, benzocyclobutene resins, polyamide resins, and epoxy resins can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, etc. can be used. Note that a plurality of insulating films formed of these materials may be laminated.

[0117] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0118] (Embodiment 2) In the present embodiment, a modified example of the semiconductor device and the method of manufacturing the semiconductor device shown in FIGS. 1 and 2 of Embodiment 1 will be described with reference to FIGS. 3 to 5. Note that the same reference numerals as those shown in FIGS. 1 and 2 are used, and repeated descriptions thereof are omitted.

[0119] <Example of Configuration of Semiconductor Device (Modified Example)> FIGS. 3(A) and 3(B) show a plan view and a cross-sectional view of a transistor having a top gate structure as an example of a semiconductor device. FIG. 3(A) is a plan view, and FIG. 3(B) corresponds to a cross-sectional view taken along the dashed line X2 - Y2 in FIG. 3(A). In FIG. 3(A), in order to avoid complication, some of the components of the transistor 160 (for example, the gate insulating film 1 10, etc.) are omitted.

[0120] The transistor 160 shown in FIGS. 3(A) and 3(B) includes a base insulating film 104 on a substrate 102, and an oxide semiconductor film 106 including regions 106c, 106d, 106 e, and 106f formed on the base insulating film 104, and is formed on the oxide semiconductor film 106 and a gate insulating film 110 that is in contact with the gate insulating film 110 and at least an oxide semiconductor film 10. A gate electrode 112 is provided in a region overlapping with the gate insulating film 110, and a gate electrode An interlayer insulating film 114 is formed on the electrode 112, and an oxide semiconductor is provided on the interlayer insulating film 114. The semiconductor device includes a source electrode 108a and a drain electrode 108b electrically connected to the conductive film 106. nothing.

[0121] The oxide semiconductor film 106 includes a region 106c which functions as a channel formation region and a region 1 06d, and a region 106e which functions as a pair of low resistance regions sandwiching a channel formation region. , and region 106f.

[0122] In addition, as shown in FIG. 3B, the oxide semiconductor film 106 has an edge portion at an angle of 20° to 50°. It is preferable that the oxide semiconductor film 106 has a tapered shape. Oxygen is easily released from the edge of the oxide semiconductor film 106, which easily causes oxygen vacancies. The end of 106 is tapered to suppress the occurrence of oxygen vacancies, and the transistor 160 The occurrence of leakage current can be reduced.

[0123] The gate insulating film 110 is made of an oxide insulating film having sufficient voltage resistance and insulating properties. When the gate insulating film 110 has a single-layer structure, for example, silicon oxide is used. For example, an oxide containing silicon such as the following may be used.

[0124] In addition, by using an oxide containing silicon as the gate insulating film 110, By heating the film, part of the oxygen can be desorbed, so that the oxide semiconductor film 10 Oxygen can be supplied to 6 to compensate for oxygen deficiencies in the oxide semiconductor film 106. In particular, it is preferable that at least an amount of oxygen exceeding the stoichiometric composition is present in the gate insulating film 110. Preferably, for example, as the gate insulating film 110, silicon oxide represented by SiO 2+α (where α > 0) is used. By using such a silicon oxide film as the gate insulating film 1 10, oxygen can be supplied to the oxide semiconductor film 106, and the transistor characteristics of the transistor 160 using the oxide semiconductor film 106 can be improved. However, when a silicon oxide film is used as the gate insulating film 110, there is a risk that silicon in the gate insulating film 110 is incorporated into the oxide semiconductor film 106 as an impurity. When silicon or the like, which is a constituent element of the gate insulating film 110, is incorporated into the oxide semiconductor film 106 as an impurity, it becomes a factor affecting the characteristics of the transistor. Also, when the oxide semiconductor film 106 is a CAAC-OS film, the constituent elements of the gate insulating film 110 are mixed into the oxide semiconductor film 106, the bonds in the crystal part of the oxide semiconductor film 106 are broken, and an amorphous region is formed in a large amount in the oxide semiconductor film 106 near the gate insulating film 110. In particular, impurities such as silicon are easily incorporated in the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110. Since the channel region of the transistor 160 is formed in the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110, if impurities such as silicon are incorporated in the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110, the electrical characteristics of the transistor 150 may be fluctuated.

[0125] However, when a silicon oxide film is used as the gate insulating film 110, there is a risk that silicon in the gate insulating film 110 is incorporated into the oxide semiconductor film 106 as an impurity. When silicon or the like, which is a constituent element of the gate insulating film 110, is incorporated into the oxide semiconductor film 106 as an impurity, it becomes a factor affecting the characteristics of the transistor. Also, when the oxide semiconductor film 106 is a CAAC-OS film, the constituent elements of the gate insulating film 110 are mixed into the oxide semiconductor film 106, the bonds in the crystal part of the oxide semiconductor film 106 are broken, and an amorphous region is formed in a large amount in the oxide semiconductor film 106 near the gate insulating film 110.

[0126] In particular, in the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110, impurities such as silicon are easily incorporated. Since the channel region of the transistor 160 is formed in the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110, if impurities such as silicon are incorporated in the vicinity of the interface between the oxide semiconductor film 106 and the gate insulating film 110, there is a risk that the electrical characteristics of the transistor 150 will be fluctuated. ​

[0127] Therefore, in the semiconductor device according to this embodiment, impurities such as silicon incorporated near the interface between the oxide semiconductor film 106 and the gate insulating film 110 are suppressed. As a result, in the oxide semiconductor film 106, a region is formed in which the silicon concentration decreases from the interface with the gate insulating film 110 toward the oxide semiconductor film 106 at a concentration of 1.0 atomic % or less. This region is shown as region 106c and region 106e in FIG. 3(B). Further, it is more preferable that the silicon concentration included in region 106c and region 106e is 0.1 atomic % or less. Also, region 106c and region 106e exist in contact with the gate insulating film 110 with a thickness of 5 nm or less. In FIG. 3(B), the region on the base insulating film 104 side in the oxide semiconductor film 106 is shown as region 106d and region 106f, and the region close to the gate insulating film 110 is shown as region 106c and region 106e, respectively. When the gate insulating film 110 contains impurities such as carbon, this may also be incorporated as an impurity into the oxide semiconductor film 106 in the same manner as the above-described silicon. Therefore, the carbon concentration included in region 106c and region 106e is 1.0×10

[0128] atoms / cm

[0129] or less, more preferably 1.0×10 atoms / cm or less. To prevent impurities such as silicon from being mixed into the oxide semiconductor film 106, when forming the gate insulating film 110, it may be formed so as not to damage the oxide semiconductor film 106. 106c and region 106e is 1.0×10 20 atoms / cm 3 or less, more preferably 1.0×10 19 atoms / cm 3 or less.

[0130] ​​. For example, when forming a silicon oxide film for the gate insulating film 110 by sputtering, the momentum of silicon, which is a constituent element of the gate insulating film 110, hitting the oxide semiconductor film 106 may be weakened. Specifically, the film formation power during the formation of the gate insulating film 110 may be lowered, the film formation pressure during the formation of the gate insulating film 110 may be increased, or the distance between the target and the substrate (T-S distance) during the formation of the gate insulating film 110 may be increased. However, the method for forming the gate insulating film 110 is not limited thereto. For example, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, etc. can be used by the PE-CVD method. The PE-CVD method is preferable because it causes less damage to the oxide semiconductor film 106 serving as the underlying film than the sputtering method.

[0131] Thus, by reducing the concentrations of impurities such as silicon and carbon incorporated into the regions 106c and 106e of the oxide semiconductor film 106, fluctuations in the electrical characteristics of the transistor 160 can be suppressed. Further, when the oxide semiconductor film 106 is a CAAC-OS film, a crystalline portion can be formed up to the vicinity of the interface with the gate insulating film 110. By manufacturing the transistor 160 using such an oxide semiconductor film 106, a semiconductor device having stable electrical characteristics can be obtained.

[0132] Details of other components will be described with reference to FIGS. 4 and 5 in the method for manufacturing the transistor 160 described later.

[0133] <Method for Manufacturing Transistor 160> Hereinafter, with reference to FIGS. 4 and 5, the manufacturing method of the transistor 160 shown in FIG. 3 according to the present embodiment will be described. ​​​​​​​​​​​​An example of the manufacturing method will be described.

[0134] First, a substrate 102 is prepared. Regarding the substrate 102, it can have the same configuration as that described in Embodiment 1. and can have a similar configuration.

[0135] Next, an underlayer insulating film 104 is formed on the substrate 102 (see FIG. 4(A)). The underlayer insulating film 1 04 has a function of preventing the diffusion of impurity elements such as hydrogen and moisture from the substrate 102, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0136] In addition, as another effect of the underlayer insulating film 104, oxygen can be supplied to the oxide semiconductor film 1 06 formed later. For example, when an insulating film containing an oxide is used as the underlayer insulating film 104, a part of oxygen can be desorbed by heating the underlayer insulating film 104. can be desorbed by heating the underlayer insulating film 104, so that oxygen can be supplied to the oxide semiconductor film 106 and oxygen deficiency in the oxide semiconductor film 106 can be compensated. In particular, it is preferable that at least an amount of oxygen exceeding the stoichiometric composition exists in the underlayer insulating film 104. For example, as the underlayer insulating film 104, it is preferable to use a silicon oxide film represented by SiO (where α > 0). By using such a silicon oxide film as the underlayer insulating film 104, oxygen can be supplied to the oxide semiconductor film 106, and the transistor characteristics of the transistor 160 using the oxide semiconductor film 106 can be improved. can be improved. can be improved. 2+α (where α > 0). By using such a silicon oxide film as the underlayer insulating film 104, oxygen can be supplied to the oxide semiconductor film 106, and the transistor characteristics of the transistor 160 using the oxide semiconductor film 106 can be improved. By using such a silicon oxide film as the underlayer insulating film 104, oxygen can be supplied to the oxide semiconductor film 106, and the transistor characteristics of the transistor 160 using the oxide semiconductor film 106 can be improved. can be improved. can be improved.

[0137] In addition, before forming the underlayer insulating film 104, plasma treatment or the like is performed on the substrate 102. That's fine. As the plasma treatment, for example, argon gas is introduced to generate plasma. Reverse sputtering can be performed. Reverse sputtering means applying a voltage to the substrate side 102 using an RF power source to form plasma near the substrate 102 and modify the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of the argon atmosphere. That's also fine. When reverse sputtering is performed, powdery substances (also called particles, dust) adhering to the surface of the substrate 102 can be removed.

[0138] Next, an oxide semiconductor film 106 is formed on the underlying insulating film 104 (see Fig. 4(A)). Also, the oxide semiconductor film 106 is preferably a CAAC-OS film. Note that the underlying insulating film 104 and the oxide semiconductor film 106 are preferably formed continuously without being exposed to the air.

[0139] The oxide semiconductor film 106 can have the same configuration as that described in Embodiment 1.

[0140] Next, a gate insulating film 110 is formed to cover the oxide semiconductor film 106 (see Fig. 4(B)). Here, the film thickness of the gate insulating film 110 can be, for example, 1 nm or more and 500 nm or less. Also, there is no particular limitation on the method for manufacturing the gate insulating film 110. For example, sputtering, MBE, CVD, pulsed laser deposition, ALD, etc. can be appropriately used to manufacture the gate insulating film 110.

[0141] It is preferable to use an oxide insulating film having sufficient breakdown voltage and insulation properties for the gate insulating film 110. When the gate insulating film 110 has a single-layer structure, for example, like silicon oxide. An oxide containing no silicon may be used.

[0142] Also, when the gate insulating film 110 is formed, impurities such as silicon are incorporated near the interface between the oxide semiconductor film 106 and the gate insulating film 110. As a result, in the oxide semiconductor film 106, a region 106g is formed near the interface with the gate insulating film 110, and the oxide semiconductor film 106 other than the region 106g becomes a region 106h. Note that the region 106g is a part that later becomes the region 106c and the region 106e, and the region 106h is a part that later becomes the region 106d and the region 106f. In addition, the silicon concentration contained in the region 106g is 1.0 atomic% or less, more preferably, 0.1 atomic% or less. Also, the region 106g exists in contact with the gate insulating film 110 with a thickness of 5 nm or less.

[0143] In addition, when the gate insulating film 110 contains impurities such as carbon, this is also incorporated as an impurity into the region 106g of the oxide semiconductor film 106 in the same manner as the above silicon. Therefore, the carbon concentration contained in the region 106g is 1.0×10 atoms / cm or less, more preferably

[0144] 1.0×10 atoms / cm or less. 20 atoms / cm 3 or less, more preferably 1.0×10 19 atoms / cm 3 or less.

[0145] Also, the gate insulating film 110 may have a stacked structure. When the gate insulating film 110 has a stacked structure, for example, gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, yttrium oxide, lanthanum oxide or silicon oxynitride nitride, etc. may be stacked on an oxide containing silicon. Also, on an oxide containing silicon, oxidation Hafnium, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen is added Hafnium silicate (HfSiO x N y (x>0, y>0)), hafnium aluminium minate (HfAl x O y (x>0, y>0)) stomach.

[0146] By using an oxide containing silicon as the gate insulating film 110, the insulating film By heating, part of oxygen can be released from the oxide semiconductor film 106. By supplying oxygen, oxygen vacancies in the oxide semiconductor film 106 can be filled. It is preferable that the amount of oxygen in the insulating film 110 exceeds at least the stoichiometric composition. For example, the gate insulating film 110 is made of SiO 2+α (where α>0) It is preferable to use a silicon oxide film as the gate insulating film 110. By using the oxide semiconductor film 106 as the second oxide semiconductor film, oxygen can be supplied to the oxide semiconductor film 106. The transistor characteristics of the transistor 160 using the conductive film 106 can be improved. .

[0147] In addition, the gate insulating film 110 is formed by preventing impurities such as silicon from being mixed into the oxide semiconductor film 106. In order to prevent this, the oxide semiconductor film 106 is damaged when the gate insulating film 110 is formed. For example, the gate insulating film 110 may be formed by sputtering an oxide film. When forming a silicon film, silicon, which is a constituent element of the gate insulating film 110, is an oxide semiconductor. The impact on the film 106 may be weakened. Specifically, during the formation of the gate insulating film 110, the film formation power can be reduced, the film formation pressure during the formation of the gate insulating film 110 can be increased, or the distance between the target and the substrate (T-S distance) during the formation of the gate insulating film 110 can be increased, etc. However, the method for forming the gate insulating film 110 is not limited to this. For example, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, etc. can be used by the PE-CVD method. The PE-CVD method is preferable because it causes less damage to the oxide semiconductor film 10 6, which serves as the underlying film, compared to the sputtering method.

[0148] Next, a conductive film for forming a gate electrode (including wirings formed in the same layer) is formed on the gate insulating film 110. The conductive film used for the gate electrode may have the same configuration as the materials described in Embodiment 1, etc.

[0149] Next, a resist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form the gate electrode 112, and then the resist mask is removed (see Fig. 4 (C)). Also, the resist mask for forming the gate electrode 112 may be formed by the inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Note that the etching of the gate electrode 112 may be dry etching, wet etching, or both may be used.

[0150] Next, using the gate electrode 112 as a mask, a dopant 181 is introduced into the oxide semiconductor film 106 to form 106e and 106f that function as a pair of low-resistance regions (see Fig. 4(D) ).

[0151] Dopant 181 is an impurity that changes the conductivity of the oxide semiconductor film 106. The dop ant 181 can be one or more selected from any of group 15 elements (typically phosphorus (P), arsenic (As), and an timony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar ), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (C l), titanium (Ti), and zinc (Zn). It is possible to use them.

[0152] Dopant 181 can also be introduced into the oxide semiconductor film 106 through another film (for example, the gate insulating film 110) by an implantation method. As the method for introducing dopant 181, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. In that case, it is preferable to use ions of the dopant 181 alone or ions of fluoride or chloride. The introduction process of dopant 181 may be appropriately set and controlled by implantation conditions such as acceleration voltage and dose amount, and the film thickness of the film to be passed through. In this embodiment, phosphorus is used as dopant 181, and phosphorus ions are implanted by an ion implantation method. Note that the dose amount of dopant 181 is 1×10

[0153] ions / cm or more and 5×10 ions / cm or less. 13 ions / cm 2 or more and 5×10 16 ions / cm 2 or less is sufficient. .

[0154] The concentration of dopant 181 in the low-resistance region is 5×10 18 / cm 3 or more and 1×10 2 2 / cm 3 It is preferably as follows.

[0155] Further, when introducing the dopant 181, the substrate 102 may be heated.

[0156] Note that the process of introducing the dopant 181 into the oxide semiconductor film 106 may be performed multiple times, and a plurality of types of dopants may be used.

[0157] Further, after the introduction process of the dopant 181, a heat treatment may be performed. As the heat treatment conditions, it is preferably performed at a temperature of 300°C or higher and 700°C or lower, preferably 300°C or higher and 450°C or lower for 1 hour in an oxygen atmosphere. Also, the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in the atmosphere (ultra-dry air).

[0158] When the oxide semiconductor film 106 is a crystalline oxide semiconductor film or a CAAC-OS film, it may be partially amorphized by the introduction of the dopant 181. In this case, by performing a heat treatment after the introduction of the dopant 181, the crystallinity of the oxide semiconductor film 106 can be restored.

[0159] Therefore, in the oxide semiconductor film 106, a region 106c that functions as a channel formation region, and regions 106e and 106f that function as low-resistance regions sandwiching the region 106d are provided to form the oxide semiconductor film 106.

[0160] Next, an interlayer insulating film 114 is formed on the gate insulating film 110 and the gate electrode 112 (see FIG. 5(A)). (See FIG. 5(A).)

[0161] As the interlayer insulating film 114, it is preferable to use an inorganic insulating film, such as a silicon oxide film, an acid Silicon nitride film, aluminum oxide film, aluminum oxynitride film, gallium oxide film, acid An oxide insulating film such as a hafnium oxide film may be used alone or in a stacked layer. Also, the above-mentioned On the oxide insulating film, a single layer or a stack of nitride insulating films such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, and an aluminum oxynitride film may be further formed. For example Using the sputtering method, a stack of a silicon oxide film and an aluminum oxide film is formed in order from the gate electrode 112 side. For example, using the sputtering method, a stack of a silicon oxide film and an aluminum oxide film is formed in order from the gate electrode 112 side. When an aluminum oxide film is used as the interlayer insulating film, the aluminum oxide film can prevent hydrogen, moisture, and any impurities that cause fluctuations in the electrical characteristics of the transistor 160 from mixing into the oxide semiconductor film 106 during and after the manufacturing process. Also, the aluminum oxide film can prevent oxygen, which is the main component material constituting the oxide semiconductor, from being released from the oxide semiconductor film 106 during and after the manufacturing process.

[0162] When an aluminum oxide film is used as the interlayer insulating film, the aluminum oxide film can prevent hydrogen, moisture, and any impurities that cause fluctuations in the electrical characteristics of the transistor 160 from mixing into the oxide semiconductor film 106 during and after the manufacturing process. Also, the aluminum oxide film can prevent oxygen, which is the main component material constituting the oxide semiconductor, from being released from the oxide semiconductor film 106 during and after the manufacturing process. When an aluminum oxide film is used as the interlayer insulating film, the aluminum oxide film can prevent hydrogen, moisture, and any impurities that cause fluctuations in the electrical characteristics of the transistor 160 from mixing into the oxide semiconductor film 106 during and after the manufacturing process. Also, the aluminum oxide film can prevent oxygen, which is the main component material constituting the oxide semiconductor, from being released from the oxide semiconductor film 106 during and after the manufacturing process. When an aluminum oxide film is used as the interlayer insulating film, the aluminum oxide film can prevent hydrogen, moisture, and any impurities that cause fluctuations in the electrical characteristics of the transistor 160 from mixing into the oxide semiconductor film 106 during and after the manufacturing process. Also, the aluminum oxide film can prevent oxygen, which is the main component material constituting the oxide semiconductor, from being released from the oxide semiconductor film 106 during and after the manufacturing process. When an aluminum oxide film is used as the interlayer insulating film, the aluminum oxide film can prevent hydrogen, moisture, and any impurities that cause fluctuations in the electrical characteristics of the transistor 160 from mixing into the oxide semiconductor film 106 during and after the manufacturing process. Also, the aluminum oxide film can prevent oxygen, which is the main component material constituting the oxide semiconductor, from being released from the oxide semiconductor film 106 during and after the manufacturing process. When an aluminum oxide film is used as the interlayer insulating film, the aluminum oxide film can prevent hydrogen, moisture, and any impurities that cause fluctuations in the electrical characteristics of the transistor 160 from mixing into the oxide semiconductor film 106 during and after the manufacturing process. Also, the aluminum oxide film can prevent oxygen, which is the main component material constituting the oxide semiconductor, from being released from the oxide semiconductor film 106 during and after the manufacturing process.

[0163] After forming the interlayer insulating film 114, it is preferable to perform a heat treatment on the oxide semiconductor film 106. The temperature of the heat treatment is 300°C or higher and 700°C or lower, or lower than the distortion point of the substrate. After forming the interlayer insulating film 114, it is preferable to perform a heat treatment on the oxide semiconductor film 106. The temperature of the heat treatment is 300°C or higher and 700°C or lower, or lower than the distortion point of the substrate. After forming the interlayer insulating film 114, it is preferable to perform a heat treatment on the oxide semiconductor film 106. The temperature of the heat treatment is 300°C or higher and 700°C or lower, or lower than the distortion point of the substrate.

[0164] The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (such as argon or helium), but it is preferable that the atmosphere of the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Also, nitrogen, oxygen, The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (such as argon or helium), but it is preferable that the atmosphere of the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Also, nitrogen, oxygen, Alternatively, the purity of the rare gas is preferably 6N (99.9999%) or higher, more preferably 7N (99.9999 9%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). This is preferred.

[0165] By the heat treatment after forming the oxide semiconductor film, oxygen, which is one of the main component materials constituting the oxide semiconductor, may be simultaneously reduced. However, in this heat treatment, oxygen can be supplied to the oxide semiconductor film 106 from the underlying insulating film 104 or the gate insulating film 110 formed of an oxide containing silicon, so that the oxygen deficiency of the oxide semiconductor film 106 can be compensated.

[0166] By performing the heat treatment as described above, the oxide semiconductor film 106 can be highly purified so as to contain as few impurities as possible other than its main components. In the highly purified oxide semiconductor film 10 6, carriers derived from donors are extremely few (close to zero), and the carrier concentration is 1 × 10 14 / cm 3 less than, preferably 1 × 10 12 / cm 3 less than, more preferably 1 × 1 0 11 / cm 3 less than. In this way, an i-type (intrinsic) oxide semiconductor film 10 6 can be formed.

[0167] Next, openings reaching the oxide semiconductor film 106 (region 1 06e or region 106f) are formed in the gate insulating film 110 and the interlayer insulating film 114, and a conductive film to be used for the source electrode and the drain electrode (including wiring formed in the same layer) is formed in the openings. As the conductive film to be used for the source electrode and the drain electrode, the same structure as the materials described in Embodiment 1 can be used.​ It suffices to achieve this.

[0168] Next, a resist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form the source electrode 108a and the drain electrode 108b, and then the resist mask is removed (see Fig. 5(B)).

[0169] The transistor 160 is formed through the above steps (see Fig. 5(B)). In the transistor 16 0, the impurity concentrations such as silicon incorporated in the regions 106c and 106e of the oxide semiconductor film 106 are reduced. Further, when the oxide semiconductor film 106 is a CAAC-OS film, crystalline portions can be formed up to the vicinity of the interface with the gate insulating film 110. As a result, the transistor 160 can have stable electrical characteristics.

[0170] Also, a planarization insulating film may be provided on the transistor 160. As the planarization insulating film, organic materials having heat resistance such as acrylic resins, polyimide resins, benzocyclobutene resins, polyamide resins, and epoxy resins can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, etc. can be used. Further, a plurality of insulating films formed of these materials may be laminated.

[0171] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0172] (Embodiment 3) In this embodiment, the transistors shown in this specification are used, and in a situation where no power is supplied, An example of a semiconductor device that can retain memory contents and has no write count limit will be described with reference to FIG. The surface will be used for the description.

[0173] FIG. 6 is an example of the configuration of a semiconductor device. FIG. 6(A) shows a cross-sectional view of the semiconductor device, FIG. 6 (B) shows a plan view of the semiconductor device, and FIG. 6(C) shows a circuit diagram of the semiconductor device. Here FIG. 6(A) corresponds to the cross-section at C1 - C2 and D1 - D2 in FIG. 6(B).

[0174] The semiconductor device shown in FIGS. 6(A) and 6(B) has a transistor 260 using a first semiconductor material at the lower part and a transistor 150 using a second semiconductor material at the upper part. That is. As the transistor 150, the structure of the transistor shown in Embodiment 1 can be applied. However, the transistor 150 is an example in which a source electrode 1 08a and a drain electrode 108b are provided in contact with the oxide semiconductor film 106. In this embodiment Although not described, the transistor used in Embodiment 2 can also be applied. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps.

[0175] For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (e.g., single crystal silicon, etc.), and the second semiconductor material can be an oxide semiconductor. As a material other than an oxide semiconductor a transistor using single crystal silicon is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics.

[0176] Note that all of the above transistors are described as n-channel type transistors. ​​However, it goes without saying that a p-channel type transistor can be used. Also, in addition to being used for the transistor 150 as shown in Embodiment 1 using an oxide semiconductor to hold information, the specific configuration of the semiconductor device, such as the materials used for the semiconductor device and the structure of the semiconductor device, does not need to be limited to what is shown here. In addition to being used for the transistor 150 as shown in Embodiment 1 using an oxide semiconductor to hold information, the specific configuration of the semiconductor device, such as the materials used for the semiconductor device and the structure of the semiconductor device, does not need to be limited to what is shown here. In addition to being used for the transistor 150 as shown in Embodiment 1 using an oxide semiconductor to hold information, the specific configuration of the semiconductor device, such as the materials used for the semiconductor device and the structure of the semiconductor device, does not need to be limited to what is shown here. In addition to being used for the transistor 150 as shown in Embodiment 1 using an oxide semiconductor to hold information, the specific configuration of the semiconductor device, such as the materials used for the semiconductor device and the structure of the semiconductor device, does not need to be limited to what is shown here.

[0177] The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. The transistor 260 in FIG. 6(A) has a channel formation region 216 provided on a substrate 200 containing a semiconductor material (for example, silicon or the like), impurity regions 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity regions 220, a gate insulating film 208 provided on the channel formation region 216, and a gate electrode 210 provided on the gate insulating film 208. Note that, in the figure, there may be cases where the source electrode and the drain electrode are not explicitly shown, but for convenience, such a state may be included and referred to as a transistor. Also, in this case, in order to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region.

[0178] An element isolation insulating film 206 is provided on the substrate 200 so as to surround the transistor 260, and an insulating film 228 and an insulating film 230 are provided so as to cover the transistor 260. Note that, in order to achieve high integration, it is desirable that the transistor 260 has a configuration without a sidewall insulating film as shown in FIG. 6(A). On the other hand, when emphasizing the characteristics of the transistor 260, a sidewall insulating film is provided on the side surface of the gate electrode 210. An element isolation insulating film 206 is provided on the substrate 200 so as to surround the transistor 260, and an insulating film 228 and an insulating film 230 are provided so as to cover the transistor 260. Note that, in order to achieve high integration, it is desirable that the transistor 260 has a configuration without a sidewall insulating film as shown in FIG. 6(A). On the other hand, when emphasizing the characteristics of the transistor 260, a sidewall insulating film is provided on the side surface of the gate electrode 210. An element isolation insulating film 206 is provided on the substrate 200 so as to surround the transistor 260, and an insulating film 228 and an insulating film 230 are provided so as to cover the transistor 260. Note that, in order to achieve high integration, it is desirable that the transistor 260 has a configuration without a sidewall insulating film as shown in FIG. 6(A). On the other hand, when emphasizing the characteristics of the transistor 260, a sidewall insulating film is provided on the side surface of the gate electrode 210. An element isolation insulating film 206 is provided on the substrate 200 so as to surround the transistor 260, and an insulating film 228 and an insulating film 230 are provided so as to cover the transistor 260. Note that, in order to achieve high integration, it is desirable that the transistor 260 has a configuration without a sidewall insulating film as shown in FIG. 6(A). On the other hand, when emphasizing the characteristics of the transistor 260, a sidewall insulating film is provided on the side surface of the gate electrode 210. An element isolation insulating film 206 is provided on the substrate 200 so as to surround the transistor 260, and an insulating film 228 and an insulating film 230 are provided so as to cover the transistor 260. Note that, in order to achieve high integration, it is desirable that the transistor 260 has a configuration without a sidewall insulating film as shown in FIG. 6(A). On the other hand, when emphasizing the characteristics of the transistor 260, a sidewall insulating film is provided on the side surface of the gate electrode 210. It may also be an impurity region 220 including regions with different impurity concentrations.

[0179] The transistor 260 using a single-crystalline semiconductor substrate can operate at high speed. Therefore, by using the transistor as a read transistor, information can be read out at high speed. Two insulating films are formed to cover the transistor 260. As a process before forming the transistor 150 and the capacitor element 264, a CMP process is performed on the two insulating films to form a planarized insulating film 228 and insulating film 230, and at the same time, the upper surface of the gate electrode 210 is exposed.

[0180] The insulating film 228 and the insulating film 230 can typically be inorganic insulating films such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. The insulating film 228 and the insulating film 230 can be formed by using a plasma CVD method, a sputtering method, or the like. The insulating film 228 and the insulating film 230 can be formed by using a plasma CVD method, a sputtering method, or the like. formed.

[0181] In addition, organic materials such as polyimide-based resins, acrylic-based resins, benzocyclobutene-based resins, etc. can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), etc. can be used. When using an organic material, the insulating film 228 and the insulating film 230 may be formed by a wet method such as a spin coating method or a printing method. formed.

[0182] In this embodiment, a silicon nitride film is used as the insulating film 228, and a silicon oxide film is used as the insulating film 23 0.

[0183] An oxide semiconductor is formed on an insulating film 230 that has been sufficiently planarized by a polishing process (e.g., a CMP process). The average surface roughness of the surface of the insulating film 230 is preferably 0.15 nm or less.

[0184] The transistor 150 shown in FIG. 6(A) is a transistor that uses an oxide semiconductor in the channel formation region. Here, the oxide semiconductor film 106 included in the transistor 150 is preferably of high purity. By using a high-purity oxide semiconductor, a transistor 150 with extremely excellent off characteristics can be obtained.

[0185] Since the transistor 150 has a small off-current, by using it, it is possible to retain the stored content for a long time. That is, it is possible to obtain a semiconductor memory device that does not require a refresh operation or has an extremely low refresh operation frequency, and thus the power consumption can be sufficiently reduced.

[0186] An insulating film 180 is provided on the transistor 150 in a single layer or a stack. In this embodiment, as the insulating film 180, a stack of an aluminum oxide film and a silicon oxide film is used starting from the gate electrode 112 side. Note that by making the aluminum oxide film have a high density (e.g., a film density of 3.2 g / cm or more, preferably 3.6 g / cm 3 or more), it is possible to impart stable electrical characteristics to the transistor 3 150, which is preferable.

[0187] Also, via the gate insulating film 110 and the insulating film 180, a conductive film 182 is provided in a region that overlaps with the source electrode 108a of the transistor 150, and the source electrode 108a ​​​​​The gate insulating film 110, the insulating film 180, and the conductive film 182 constitute a capacitor element 264. That is, the source electrode 108a of the transistor 150 functions as one electrode of the capacitor element 264, and the conductive film 182 functions as the other electrode of the capacitor element 264. When a capacitor is not required, the capacitor element 264 may not be provided. Alternatively, the capacitor element 264 may be separately provided above the transistor 150.

[0188] An insulating film 184 is provided over the transistor 150 and the capacitor element 264. Then, a wiring 186 for connecting the transistor 150 and other transistors is provided over the insulating film 184. Although not shown in FIG. 6(A), the wiring 186 is electrically connected to the drain electrode 108b through an electrode formed in an opening formed in the insulating film 180, the gate insulating film 110, etc. Here, the electrode is preferably provided so as to overlap at least a part of the oxide semiconductor film 106 of the transistor 150.

[0189] In FIGS. 6(A) and 6(B), the transistor 260 and the transistor 150 are provided so as to overlap at least partially, and it is preferable that at least a part of the source region or the drain region of the transistor 260 overlaps with a part of the oxide semiconductor film 106. Also, the transistor 150 and the capacitor element 264 are provided so as to overlap at least partially with the transistor 260. For example, the conductive film 182 of the capacitor element 264 is provided so as to overlap at least partially with the gate electrode 210 of the transistor 260. By adopting such a planar layout, the occupied area of the semiconductor device can be reduced. ​​​Since it is possible, high integration can be achieved.

[0190] Note that the electrical connection between the drain electrode 108b and the wiring 186 may be made by directly contacting the drain electrode 108b and the wiring 186, or an electrode may be provided on the intervening insulating film, and the connection may be made through the electrode There may also be a plurality of electrodes intervening therebetween.

[0191] Next, an example of the circuit configuration corresponding to FIGS. 6(A) and 6(B) is shown in FIG. 6(C).

[0192] In FIG. 6(C), one of the source electrode or the drain electrode of the first wiring (1st Line) and the transistor 260 is electrically connected, and the second wiring (2nd Lin e) is electrically connected to the other of the source electrode or the drain electrode of the transistor 260. Also, one of the source electrode of the third wiring (3rd Line) and the transistor 150 or the drain electrode is electrically connected, and the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 150. Then, the gate electrode of the transistor 260 and the other of the source electrode or the drain electrode of the transistor 150 are electrically connected to one of the electrodes of the capacitor element 264, and the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 264.

[0193] In the semiconductor device shown in FIG. 6(C), by taking advantage of the feature that the potential of the gate electrode of the transistor 260 can be held, information can be written, held, and read out as follows.

[0194] The writing and holding of information will be described. First, the potential of the fourth wiring is set to that of the transistor Set the potential at which the transistor 150 turns on, turning on the transistor 150. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 260 and the capacitor element 264. That is, a predetermined charge is applied to the gate electrode of the transistor 260 ( writing). Here, assume that either one of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. Then, set the potential of the fourth wiring to the potential at which the transistor 150 turns off, turning off the transistor 150, so that the charge applied to the gate electrode of the transistor 260 is retained ( holding). Since the off-current of the transistor 150 is extremely small, the charge on the gate electrode of the transistor 260 is retained for a long time.

[0195] Next, the reading of information will be described. In a state where a predetermined potential (constant potential) is applied to the first wiring, when an appropriate potential (reading potential) is applied to the fifth wiring, the second wiring takes a different potential according to the amount of charge held on the gate electrode of the transistor 260. Generally, when the transistor 260 is an n-channel type, the apparent threshold voltage V

[0196] when a High level charge is applied to the gate electrode of the transistor 260 is lower than the apparent threshold voltage V when a Low level charge is applied to the gate electrode of the transistor 260. Here, the apparent threshold voltage means the potential of the fifth wiring required to turn the transistor 260 "on". Therefore, the potential of the fifth wiring is V and V th_H th_L th_H th_L ​​​​​​​​​​​By setting the potential between them to V0, the charge applied to the gate electrode of the transistor 260 can be determined. For example, in writing, when a High-level charge is applied, if the potential of the fifth wiring becomes V0 (> V ), the transistor 260 enters the "on state". When a Low-level charge is applied, even if the potential of the fifth wiring becomes V0 (< V ), the transistor 260 remains in the "off state". Therefore, by observing the potential of the second wiring, the stored information can be read out th_H ). . When a Low-level charge is applied, even if the potential of the fifth wiring becomes V0 (< V ), the transistor 260 remains in the "off state". th_L ). For this reason, by looking at the potential of the second wiring, the stored information can be read out.

[0197] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. In the case of a memory cell from which information is not read, a potential such that the transistor 260 enters the "off state" regardless of the state of the gate electrode, that is, a potential smaller than V , may be applied to the fifth wiring. Or, a potential such that the transistor 260 enters the "on state" regardless of the state of the gate electrode, that is, a potential larger than V , may be applied to the fifth wiring. th_ H . Or, a potential such that the transistor 260 enters the "on state" regardless of the state of the gate electrode, that is, a potential larger than V , may be applied to the fifth wiring. th_L .

[0198] In the semiconductor device shown in this embodiment, by applying a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, it is possible to hold the stored content for an extremely long time . That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced . Also, when there is no power supply (however, it is desirable that the potential is fixed) , ​​​Even so, it is possible to retain the memory content over a long period of time.

[0199] In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of element degradation. For example, unlike conventional non-volatile memories, since it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can also be easily realized.

[0200] In addition, the impurity concentration of silicon or the like incorporated into the region 106a of the oxide semiconductor film 106 of the transistor 150 is reduced. Also, when the oxide semiconductor film 106 is a CAAC-OS film, a crystal part can be formed up to the vicinity of the interface with the gate insulating film 110. Thereby, the transistor 150 can have stable electrical characteristics.

[0201] Therefore, it is possible to provide a semiconductor device that realizes miniaturization and high integration and has high electrical characteristics.

[0202] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0203] (Embodiment 4) In this embodiment, the transistor shown in Embodiment 1 or Embodiment 2 is used. used, and it is possible to retain the stored content even when no power is supplied, and there is no limit on the number of write operations. For a semiconductor device, a configuration different from that shown in Embodiment 3 will be described with reference to FIG. 7. For a semiconductor device having the above characteristics and a configuration different from that shown in Embodiment 3, an explanation will be given using FIG. 7. used for the description.

[0204] FIG. 7(A) shows an example of the circuit configuration of the semiconductor device, and FIG. 7(B) is a conceptual diagram showing an example of the semiconductor device. First, the semiconductor device shown in FIG. 7(A) will be described, and then the semiconductor device shown in FIG. 7(B) will be described below. First, the semiconductor device shown in FIG. 7(A) will be described, and then the semiconductor device shown in FIG. 7(B) will be described below. (B) will be described below.

[0205] In the semiconductor device shown in FIG. 7(A), the bit line BL is electrically connected to the source electrode or the drain electrode of the transistor 150, the word line WL is electrically connected to the gate electrode of the transistor 150, and the source electrode or the drain electrode of the transistor 150 is electrically connected to the first terminal of the capacitor element 354. The transistor 150 using an oxide semiconductor has a characteristic that the off-current is extremely small. Therefore, by turning off the transistor 150, the potential of the first terminal of the capacitor element 354 (or the charge stored in the capacitor element 354) can be held for an extremely long time. The transistor 150 using an oxide semiconductor has a characteristic that the off-current is extremely small. Therefore, by turning off the transistor 150, the potential of the first terminal of the capacitor element 354 (or the charge stored in the capacitor element 354) can be held for an extremely long time. The transistor 150 using an oxide semiconductor has a characteristic that the off-current is extremely small. Therefore, by turning off the transistor 150, the potential of the first terminal of the capacitor element 354 (or the charge stored in the capacitor element 354) can be held for an extremely long time.

[0206] The transistor 150 using an oxide semiconductor has a characteristic that the off-current is extremely small. Therefore, by turning off the transistor 150, the potential of the first terminal of the capacitor element 354 (or the charge stored in the capacitor element 354) can be held for an extremely long time. Next, a case where information is written and held in the semiconductor device (memory cell 350) shown in FIG. 7(A) will be described. First, the potential of the word line WL is set to a potential at which the transistor 150 is turned on, and the transistor 150 is turned on. As a result, the potential of the bit line BL becomes the potential of the capacitor element 354. First, the potential of the word line WL is set to a potential at which the transistor 150 is turned on, and the transistor 150 is turned on. As a result, the potential of the bit line BL becomes the potential of the capacitor element 354.

[0207] Next, a case where information is written and held in the semiconductor device (memory cell 350) shown in FIG. 7(A) will be described. Next, a case where information is written and held in the semiconductor device (memory cell 350) shown in FIG. 7(A) will be described.

[0208] First, the potential of the word line WL is set to a potential at which the transistor 150 is turned on, and the transistor 150 is turned on. As a result, the potential of the bit line BL becomes the potential of the capacitor element 354. First, the potential of the word line WL is set to a potential at which the transistor 150 is turned on, and the transistor 150 is turned on. As a result, the potential of the bit line BL becomes the potential of the capacitor element 354. is applied to the first terminal of (write). Then, the potential of the word line WL is set to a potential at which the transistor 150 is turned off, and the transistor 150 is turned off, so that the potential of the first terminal of the capacitor element 354 is held (hold).

[0209] Since the off-current of the transistor 150 is extremely small, the electric potential at the first terminal of the capacitor element 354 (or the charge stored in the capacitor element) can be held for a long time.

[0210] Next, reading of information will be described. When the transistor 150 is turned on, the floating bit line BL in a floating state and the capacitor element 354 are conducted, and charge is redistributed between the bit line BL and the capacitor element 354. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL takes different values depending on the potential at the first terminal of the capacitor element 354 (or the charge stored in the capacitor element 354). For example, if the potential at the first terminal of the capacitor element 354 is V, the capacitance of the capacitor element 354 is C, the capacitance component of the bit line BL (hereinafter also referred to as the bit line capacitance) is CB, and the potential of the bit line BL before charge redistribution is VB0, then the potential of the bit line BL after charge redistribution is

[0211] (CB*VB0 + C*V) / (CB + C). Therefore, as the state of the memory cell 350, assuming that the potential at the first terminal of the capacitor element 354 takes two states of V1 and V0 (V1 > V0), the potential of the bit line BL when holding the potential V1 (= (CB*VB0 + C*V1) ) / (CB + C)) is higher than the potential of the bit line BL when holding the potential V0 (= (CB*VB0 + C*V0) / (CB + C)). It can be seen that

[0212] ​​​ Then, information can be read by comparing the potential of the bit line BL with a predetermined potential. It is possible.

[0213] As described above, the semiconductor device shown in FIG. 7(A) has a very small off-current of the transistor 150. Therefore, the charge stored in the capacitor element 354 can be held for a long time. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low. Thus, the power consumption can be sufficiently reduced. Also, even when there is no power supply, the stored content can be held for a long time. It is possible. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low. Therefore, the power consumption can be sufficiently reduced. Also, even when there is no power supply, the stored content can be held for a long time. It is possible. Also, even when there is no power supply, the stored content can be held for a long time. It is possible.

[0214] Next, the semiconductor device shown in FIG. 7(B) will be described.

[0215] The semiconductor device shown in FIG. 7(B) has a memory cell array 351a and 351b having a plurality of memory cells 350 shown in FIG. 7(A) as a memory circuit in the upper part, and a peripheral circuit 353 necessary for operating the memory cell array 351 (memory cell arrays 351a and 351b) in the lower part. The peripheral circuit 353 is electrically connected to the memory cell array 351. It has a plurality of memory cells 350 shown in FIG. 7(A) as a memory circuit in the upper part, and a peripheral circuit 353 necessary for operating the memory cell array 351 (memory cell arrays 351a and 351b) in the lower part. The peripheral circuit 353 is electrically connected to the memory cell array 351. By adopting the configuration shown in FIG. 7(B), the peripheral circuit 353 can be provided directly below the memory cell array 351 (memory cell arrays 351a and 351b), so that the semiconductor device can be miniaturized. It has a peripheral circuit 353 necessary for operating the memory cell array 351 (memory cell arrays 351a and 351b). The peripheral circuit 353 is electrically connected to the memory cell array 351. It is connected.

[0216] By adopting the configuration shown in FIG. 7(B), the peripheral circuit 353 can be provided directly below the memory cell array 351 (memory cell arrays 351a and 351b). It is possible to miniaturize the semiconductor device. It is possible to miniaturize the semiconductor device.

[0217] The transistor provided in the peripheral circuit 353 preferably uses a semiconductor material different from that of the transistor 150. For example, silicon, germanium, silicon germanium It is more preferable to use a semiconductor material different from that of the transistor 150. For example, silicon, germanium, silicon germanium , silicon carbide, gallium arsenide, etc. can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material or the like may be used. With such a semiconductor material used, the transistor can operate at a sufficiently high speed. Therefore, various circuits (logic circuits, drive circuits, etc.) that require high speed operation can be preferably realized by the transistor.

[0218] Note that in the semiconductor device shown in FIG. 7(B), a configuration in which two memory cell arrays 351 (memory cell array 351a and memory cell array 351b) are stacked is illustrated, but the number of memory cell arrays to be stacked is not limited to this. A configuration in which three or more memory cell arrays are stacked may also be used.

[0219] In this way, a peripheral circuit using a transistor made of a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a memory circuit using a transistor made of an oxide semiconductor ( more broadly, a transistor with a sufficiently small off-current) are integrally provided to realize a semiconductor device having unprecedented characteristics. Also, by forming the peripheral circuit and the memory circuit in a stacked structure, integration of the semiconductor device can be achieved.

[0220] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0221] (Embodiment 5) In this embodiment, an example of applying the semiconductor device shown in the previous embodiment to portable devices such as mobile phones, smartphones, and e-books will be described with reference to FIGS. 8 to 11.

[0222] ​​In portable devices such as mobile phones, smartphones, and e-books, SRAM or DRAM is used for temporary storage of image data and the like. The reason for using SRAM or DRAM is that flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

[0223] A normal SRAM is composed of six transistors, transistors 801 to 806, as shown in Fig. 8(A), and is driven by an X decoder 807 and a Y decoder 808. Transistors 803 and 805, and transistors 804 and 806 form inverters, enabling high-speed driving. However, since one memory cell is composed of six transistors, it has the drawback of a large cell area. When the minimum dimension of the design rule is F, the memory cell area of SRAM is usually 100 to 150F. 2 Therefore, SRAM has the highest unit price per bit among various memories.

[0224] In contrast, a DRAM memory cell is composed of a transistor 811 and a holding capacitor 812, as shown in Fig. 8(B), and is driven by an X decoder 813 and a Y decoder 814. One cell has a configuration of one transistor and one capacitor, and the area is small. The memory cell area of DRAM is usually 10F or less. However, DRAM always requires refreshing and consumes power even when no rewriting is performed. 2

[0225] ​​​​​​​​​​​​​​However, the memory cell area of the semiconductor device described in the previous embodiment is about 10F 2 or so and frequent refreshing is not required. Therefore, the memory cell area can be reduced, and the power consumption can be reduced accordingly.

[0226] Next, FIG. 9 shows a block diagram of a mobile device. The mobile device shown in FIG. 9 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a dis play controller 911, a memory circuit 912, a display 913, a touch sensor 91 9, an audio circuit 917, a keyboard 918, etc. The display 913 is composed of a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 has a CPU 907, a DSP 908, and an interface 9 09 (IF909). Generally, the memory circuit 912 is composed of SRAM or DRAM, and by adopting the semiconductor device described in the previous embodiment in this part, the writing and reading of information can be fast, long-term memory retention is possible, and the power consumption can be sufficiently reduced.

[0227] Next, FIG. 10 shows an example in which the semiconductor device described in the previous embodiment is used in the memory circuit 950 of the display. The memory circuit 950 shown in FIG. 10 is composed of a memory 952, a memory 953 , switches 954 and 955, and a memory controller 951. Also, the memory circuit receives input image data (input image data) input from a signal line, the memory Reads and controls the data (stored image data) stored in the memory 952 and the memory 953 A display controller 956 that performs operations, and a display 957 that is displayed by a signal from the display controller 956 are connected.

[0228] First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. And the image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and is displayed.

[0229] If there is no change in the input image data A, the stored image data A is usually read from the memory 952 via the switch 955 at a cycle of about 30 to 60 Hz and read from the display controller 956.

[0230] Next, for example, when the user performs an operation to rewrite the screen (that is, when there is a change in the input image data A), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this period, the stored image data A is also regularly read from the memory 952 via the switch 955. When the new image data (stored image data B) is completely stored in the memory 953, starting from the next frame of the display 957, the stored image data B is read, and the stored image data B is sent to the display 957 via the switch 955 and the display controller 956, and the display is performed. This reading continues until new image data is received by the memory. 55 and the display controller 956, and the stored image data B is sent to the display 957 and the display is performed. This reading continues until new image data is received by the memory. ​​​​​​​​​​​This will continue until it is stored in memory 952.

[0231] In this way, the memory 952 and the memory 953 alternately write image data and The display 957 is displayed by reading out the data. The memory 952 and the memory 953 are not limited to being separate memories, but may be divided into one memory. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 9 By adopting 53, it is possible to write and read information at high speed and to store data for a long period of time. It is possible to maintain the operation time and reduce power consumption sufficiently.

[0232] Next, a block diagram of an electronic book is shown in Fig. 11. Fig. 11 shows a battery 1001, a power supply circuit 1002, microprocessor 1003, flash memory 1004, audio circuit 1005 , keyboard 1006, memory circuit 1007, touch panel 1008, display 10 09, and a display controller 1010.

[0233] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 is to temporarily store the contents of the book. An example of a feature is when a user uses the highlight feature. When reading an e-book, you may want to mark a specific part. The highlight function is called the highlight function, and it can be used to change the display color, underline, highlight text, etc. The aim is to differentiate the text from its surroundings by making it bolder or by changing the font style. This is a function that stores and retains the information specified by the user. It may be copied to the flash memory 1004. Even in such a case, by adopting the semiconductor device described in the previous embodiment, writing and reading of information can be performed at high speed, long-term memory retention is possible, and power consumption can be sufficiently reduced.

[0234] As described above, the semiconductor device according to the previous embodiment is mounted on the portable device shown in this embodiment. Therefore, a portable device with high-speed reading, long-term memory retention, and reduced power consumption is realized.

[0235] The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

Example

[0236] In this example, silicon (Si) was intentionally added to the oxide semiconductor film, and its characteristics were evaluated. The details of the evaluation method will be described below.

[0237] First, the oxide semiconductor film was formed using a sputtering apparatus. Therefore, Si was intentionally added to the metal oxide target used in the sputtering apparatus. As the metal oxide target, a target obtained by adding SiO2 to an In-Ga-Zn-based oxide (hereinafter, IGZO) was produced. That is, it is a target of an In-Ga-Zn-Si-based oxide.

[0238] In this example, as the IGZO target, target A in which 2 wt% of SiO2 was added to a target having a composition ratio of In:Ga:Zn = 1:1:1 [atomic number ratio], and In: ​​​​​​​​​​A target with a composition ratio of Ga:Zn = 1:1:1 [atomic ratio] was added with 5 wt% of SiO2 The prepared target B and the target C without adding SiO2 (In:Ga:Zn = 1:1: 1 [atomic ratio]) were used for three targets.

[0239] In addition, the thin film prepared using target A was described as IGZO - SiOx(2wt.%), the thin film prepared using target B was described as IGZO - SiOx(5wt.%), and the thin film prepared using target C may be described as IGZO as follows.

[0240] Next, using the above - mentioned target A, target B, and target C, oxide semiconductor thin films were formed and various evaluations were performed. As the evaluation methods, the sheet resistance, composition, and crystallinity of the obtained thin films were evaluated respectively.

[0241] (Sheet Resistance Evaluation) On a glass substrate, using target C by sputtering method, power = 100w, pressure = 0.4Pa, substrate temperature = 200°C, Ar / O2 = 10 / 5 sccm (O2 = 33%) under the conditions to form an oxide semiconductor film, and then a heat treatment at 450°C for 1 hour in a nitrogen atmosphere was carried out, subsequently, a heat treatment at 450°C for 1 hour in an oxygen atmosphere was carried out for sample 1, and on a glass substrate using target C by sputtering method, power = 100w, pressure = 0.4Pa, substrate temperature = 200°C, Ar / O2 = 0 / 15 sccm (O2 = 100%) under the conditions to oxidize the semiconductor film, and then a heat treatment at 450°C for 1 hour in a nitrogen atmosphere was carried out, followed by a heat treatment at 450°C for 1 hour in an oxygen atmosphere for sample 2, and on a glass substrate using target A by sputtering method, power = 100w, pressure = 0.4Pa, substrate temperature = An oxide semiconductor film was formed under the conditions of 200 °C and Ar / O2 = 10 / 5 sccm (O2 = 33%). After that, a heat treatment at 450 °C for 1 hour was carried out in a nitrogen atmosphere, and then a heat treatment at 450 °C for 1 hour was carried out in an oxygen atmosphere. Sample 3, On a glass substrate, using target A, by sputtering method, power = 100 w, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 sccm (O2 = 100%). An oxide semiconductor film was formed under these conditions. After that, a heat treatment at 450 °C for 1 hour was carried out in a nitrogen atmosphere, and then a heat treatment at 450 °C for 1 hour was carried out in an oxygen atmosphere. Sample 4, On a glass substrate, using target B, by sputtering method, power = 100 w, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 10 / 5 sccm (O2 = 33%). An oxide semiconductor film was formed under these conditions. After that, a heat treatment at 450 °C for 1 hour was carried out in a nitrogen atmosphere, and then a heat treatment at 450 °C for 1 hour was carried out in an oxygen atmosphere. Sample 5, On a glass substrate, using target B, by sputtering method, power = 100 w, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 sccm (O2 = 100%). An oxide semiconductor film was formed under these conditions. After that, a heat treatment at 450 °C for 1 hour was carried out in a nitrogen atmosphere, and then a heat treatment at 450 °C for 1 hour was carried out in an oxygen atmosphere. Sample 6, On a glass substrate, using target B, by sputtering method, power = 100 w, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 scc m (O2 = 100%). An oxide semiconductor film was formed under these conditions. After that, a heat treatment at 450 °C for 1 hour was carried out in a nitrogen atmosphere, and then a heat treatment at 450 °C for 1 hour was carried out in an oxygen atmosphere. Samples 1 to 6 were each prepared.

[0242] Note that the film thickness of the oxide semiconductor films formed for Samples 1 to 6 was 100 nm. The conditions, structure, etc. of the prepared samples are shown in Table 1.

[0243]

Table 1

[0244] Next, the sheet resistance of Samples 1 to 6 was measured. As for the sheet resistance evaluation, a sheet resistance measuring instrument was used. The sheet resistance measurement results of Samples 1 to 6 are shown in Fig. 17. In Fig. 17, the horizontal axis represents the item (the fabricated thin film), and the vertical axis represents the sheet resistance, respectively. Each is shown.

[0245] It can be seen from Fig. 17 that in the thin film with Si added to IGZO, the sheet resistance has increased. In particular, for Sample 5, it exceeded the measurement upper limit (5×10 5 Ω / cm 2 ) of the measuring device and could not be measured. For Sample 6, although it also exceeded the measurement upper limit of the measuring device, numerical values near the measurement upper limit were calculated due to the principle of the measuring device. However, regarding the numerical values of the measurement upper limit of the measuring device, accurate measurements are not always possible. Regarding the numerical values of the measurement upper limit, accurate measurements are not always possible. Regarding the numerical values of the measurement upper limit, accurate measurements are not always possible.

[0246] (Composition Evaluation) On a glass substrate, using Target A, by sputtering method, power = 100 w, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 sccm (O2 = 100%) Sample 7 in which an oxide semiconductor film was formed under the conditions, and on a glass substrate, using Target B, by sputtering method, power = 100 w, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O 2 = 0 / 15 sccm (O2 = 100%) Sample 8 in which an oxide semiconductor film was formed under the conditions were each fabricated.

[0247] The film thickness of the oxide semiconductor films formed for Sample 7 and Sample 8 was set to 100 nm.

[0248] Next, the composition analysis of the above Sample 7 and Sample 8 was performed. As for the composition analysis, X-ray photoelectron Electron spectroscopy (XPS: X-Ray Photoelectron Spectro py) was used. XPS is a measurement method that irradiates the surface of a sample with X-rays and measures the photoelectron energy generated, enabling analysis of the constituent elements of the sample and their electronic states. The conditions, structure, and composition analysis results of samples 7 and sample 8 are shown in Table 2.

[0249]

Table 2

[0250] From Table 2, it was found that sample 7 prepared using target A had a composition of In = 18.0 (atomic %), Ga = 15.3 (atomic %), Zn = 4.6 (atomic %), O = 61.0 (atomic %), and Si = 1. 1 (atomic %). Also, sample 8 prepared using target B had a composition of In = 16.7 (atomic %), Ga = 14.4 (atomic %), Zn = 4.3 (atomic %), O = 62.0 (atomic %), and Si = 2.6 (atomic %).

[0251] (Crystallinity evaluation) On a glass substrate, using target A, by sputtering method, with power = 100 w, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 sccm (O2 = 100%) under the conditions, sample 9 in which an oxide semiconductor film was formed, and on a glass substrate, using target A, by sputtering method, with power = 100 w, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O 2 = 0 / 15 sccm (O2 = 100%) under the conditions, an oxide semiconductor film was formed, and then, a heat treatment at 450 °C for 1 hour was carried out in a nitrogen atmosphere, and subsequently, a heat treatment at 45 0 °C for 1 hour was carried out in an oxygen atmosphere, sample 10, and on a glass substrate, using target A, by sputtering ​By the RTA method, with power = 100 W, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 sccm (O2 = 100%), an oxide semiconductor film was formed. Then, heat treatment was carried out at 650 °C for 1 hour in a nitrogen atmosphere, and subsequently, heat treatment was carried out at 650 °C for 1 hour in an oxygen atmosphere. Sample 11 was prepared. And on a glass substrate, by sputtering using target B, with power = 100 W, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 scc m (O2 = 100%), an oxide semiconductor film was formed. Sample 12 was prepared. And on a glass substrate, by sputtering using target B, with power = 100 W, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 sccm (O2 = 100%), an oxide semiconductor film was formed. Then, heat treatment was carried out at 450 °C for 1 hour in a nitrogen atmosphere, and subsequently, heat treatment was carried out at 450 °C for 1 hour in an oxygen atmosphere. Sample 13 was prepared. And on a glass substrate, by sputtering using target B, with power = 100 W, pressure = 0.4 Pa, substrate temperature = 200 °C, Ar / O2 = 0 / 15 sccm (O2 = 100%), an oxide semiconductor film was formed. Then, heat treatment was carried out at 650 °C for 1 hour in a nitrogen atmosphere, and subsequently, heat treatment was carried out at 650 °C for 1 hour in an oxygen atmosphere. Sample 14 was prepared. Samples 11, 12, 13, and 14 were fabricated respectively.

[0252] Also, the film thickness of the formed oxide semiconductor films of Samples 9 to 14 was set to 100 nm. The conditions, structures, etc. of the fabricated samples are shown in Table 3. Samples 9 to 11 have oxide semiconductor films with the same composition as Sample 7 described above, and Samples 12 to 14 have oxide semiconductor films with the same composition as Sample 8 described above.

[0253] ​​​​​​​​​

Table 3

[0254] Next, the crystallinity of Samples 9 to 14 was analyzed. For the analysis of crystallinity and as such, the X-ray diffraction method (XRD: X-Ray Diffraction) was used. XRD is a phenomenon in which X-rays show diffraction by a crystal lattice, so it is possible to measure the crystallinity of the measurement sample. The crystallinity analysis results of Samples 9 to 11 are shown in Fig. 18(A), and the crystallinity analysis results of Samples 12 to 14 are shown in Fig. 18(B), respectively.

[0255] From Fig. 18(A), in Samples 9 to 11 prepared using Target A, in Sample 9 without heat treatment and Sample 10 subjected to heat treatment at 450°C, no distinct diffraction peaks indicating crystallinity were confirmed. On the other hand, in Sample 11 subjected to heat treatment at 650°C, a diffraction peak indicating crystallization was confirmed at around 2θ = 3 1°.

[0256] Also, from Fig. 18(B), in Samples 12 to 14 using Target B, in Sample 12 without heat treatment, Sample 13 subjected to heat treatment at 450°C, and Sample 14 subjected to heat treatment at 650°C, no distinct diffraction peaks indicating crystallinity were confirmed.

[0257] From the above results, Samples 9 to 11 prepared using Target A have a silicon (Si) concentration of 1.1 atomic% in the oxide semiconductor film, and Samples 12 to 14 prepared using Target B have a silicon (Si) concentration of 2.6 atomic% in the oxide semiconductor film. Thus, it was found that the crystallization is inhibited by the high content of Si concentration in the oxide semiconductor film.

Explanation of Signs

[0258] 102 Substrate 104 Underlying insulating film 106 Oxide semiconductor film 106a Region 106b Region 106c Region 106d Region 106e Region 106f Region 106g Region 106h Region 108a Source electrode 108b Drain electrode 110 Gate insulating film 112 Gate electrode 114 Interlayer insulating film 150 Transistor 160 Transistor 180 Insulating film 181 Dopant 182 Conductive film 184 Insulating film 186 Wiring 200 Substrate 206 Element isolation insulating film 208 Gate insulating film 210 Gate electrode 216 Channel formation region 220 Impurity region 224 Intermetallic compound region 228 Insulating film 230 Insulating film 260 Transistor 264 Capacitor element 350 Memory cell 351 Memory cell array 351a Memory cell array 351b Memory cell array 353 Peripheral circuit 354 Capacitor element 801 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 X Decoder 808 Y Decoder 811 Transistor 812 Holding Capacity 813 X Decoder 814 Y Decoder 901 RF Circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power Supply Circuit 906 Application Processor 907 CPU 908 DSP 909 Interface 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display Unit 915 Source Driver 916 Gate Driver 917 Audio Circuit 918 Keyboard 919 Touch Sensor 950 Memory Circuit 951 Memory Controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display Controller 957 Display 1001 Battery 1002 Power Supply Circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 Keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller

Claims

Claim 1 a base insulating film; an oxide semiconductor film formed on the base insulating film; a source electrode and a drain electrode formed on the oxide semiconductor film; a gate insulating film containing silicon oxide formed on the oxide semiconductor film, the source electrode, and the drain electrode; a gate electrode provided in a region in contact with the gate insulating film and overlapping at least the oxide semiconductor film; and the oxide semiconductor film has a region with a silicon concentration of 1.0 atomic % or less from the interface with the gate insulating film toward the oxide semiconductor film; a semiconductor device including a crystal part at least in the region.

Images