Semiconductor device

Abstract

To provide a semiconductor device capable of obtaining a feedback capacitance Cres more effectively.SOLUTION: A semiconductor device 1 comprises: a gate potential trench 5 which is formed in a gate finger region 11 on a main surface side of a semiconductor substrate 2; a predetermined potential trench 6 which is formed on the main surface side of the semiconductor substrate 2 so as to sandwich the gate potential trench 5; a drift region 3 of a first conductivity type which is formed in a first region 7 between the gate potential trench 5 and the predetermined potential trench 6; and a well region 4 of a second conductivity type which is located above the drift region 3 and is formed in a second region 8 on the side opposite to the side where the gate potential trench 5 is located relative to the predetermined potential trench 6.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] For example, as a technology related to a semiconductor device constituting an IGBT (Insulated Gate Bipolar Transistor), Patent Document 1 is known. Patent Document 1 describes a semiconductor device constituting an EGE (Emitter-Gate-Emitter) type trench gate IGBT. In the semiconductor device of Patent Document 1, a plurality of gate potential trenches each having a shape surrounded by a quadrangular outer shape and a quadrangular inner shape in a plan view are provided in parallel in a gate wiring lead-out region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device of Patent Document 1, a plurality of gate potential trenches are formed in a P-type P-well region (floating region), and an N-type drift region is formed in a region inside the inner shape of the gate potential trench in a plan view, whereby the capacitance formed between the trench gate electrode and the drift region is used as a feedback capacitance Cres. A semiconductor device capable of more effectively obtaining the feedback capacitance Cres is desired.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, a semiconductor device includes a semiconductor substrate including an active cell region where transistors are operably formed and a gate finger region where gate wiring is drawn out. In the gate finger region, a gate potential trench is formed on the main surface side of the semiconductor substrate, and a predetermined potential trench having a predetermined potential different from that of the gate is formed so as to sandwich the gate potential trench on the main surface side of the semiconductor substrate. A drift region of a first conductivity type is formed in a first region between the gate potential trench and the predetermined potential trench in the semiconductor substrate. A well region of a second conductivity type is formed in a second region above the drift region in the semiconductor substrate and on the side opposite to the side where the gate potential trench is located with respect to the predetermined potential trench.

Effects of the Invention

[0007] According to the above embodiment, the feedback capacitance Cres can be obtained more effectively.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. For the sake of clarity of explanation, the following description and drawings are appropriately omitted and simplified. Also, in each drawing, the same elements are denoted by the same reference numerals, and redundant explanations are omitted as necessary.

[0010] In each drawing, an XYZ three-dimensional orthogonal coordinate system is shown, and the XY plane is a plane parallel to the surface (front or back surface) of the semiconductor substrate. The Z direction orthogonal to the XY plane is the vertical direction, height direction, or thickness direction in the semiconductor substrate. Plan view means viewing the XY plane from the Z direction.

[0011] (Outline of Embodiment) FIG. 1 shows a configuration example of a related IGBT parallel connection circuit studied by the inventor. For example, in an IGBT for a high-current inverter, in order to ensure the required current capacity, as shown in FIG. 1, semiconductor chips constituting the IGBT are connected in parallel and operated. As shown in FIG. 1, when a load short-circuit test was performed in a module state where four IGBTs were connected in parallel, oscillation occurred and the phenomenon that the semiconductor device was destroyed was confirmed.

[0012] As shown in FIG. 1, a displacement current Idis flows through the parasitic feedback capacitance Cres between the gate and the collector, and oscillation occurs due to a resonance loop via the feedback capacitance Cres. As a countermeasure against oscillation, it is effective to increase the feedback capacitance Cres (damping capacitance). For example, in a trench gate type IGBT, a method of adjusting the depth of the gate potential trench connected to the gate potential to increase the feedback capacitance Cres can be considered. However, if the depth of the trench inside the active cell that determines the characteristics of the IGBT is adjusted to increase the feedback capacitance Cres, the basic characteristics of the IGBT may change. Also, since the depth of all trenches changes uniformly depending on the manufacturing process, fine adjustment of the feedback capacitance Cres is difficult. Therefore, in the embodiment, a device layout method that adds the feedback capacitance Cres in a region that does not affect the characteristics of the IGBT such as outside the active cell and enables fine adjustment is provided.

[0013] FIG. 2 is a plan view showing a schematic configuration of the semiconductor device 1 according to the embodiment. FIG. 3 is a cross-sectional view showing a schematic configuration in the gate finger region of the semiconductor device 1, and shows the cross-section taken along line A-A' in FIG. 2. The semiconductor device 1 constitutes, for example, a trench gate type IGBT. The semiconductor device 1 may be other semiconductor devices having the configurations shown in FIGS. 2 and 3. For example, the semiconductor device 1 may constitute a transistor such as a power MOSFET (metal-oxide-semiconductor field-effect transistor) or other semiconductor elements.

[0014] As shown in FIG. 2, the semiconductor device 1 includes a semiconductor substrate 2. The semiconductor substrate 2 has an active cell region 10 and a gate finger region 11. The active cell region 10 is a region where active cells are formed, for example, a region where transistors such as IGBTs are operably (actively) formed. The gate finger region 11 is a region where gate wiring is drawn out from the transistors in the active cell region 10. For example, the gate finger region 11 extends outside the active cell region 10 along the end of the active cell region 10. The gate finger region 11 is also a non-active cell region where no active cells are formed.

[0015] As shown in FIG. 3, in the gate finger region 11 of the semiconductor device 1, a drift region 3, a well region 4, a gate potential trench 5, and a predetermined potential trench 6 are formed in the semiconductor substrate 2.

[0016] The gate potential trench 5 is a trench connected to the gate potential. A trench gate electrode is formed inside the gate potential trench 5. The gate potential trench 5 is formed from the main surface side of the semiconductor substrate 2. For example, when the main surface of the semiconductor substrate 2 is called the surface, any surface of the semiconductor substrate 2 may be used as the main surface.

[0017] The predetermined potential trench 6 is a trench connected to a predetermined potential different from the gate. Inside the predetermined potential trench 6 is a trench in which an electrode of the predetermined potential is formed. For example, when the semiconductor device 1 constitutes an IGBT, the predetermined potential trench 6 is an emitter potential trench connected to the emitter potential. The predetermined potential trench 6 is formed on the main surface side of the semiconductor substrate 2 and is arranged so as to sandwich the gate potential trench 5. For example, the predetermined potential trench 6a and the predetermined potential trench 6b face each other with the gate potential trench 5 therebetween.

[0018] The drift region 3 is a semiconductor region of the first conductivity type (e.g., N-type) formed in the semiconductor substrate 2. The drift region 3 is formed in the first region 7 between the gate potential trench 5 and the predetermined potential trench 6 in the semiconductor substrate 2. For example, the first region 7 includes regions on both sides of the gate potential trench 5. That is, the first region 7 includes the region between the predetermined potential trench 6a and the gate potential trench 5 and the region between the predetermined potential trench 6b and the gate potential trench 5. The gate potential trench 5 is covered by the drift region 3 from the main surface side of the semiconductor substrate 2 to the bottom of the gate potential trench 5.

[0019] The well region 4 is a semiconductor region of the second conductivity type (e.g., P-type) formed above the drift region 3 in the semiconductor substrate 2. The well region 4 is formed in the second region 8 on the side opposite to the side where the gate potential trench 5 is located (the side facing the gate potential trench 5) with respect to the predetermined potential trench 6. For example, the second region 8 includes regions on both sides of the first region 7. That is, the second region 8 includes the second region 8a on the side opposite to the side where the gate potential trench 5 is located with respect to the predetermined potential trench 6a and the second region 8b on the side opposite to the side where the gate potential trench 5 is located with respect to the predetermined potential trench 6b. The well region 4 is connected to a predetermined potential (e.g., emitter potential) and is separated from the gate potential trench 5.

[0020] In a semiconductor device, a gate finger region for connecting a gate electrode of an active cell to a gate wiring occupies a certain area. As described above, in the embodiment, a structure capable of adding a feedback capacitance is provided in this gate finger region. In the gate finger region, a drift region of a first conductivity type is formed in a region between a gate potential trench and a predetermined potential trench such as an emitter potential, and a well region of a second conductivity type connected to a predetermined potential is not formed. Thereby, the gate potential trench and the well region are separated, and the feedback capacitance Cres can be effectively obtained. By adopting such a structure for the gate finger region, the feedback capacitance Cres can be added while suppressing the influence on the characteristics of the transistor.

[0021] (Embodiment 1) Next, Embodiment 1 will be described. FIGS. 4A and 4B are plan views showing a configuration example of a semiconductor device 100 according to the present embodiment. For example, the semiconductor device 100 constitutes a trench gate type N-channel IGBT. As shown in FIG. 1, a plurality of IGBTs can be connected in parallel and used as a large current inverter. The semiconductor device 100 is not limited to an N-channel IGBT, and may constitute a P-channel IGBT. The semiconductor device 100 is not limited to a trench gate type IGBT, and may constitute a transistor having another structure.

[0022] As shown in FIG. 4A, the semiconductor device 100 includes a semiconductor substrate SUB that becomes a semiconductor chip. A gate wiring GW and an emitter wiring EW are formed on the semiconductor substrate SUB. The gate wiring GW is a wiring (electrode) for leading out a gate electrode in the semiconductor substrate SUB to the outside. The emitter wiring EW is a wiring (electrode) for leading out an emitter electrode in the semiconductor substrate SUB to the outside. For example, the gate wiring GW and the emitter wiring EW are metal films made of aluminum (Al) or the like.

[0023] The region that overlaps with the emitter wiring EW in a plan view becomes the active cell region 101. Inside the outer peripheral end of the emitter wiring EW, there is the outer peripheral end of the active cell region 101. The active cell region 101 is a region where main elements such as IGBTs are formed operably on the semiconductor substrate SUB. In this example, emitter wirings EW1 to EW5 are arranged in five active cell regions 101-1 to 101-5, respectively. For example, the emitter wiring EW is rectangular in a plan view. The five rectangular emitter wirings EW1 to EW5 are arranged in parallel at regular intervals. For example, the X direction is called the horizontal direction (the first direction), and the emitter wirings EW1 to EW5 extend in the horizontal direction.

[0024] The gate wiring GW is arranged so as to sandwich the emitter wiring EW (active cell region 101) in a comb shape in a plan view. The gate wiring GW may be a line-shaped wiring that encircles the outside of the emitter wiring EW. The emitter wiring EW may be formed entirely inside the gate wiring GW on the semiconductor substrate SUB. For example, the gate wiring GW is arranged at a distance from the emitter wiring EW in the region between the plurality of emitter wirings EW and the region of the outer peripheral end of the semiconductor substrate SUB (excluding the right end portion). It can also be said that the gate wiring GW is arranged in the non-active cell region 102 outside the active cell region 101. The non-active cell region 102 is a region where main elements such as IGBTs are not formed operably.

[0025] For example, the regions outside the two long sides extending in the horizontal direction of the active cell region 101 (emitter wiring EW) in a plan view become the gate finger regions 103. The gate finger region 103 is a region for drawing out the gate wiring from the gate electrode of the active cell and connecting it to the gate pad. The gate finger region 103 is included in the non-active cell region 102. The gate finger region 103 extends in the horizontal direction along the long side (end portion) of the active cell region 101. The gate wiring GW extending in the horizontal direction is arranged in the gate finger region 103.

[0026] On both sides of the two long sides of the active cell region 101-1, gate finger regions 103-1 and 103-2 are formed. The gate finger region 103-1 is a region at the lateral short-side end of the semiconductor substrate SUB that extends in the lateral direction. The gate finger region 103-1 includes a gate wiring GW disposed at the first short-side end of the semiconductor substrate SUB and a part of the emitter wiring EW1 that faces the gate wiring GW.

[0027] On both sides of the two long sides of the active cell region 101-2, gate finger regions 103-2 and 103-3 are formed. The gate finger region 103-2 is a region between the active cell regions 101-1 and 101-2. The gate finger region 103-2 includes a gate wiring GW between the emitter wirings EW1 and EW2 and a part of the emitter wiring EW1 and a part of the emitter wiring EW2 that face the gate wiring GW.

[0028] On both sides of the two long sides of the active cell region 101-3, gate finger regions 103-3 and 103-4 are formed. The gate finger region 103-3 is a region between the active cell regions 101-2 and 101-3. The gate finger region 103-3 includes a gate wiring GW between the emitter wirings EW2 and EW3 and a part of the emitter wiring EW2 and a part of the emitter wiring EW3 that face the gate wiring GW.

[0029] On both sides of the two long sides of the active cell region 101-4, gate finger regions 103-4 and 103-5 are formed. The gate finger region 103-4 is a region between the active cell regions 101-3 and 101-4. The gate finger region 103-4 includes a gate wiring GW between the emitter wirings EW3 and EW4 and a part of the emitter wiring EW3 and a part of the emitter wiring EW4 that face the gate wiring GW (shown in the enlarged view of FIG. 4A).

[0030] On both sides of the two long sides of the active cell region 101-5, gate finger regions 103-5 and 103-6 are formed. The gate finger region 103-5 is the region between the active cell regions 101-4 and 101-5. The gate finger region 103-5 includes the gate wiring GW between the emitter wirings EW4 and EW5, a part of the emitter wiring EW4 facing the gate wiring GW, and a part of the emitter wiring EW5. The gate finger region 103-6 is the region of the second short-side end portion extending in the lateral direction of the semiconductor substrate SUB. The gate finger region 103-6 includes the gate wiring GW disposed at the second short-side end portion of the semiconductor substrate SUB and a part of the emitter wiring EW5 facing the gate wiring GW.

[0031] For example, the Y direction is called the vertical direction (the second direction), and the end region 104 of the active cell region 101 extending in the vertical direction orthogonal to the lateral direction in which the gate finger region 103 extends is called. The end region 104 may be included in the non-active cell region 102. The end region 104-1 is the region of the first long-side end portion extending in the vertical direction of the semiconductor substrate SUB. For example, a gate wiring GW extending in the vertical direction is disposed in the end region 104-1. The end region 104-2 is the region of the second long-side end portion extending in the vertical direction of the semiconductor substrate SUB. For example, no gate wiring GW extending in the vertical direction is disposed in the end region 104-2. For example, when the X direction is the left-right direction, the end region 104-1 is the region of the left end portion of the semiconductor substrate SUB. The end region 104-2 is the region of the right end portion of the semiconductor substrate SUB. The gate wiring GW is disposed in the gate finger regions 103-1 to 103-6 and the end region 104-1. It can be said that the gate wiring GW in the gate finger regions 103-1 to 103-6 and the gate wiring GW in the end region 104-1 are connected. Also, as shown in FIG. 4B, the emitter wiring EW may be formed at the outer peripheral end portion of the semiconductor substrate SUB and disposed so as to surround the gate wiring GW. In this case, the emitter wirings EW1 to EW5 are connected by the emitter wiring EW at the outer peripheral end portion of the semiconductor substrate SUB.

[0032] For example, the surfaces of the gate wiring GW and the emitter wiring EW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the gate wiring GW and the emitter wiring EW exposed at the opening become the gate pad GP and the emitter pad EP. The gate pad GP and the emitter pad EP are external terminals for connecting bonding wires or the like. For example, the emitter pad EP is formed at the center of each of the emitter wirings EW1 to EW5. The gate pad GP is formed at the center of the left end of the semiconductor substrate SUB, that is, on the left side of the emitter wiring EW3. In this case, the central emitter wiring EW3 has a smaller shape than the other emitter wirings EW.

[0033] Here, the semiconductor device of the comparative example will be described. FIG. 5 is a cross-sectional view of the gate finger region of the semiconductor device 900 of the comparative example. FIG. 5 shows a cross-section taken along line B-B' in the gate finger region 103-4 of FIG. 4A.

[0034] For example, the semiconductor substrate SUB is a silicon substrate. An N-drift layer ND (drift region), which is an N-type semiconductor region, is formed on the back surface (lower surface) Sb side of the semiconductor substrate SUB. An N-buffer layer BF, which is an N-type semiconductor region, is formed under the N-drift layer ND of the semiconductor substrate SUB. A P-collector layer PC, which is a P-type semiconductor region, is formed under the N-buffer layer BF of the semiconductor substrate SUB. A collector electrode CE is formed on the back surface Sb (under the P-collector layer PC) of the semiconductor substrate SUB. For example, the collector electrode CE is a metal film made of aluminum (Al) or the like.

[0035] A P-well region PW, which is a P-type semiconductor region, is formed on the surface (upper surface) Sa side of the N-drift layer ND of the semiconductor substrate SUB. The P-well region PW is a region connected to the emitter potential.

[0036] A gate potential trench GT for a gate electrode is formed on the surface Sa side of a semiconductor substrate SUB. A trench gate electrode GE is embedded in the gate potential trench GT via a gate oxide film GI. The trench gate electrode GE is an electrode electrically connected to a gate wiring GW. For example, the trench gate electrode GE is composed of N+ polysilicon or the like. The gate potential trench GT is formed so as to reach from the surface Sa side of the semiconductor substrate SUB to the middle of a P-well region PW. That is, the P-well region PW is formed to a position deeper than the bottom of the gate potential trench GT. The entire part including the bottom of the gate potential trench GT is covered with the P-well region PW. This prevents the electric field strength from concentrating on the bottom of the gate potential trench GT.

[0037] An interlayer insulating film IL is formed on the surface Sa side of the semiconductor substrate SUB so as to cover the gate potential trench GT and the P-well region PW. A contact hole CH for an emitter contact EC is formed in the interlayer insulating film IL. The contact hole CH is formed so as to penetrate the interlayer insulating film IL from the upper side (surface side) of the interlayer insulating film IL and reach an internal region of the P-well region PW. An emitter contact EC is embedded in the inner surface of the contact hole CH. For example, the emitter contact EC is composed of a metal plug such as titanium or tungsten.

[0038] An emitter wiring EW such as an aluminum (Al) film is formed on the interlayer insulating film IL so as to cover the interlayer insulating film IL and the emitter contact EC. Thereby, the emitter wiring EW and the P-well region PW are electrically connected via the emitter contact EC.

[0039] FIG. 6 shows the parasitic capacitance generated in the semiconductor device 900 of the comparative example in FIG. 5. As shown in FIG. 6, in the semiconductor device 900 of the comparative example, the gate potential trench GT is in contact with the P-well region PW connected to the emitter potential via the gate oxide film GI. For this reason, an input capacitance Cies parasitic between the gate and the emitter is formed. Therefore, in the structure of the semiconductor device 900 of the comparative example, it is not possible to generate a feedback capacitance Cres in the gate finger region 103. In the present embodiment, by changing the structure of this gate finger region 103, it is possible to add a feedback capacitance Cres.

[0040] FIGS. 7 and 8 are enlarged plan views of the active cell region and the end portion of the gate finger region of the semiconductor device 100 according to the present embodiment. FIG. 7 is an enlarged plan view of a region 100a including the end portions of the active cell region 101-4, the gate finger region 103-5, and the active cell region 101-5 in FIG. 4A. FIG. 8 is an enlarged plan view of a region 100b including the end portions of the active cell region 101-5 and the gate finger region 103-6 in FIG. 4A. FIGS. 7 and 8 show a state in which the gate wiring, the emitter wiring, and the interlayer insulating film are seen through.

[0041] In this example, in the active cell region 101, a GE (gate-emitter) type trench gate IGBT in which a gate potential trench and an emitter potential trench are arranged in one direction while being separated is formed. Not limited to this, an EGE type trench gate IGBT in which emitter potential trenches are arranged in one direction while being separated on both sides of the gate potential trench may be formed.

[0042] As shown in FIGS. 7 and 8, in the active cell region 101 (101-4 in FIG. 7, 101-5 in FIG. 8), the gate potential trench GT and the emitter potential trench ET are spaced apart and extend linearly in the vertical direction. An N+ source region SA is disposed between the gate potential trench GT and the emitter potential trench ET. The gate potential trench GT and the emitter potential trench ET are arranged to face each other via the N+ source region SA, thereby constituting a GE-type trench gate IGBT. A P well region PW is disposed between the pair of the gate potential trench GT and the emitter potential trench ET that constitute the IGBT.

[0043] FIG. 9 shows a C-C' cross section of the active cell region 101 (in FIG. 7, 101-4; in FIG. 8, 101-5) of the semiconductor device 100 in FIGS. 7 and 8. In the example of FIG. 9, the base configuration is the same as that in FIG. 5.

[0044] As shown in FIG. 9, in the active cell region 101 of the semiconductor device 100, an N-drift layer ND is formed on the semiconductor substrate SUB, similar to FIG. 5. Further, an N buffer layer BF, a P collector layer PC, and a collector electrode CE are laminated in this order on the back surface Sb side of the N-drift layer ND.

[0045] On the surface Sa side of the semiconductor substrate SUB, a gate potential trench GT for a gate electrode and an emitter potential trench ET for an emitter electrode are formed. Similar to FIG. 5, in the gate potential trench GT, a trench gate electrode GE is embedded via a gate oxide film GI inside the trench.

[0046] Similar to the gate potential trench GT, in the emitter potential trench ET, a trench emitter electrode EE is embedded via an emitter oxide film EI inside the trench. The trench emitter electrode EE is an electrode that is electrically connected to the emitter wiring EW. For example, the trench emitter electrode is composed of N+ polysilicon or the like, similar to the trench gate electrode GE.

[0047] The gate potential trench GT and the emitter potential trench ET are formed so as to reach from the surface Sa side of the semiconductor substrate SUB to the middle of the semiconductor substrate SUB. For example, the gate potential trench GT and the emitter potential trench ET have the same width and the same depth. For example, the width of the trench is the lateral width of the opening of the trench. The depth of the trench is the length from the surface of the semiconductor substrate SUB to the bottom of the trench.

[0048] In the region 101a of the semiconductor substrate SUB between the gate potential trench GT and the emitter potential trench ET, an N-hole barrier layer DD, which is an N-type semiconductor region, is formed on the N-drift layer ND. In the region 101a, the N-hole barrier layer DD is formed to the depth of the bottoms of the gate potential trench GT and the emitter potential trench ET. For example, the N-hole barrier layer DD is formed to be deeper from the bottoms of the gate potential trench GT and the emitter potential trench ET toward the center of the region 101a. The N-type impurity concentration of the N-hole barrier layer DD is higher than the N-type impurity concentration of the N-drift layer ND and lower than the N-type impurity concentration of the N+-source region SA of the N+ type.

[0049] In the region 101a, a P-channel layer PH, which is a P-type semiconductor region, is formed on the N-hole barrier layer DD. In the P-channel layer PH, a P+-contact layer PH2, which is a P+-type semiconductor region, is formed in a region on the surface Sa side of the P-channel layer PH that is in contact with the emitter potential trench ET. In the region 101a, an N+-source region SA (emitter region), which is an N+-type semiconductor region, is formed on the P-channel layer PH and the P+-contact layer PH2.

[0050] In the regions 101b of the semiconductor substrate SUB on both sides of the region 101a where the gate potential trench GT and the emitter potential trench ET face each other, a P-well region PW connected to the emitter potential is formed from above the N-drift layer ND to the surface Sa side of the semiconductor substrate SUB. The region 101b includes a region on the side opposite to the side where the emitter potential trench ET is located with respect to the gate potential trench GT, and a region on the side opposite to the side where the gate potential trench GT is located with respect to the emitter potential trench ET. In the region 101b, the P-well region PW is formed to the depth of the bottoms of the gate potential trench GT and the emitter potential trench ET. For example, the P-well region PW is formed to be deeper from the bottoms of the gate potential trench GT and the emitter potential trench ET toward the center of the region 101b.

[0051] On the surface Sa side of the semiconductor substrate SUB, an interlayer insulating film IL is formed so as to cover the gate potential trench GT, the emitter potential trench ET, the N+ source region SA, and the P-well region PW. In the interlayer insulating film IL, a contact hole CH for the emitter contact EC is formed in a region that overlaps in plan view with the position where the N+ source region SA and the emitter potential trench ET are in contact. The contact hole CH is formed to penetrate the interlayer insulating film IL from the upper side (surface side) of the interlayer insulating film IL and reach the N+ source region SA, the P-channel layer PH, the P+ contact layer PH2, and the trench emitter electrode EE. The emitter contact EC is embedded in the inner surface of the contact hole CH.

[0052] Furthermore, on the interlayer insulating film IL, an emitter wiring EW is formed so as to cover the interlayer insulating film IL and the emitter contact EC. Thereby, the emitter wiring EW is electrically connected to the N+ source region SA, the channel layer PH, the P+ contact layer PH2, and the trench emitter electrode EE through the emitter contact EC.

[0053] FIG. 10 is an enlarged plan view of the gate finger region of the semiconductor device 100 according to the present embodiment. FIG. 10 is a plan view further enlarging the gate finger region 103-5 of the region 100a in FIG. 7. In the case of the gate finger region 103-6 of the region 100b in FIG. 8, it has the configuration of the upper half (the upper half of the drawing) of FIG. 10.

[0054] As shown in FIG. 10, in the gate finger region 103 (for example, 103-5), the gate potential trench GT extends and is arranged in a comb shape (finger shape) in a plan view. In the example of FIG. 10, two comb-shaped gate potential trenches GT are arranged opposite to each other. The comb-shaped portion 200 faces the comb-shaped portion 200. The gate potential trench GT includes an extending portion GTa that extends linearly in the lateral direction and a protruding portion GTb that protrudes linearly in the longitudinal direction orthogonally from the extending portion GTa.

[0055] The protruding portions GTb1 and GTb2 extending from the extending portion GTa are connected by a lateral connecting portion GTc at the ends of the extended tips. The extending portion GTa, the protruding portion GTb1, the protruding portion GTb2, and the connecting portion GTc constitute a quadrangular comb-shaped portion 200 in a plan view.

[0056] A gate contact GC is formed on the gate potential trench GT that overlaps with the gate wiring GW in a plan view. For example, a gate contact GC extending in the lateral direction is formed at the center above the connecting portion GTc extending in the lateral direction. As long as it is a region where the gate wiring GW and the gate potential trench GT overlap in a plan view, the gate contact GC may be formed in other regions.

[0057] The gate contact GC has the same structure as the emitter contact EC. That is, a contact hole is formed that penetrates the interlayer insulating film IL from the upper side (surface side) of the interlayer insulating film IL and reaches the trench gate electrode GE, and the gate contact GC is embedded in this contact hole. The gate wiring GW and the trench gate electrode GE are electrically connected via the gate contact GC.

[0058] As shown in FIG. 10, in the gate finger region 103, emitter potential trenches ET are arranged along both sides of the comb-shaped gate potential trench GT. That is, the emitter potential trenches ET are arranged so as to sandwich the comb-shaped gate potential trench GT. The emitter potential trenches ET are spaced apart from the gate potential trench GT and extend linearly in the same direction as the gate potential trench GT at positions on both sides of the gate potential trench GT.

[0059] The emitter potential trench ET includes an outer portion ETa arranged outside the comb-shaped portion 200 of the gate potential trench GT in a plan view and an inner portion ETb arranged inside the comb-shaped portion 200 of the gate potential trench GT in a plan view.

[0060] The outer portion ETa extends in a comb shape along the gate potential trench GT at a position outside the comb-shaped portion 200 of the gate potential trench GT. The outer portion ETa includes an outer portion ETa1 extending laterally opposite to the extending portion GTa of the gate potential trench GT, an outer portion ETa2 extending longitudinally opposite to the protruding portion GTb1 of the gate potential trench GT, an outer portion ETa3 extending longitudinally opposite to the protruding portion GTb2 of the gate potential trench GT, and an outer portion ETa4 extending laterally opposite to the connecting portion GTc of the gate potential trench GT.

[0061] The inner portion ETb is arranged in a square shape in a plan view along the gate potential trench GT at a position inside the comb-shaped portion 200 of the gate potential trench GT. The inner portion ETb includes an inner portion ETb1 extending laterally opposite to the extending portion GTa of the gate potential trench GT, an inner portion ETb2 extending longitudinally opposite to the protruding portion GTb1 of the gate potential trench GT, an inner portion ETb3 extending longitudinally opposite to the protruding portion GTb2 of the gate potential trench GT, and an inner portion ETb4 extending laterally opposite to the connecting portion GTc of the gate potential trench GT.

[0062] The outer part ETa2 and the inner part ETb2 of the emitter potential trench sandwich the protruding part GTb1 of the gate potential trench and face each other. The outer part ETa3 and the inner part ETb3 of the emitter potential trench sandwich the protruding part GTb2 of the gate potential trench and face each other. The outer part ETa4 and the inner part ETb4 of the emitter potential trench sandwich the connecting part GTc of the gate potential trench and face each other.

[0063] An N-drift layer ND is disposed in the region where the gate potential trench GT is sandwiched by the emitter potential trench ET. That is, the N-drift layer ND is disposed in the region between the outer part ETa of the emitter potential trench and the gate potential trench GT, and in the region between the inner part ETb of the emitter potential trench and the gate potential trench GT.

[0064] A P-well region PW is disposed in the region opposite to the side where the gate potential trench GT is located with respect to the emitter potential trench ET. That is, the P-well region PW is disposed inside the region surrounded by the inner part ETb of the emitter potential trench. As shown in FIG. 10, when the outer parts ETa of the emitter potential trench ET face each other in the vertical direction, the P-well region PW is disposed in the region between the outer parts ETa of the opposing emitter potential trenches ET. When the outer part ETa of the emitter potential trench ET faces the end of the semiconductor substrate SUB, the P-well region PW is disposed in the region between the outer part ETa of the emitter potential trench ET and the end of the semiconductor substrate SUB.

[0065] Emitter contacts EC are formed over an emitter wiring EW, an emitter potential trench ET overlapping the emitter wiring EW in plan view, and a P-well region PW. For example, a plurality of emitter contacts EC extending in the vertical direction are arranged in parallel in the horizontal direction. Emitter contacts EC are formed at positions where the inner part ETb2 of the emitter potential trench contacts the P-well region, at the center of the P-well region between the inner part ETb2 and the inner part ETb3 of the emitter potential trench, and at positions where the inner part ETb3 of the emitter potential trench contacts the P-well region. As a result, the emitter wiring EW, the trench emitter electrode EE, and the P-well region PW are electrically connected via the emitter contacts EC.

[0066] FIG. 11 shows an example of a D-D' cross section in the gate finger region 103 (e.g., 103-5) of the semiconductor device 100 of FIG. 10. In the example of FIG. 11, the base configuration is the same as that in FIGS. 5 and 9.

[0067] As shown in FIG. 11, in the gate finger region 103 of the semiconductor device 100, an N-drift layer ND is formed on the semiconductor substrate SUB, similar to FIGS. 5 and 9. Further, a buffer layer BF, a P-collector layer PC, and a collector electrode CE are laminated in this order on the back surface Sb side of the N-drift layer ND.

[0068] A gate potential trench GT and an emitter potential trench ET are formed on the surface Sa side of the semiconductor substrate SUB. Similar to FIGS. 5 and 9, a trench gate electrode GE is embedded in the trench gate potential trench GT via a gate oxide film GI. Similar to FIG. 9, a trench emitter electrode EE is embedded in the trench emitter potential trench ET via an emitter oxide film EI.

[0069] Similar to FIG. 9, the gate potential trench GT and the emitter potential trench ET are formed so as to reach from the surface Sa side of the semiconductor substrate SUB to the middle of the semiconductor substrate SUB. In the example of FIG. 11, the gate potential trench GT and the emitter potential trench ET in the active cell region 101 have the same width and the same depth, similar to FIG. 9.

[0070] As described with reference to FIG. 10, in the gate finger region 103, an emitter potential trench ET is formed so as to sandwich the gate potential trench GT. For example, the gate potential trench GT (e.g., the protruding portion GTb1 in FIG. 10) is sandwiched by the first emitter potential trench ET (e.g., the outer portion ETa2 in FIG. 10) and the second emitter potential trench ET (e.g., the inner portion ETb2 in FIG. 10).

[0071] In the region 103a (the first region) where the emitter potential trench ET sandwiches the gate potential trench GT, an N-drift layer ND is formed up to the surface Sa side of the semiconductor substrate SUB. The region 103a includes the region (opposing region) between the first emitter potential trench ET (e.g., the outer portion ETa2 in FIG. 10) and the gate potential trench GT, and the region (opposing region) between the second emitter potential trench ET (e.g., the inner portion ETb2 in FIG. 10) and the gate potential trench GT. The gate potential trench GT is covered with the N-drift layer ND from the surface Sa side of the semiconductor substrate SUB to the bottom of the trench. In the region 103a, a P-well region PW as shown in FIG. 5 is not formed. Also, in the region 103a, an N+ source region SA as shown in FIG. 9 is not formed, so it does not operate as a transistor.

[0072] In the regions 103b (the second regions) on both sides of the region 103a where the emitter potential trench ET sandwiches the gate potential trench GT, a P-well region PW is formed up to the surface Sa side of the semiconductor substrate SUB on the N-drift layer ND. The region 103b includes the region on the side opposite to the side where the gate potential trench GT is located with respect to the first emitter potential trench ET (e.g., the outer portion ETa2 in FIG. 10), and the region on the side opposite to the side where the gate potential trench GT is located with respect to the emitter potential trench ET (e.g., the inner portion ETb2 in FIG. 10). In the region 103b, a P-well region PW is formed on the N-drift layer ND in the same manner as in FIGS. 5 and 9.

[0073] For example, the P-well region PW is formed in the region 103b from the surface Sa side of the semiconductor substrate SUB to a position deeper than the bottoms of the gate potential trench GT and the emitter potential trench ET. For example, the P-well region PW protrudes from the region 103b toward the region 103a at the positions of the bottoms of the two emitter potential trenches ET, but is separated by the emitter potential trench ET. The P-well regions on both sides of the region 103a tend to spread toward the region 103a side during formation, but are pressed in by the emitter potential trench ET and maintained in a separated state. As a result, the P-well region PW and the gate potential trench GT are separated from each other.

[0074] On the surface Sa side of the semiconductor substrate SUB, an interlayer insulating film IL is formed so as to cover the gate potential trench GT, the emitter potential trench ET, the N-drift layer ND, and the P-well region PW. In the interlayer insulating film IL, a contact hole CH for the emitter contact EC is formed in a region that overlaps, in plan view, with the position where the P-well region PW and the emitter potential trench ET are in contact. The contact hole CH is formed to penetrate the interlayer insulating film IL from the upper side (surface side) of the interlayer insulating film IL and reach the trench emitter electrode EE and the P-well region PW. The emitter contact EC is embedded in the inner surface of the contact hole CH.

[0075] Furthermore, an emitter wiring EW is formed on the interlayer insulating film IL so as to cover the interlayer insulating film IL and the emitter contact EC. As a result, the emitter wiring EW is electrically connected to the trench emitter electrode EE and the P-well region PW via the emitter contact EC.

[0076] FIG. 12 shows the parasitic capacitance generated in the semiconductor device 100 of FIG. 11. As shown in FIG. 12, in the semiconductor device 100 according to the present embodiment, unlike the comparative example of FIG. 6, the gate potential trench GT is not in contact with the P-well region PW. Therefore, a feedback capacitance Cres that parasitically exists between the gate and the collector is formed. Specifically, the feedback capacitance Cres is formed between the entire surface of the gate potential trench GT and the N-drift layer ND. For example, the feedback capacitance Cres depends on the area where the gate potential trench GT and the N-drift layer ND are in contact.

[0077] In the structure of FIG. 12, unlike the comparative example of FIG. 6, since there is no P-well region PW for relaxing the electric field at the bottom of the gate potential trench GT, the electric field strength may concentrate at the bottom. However, the structure in which the emitter potential trenches ET are arranged on both sides of the gate potential trench GT shown in FIG. 12 is equivalent to an EGE type trench gate IGBT, so there is no problem with the breakdown voltage. Further, by narrowing the pitch between the gate potential trench GT and the emitter potential trench ET, the electric field strength applied to the gate potential trench GT can be dispersed to the emitter potential trench ET, so that a decrease in breakdown voltage due to electric field concentration is unlikely to occur.

[0078] FIG. 13 shows another example of the D-D' cross section in the gate finger region 103 of the semiconductor device 100 shown in FIG. 11. In the example of FIG. 13, the width and depth of the gate potential trench GT are different from those in the example of FIG. 11. That is, compared with the example of FIG. 13, the width of the gate potential trench GT is wider and the position of the bottom is deeper. It can also be said that the gate potential trench GT is wider and the position of the bottom is deeper than the emitter potential trench ET. For example, when the trench opening width is widened to form a trench, there is a phenomenon that the position of the bottom of the formed trench becomes deeper. By utilizing this, the trench is formed by widening only the width of the gate potential trench GT, so that the gate potential trench GT can be dug deeper. As a result, the area where the gate potential trench GT is in contact with the N-drift layer ND increases, so that the feedback capacitance Cres can be further increased.

[0079] FIG. 14 shows an example of an E-E' cross-section in the end region 104 (e.g., end region 104-2) of the active cell region 101 of the semiconductor device 100 in FIGS. 7 and 8. The example in FIG. 14 is an example in which the emitter potential trench-gate potential trench-emitter potential trench structure in FIG. 11 is applied to the gate potential trench-emitter potential trench structure.

[0080] As shown in FIG. 14, also at the right end of the active cell region 101, an emitter potential trench ET is added along the gate potential trench GT. Thereby, the emitter potential trench ET is arranged to go around the outer periphery of the active cell region 101. In the example of FIG. 14, similar to the GE type IGBT in FIG. 9, the emitter potential trench ET is formed opposite to the gate potential trench GT. Similar to FIG. 11, an N-drift layer ND is formed in the region 103a between the gate potential trench GT and the emitter potential trench ET. Similar to FIG. 11, P-well regions PW are formed in the regions 103b on both sides of the region 103a. The region 103b includes a region on the side opposite to the side where the emitter potential trench ET is located with respect to the gate potential trench GT and a region on the side opposite to the side where the gate potential trench GT is located with respect to the emitter potential trench ET.

[0081] As in FIG. 14, by adding an emitter potential trench so as to run parallel to the gate potential trench also at the outermost periphery of the active cell region, the P-well region connected to the emitter potential and the gate potential trench can be separated, and a region for forming the feedback capacitance Cres can be added.

[0082] As described above, in this embodiment, in the gate finger region, an emitter potential trench is arranged so as to surround the gate potential trench, and a semiconductor device having a structure (DCBGT: Dumping Capacitance Bare Gate Trench) in which the P-well region connected to the emitter potential by the emitter potential trench is separated from the gate potential trench is provided. That is, an emitter potential trench is added so that the gate potential trench outside the active cell region does not contact the P-well region, and the gate potential trench and the P-well region are separated. With this structure, since the gate potential trench does not contact the P-well region connected to the emitter potential, the capacitance around the gate potential trench contributes to the feedback capacitance Cres. By increasing the feedback capacitance Cres, oscillation during load short circuit can be suppressed. Also, since only the layout outside the active cell region is changed, it does not affect the DC characteristics of the IGBT.

[0083] In Patent Document 1, in the gate finger region, a rectangular gate potential trench is added in a plan view, and the P-well region inside the rectangle of the gate potential trench is removed to provide a semiconductor device with a DCT (Dumping Capacitance Trench) structure in which the feedback capacitance Cres is added. However, in Patent Document 1, since one side of the added gate potential trench is in contact with the P-well region, it may be affected by the gate potential fluctuation (displacement current) during switching. Also, since there is no emitter potential around the gate potential trench, it is difficult to discharge carriers.

[0084] On the other hand, in this embodiment, since there is no portion where the P-well region connected to the emitter potential contacts the gate potential trench, the influence of the gate potential fluctuation (displacement current) during switching can be suppressed. Also, since the added emitter potential trench acts as a parasitic PMOS (well region, N-drift layer, P-collector layer), the discharge of carriers accumulated between the gate potential trench and the emitter potential trench is promoted.

[0085] (Embodiment 2) Next, Embodiment 2 will be described. In this embodiment, an example of adding another semiconductor region between the gate potential trench and the emitter potential trench in the semiconductor device shown in Embodiment 1 will be described.

[0086] FIG. 15 is an example of a cross-sectional view of the gate finger region 103 of the semiconductor device 100 according to this embodiment. FIG. 15 is a modified example of FIG. 11, and similar to FIG. 11, it is a cross-sectional view taken along the line D-D' of the gate finger region 103 in FIG. 10.

[0087] In the example of FIG. 15, a P-channel layer PH is added to the region 103a with respect to the example of FIG. 11. That is, in the region 103a, a P-channel layer PH (channel region), which is a P-type semiconductor region, is formed from the N-drift layer ND to the surface Sa side of the semiconductor substrate SUB. The depth of the P-channel layer PH is shallower than the bottoms of the gate potential trench GT and the emitter potential trench ET. The P-channel layer PH is the same semiconductor region as the P-channel layer PH in the active cell region 101 of FIG. 9. Note that a P-channel layer PH may be added to the end region 104 of the active cell region 101 in FIG. 14 in the same manner as in FIG. 15.

[0088] As shown in FIG. 16, when a P-channel layer PH is added to the region 103a as in FIG. 15, the area forming the feedback capacitance Cres in the (a) portion of the gate potential trench GT is reduced by the added P-channel layer PH. For example, when the feedback capacitance Cres increases excessively in the configuration of Embodiment 1, by adding the P-channel layer PH, it can be adjusted to reduce the feedback capacitance Cres compared to the configuration of Embodiment 1.

[0089] FIG. 17 is another example of a cross-sectional view of the gate finger region 103 of the semiconductor device 100 according to this embodiment. FIG. 17 is a modified example of FIG. 15, and similar to FIG. 15, it is a cross-sectional view taken along the line D-D' of the gate finger region 103 in FIG. 10.

[0090] In the example of FIG. 17, an N-hole barrier layer DD is added to region 103a with respect to the example of FIG. 11. That is, in region 103a, an N-hole barrier layer DD (hole barrier region), which is an N-type semiconductor region, is formed from above the N-drift layer ND to the surface Sa side of the semiconductor substrate SUB. The depth of the N-hole barrier layer DD is deeper than the bottoms of the gate potential trench GT and the emitter potential trench ET, but shallower than the P-well region PW. The N-hole barrier layer DD is the same semiconductor region as the N-hole barrier layer DD in the active cell region 101 of FIG. 9. Note that an N-hole barrier layer DD may be added to the end region 104 of the active cell region 101 of FIG. 14 in the same manner as in FIG. 17.

[0091] As shown in FIG. 18, when an N-hole barrier layer DD is added to region 103a as in FIG. 17, carriers contributing to the feedback capacitance Cres in the (b) portion (oxide film) of the gate potential trench GT increase due to the added N-hole barrier layer DD. Therefore, by adding the N-hole barrier layer DD, the feedback capacitance Cres can be further increased compared to the configuration of Embodiment 1.

[0092] FIG. 19 shows still another example of a cross-sectional view of the gate finger region 103 of the semiconductor device 100 according to the present embodiment. FIG. 19 is a modified example of FIG. 11, similar to FIGS. 15 and 17, and is a cross-sectional view taken along the line D-D' of the gate finger region 103 of FIG. 10.

[0093] The example of FIG. 19 is an example combining FIGS. 15 and 17. That is, in the example of FIG. 19, a P-channel layer PH and an N-hole barrier layer DD are added to region 103a with respect to the example of FIG. 11. In region 103a, an N-hole barrier layer DD similar to that in FIG. 17 is formed above the N-drift layer ND, and further, a P-channel layer PH similar to that in FIG. 15 is formed from above the N-hole barrier layer DD to the surface Sa side of the semiconductor substrate SUB. Note that a P-channel layer PH and an N-hole barrier layer DD may be added to the end region 104 of the active cell region 101 of FIG. 14 in the same manner as in FIG. 19.

[0094] As shown in FIG. 20, when a P-channel layer PH and an N-hole barrier layer DD are added to the region 103a as in FIG. 19, the area forming the feedback capacitance Cres in the (a) portion of the gate potential trench GT decreases by the amount of the added P-channel layer PH, and the carriers contributing to the feedback capacitance Cres in the (b) portion (oxide film) of the gate potential trench GT increase by the amount of the added N-hole barrier layer DD. Therefore, the increase and decrease of the feedback capacitance Cres can be adjusted according to the added amounts of the P-channel layer PH and the N-hole barrier layer DD.

[0095] Note that an input capacitance Cies, which is a special capacitance, is formed between the gate potential trench GT and the emitter potential trench ET, and this capacitance contributes to the stability of the switching characteristics. For example, by adding the N-hole barrier layer DD as in FIG. 19, it is possible to increase not only the feedback capacitance Cres but also the input capacitance Cies. Therefore, the added amount of the N-hole barrier layer DD can be used as a design parameter for adjusting the feedback capacitance Cres and the input capacitance Cies, and the degree of freedom in design can be ensured.

[0096] As described above, in the semiconductor device shown in Embodiment 1, a P-channel layer PH or an N-hole barrier layer DD may be added between the gate potential trench and the emitter potential trench. Thereby, the formed feedback capacitance Cres can be adjusted, and the input capacitance Cies can also be adjusted. For example, by increasing the feedback capacitance Cres according to the addition of the P-channel layer PH, oscillation during load short circuit can be further suppressed. By adjusting the feedback capacitance Cres and the input capacitance Cies according to the addition of the N-hole barrier layer DD, the switching characteristics can be set more appropriately.

[0097] Although the invention made by the present inventor has been specifically described based on the embodiments, it goes without saying that the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

[0098] For example, in the semiconductor device according to the above embodiment, the conductivity type (P-type or N-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. may be inverted. Therefore, when one of the N-type and P-type conductivity types is defined as the first conductivity type and the other is defined as the second conductivity type, the first conductivity type can be P-type and the second conductivity type can be N-type, or conversely, the first conductivity type can be N-type and the second conductivity type can be P-type.

Explanation of Reference Numerals

[0099] 1 Semiconductor device 2 Semiconductor substrate 3 Drift region 4 Well region 5 Gate potential trench 6, 6a, 6b Predetermined potential trench 7 First region 8, 8a, 8b Second region 10 Active cell region 11 Gate finger region 100 Semiconductor device 100a, 100b Region 101 Active cell region 101a, 101b Region 102 Non-active cell region 103 Gate finger region 103a, 103b Region 104 End region 200 Comb-shaped portion BF N-buffer layer CE Collector electrode CH Contact hole DD N-hole barrier layer EC Emitter contact EE Trench emitter electrode EI Emitter oxide film EP Emitter pad ET Emitter potential trench ETa Outer portion ETb Inner portion EW Emitter wiring GC Gate contact GE Trench Gate Electrode GI Gate Oxide Film GP Gate Pad GT Gate Potential Trench GTa Extension GTb Protrusion GTc Connection Part GW Gate Wiring IL Interlayer Insulation Film ND N-Drift Layer PC P-Collector Layer PH P-Channel Layer PH2 P+ Contact Layer PW P-Well Region SA N+ Source Region Sa Surface Sb Back Surface SUB Semiconductor Substrate

Claims

1. A semiconductor substrate including an active cell region in which a transistor is operably formed and a gate finger region for drawing out a gate wiring, in the gate finger region, a gate potential trench formed on the main surface side of the semiconductor substrate, a predetermined potential trench having a predetermined potential different from that of the gate and formed so as to sandwich the gate potential trench on the main surface side of the semiconductor substrate, a drift region of a first conductivity type formed in a first region between the gate potential trench and the predetermined potential trench in the semiconductor substrate, a well region of a second conductivity type formed in a second region above the drift region in the semiconductor substrate and on the side opposite to the side where the gate potential trench is located with respect to the predetermined potential trench, A semiconductor device comprising:

2. The well region is connected to the predetermined potential, The gate potential trench and the well region are separated from each other. The semiconductor device according to claim 1.

3. The gate potential trench is covered by the drift region from the main surface side of the semiconductor substrate to the bottom of the gate potential trench. The semiconductor device according to claim 1.

4. The width of the gate potential trench is wider than the width of the predetermined potential trench. The semiconductor device according to claim 1.

5. The depth of the gate potential trench is deeper than the depth of the predetermined potential trench. The semiconductor device according to claim 1.

6. The first region includes a channel region of the second conductivity type formed above the drift region. The semiconductor device according to claim 1.

7. The first region includes a hole barrier region of the first conductivity type formed above the drift region. The semiconductor device according to claim 1.

8. The first region includes a channel region of the second conductivity type formed above the hole barrier region. The semiconductor device according to claim 7.

9. At an end of the active cell region extending in a direction orthogonal to the direction in which the gate finger region extends in plan view, the gate potential trench, the predetermined potential trench formed so as to face the gate potential trench, the drift region formed in a region between the gate potential trench and the predetermined potential trench at the end, The semiconductor device according to claim 1.

10. The gate finger region is a region that is outside the active cell region in a plan view and extends along a first end portion of the active cell region. The semiconductor device according to claim 1.

11. Comprising a plurality of the active cell regions, The gate finger region is a region between the plurality of active cell regions. The semiconductor device according to claim 1.

12. An interlayer insulating film formed on the semiconductor substrate, A predetermined potential wiring formed on the interlayer insulating film, A predetermined potential contact that connects the predetermined potential wiring, the predetermined potential trench, and the well region through the interlayer insulating film. The semiconductor device according to claim 1, comprising:

13. An interlayer insulating film formed on the semiconductor substrate, A gate wiring formed on the interlayer insulating film, A gate contact that connects the gate wiring and the gate potential trench through the interlayer insulating film. The semiconductor device according to claim 1, comprising:

14. The transistor is an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device according to claim 1.

15. The predetermined potential trench is an emitter potential trench connected to an emitter potential. The semiconductor device according to claim 14.

16. Comprising a semiconductor substrate including an active cell region in which a transistor is formed to be operable, At an end of the active cell region, A gate potential trench formed on a main surface side of the semiconductor substrate, A predetermined potential trench having a predetermined potential different from that of the gate, formed on the main surface side of the semiconductor substrate so as to face the gate potential trench, A drift region of a first conductivity type formed in a first region between the gate potential trench and the predetermined potential trench in the semiconductor substrate, A second conductivity type well region formed in a region above the drift region in the semiconductor substrate and in a second region on a side opposite to the side where the gate potential trench is located with respect to the predetermined potential trench. A semiconductor device, comprising:

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