Semiconductor device

Abstract

To provide a semiconductor device capable of preventing a leakage current from a Schottky junction side to a semiconductor substrate side when a forward voltage is applied.SOLUTION: A semiconductor device includes: an n-type first semiconductor region 12 having a main surface 12a; a p-type semiconductor substrate 11 in contact with the first semiconductor region on a side opposite to the main surface; a first electrode layer 13A provided on the main surface and forms a Schottky junction 14 with the first semiconductor region; an n-type second semiconductor region 16 formed on a main surface side in the first semiconductor region and having higher concentration than the first semiconductor region; a second electrode layer 13K provided on the main surface and forming an ohmic junction with the second semiconductor region; and a p-type guard-ring region 17 arranged between the Schottky junction and the second semiconductor region so as to be closer to the Schottky junction and spaced apart from the Schottky junction.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a Schottky barrier diode. The Schottky barrier diode described in Patent Document 1 has an active region in which a Schottky metal is in Schottky contact with the surface of an epitaxial semiconductor layer, and an outer peripheral trench dug from the surface of the epitaxial semiconductor layer at a boundary portion between the active region and an outer peripheral region surrounding the active region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] One embodiment of the present disclosure relates to a semiconductor device capable of preventing a leakage current from the Schottky junction side to the semiconductor substrate side when a forward voltage is applied.

[0005] The semiconductor device according to the present disclosure has a main surface, an n-type first semiconductor region, a p-type semiconductor substrate in contact with the first semiconductor region on the side opposite to the main surface, a first electrode layer provided on the main surface and forming a Schottky junction with the first semiconductor region, an n-type second semiconductor region formed on the main surface side in the first semiconductor region and having a higher concentration than the first semiconductor region, a second electrode layer provided on the main surface and forming an ohmic junction with the second semiconductor region, and a p-type guard ring region disposed closer to the Schottky junction and spaced apart from the Schottky junction between the Schottky junction and the second semiconductor region.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

[0007] [Detailed Description] Hereinafter, various exemplary embodiments will be described with reference to the drawings. The same or corresponding parts in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted.

[0008] First, the basic structure of the semiconductor device will be described. Figure 1 is a plan view of a semiconductor device according to an embodiment.

[0009] The semiconductor device 1 includes a rectangular parallelepiped-shaped chip 2 (semiconductor chip). The chip 2 has a first main surface 3 on one side and a second main surface 4 (see Figure 3) on the other side. The chip 2 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4. The thickness direction of the chip 2 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The direction from the first main surface 3 (upper surface) to the second main surface 4 (back surface) of the semiconductor substrate 11 is defined as the positive direction of the Z-axis, and the negative direction of the Z-axis indicates the direction from the second main surface 4 to the first main surface 3 of the semiconductor substrate 11. The positive direction of the Z-axis corresponds to the depth direction of the chip 2.

[0010] The first main surface 3 and the second main surface 4 are each perpendicular to the Z-axis. The planar shape (shape in plan view) of the first main surface 3 as viewed from the normal direction (Z-axis direction) of the first main surface 3 is rectangular (quadrilateral). The shape in plan view of the second main surface 4 is rectangular (quadrilateral). The first side surface 5A and the second side surface 5B that constitute two opposite sides of the rectangle in plan view extend along the Y-axis direction, respectively. The third side surface 5C and the fourth side surface 5D that constitute the other two opposite sides of the rectangle in plan view extend along the X-axis direction, respectively. These adjacent side surfaces are orthogonal in plan view, but can also intersect at an angle other than orthogonal.

[0011] An example of the semiconductor material constituting the chip 2 is silicon (Si). A compound semiconductor can also be used as the semiconductor material constituting the chip 2. Examples of compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and mixed crystal semiconductors using these semiconductors. As the III-V compound semiconductor, Ga-containing semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN) can be used. As the IV-IV compound semiconductor, Si-containing semiconductors such as silicon carbide (SiC) and silicon germanium (SiGe) can be used. Hereinafter, unless otherwise specified, the semiconductor material constituting the chip 2 is silicon.

[0012] The semiconductor device 1 includes a plurality of device regions 6 provided on the first main surface 3. There is a gap between each device region 6 and each side surface (from the first side surface 5A to the fourth side surface 5D) of the chip 2. The number, arrangement, and shape of the device regions 6 are arbitrary and are not limited to a specific number, arrangement, and shape. Each of the plurality of device regions 6 includes a functional device formed by using regions inside and outside the chip 2. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined.

[0013] The semiconductor switching device includes at least one of, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0014] The plurality of device regions 6 includes a Schottky barrier diode region 10. With reference to FIGS. 2 and 3, the semiconductor device 1 will be described focusing on the Schottky barrier diode region 10. FIG. 2 is an enlarged view of region II in FIG. 1. FIG. 3 is a schematic diagram of a cross-sectional configuration taken along line III-III in FIG. 2. In the following description, the Schottky barrier diode may be referred to as an "SBD". In the following description, an example of a p-type impurity (trivalent element) is boron (B), and examples of n-type impurities (pentavalent elements) are phosphorus (P) or arsenic (As).

[0015] The Schottky barrier diode region 10 (SBD region 10) has a p-type semiconductor substrate 11, an n-type semiconductor layer (first semiconductor region) 12, a first electrode layer 13A, and a second electrode layer 13K.

[0016] The semiconductor substrate 11 is formed of silicon. The semiconductor substrate 11 may be a common semiconductor substrate 11 for the plurality of device regions 6 in the semiconductor device 1. The back surface of the semiconductor substrate 11 is the second main surface 4 of the chip 2. In the present embodiment, the semiconductor substrate 11 is grounded. A reference potential may be applied to the semiconductor substrate 11.

[0017] The semiconductor substrate 11 has a p-type underlying substrate (first part) 111. The underlying substrate 111 is formed of silicon. The p-type impurity concentration of the underlying substrate 111 may be 1×10 16 cm -3 or more and 1×10 19 cm -3 or less. An example of the thickness of the underlying substrate 111 may be 50 um or more and 400 um or less. In the present embodiment, the underlying substrate 111 is grounded.

[0018] The semiconductor substrate 11 may have a p-type epitaxial semiconductor layer (second part) 112 on the underlying substrate 111. The epitaxial semiconductor layer 112 is formed of silicon. The epitaxial semiconductor layer 112 is a layer formed by epitaxial growth on the underlying substrate 111. The p-type impurity concentration of the epitaxial semiconductor layer 112 may be lower than the p-type impurity concentration of the underlying substrate 111. The p-type impurity concentration in the epitaxial semiconductor layer 112 may be 1×10 16 cm -3 or more and 1×10 18 cm -3 or less. The thickness of the epitaxial semiconductor layer 112 may be 1 um or more and 30 um or less.

[0019] The configuration of the semiconductor substrate 11 is not limited to the two-layer structure as shown in FIG. 3, and a single-layer structure may also be used. The semiconductor substrate 11 may have a plurality of layers of three or more layers.

[0020] The semiconductor layer 12 has a main surface 12a. In the form shown in FIG. 3, the main surface 12a corresponds to the first main surface 3 of the chip. The semiconductor layer 12 is in contact with the semiconductor substrate 11 on the side opposite to the main surface 12a. The semiconductor layer 12 in the present embodiment has an n-type buried semiconductor layer 121 and an n-type epitaxial semiconductor layer 122.

[0021] The buried semiconductor layer 121 is a layer buried between the semiconductor substrate 11 and the epitaxial semiconductor layer 112. The buried semiconductor layer 121 is formed of silicon. The n-type impurity concentration of the buried semiconductor layer 121 is 5×10 17 cm-3 Above and 1×10 21 cm -3 Below may be acceptable. The thickness of the embedded semiconductor layer 121 may be 0.5 um or more and 5 um or less.

[0022] The embedded semiconductor layer 121 can be formed by ion implantation on the surface of the substrate that is to become the semiconductor substrate 11 (hereinafter referred to as the "first substrate"). The thickness of the first substrate may be the thickness of the semiconductor substrate 11 plus the thickness of the embedded semiconductor layer 121. For example, when the semiconductor substrate 11 has an epitaxial semiconductor layer 112, the epitaxial semiconductor layer 112 is formed with a thickness assuming the formation of the embedded semiconductor layer 121. The embedded semiconductor layer 121 is, for example, a layer for suppressing parasitic operation.

[0023] The epitaxial semiconductor layer 122 is a layer formed by epitaxial growth on the embedded semiconductor layer 121. The epitaxial semiconductor layer 122 is formed of silicon. The n-type impurity concentration of the epitaxial semiconductor layer 122 may be lower than that of the embedded semiconductor layer 121. The n-type impurity concentration of the epitaxial semiconductor layer 122 is 1×10 15 cm -3 Above and 1×10 18 cm -3 Below may be acceptable. An example of the thickness of the epitaxial semiconductor layer 122 is 0.5 um or more and 30 um or less.

[0024] The embedded semiconductor layer 121 and the epitaxial semiconductor layer 122 may be common layers for a plurality of device regions 6 in the semiconductor device 1. In one embodiment, the embedded semiconductor layer 121 may be formed for each of the plurality of device regions 6 according to the device characteristics of each of the plurality of device regions 6. The device region 6 may not have the embedded semiconductor layer 121.

[0025] The first electrode layer 13A is formed on the main surface 12a of the semiconductor layer 12. The first electrode layer 13A functions as an anode in a Schottky barrier diode (SBD). The first electrode layer 13A is formed of a metal that makes a Schottky contact with the semiconductor layer 12. Therefore, the contact region between the first electrode layer 13A and the semiconductor layer 12 is the Schottky junction 14. Examples of the material of the first electrode layer 13A include cobalt (Co) silicide, titanium, tungsten, hafnium, aluminum, chromium, and the like. The first electrode layer 13A forms a Schottky barrier (potential barrier) of, for example, 0.5 eV or more and 0.9 eV or less between itself and the semiconductor constituting the semiconductor layer 12. The thickness of the first electrode layer 13A may be 0.01 μm or more and 1 μm or less. The planar shape of the first electrode layer 13A is not limited. An example of the planar shape of the first electrode layer 13A is a rectangle as shown in FIG. 2.

[0026] In the main surface 12a of the semiconductor layer 12, a semiconductor region (second semiconductor region) 16 having the same conductivity type (n-type) as the semiconductor layer 12 is formed at a distance from the first electrode layer 13A. The n-type impurity concentration of the semiconductor region 16 may be higher than the n-type impurity concentration of the epitaxial semiconductor layer 122. The n-type impurity concentration of the semiconductor region 16 may be 1×10 17 cm -3 or more and 1×10 19 cm -3 or less. The thickness of the semiconductor region 16 may be 0.01 μm or more and 0.3 μm or less. In the present embodiment, the semiconductor region 16 surrounds the first electrode layer 13A in a plan view.

[0027] The second electrode layer 13K is formed on the semiconductor region 16 among the main surfaces 12a. The second electrode layer 13K functions as a cathode in the SBD. The second electrode layer 13K is formed of a metal that makes an ohmic contact with the semiconductor region 16. Therefore, the contact region between the second electrode layer 13K and the semiconductor region 16 is the ohmic junction 15. Examples of the material of the second electrode layer 13K are titanium, tungsten, hafnium, aluminum, chromium, etc. The thickness of the second electrode layer 13K may be 0.01 μm or more and 1 μm or less. In the form where the semiconductor region 16 surrounds the first electrode layer 13A in plan view as described above, the second electrode layer 13K also surrounds the first electrode layer 13A.

[0028] On the main surface 12a of the semiconductor layer 12, a guard ring region 17 is formed closer to the Schottky junction 14 between the Schottky junction 14 and the semiconductor region 16. The guard ring region 17 is, for example, a region for preventing a breakdown voltage drop due to electric field concentration when a reverse voltage is applied.

[0029] The guard ring region 17 of the present embodiment surrounds the Schottky junction 14 in plan view. The guard ring region 17 is formed slightly separated from the Schottky junction 14. The distance d between the guard ring region 17 and the Schottky junction 14 is the distance at which the depletion layer generated when a reverse voltage is applied spreads to the guard ring region 17 (in other words, is connected to the guard ring region 17 side). An example of the distance d is 0.05 μm or more and 2 μm or less. The distance d may also be 0.01 μm or more and 3 μm or less. The guard ring region 17 is a p-type semiconductor region the same as the semiconductor substrate 11. The p-type impurity concentration of the guard ring region 17 is 1×10 18 cm -3 or more and 1×10 21 cm -3 or less. The thickness of the guard ring region 17 may be 0.05 μm or more and 0.3 μm or less.

[0030] As shown in FIG. 3, a p-type semiconductor region 171 may be formed in the semiconductor layer 12 so as to include the guard ring region 17. The semiconductor region 171 is a region for ensuring breakdown voltage. The p-type impurity concentration of the semiconductor region 171 may be lower than that of the guard ring region 17. The p-type impurity concentration of the semiconductor region 171 may be 1×10 16 cm -3 or more and 1×10 19 cm -3 or less. The semiconductor region 171 is formed deeper than the guard ring region 17. The thickness of the semiconductor region 171 may be 0.2 μm or more and 5 μm or less. In plan view, the end of the semiconductor region 171 on the Schottky junction 14 side may be the same as that of the guard ring region 17. That is, in plan view, the distance between the semiconductor region 171 and the Schottky junction 14 is the same as the distance d. The semiconductor region 171 is also spaced apart from the semiconductor region 16 in plan view.

[0031] In the form in which the semiconductor region 171 is formed in the semiconductor layer 12, after the semiconductor region 171 is formed by ion implantation, the guard ring region 17 can be formed by selectively implanting further impurities into the region to be the guard ring region 17.

[0032] An insulating layer 18 may be provided on the main surface 12a side of the semiconductor layer 12. The insulating layer 18 may be formed of silicon dioxide (SiO2), silicon nitride (SiN), or the like.

[0033] In the form illustrated in FIG. 3, the insulating layer 18 is formed to have a first opening region 181 and a second opening region 182. The first electrode layer 13A is disposed in the first opening region 181. Thereby, the first electrode layer 13A is disposed so as to be in contact with the main surface 12a exposed from the first opening region 181. In the present embodiment, the guard ring region 17 is also disposed in the first opening region 181. The second opening region 182 is located on the semiconductor region 16, and the second electrode layer 13K is disposed in the second opening region 182. Thereby, the second electrode layer 13K is disposed so as to be in contact with the semiconductor region 16 exposed from the second opening region 182. In such an arrangement, the first electrode layer 13A and the second electrode layer 13K can be separated by the insulating layer 18.

[0034] The portion where the insulating layer 18 is formed may have a STI (Shallow Trench Isolation) structure. That is, the insulating layer 18 may be embedded in a shallow groove 18a formed by etching or the like from the main surface 12a. The insulating layer 18 is formed according to the material for forming the insulating layer 18. For example, the insulating layer 18 may be formed by thermally oxidizing a part of the main surface 12a, or may be formed by a sputtering method, a CVD method, or the like.

[0035] In a plan view, an isolation structure portion 20 for element isolation may be formed outside the semiconductor region 16. The isolation structure portion 20 of the present embodiment surrounds the semiconductor region 16 in a plan view. In the SBD region 10, the region surrounded by the isolation structure portion 20 functions substantially as a Schottky barrier diode (SBD) in a plan view. The isolation structure portion 20 has a function of separating a region that functions substantially as an SBD in the SBD region 10 from other device regions 6. As illustrated in FIG. 3, an example of the isolation structure portion 20 has a DTI (Deep Trench Isolation) structure.

[0036] The isolation structure portion 20 in this embodiment has a groove 21 extending from the first main surface 3 (main surface 12a) side to the underlying substrate 111, and the groove 21 is filled with a conductive material 23 via an insulating layer 22. The insulating layer 22 is formed of, for example, silicon dioxide. An example of the conductive material 23 is polysilicon. A sinker layer (impurity-added layer) 24 may be formed on the outer periphery of the groove 21. The sinker layer 24 is an n-type semiconductor layer. The n-type impurity concentration of the sinker layer 24 is 1×10 16 cm -3 or more and 1×10 20 cm -3 or less.

[0037] As shown in FIG. 3, the insulating layer 18 may have a third opening region 183 that exposes the conductive material 23 included in the isolation structure portion 20. By connecting a terminal to the conductive material 23 exposed from the third opening region 183, a desired potential (reference potential, ground potential, etc.) can be applied to the conductive material 23.

[0038] The configuration shown in FIG. 3 is manufactured, for example, as follows. That is, as described above, an epitaxial semiconductor layer 122 is formed on the semiconductor substrate 11 on which the buried semiconductor layer 121 is formed.

[0039] Thereafter, the isolation structure portion 20 is formed. Specifically, a groove 21 is formed by etching or the like from the main surface 12a of the epitaxial semiconductor layer 122 toward the underlying substrate 111, and ion implantation is performed on the inner surface of the groove 21 to form the sinker layer 24. Thereafter, the insulating layer 22 is formed by thermally oxidizing the inner surface of the groove 21. After removing the insulating layer 22 at the bottom of the groove 21, the groove 21 is filled with the conductive material 23. When forming the insulating layer 22, after thermally oxidizing the inner surface of the groove 21, silicon dioxide may be further formed using TEOS (Si(OC2H5)4).

[0040] Next, after forming a groove 18a by etching or the like so as to have a first opening region 181, a second opening region 182, and a third opening region 183 in the main surface 12a of the epitaxial semiconductor layer 122, an insulating layer 18 is formed in the groove 18a by a sputtering method, a CVD method, or the like.

[0041] After forming the insulating layer 18, a semiconductor region 171 is formed by ion implantation according to the conductivity type of the region to be formed, and then a guard ring region 17 is formed and a semiconductor region 16 is formed.

[0042] Thereafter, a first electrode layer 13A and a second electrode layer 13K are formed respectively. The first electrode layer 13A and the second electrode layer 13K can be formed by, for example, a CVD method. When forming the first electrode layer 13A, other regions may be masked so that the first electrode layer 13A is formed at a position separated from the guard ring region 17 by a distance d.

[0043] The semiconductor device 1 (specifically, the SBD region 10) has a main surface 12a, an n-type semiconductor layer 12, a p-type semiconductor substrate 11 in contact with the semiconductor layer 12 on the side opposite to the main surface 12a, a first electrode layer 13A provided on the main surface 12a and forming a Schottky junction 14 with the semiconductor layer 12, an n-type semiconductor region 16 formed on the main surface 12a side in the semiconductor layer 12 and having a higher concentration than the semiconductor layer 12, a second electrode layer 13K provided on the main surface 12a and forming an ohmic junction 15 with the semiconductor region 16, and a p-type guard ring region 17 disposed closer to the Schottky junction 14 and spaced apart from the Schottky junction 14 between the Schottky junction 14 and the semiconductor region 16.

[0044] In the above configuration, the first electrode layer 13A forms a Schottky junction 14 with the n-type semiconductor layer 12. The semiconductor region 16 is a region formed in the semiconductor layer 12 and having a higher concentration of n-type, and the second electrode layer 13K forms an ohmic junction 15 with the semiconductor layer 12. Therefore, the SBD region 10 functions as a Schottky barrier diode in the semiconductor device 1.

[0045] The semiconductor device 1 has a p-type guard ring region 17 formed in an n-type semiconductor layer 12. In this case, since the boundary portion between the guard ring region 17 and the semiconductor layer 12 corresponds to a pn junction, a depletion layer is formed. When a reverse voltage is applied to the SBD region 10, the depletion layer at the Schottky junction 14 is connected to the depletion layer at the boundary portion between the guard ring region 17 and the semiconductor layer 12, so that a depletion layer also exists in the gap portion between the Schottky junction 14 and the guard ring region 17. Therefore, an electric field relaxation effect can be obtained at the end (termination end) of the Schottky junction 14, and the breakdown voltage can be ensured. At the end of the contact region between the first electrode layer 13A and the semiconductor layer 12 (the Schottky junction 14 in this embodiment), the semiconductor crystal structure is likely to be disturbed. When such a disturbance of the semiconductor crystal structure occurs, there is also a possibility that a leakage current is generated between the first electrode layer 13A and the second electrode layer 13K when a reverse voltage is applied, but the above-mentioned depletion layer can also prevent the leakage current.

[0046] The above guard ring region 17 is p-type and is formed in the n-type semiconductor layer 12. The n-type semiconductor layer 12 is in contact with the p-type semiconductor substrate 11. Therefore, the SBD region 10 has a pnp-type parasitic transistor from the guard ring region 17 toward the semiconductor substrate 11. Thus, even if the above parasitic transistor exists in the SBD region 10, since the guard ring region 17 is slightly separated from the Schottky junction 14, the pnp-type parasitic transistor does not turn on when a forward voltage is applied. As a result, a leakage current toward the semiconductor substrate 11 caused by the parasitic transistor when a forward voltage is applied can be prevented. Therefore, in the above semiconductor device 1, while maintaining the effects such as electric field relaxation when a reverse voltage is applied, a leakage current from the Schottky junction 14 toward the semiconductor substrate 11 when a forward voltage is applied can be prevented.

[0047] In a form where the distance d between the Schottky junction 14 and the guard ring region 17 is 0.05 μm or more and 2 μm or less, when a reverse voltage is applied, the depletion layer easily spreads to the guard ring region 17. Therefore, it is easy to relieve the electric field concentration when a reverse voltage is applied, and it is possible to further prevent leakage current.

[0048] In a form where the Schottky junction 14 is surrounded by the guard ring region 17 in a plan view, it is possible to relieve the electric field concentration at the outer periphery of the Schottky junction 14. Since the guard ring region 17 is disposed between the semiconductor region 16 and the Schottky junction 14, in a form where the guard ring region 17 surrounds the Schottky junction 14, the guard ring region 17 is surrounded by the semiconductor region 16.

[0049] The configuration effectiveness of the semiconductor device 1 (specifically, the SBD region 10) will be further described with reference to FIGS. 4 and 5.

[0050] FIG. 4 is a drawing focusing on the main part in the present disclosure in the SBD region 10 shown in FIG. 3. The SBD region shown in FIG. 4 is referred to as an SBD region 10A. FIG. 5 is a drawing showing a configuration example of a reference Schottky barrier diode. The SBD region shown in FIG. 5 is referred to as an SBD region 10ref. In the description of FIGS. 4 and 5, for convenience of explanation, elements corresponding to the elements shown in FIGS. 2 and 3 are denoted by the same reference numerals, and redundant explanations are omitted.

[0051] In FIG. 4, an n-type semiconductor region (first semiconductor region) 12A is formed on a grounded p-type semiconductor substrate 11. The p-type impurity concentration of the semiconductor substrate 11 may be the same as that of the epitaxial semiconductor layer 112 shown in FIG. 3.

[0052] The semiconductor region 12A corresponds to the semiconductor layer 12 shown in FIG. 3. Therefore, the main surface of the semiconductor region 12A is also referred to as the main surface 12a. In the SBD region 10A shown in FIG. 4, the main surface of the semiconductor substrate 11 and the main surface 12a of the semiconductor region 12A are common. In the configuration shown in FIG. 4, for example, the semiconductor region 12A can be formed by implanting n-type impurities from the main surface of the semiconductor substrate 11. In the configuration shown in FIG. 4, the portion of the semiconductor region 12A on the side opposite to the main surface 12a is in contact with the semiconductor substrate 11.

[0053] An insulating layer 18 having a first opening region 181 and a second opening region 182 is formed on the main surface 12a. A first electrode layer 13A is formed in the first opening region 181. As a result, similar to the case of the configuration shown in FIG. 3, the first electrode layer 13A is in contact with the semiconductor region 12A, and a Schottky junction 14 is formed. The first electrode layer 13A functions as an anode. In the semiconductor region 12A, an n-type semiconductor region 16 is formed at a position corresponding to the second opening region 182. A second electrode layer 13K is formed in the second opening region 182. As a result, similar to the case of the configuration shown in FIG. 3, the second electrode layer 13K is in contact with the semiconductor region 16, and an ohmic junction 15 is formed. The second electrode layer 13K functions as a cathode.

[0054] The shape etc. of the first electrode layer 13A and the second electrode layer 13K in plan view (when viewed from the Z-axis direction) are the same as those of the SBD region 10 shown in FIG. 3.

[0055] In the semiconductor region 12A, a p-type guard ring region 17 is formed closer to the Schottky junction 14 between the Schottky junction 14 and the semiconductor region 16. The guard ring region 17 is arranged slightly spaced apart from the Schottky junction 14. The distance d between the Schottky junction 14 and the guard ring region 17 is as described above. In the configuration shown in FIG. 4, the p-type impurity concentration of the guard ring region 17 may be the same as that of the guard ring region 17 shown in FIG. 3.

[0056] Even in the SBD region 10A shown in FIG. 4, in a plan view, the Schottky junction 14 is surrounded by the guard ring region 17, and the guard ring region 17 may be surrounded by the semiconductor region 16.

[0057] The configuration of the reference SBD region 10ref shown in FIG. 5 is different from the SBD region 10A shown in FIG. 4 in that the guard ring region 17 is in contact with the end of the contact region 141 between the first electrode layer 13A and the main surface 12a (semiconductor layer 12).

[0058] When incorporating a Schottky barrier diode into a device (or integrated circuit) having a plurality of device regions 6 as shown in FIG. 1, as shown in FIGS. 4 and 5, the first electrode layer 13A functioning as an anode and the second electrode layer 13K functioning as a cathode are arranged on the same surface side. At the end of the contact region 141, there is a tendency for the semiconductor crystal structure to be disturbed. Therefore, when a reverse voltage is applied, there is a possibility of leakage current occurring between the first electrode layer 13A and the second electrode layer 13K. Also, since an electric field tends to concentrate at the end of the contact region 141 when a reverse voltage is applied, the breakdown voltage decreases. To solve such problems, as shown in FIG. 5, it is conceivable to arrange the guard ring region 17 so that the guard ring region 17 is in contact with the end of the contact region 141. In this case, since a pn junction is formed at the boundary between the guard ring region 17 and the semiconductor region 12A, a depletion layer surely exists at the end of the contact region 141. Thus, while achieving electric field relaxation when a reverse voltage is applied, the leakage current can also be suppressed.

[0059] However, in the configuration shown in FIG. 5, a p-type guard ring region 17, an n-type semiconductor region 12A, and a p-type semiconductor substrate 11 are arranged from the first electrode layer 13A toward the back surface of the semiconductor substrate 11. In such an arrangement, a pnp-type parasitic transistor exists in the SBD region 10ref.

[0060] In the configuration shown in FIG. 5, since the guard ring region 17 is in contact with the contact region 141, the guard ring region 17 is in contact with the first electrode layer 13A. Therefore, when a forward voltage is applied between the first electrode layer 13A and the second electrode layer 13K of the SBD region 10ref, a voltage is also applied to the above pnp-type parasitic transistor. As a result, when a forward voltage is applied, leakage current flows into the semiconductor substrate 11 through the current path as indicated by the dashed arrow in FIG. 5.

[0061] In the SBD region 10A shown in FIG. 4, the above pnp-type parasitic transistor also exists. However, in the SBD region 10A, since the guard ring region 17 is separated from the Schottky junction 14, the guard ring region 17 is not in contact with the first electrode layer 13A either. Therefore, even when a forward voltage is applied between the first electrode layer 13A and the second electrode layer 13K of the SBD region 10A, no voltage is applied to the above pnp-type parasitic transistor. As a result, unlike the case of the SBD region 10ref shown in FIG. 5, leakage current flowing toward the semiconductor substrate 11 can be prevented.

[0062] In the SBD region 10A shown in FIG. 4, the guard ring region 17 is formed in the semiconductor region 12A. Therefore, since a pn junction is formed at the boundary between the guard ring region 17 and the semiconductor region 12A, a depletion layer exists in the vicinity of the boundary between the guard ring region 17 and the semiconductor region 12A. When a reverse voltage is applied to the SBD region 10A, the depletion layer formed near the Schottky junction 14 is connected to the depletion layer of the above pn junction. Therefore, as schematically shown in FIG. 6, when a reverse voltage is applied between the first electrode layer 13A and the second electrode layer 13K of the SBD region 10A, the depletion layer 30 generated extends to the guard ring region 17. Due to the spread of such a depletion layer 30, the depletion layer 30 also exists in the gap between the guard ring region 17 and the Schottky junction 14. Therefore, even if the guard ring region 17 is separated from the Schottky junction 14, the electric field concentration at the end of the Schottky junction 14 when a reverse voltage is applied can be alleviated, and the leakage current between the first electrode layer 13A and the second electrode layer 13K when a reverse voltage is applied can also be suppressed.

[0063] As described above, while this is a drawing focusing on the gist of the present disclosure in the SBD region 10 shown in FIG. 3, the semiconductor device 1 (specifically, the Schottky barrier diode region) may be configured as shown in FIG. 4.

[0064] As understood from the above description, according to the above-described semiconductor device, it is possible to prevent leakage current from the Schottky junction side to the semiconductor substrate side when a forward voltage is applied.

[0065] Although various exemplary embodiments have been described above, the present disclosure is not limited to the above-described exemplary embodiments, and various omissions, substitutions, and changes may be made. It is possible to combine elements in different embodiments to form other embodiments. From the above description, it will be understood that all aspects of the various embodiments of the present disclosure are illustrative, and various changes can be made without departing from the scope and gist of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and gist are indicated by the claims.

[0066] Hereinafter, characteristic examples extracted from the descriptions of this specification and the drawings are shown.

[0067] [A1] (FIGS. 1 to 4) having a main surface (12a) and an n-type first semiconductor region (12, 12A), a p-type semiconductor substrate (11) in contact with the first semiconductor region on the side opposite to the main surface, a first electrode layer (13A) provided on the main surface and forming a Schottky junction (14) with the first semiconductor region, an n-type second semiconductor region (16) formed on the main surface side in the first semiconductor region and having a higher concentration than the first semiconductor region, a second electrode layer (13K) provided on the main surface and forming an ohmic junction with the second semiconductor region, Between the Schottky junction and the second semiconductor region, a p-type guard ring region (17) is disposed closer to the Schottky junction and spaced apart from the Schottky junction. A semiconductor device comprising the same.

[0068] [A2] The semiconductor device according to [A1], wherein the distance (d) between the Schottky junction and the guard ring region is 0.05 μm or more and 2 μm or less.

[0069] [A3] The Schottky junction is surrounded by the guard ring region, and the guard ring region is surrounded by the second semiconductor region. The semiconductor device according to [A1] or [A2].

[0070] [A4] Further comprising an insulating layer (18) provided on the main surface side and having a first opening region (181) and a second opening region (182), wherein the first electrode layer is formed in the first opening region, and the second electrode layer is formed in the second opening region. The semiconductor device according to any one of [A1] to [A3].

[0071] The semiconductor device according to any one of [A1] to [A4], wherein an element isolation isolation structure portion (20) is formed outside the second semiconductor region.

Explanation of symbols

[0072] 1…Semiconductor device, 2…Chip, 3…First main surface, 4…Second main surface, 5A…First side surface, 5B…Second side surface, 5C…Third side surface, 5D…Fourth side surface, 6…Device region, 10, 10A…Schottky barrier diode region (SBD region), 10ref…SBD region, 11…Semiconductor substrate, 12…Semiconductor layer (first semiconductor region), 12a…Main surface, 12A…Semiconductor region (first semiconductor region), 13A…First electrode layer, 13K…Second electrode layer, 14…Schottky junction, 15…Ohmic junction, 16…Semiconductor region (second semiconductor region), 17…Guard ring region, 18…Insulating layer, 18a…Groove, 20…Isolation structure portion, 21…Groove, 22…Insulating layer, 23…Conductive material, 24…Sinker layer, 30…Depletion layer, 111…Underlying substrate, 112…Epitaxial semiconductor layer, 121…Embedded semiconductor layer, 122…Epitaxial semiconductor layer, 141…Contact region, 171…Semiconductor region, 181…First opening region, 182…Second opening region, 183…Third opening region, d…Distance.

Claims

1. having a main surface and an n-type first semiconductor region, a p-type semiconductor substrate in contact with the first semiconductor region on the side opposite to the main surface, a first electrode layer provided on the main surface and forming a Schottky junction with the first semiconductor region, an n-type second semiconductor region formed on the main surface side in the first semiconductor region and having a higher concentration than the first semiconductor region, a second electrode layer provided on the main surface and forming an ohmic junction with the second semiconductor region, a p-type guard ring region disposed closer to the Schottky junction and spaced apart from the Schottky junction between the Schottky junction and the second semiconductor region, A semiconductor device comprising:

2. The distance between the Schottky junction and the guard ring region is 0.05 μm or more and 2 μm or less. The semiconductor device according to Claim 1.

3. The Schottky junction is surrounded by the guard ring region, The guard ring region is surrounded by the second semiconductor region. The semiconductor device according to Claim 1 or 2.

4. further comprising an insulating layer provided on the main surface side and having a first opening region and a second opening region, the first electrode layer is formed in the first opening region, the second electrode layer is formed in the second opening region. The semiconductor device according to Claim 1.

5. An element isolation structure portion for element isolation is formed outside the second semiconductor region. The semiconductor device according to Claim 1.

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