Integrated circuit device with zener diode with reduced leakage and / or increased breakdown voltage

Abstract

To provide a method of forming an integrated circuit considering and balancing tradeoffs among various factors, such as IC size, cost, complexity, performance, and yield.SOLUTION: A method of forming an integrated circuit comprises: forming a polysilicon layer having a first side over a semiconductor substrate having a top surface; forming over the semiconductor substrate a first resist layer having a second side spaced apart from the first side; forming a diode well extending into the semiconductor substrate between the first side and the second side, the diode well having a first conductivity type; forming over the semiconductor substrate a second resist layer having a third side; and forming a diode terminal extending into the semiconductor substrate between the first side and the third side, the diode terminal having an opposite second conductivity type and extending from the diode well along the top surface.SELECTED DRAWING: Figure 11

Description

Cross-reference to related applications

[0001] None applicable.

Technical Field

[0002] The examples described relate to semiconductor integrated circuits (ICs) and their manufacture, and more particularly to ICs that include an integrated Zener diode together with other devices such as, for example, metal oxide semiconductor (MOS) transistors and / or laterally diffused metal oxide semiconductor (LDMOS) transistors, but are not limited thereto.

Background Art

[0003] IC manufacturing typically involves a balance considering trade-offs among various factors including, inter alia, any one or more of IC size, cost, complexity, performance, and yield. These factors can become even more complex when the IC includes different device types, when an adjustment of a factor for one of those devices can have a trade-off impact on another device. These trade-offs can exist, for example, in an IC comprising a Zener diode and other devices. This is because factors in building the other devices can undesirably affect target Zener diode operating parameters such as breakdown voltage or leakage current. For example, in some ICs, a Zener diode and an LDMOS transistor can be included, the transistor enables higher power application and operation, and the Zener diode is coupled to the transistor to enable reverse breakdown of the Zener diode when the voltage on the LDMOS transistor increases, to protect against potential damage to the transistor gate oxide. However, some basic manufacturing methods can require additional steps or considerations targeting only one or the other of the LDMOS transistor or the Zener diode, and are inefficient.

[0004] The foregoing can have implementations in various basic devices, but this specification provides examples that can improve on some of the above concepts, as detailed below.

Summary of the Invention

[0005] In one example, a method of forming an integrated circuit is described. The method includes forming a polysilicon layer having a first side on a semiconductor substrate having a top surface, forming a first resist layer having a second side spaced from the first side on the semiconductor substrate, forming a diode well extending into the semiconductor substrate between the first side and the second side, wherein the diode well has a first conductivity type, forming a second resist layer having a third side on the semiconductor substrate, and forming a diode terminal extending into the semiconductor substrate between the first side and the third side, wherein the diode terminal has an opposite second conductivity type and extends from the diode well along the top surface.

[0006] Other aspects are described and claimed.

[0007]

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

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Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

[0009]

Figure 10

[0010]

Figure 11

DETAILED DESCRIPTION OF THE INVENTION

[0011] Figures 1 to 9 are cross-sectional views showing successive manufacturing steps and structures resulting, for example, from a semiconductor structure 100 that is part of an IC. Ultimately, semiconductor structure 100 will include IC devices such as LDMOS transistors, MOS transistors, and diodes (e.g., Zener diodes), so FIGS. 1 etc. show an LDMOS transistor area 102, a MOS transistor area 104, and a diode area 106 in which each of the respective devices is formed. As an example, the IC may provide an LDMOS transistor that operates at a voltage higher than the voltage associated with MOS transistors, such as an LDMOS transistor operating at 10 volts or more and a MOS transistor operating at 5 volts or less, and the diode may be proximate to either the MOS transistor or the LDMOS transistor, for example for voltage protection purposes. Further, in addition to the diode, the IC may include a number of other devices (not shown) that function in relation to the transistors. Such devices may be isolated at the substrate level, for example via field oxide, formed from the structures shown in FIG. 1 (and other subsequent figures) using either a shallow trench isolation (STI) or a local oxidation of silicon (LOCOS) process, and may be connected at the interconnect level to the structures shown in FIG. 1.

[0012] Starting from FIG. 1, the semiconductor structure 100 includes, for example, a semiconductor substrate 108 as part of a silicon wafer, and an isolation region 109 formed between the device areas introduced above. Such wafers typically include multiple positions, each corresponding to the same or different ICs on the wafer. Therefore, the illustrations in FIG. 1 (and subsequent figures) can be repeated at each wafer IC position. The wafer typically provides either a p-type or n-type semiconductor, and the substrate 108 can represent a part of the bulk wafer or a region formed in relation to the wafer (e.g., a well or an embedded layer). In the illustrated example, the substrate 108 is a p-type epitaxial (epi) layer. For example, a mask (e.g., resist) layer 110, which also uses a photolithography process in the same way as other masks identified below, is formed over the upper surface 108US at selective positions. The mask layer 110 includes first and second openings 112 and 114, each in an area where implantation is to be performed. For example, p-type dopant implantation is used to form respective PWELL regions (or more generally well regions) 116 and 118, through the first opening 112 in a part of the MOS transistor area 104 and through the second opening 114 in a part of the diode area 106. Each of the PWELL regions 116 and 118 can have a dopant concentration in the range of 1×10 16 / cm 3 ~3×10 17 / cm 3 and a maximum depth D1 (shown as a vertical dimension) extending from the upper surface 108US into the substrate 108 in the range of 0.5 μm to 1.5 μm.

[0013] In FIG. 2, the mask layer 110 of FIG. 1 is removed, and a mask layer 202 is formed, which is patterned to form an opening 204 therein. For example, using n-type dopant implantation, implantation is performed through the opening 204 in a part of the LDMOS transistor area 102 to form respective drift regions 206 in the substrate 108. The drift regions 206 have a concentration of 3×10 15 / cm 3 ~1×10 17 / cm 3The dopant concentration within the range, and within the range of 0.2 μm to 2 μm, may have a maximum depth D2 (indicated by the vertical dimension) extending from the upper surface 108US into the substrate 108.

[0014] In FIG. 3, the mask layer 202 of FIG. 2 is removed, and a mask layer 302 such as a SiN layer is formed, which is patterned to form an opening 304 therein. A thick LOCOS structure 306 is formed over the drift region 206 through the opening 304 in the etching mask layer 302. Generally, the LOCOS structure 306 may be formed by oxidizing a portion of the upper surface 108US exposed through the opening 304. As shown, the LOCOS structure 306 may include a central portion that, in contrast to the region around its lateral or peripheral edges, which may form what is sometimes referred to as a "bird's beak," has a greater depth in the vertical dimension toward its central area.

[0015] In FIG. 4, the mask layer 302 of FIG. 3 is removed, and polysilicon (poly) and related structures are formed from the polysilicon layer in each of the LDMOS transistor area 102, the MOS transistor area 104, and the diode area 106. First, a thin insulator layer is formed (only the portions left in FIG. 4) by growing or depositing an insulator such as an oxide on the exposed portions of the upper surface 108US. Next, a poly layer (only the portions left in FIG. 4) is formed on the insulator layer. The deposited poly layer may be doped in-situ or thereafter. The poly and the thin insulator layer are patterned and etched to form, respectively, the resulting poly structures 402, 404, and 406 separated from the upper surface 108US by the respective remaining insulator portions 408, 410, and 412 in one of each of the LDMOS transistor area 102, the MOS transistor area 104, and the diode area 106. With respect to the poly structure 402, one vertical end provides a first sidewall above the LOCOS structure 302, and the other vertical end provides a second sidewall that is laterally positioned beyond the vertical edge of the drift region 206. The combination of the poly structure 402 and the insulator portion 408, in combination with the area where the poly structure 402 overlaps the thick LOCOS structure 306, can function as the LDMOS transistor gate and respective gate dielectrics. The combination of the poly structure 404 and the insulator portion 410 can function as the MOS transistor gate and respective gate dielectrics. As will be further described below, the combination of the poly structure 406 and the insulator portion 412 can function as an implantation hard mask in relation to the diode formed in the diode area 106.

[0016] In FIG. 5, a mask layer 502 is formed over the upper surface 108US and patterned to form first and second openings 504 and 506 therein, both of which are located in the MOS transistor area 104. A relatively light dopant implantation, generally referred to as a lightly doped drain (LDD) implantation, is performed through the first and second openings 504 and 506 to form corresponding LDD regions 508 and 510 under the upper surface 108US, self-aligned to the insulator portion 410. The LDD implantation is typically provided at a lower energy than a separate (described later) n-type or p-type source / drain implantation, and it is selected from a dopant type corresponding to the desired conductivity type of the transistor formed in the MOS transistor area 104. For example, in the case of an n-type MOS (NMOS) transistor, the LDD implantation is of an n-type dopant (e.g., phosphorus and / or arsenic pocket implantation, and optional germanium preamorphization implantation (PAI)), e.g., phosphorus having a dose amount in the range of 1×10 13 ~3×10 14 atoms / cm 2 using an energy in the range of 5 keV to 80 keV, or arsenic having a dose amount in the range of 1×10 14 ~1×10 15 atoms / cm 2 using an energy in the range of 10 keV to 100 keV, and using an inclination of 0 to 35 degrees and 2 or 4 rotations. As an alternative example, in the case of a p-type MOS (PMOS) transistor, the LDD implantation is of a p-type dopant (e.g., BF2 (difluoroboron), boron, and / or indium with optional germanium PAI), e.g., BF2 having a dose amount in the range of 5×10 13 ~5×10 14 atoms / cm 2 using an energy in the range of 5 keV to 50 keV, boron having a dose amount in the range of 5×10 13 ~5×10 14 atoms / cm 2 using an energy in the range of 2 keV to 20 keV, and / or boron having a dose amount in the range of 1×10 13 ~5×10 14 atoms / cm2 Using indium having a dose amount in the range of, and optionally, at an energy in the range of 5 keV to 20 keV, 1×10 14 ~5×10 14 atoms / cm 2 Germanium PAI having a dose amount in the range of is used. Also, the PMOS LDD may include pocket implants of arsenic and / or antimony having a dose amount in the range of 1×10 13 ~1×10 14 atoms / cm 2 During the LDD implant, the poly structures 402 and 406 may or may not be masked.

[0017] In FIG. 6, the mask layer 502 of FIG. 5 is removed, and a mask layer 602 (e.g., photoresist) is formed over the upper surface 108US and patterned to form first and second openings 604 and 606. The first opening 604 is in the LDMOS area 102, and the second opening 606 is in the diode area 106. The first opening 604 is over a portion of the LDMOS transistor area 102 but is laterally spaced from the drift region 206. Thus, subsequent implant through the first opening 604 provides a DWELL structure at a target location that is self-aligned, for example, to the vertical edge of the poly structure 402 for the purpose of the operation of the LDMO transistor. Also, in this regard, the width of the first opening 604 is in the range of 0.5 μm to 1.0 μm to enable such a DWELL. Separately, the second opening 606 is in the diode area 106 and exposes an area of the upper surface 108US defined between two different types of structures, i.e., on one vertical edge by the mask layer 602 and on another vertical edge provided by the sidewall of the poly structure 406 as shown formed in FIG. 4, simultaneously with the other poly structures 402 and 404. Also, the width of the second opening between these two vertical edges is w dis shown as being controllable in the range of 30 nm to 300 nm and can provide important advantages as will be further described below. As will be described below, two sets of implantations are then carried out via the first and second openings 604 and 606, for example, sequentially and in either order, so that each of these implantations depends in part on the poly structure 406 that functions as an implant hard mask as long as it passes through the second opening 606, which is noted to be because the poly structure defines one edge of the second opening 606 (the other edge provided by the mask layer 602).

[0018] One implantation carried out through both the first opening 604 and the second opening 606 uses the same dopant as that used for the drift region 206 and a dopant type opposite to that used for the PWELL region 118. Thus, in this example where the drift region 108 is n-type and the PWELL region 118 is p-type, the implantation in FIG. 6 is, for example, n-type using arsenic. Also, the result of this implantation in FIG. 6 is called a shallow implantation region in that this implantation has an implantation energy lower than the implantation energy used for a deeper implantation, which is also described and passes through the openings 604 and 606. For example, the shallow implantation dose amount in FIG. 6 is in the range of 1.0×10 14 atoms / cm 2 ~2.0×10 14 atoms / cm 2 (for example, 1.4×10 14 atoms / cm 2) can be an energy in the range of 5 keV to 10 keV (e.g., 8 keV). The shallow implant forms a shallow well region 608 generally aligned with the first opening 604 in the substrate 108 and also forms a shallow well region 610 generally aligned with the second opening 606 in the substrate 108. In one example, each of the shallow well region 608 and the shallow well region 610 is thereby formed by the same implant simultaneously extending to a depth D3 in the substrate 108. The depth D3 is selected based on the depth D5 (see D5 in FIG. 7) of the subsequently formed source / drain, and D3 is about 50% or less of D5. For example, if D5 can be in the range of 60 nm to 200 nm, correspondingly, D3 can be in the range of 30 nm to 100 nm, respectively.

[0019] Another implant performed through both the first and second openings 604 and 606 uses the same dopant type as that used for the PWELL region 118, which is of a dopant type opposite to that of the dopant used for the drift region 206 and is p-type in the current example, to form the transistor well region 612 and the diode well region 614. This implant uses an energy greater than that of the shallow well implant to form the well regions 612 and 614 deeper and below the respective shallow well regions 608 and 610. The deeper implant targets a depth D4 that can be in the range of 300 nm to 500 nm. The deeper implant uses a dose amount and energy consistent with these targets, for example, at an energy in the range of 20 keV to 50 keV (e.g., 32 keV) and at 3×10 13 atoms / cm 2 ~6×10 13 atoms / cm 2 and in the range of (e.g., at 3×10 13 atoms / cm 2 ).

[0020] In FIG. 7, the mask layer 602 of FIG. 6 is removed, and a mask layer 702 (e.g., photoresist) is formed on the upper surface 108US, which is patterned to form first to fifth openings 704, 706, 708, 710, and 712 therein, and some of these openings are in each of the LDMOS area 102, the MOS area 104, and the diode area 106. Thereafter, sidewall spacers 714 are formed along the sidewalls of the poly structure 402, sidewall spacers 716 are formed along the sidewalls of the poly structure 404, and sidewall spacers 718 are formed along the sidewalls of the poly structure 406. The sidewall spacers 714, 716, and 718 can be formed, for example, by forming an oxide layer and / or a nitride layer on and along at least the sidewalls of each poly structure so as to leave the remaining portion of the oxide as the sidewall spacers later, followed by performing appropriate etching.

[0021] FIG. 7 also illustrates source / drain implantation in an example using, for example, an n-type dopant, corresponding to an example called NSD implantation. For example, NSD implantation using arsenic (or phosphorus or antimony) is related to the source / drain functionality of the LDMOS transistors in the LDMOS transistor area 102 and the NMOS transistors in the MOS transistor area 104. The implantation forms an n-type region in the substrate 108 through each of the first to fifth openings 704, 706, 708, 710, and 712. The NSD implantation is 1.0×10 15 atoms / cm 2 ~1.6×10 15 atoms / cm 2can have an energy in the range of 20 keV to 30 keV within the range, whereby the dopant can be implanted to a depth D5, which, recalling from above, can be in the range of 60 nm to 200 nm. As a result, the n-type implant forms the drain 720 and source 724 for the LMDOS transistor and the first and second source / drain (S / D) regions 726 and 728 for the MOS transistor. The n-type implant also forms the n-type region 730. The n-type region 730 (which couples to the n-type shallow well region 610) interfaces with the p-type material of the diode well region 614 or forms a metallurgical interface with the p-type material of the diode well region 614, thereby providing a PN junction 732 between the two, with a junction partially illustrated by the diode symbol of the schematic having a dotted outline, as between the diode well region 614 and the n-type region 730. The n-type region 730 extending away from the shallow well region 610 along the upper surface 108US can operate as the first terminal of the diode 106.

[0022] In FIG. 8, the mask layer 702 of FIG. 7 is removed and a mask layer 802 is formed over the upper surface 108US, which is patterned to form a first opening 804 in the LDMOS area 102 and a second opening 806 in the diode area 106. Then, an implant complementary to that of FIG. 7 is performed, so that if FIG. 7 uses an n-type dopant, the implant of FIG. 8 is p-type, here using boron for example. The implant of FIG. 8 may be referred to as a PSD implant, i.e., there may be cases where a p-type dopant is implanted in relation to the illustrated transistor or a transistor other than that illustrated, and there may be cases where a p-type source / drain or other region is required. The implant of FIG. 8 is at 1×10 15 atoms / cm 2 ~10×10 15 atoms / cm 2The range can be up to the depth of D5, and the energy in the range of 5 keV to 10 keV. The p-type implantation in FIG. 8 forms a p-type body region 808 in the transistor well region 612 through the first opening 804. Also, the p-type implantation in FIG. 8 forms a p-type region 810 in the PWELL region 118 through the second opening 806. The p-type region 810 is spaced apart from the n-type region 730 in that the PWELL region 118 extends up to the upper surface 108US between the p-type region 810 and the n-type region 730. The p-type region 810 provides a conductive path 812 of the same dopant type, shown by a dotted line, through the PWELL region 118 (and optionally also a part of the substrate 108) and up to the diode well region 614 so that electrical contact can be made to the p-type region 810 as the anode of the PN junction 732. The p-type region 810 can operate as the second terminal of the diode 106.

[0023] In FIG. 9, the mask layer 802 of FIG. 8 has been removed. Thereafter, connections can be made to the LDMOS transistors within the LDMOS transistor area 102, the MOS transistors within the MOS transistor area 104, and the diodes within the diode area 106, either to each other or to other devices. To facilitate such connections, for example, in FIG. 9, silicide conductive regions 902, 904, 906, 908, 910, 912, 914, 916, and 918 are formed along the selected semiconductor surface, for example, along and laterally on the surfaces of the drain 720, source 724, and body region 808, S / D regions 726, S / D region 728, p-type region 810, n-type region 730, and poly structures 402, 404, and 406, respectively. In this regard, an electrical path through the PN junction 732 can be realized by electrical contact to the silicide conductive region 914 as the diode anode and to the silicide conductive region 916 as the diode cathode. Along that electrical path, an ionization region 920 is presented that represents a location where diode breakdown (or impact ionization) can occur due to the p-type / n-type (PN) junction or interface between the p-type material of the diode well region 614 and the n-type material of the n-type region 730. In particular, by forming the diode well region 614, it presents a lower p-type dopant concentration compared to the PWELL region 118 in which the diode well region 614 is formed. As a result, in the ionization region 920, an area is created where one or more favorable attributes can be realized, including an increase in breakdown voltage and / or a decrease in current leakage, due to the relatively high p-type dopant concentration from the diode well region 614 in the area of the ionization region 920, i.e., in the PN junction 732 of the diode well region 614 to the n-type region 730. Thus, either or both of these attributes can be implemented without adding additional manufacturing steps beyond those already implemented in the formation of other devices (e.g., when forming MOS transistors and LDMOS transistors).

[0024] Also, in FIG. 9, note that the ionization region 920 occurs at approximately depth D5, i.e., the depth of the PN junction 732 between the n-type region 730 and the p-type diode well region 614. Temporarily returning to FIG. 6, the shallow well region 610 and the additional diode well region 614 are formed through the second opening 606, and recall that the opening has a width w d It should be recalled that it has. The depth D5 at which the ionization region 920 occurs in FIG. 9 is shown, but the width w in FIG. 6 d It should also be noted that, in one example, is approximately equal to the depth D5. However, in other examples, w d can vary with respect to the depth D5, for example, can be a height approximately 50% greater than D5, or a low height approximately 50% less than D5. In this context, "about" means ±5%. This width-to-depth relationship is shown by the examples given above, where 60 nm ≦ D5 ≦ 200 nm, and 30 nm ≦ w ≦ d ≦ 300 nm, and therefore, the minimum width of w d is 50% less than the minimum depth of D5, and the maximum width of w d is stated to be 50% greater than the maximum depth of D5. Also, the depth D5, as related to the NSD implant, is likely to have a depth related to other devices within the semiconductor structure 100, such as the source 724 for the LMDOS transistor and the first and second source / drain (S / D) regions 726 and 728 for the MOS transistor, and nominally also establishes the depth at which the n-type region 730 functions as the cathode of the diode within the diode area 106. This depth can be partially restricted by the minimum accurate aperture size achievable in a photolithography process, such as in a photoresist, typically used to define the width of the implant opening, such as the first opening 604 in FIG. 6, or the first to fourth openings 704, 706, 708, and 710 in FIG. 7. However, in FIG. 6, the width w that affects the position of the relatively high dopant concentration provided by the diode well region 614 dNote that the second opening 606 having [it] is not so restricted. This is because it is not restricted on both sides by the photoresist, has a boundary from the vertical edge of the mask layer 602 on one side (e.g., the left side in FIG. 6), and has a boundary from the vertical edge of the poly structure 406 on the other side (e.g., the right side in FIG. 6). As a result, in FIG. 6, when the diode well region 614 is formed while the basic line DWELL injection process for other non - diode devices is carried out, a relatively narrow width of the diode well region 614 can be achieved by the addition of the poly hard mask, and it is partially self - aligned to the vertical sidewalls of the hard mask poly structure 404. Thus, the width w d correspondingly adjusts the width and dopant concentration depth profile for forming the diode well region 614, and these factors support the subsequent formation, positioning, and behavior at the PN junction 732 (as also shown as the ionization region 920 in FIG. 9) in FIG. 7. Also, this is achieved by using poly (e.g., poly structure 406) as the hard mask in combination with the conventional (e.g., photoresist) mask used for DWELL injection for other devices (e.g., for LDMOS transistors). Thus, as shown in FIG. 7 and further as shown in FIG. 9, when the n - type region 730 is subsequently formed, the PN junction 732 provides the resulting ionization region 920 having a relatively high p - type dopant concentration desirable at its position, thereby increasing the diode breakdown voltage and reducing the diode leakage.

[0025] Finally, with respect to FIG. 9, additional electrical connections may be made, for example, via a metal layer and metal vias (not shown), generally formed on the structure of FIG. 9 and contacting appropriate ones of the silicide conductive regions.

[0026] FIG. 10 is a plan view of a diode 1000 including the diode portion of the semiconductor structure 100 of FIG. 9. Diode 1000 is generally symmetric about a poly structure 406 shown as a rectangle (or square). Thus, in each linear dimension in which poly structure 406 is formed, a diode well region 614 is shown outward of that dimension (spaced from poly structure 406 by non-referenced sidewall spacers), an n-type region 730 (cathode) is shown further outward of diode well region 614, and a p-type region (anode) 810 is shown further outward of n-type region 730 (cathode). Thus, FIG. 10 shows the foregoing different perspectives as an example in which the n-type region (cathode) 730 completely surrounds the diode well region 614 and the p-type region 810 (cathode) completely surrounds the n-type region (cathode) 730.

[0027] FIG. 11 is a flowchart of an exemplary method 1100 that summarizes the various steps described above for manufacturing a semiconductor structure 100 that ultimately provides a structure 100 as shown, for example, in FIGS. 9 and 10. This method 1100 begins at step 1102 where a semiconductor substrate 108 of FIG. 1 is obtained. The semiconductor substrate 108 may be a bare wafer at this stage, or may already have one or more semiconductor features formed thereon. The semiconductor substrate 108 also includes one or more areas, or one or more electrical structures proximate to such areas, within which it is desirable to form a semiconductor or silicon including, for example, a device such as a diode and one or more of an LDMOS transistor and a MOS transistor. Next, in step 1104, a polysilicon member such as the polysilicon structure 406 of FIG. 4 is formed on the surface of the semiconductor substrate 108. Next, in step 1106, using a portion of the polysilicon member of step 1104 as a hard mask, a PN junction region such as the diode well region 614 of FIG. 6 is formed in the semiconductor substrate 108. Next, in step 1108, one of a diode anode or a diode cathode, such as the n-type region 730 (cathode) of FIG. 7, is formed in the semiconductor substrate 108. Thereafter, step 1110 generally represents that additional structures may be formed in connection with the diode (and optionally other devices and interconnects to and between these and other devices) associated with the semiconductor substrate 108 of step 1102, after step 1108.

[0028] From the above, one of ordinary skill in the art will understand that examples for semiconductor IC manufacturing are provided with respect to an IC including a Zener diode having other devices such as MOS transistors and / or LDMOS transistors, for example, formed at least in part using a simultaneous processing step. Such examples provide various advantages, some of which are described above and others are also included. For example, although a certain dopant type is described, complementary (opposite) conductivity types are also contemplated, whereby the positions of the diode anode and cathode are reversed. Other examples may implement other types of IC structures that provide processes that can be used simultaneously to form the diode structures described herein. Accordingly, each of the diode breakdown voltage and leakage can be well adjusted, for example, without using additional masks directed only to one or the other of these attributes. These advantages can be realized for more complex structures of multiple devices on the same substrate (and IC), thereby realizing extended improvements across the devices. Within the scope of the claims of the present invention, further additional modifications in the described embodiments are possible and other embodiments are possible.

Claims

1. A method of forming an integrated circuit, comprising: forming a polysilicon layer having a first side on a semiconductor substrate having a top surface; forming a first resist layer having a second side spaced from the first side on the semiconductor substrate; forming a diode well having a first conductivity type extending into the semiconductor substrate between the first side and the second side; forming a second resist layer having a third side on the semiconductor substrate; forming a diode terminal extending into the semiconductor substrate between the first side and the third side, the diode terminal having an opposite second conductivity type and extending from the diode well along the top surface, the diode terminal being formed; A method comprising the steps of:

2. The method according to claim 1, wherein the diode terminal is a first diode terminal, and the diode well and the first diode terminal extend into a well region having the first conductivity type; The method further comprising forming a second diode terminal extending into the well region, the second diode terminal being spaced from the first diode terminal and having the first conductivity type.

3. The method according to claim 1, wherein the diode well is p-type and the diode terminal is n-type.

4. The method according to claim 1, further comprising forming a shallow well between the PN junction and the top surface between the first side and the second side, the shallow well overlapping the diode terminal and having the second conductivity type.

5. The method according to claim 4, wherein a first depth of the shallow well is approximately half of a second depth of the diode terminal.

6. The method according to claim 4, wherein the shallow well has a depth approximately equal to half of a width between the first side and the second side.

7. The method according to claim 1, wherein a width between the first side and the second side ranges from 30 nm to 300 nm.

8. The method according to claim 1, wherein a width between the first side and the second side is approximately equal to a depth of a metallurgical interface between the diode terminal and the diode well.

9. The method according to claim 1, wherein the width between the first side and the second side is substantially equal to the depth of the diode terminal extending into the semiconductor substrate.

10. The method according to claim 1, wherein the implantation for forming the diode well also forms a DWELL of a transistor extending into the semiconductor substrate.

11. A method of forming an integrated circuit, forming an exposed area of the semiconductor substrate between a resist mask and a polysilicon structure mask; implanting an n-type dopant and a p-type dopant into the semiconductor substrate through the exposed area, thereby forming a PN junction under the exposed area; forming a diode terminal extending into the semiconductor substrate along the top surface of the semiconductor substrate from the PN junction; comprising.

12. The method according to claim 11, wherein the width between the resist mask and the polysilicon structure mask is substantially equal to the depth of the diode terminal.

13. The method according to claim 11, wherein the diode terminal is a first diode terminal having a first conductivity type, the method further comprising forming a second diode terminal having a second, opposite conductivity type spaced from the first diode terminal along the top surface.

14. The method according to claim 11, wherein the diode terminal has a first conductivity type, the method further comprising forming a shallow well having the first conductivity type between the PN junction and the top surface.

15. The method according to claim 11, further comprising forming a transistor extending over and into the semiconductor substrate, including forming a DWELL of the transistor using the resist mask.

16. An integrated circuit (IC) comprising: a polysilicon member on the surface of a semiconductor substrate; a PN junction under the surface, the PN junction being self-aligned to the polysilicon member; a diode contact extending away from the PN junction along the surface; including.

17. The IC according to claim 16, wherein the diode terminal is a first diode terminal having a first conductivity type, The IC further includes a second diode terminal having a second conductivity type opposite to that of the first diode terminal and spaced apart from the first diode terminal along the surface. **Claim 18** The IC according to claim 17, wherein a DWELL having the second conductivity type extends from the PN junction into the semiconductor substrate. **Claim 19** The IC according to claim 16, wherein a first DWELL region having a certain conductivity type extends from the PN junction into the semiconductor substrate. The IC further includes a MOS transistor extending into the semiconductor substrate. The MOS transistor includes a second DWELL region having the conductivity type and having the same depth as the first DWELL region. **Claim 20** The IC according to claim 16, wherein the diode terminal having a certain conductivity type extends to a first depth into the semiconductor substrate. The IC further includes a MOS transistor including a source region and a drain region having the conductivity type and extending to the same second depth into the semiconductor substrate.

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