Imaging device and electronic appliance

Abstract

To provide an imaging device with high resolution and sensitivity.SOLUTION: In an imaging device, a pixel circuit 331 has a first element layer 100 and a second element layer 101. The first element layer has a photoelectric conversion device 240 and a first transistor 103. The second element layer has second to fourth transistors 104 to 106. One electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor. One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor. The photoelectric conversion device and at least a part of the second transistor, the third transistor, and the fourth transistor overlap with each other.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field of one aspect is related to an object, a method, or a manufacturing method. Or, one aspect of the present invention is related to a process, a machine, a manufacture, or a composition (composition ·of·matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, memory devices, imaging devices, their driving methods, or their manufacturing methods, which can be cited as an example.

[0003] Note that in this specification etc., the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. Also, memory devices display devices, imaging devices, and electronic devices may have semiconductor devices.

Background Art

[0004] Imaging devices typified by CMOS image sensors are used in various image / video devices such as digital still cameras, video cameras, and smartphones. Furthermore, in a society where IoT ( Internet of Things) is advancing, imaging devices are used in various fields such as surveillance cameras, in-vehicle sensors, medical devices, and sensors for robots.

[0005] As the resolution of imaging devices increases, the pixel size is being miniaturized. The miniaturization of the pixel size As the size is reduced, the occupied area of the photodiode is also reduced. As a result, there is a risk that the sensitivity or dynamic range of the imaging device cannot be sufficiently obtained.

[0006] For example, a CMOS image sensor is disclosed in which a part of the pixel circuit is shared by a plurality of pixels to reduce the occupied area of elements other than the photodiode and improve the occupied area of the photodiode (see Patent Document 1). (See Patent Document 1).

Prior Art Documents

Patent Documents

Patent Document 1

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a high-sensitivity imaging device as one of the problems. Or, one aspect of the present invention is to provide a high-resolution imaging device as one of the problems. Or, one aspect of the present invention is to provide a highly functional imaging device as one of the problems. Or, one aspect of the present invention is to provide a small-sized imaging device as one of the problems. Or, one aspect of the present invention is to provide an imaging device capable of high-speed operation as one of the problems. Or, one aspect of the present invention is to provide a novel imaging device or the like as one of the problems. Or, one aspect of the present invention is to provide a driving method for the above imaging device as one of the problems. Or, one aspect of the present invention is to provide a novel electronic device or the like as one of the problems.

[0009] It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a semiconductor device including a first semiconductor substrate and a second semiconductor substrate. The substrate has a photoelectric conversion device and a first transistor, and the second semiconductor substrate has a first a second transistor, a third transistor, and a fourth transistor; One of the electrodes of the device is electrically connected to one of the source and drain of the first transistor. The other of the source and drain of the first transistor is connected to the the source and drain of the second transistor are electrically connected to one of the source and drain of the second transistor; One of the drains is electrically connected to the gate of the third transistor. One of the source and drain of the first transistor is connected to one of the source and drain of the fourth transistor. a photoelectric conversion device, a second transistor, a third transistor, and a and at least a part of the fourth transistor overlap with the first transistor.

[0011] In the above, a first semiconductor substrate is provided on a surface on which the first transistor is formed. A first insulating layer and a first conductive layer are disposed, and the first conductive layer is embedded in the first insulating layer. a region electrically connected to the other of the source and drain of the first transistor, A second insulating film is formed on the surface of the second semiconductor substrate on which the second to fourth transistors are formed. A layer and a second conductive layer are arranged, and the second conductive layer has a region embedded in the second insulating layer and is electrically connected to the gate of the third transistor, and is preferably directly joined to the first conductive layer and the second conductive layer and the first insulating layer and the second insulating layer are preferably directly joined.

[0012] Also, in the above, the first semiconductor substrate and the second semiconductor substrate are preferably silicon substrates. Further, the first semiconductor substrate contains an element that imparts p-type conductivity, and the region that functions as one of the electrodes of the photoelectric conversion device and the source and drain of the first transistor preferably contains an element that imparts n-type conductivity. Also, one of the electrodes of the photoelectric conversion device and one of the source and drain of the first transistor are preferably formed in the same region.

[0013] Also, in the above, a first capacitor is arranged between the second semiconductor substrate and the second insulating layer, and one of the electrodes of the first capacitor is preferably electrically connected to the gate of the third transistor.

[0014] Also, in the above, a third semiconductor substrate is arranged on the surface of the second semiconductor substrate where the second to fourth transistors are not formed, and a fifth transistor is formed on the third semiconductor substrate. The fifth transistor is preferably electrically connected to the other of the source and drain of the fourth transistor via a second capacitor.

[0015] Also, in the above, a memory circuit is arranged between the second semiconductor substrate and the third semiconductor substrate, and the memory circuit preferably includes a transistor having a metal oxide in the channel formation region. ​​​​​​​​​​​​ preferable.

[0016] In the above, the metal oxide is In, Zn, and M (M is Al, Ti, Ga, G one or more of: e, Sn, Y, Zr, La, Ce, Nd, or Hf; is preferred.

[0017] Another aspect of the present invention is an electronic device including the imaging device described above and a display device. It is a vessel. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a highly sensitive imaging device can be provided. According to one aspect of the present invention, a high-resolution imaging device can be provided. According to one embodiment of the present invention, a high-performance imaging device can be provided. In accordance with one embodiment of the present invention, a small-sized imaging device can be provided. According to one embodiment of the present invention, a novel imaging device can be provided. According to one embodiment of the present invention, an imaging device or the like can be provided. According to one embodiment of the present invention, a novel electronic device can be provided. etc. can be provided. [Brief explanation of the drawings]

[0019]

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Embodiments for Carrying Out the Invention

[0020] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and its forms and details can be variously changed without departing from the spirit and scope of the present invention. Those skilled in the art can easily understand that modifications are possible. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and repeated descriptions thereof may be omitted. Note that the hatching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings. In addition, even if an element is illustrated as a single element on a circuit diagram, the element may be composed of a plurality of elements as long as there is no functional inconvenience. For example, a transistor operating as a switch may be connected in series or in parallel. Also, a capacitor may be divided and arranged at a plurality of positions. Moreover, there are cases where one conductor has a plurality of functions such as wiring, electrodes, and terminals, and in this specification, a plurality of names may be used for the same element. Also, even if elements are illustrated as being directly connected on a circuit diagram, in actuality, the elements may be connected via one or a plurality of conductors, and such a configuration is included in the scope of direct connection in this specification. (Embodiment 1) In this embodiment, an imaging device according to one aspect of the present invention will be described with reference to FIGS. 1 to 13.

[0021] One aspect of the present invention is an imaging device having a pixel circuit composed of elements formed on each of two semiconductor substrates. Here, the pixel circuit includes at least a photoelectric conversion device and a plurality of

[0022]

[0023]

[0024]

[0023] (Embodiment 1) In this embodiment, an imaging device according to one aspect of the present invention will be described with reference to FIGS. 1 to 13. will be described.

[0024] One aspect of the present invention is an imaging device having a pixel circuit composed of elements formed on each of two semiconductor substrates. Here, the pixel circuit includes at least a photoelectric conversion device and a plurality of It has a number of transistors and a photoelectric conversion device on a first semiconductor substrate, and forms a part of the plurality of transistors on the first semiconductor substrate, and forms most of the plurality of transistors on a second semiconductor substrate. Accordingly, the number of transistors formed on the first semiconductor substrate can be reduced by the number of transistors formed on the second semiconductor substrate, so that the occupied area of the photoelectric conversion device can be increased. Thereby, even when the pixel size is miniaturized, the ratio of the occupied area of the photoelectric conversion device in each pixel can be increased, so that a high-resolution and high-sensitivity imaging device can be provided. For example, in an imaging device with pixels having a 4-transistor configuration, a photoelectric conversion device, a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor are formed in the pixel circuit. In this case, the photoelectric conversion device and the transfer transistor may be provided on the first semiconductor substrate, and the reset transistor, the source follower transistor, and the selection transistor may be provided on the second semiconductor substrate. With such a configuration, the occupied area of the photoelectric conversion device in each pixel can be increased by the area of the three transistors provided on the second semiconductor substrate. <Configuration 1 of the imaging device> FIG. 1(A) is a block diagram of an imaging device according to an aspect of the present invention. The imaging device has a pixel section 330, a drive circuit 332, and a drive circuit 333. The pixel section 330 has a plurality of pixel circuits 331 arranged in a matrix. The pixel circuit 331 has a photoelectric conversion device and a plurality of transistors. Here, the photoelectric conversion device

[0025]

[0026] <Configuration 1 of the imaging device> FIG. 1(A) is a block diagram of an imaging device according to an aspect of the present invention. The imaging device has a pixel section 330, a drive circuit 332, and a drive circuit 333. The pixel section 330 has a plurality of pixel circuits 331 arranged in a matrix. The pixel circuit 331 has a photoelectric conversion device and a plurality of transistors.

[0027] 331 has a photoelectric conversion device and a plurality of transistors. Here, the photoelectric conversion device S preferably has sensitivity to visible light. For example, a photodiode using silicon in a photoelectric conversion device can be used for the photoelectric conversion layer.

[0028] The drive circuit 332 can control operations such as the data acquisition operation and the selection operation of the pixel circuit 331. For the drive circuit 332, for example, a shift register or the like can be used.

[0029] The drive circuit 333 includes a readout circuit electrically connected to the pixel circuit 331, and a drive circuit that controls the operation of the readout circuit. The readout circuit has a correlated double sampling (CDS) circuit for reducing noise and an A / D converter for converting analog data into digital data. correlated double sampling (CDS)

[0030] <Pixel Circuit> FIG. 1(B) is a circuit diagram for explaining an example of the pixel circuit 331. The pixel circuit 331 can include a photoelectric conversion device 240, a transistor 103, a transistor 104, a transistor 105, a transistor 106, and a capacitor 108. Here, the pixel circuit 331 is composed of an element layer 100 and an element layer 101 provided under the element layer 100, and the element layer 100 and the element layer 101 are formed on different semiconductor substrates. The photoelectric conversion device 240 and the transistor 103 are formed in the element layer 100, and the transistor 104, the transistor 105, the transistor 106, and the capacitor 108 are formed in the element layer 101. Note that a configuration without the capacitor 108 may also be used.

[0031] ​​​​​​​​​​​​In the following description, an n-channel transistor is assumed for each transistor. . However, in order to apply it to a p-channel transistor, terms, symbols, etc. may be appropriately changed.

[0032] Note that the photoelectric conversion device 240 preferably has sensitivity in the visible light region. For example, , a photodiode using silicon for the photoelectric conversion layer can be used for the photoelectric conversion device 240.

[0033] One electrode (cathode) of the photoelectric conversion device 240 is electrically connected to one of the source and drain of the transistor 103. The other of the source and drain of the transistor 103 is electrically connected to one of the source and drain of the transistor 104. The other of the source and drain of the transistor 104 is electrically connected to one of the source and drain of the transistor 105. One of the source and drain of the transistor 105 is electrically connected to the gate of the transistor 106. One of the source and drain of the transistor 106 is electrically connected to one of the source and drain of the transistor 107. One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105.

[0034] Also, the other of the source and drain of the transistor 103 is electrically connected to the wiring 124, and the gate of the transistor 105 is electrically connected to the wiring 125. The wiring 124 and the wiring 125 are connected at the junction 130 between the element layer 100 and the element layer 101. In this way, the other of the source and drain of the transistor 103 in the element layer 100, one of the source and drain of the transistor 104 in the element layer 101, and the gate of the transistor 105 are electrically connected.

[0035] Here, the other of the source and drain of transistor 103, wiring 124, junction 13 0, wiring 125, one of the source and drain of transistor 104, capacitor 108 One of the electrodes of and the node connecting the gate of transistor 105 is defined as node FD. Node FD can function as a charge detection unit.

[0036] The other electrode (anode) of the photoelectric conversion device 240 is electrically connected to wiring 121 . The gate of transistor 103 is electrically connected to wiring 127. Transistor 1 The other of the source and drain of 04 is electrically connected to wiring 122. Transistor The other of the source and drain of 105 is electrically connected to wiring 123. Transistor The gate of 104 is electrically connected to wiring 126. The gate of transistor 106 is electrically connected to wiring 128. The other electrode of capacitor 108 is electrically connected to a reference potential line such as, for example, a GND wire . The other of the source and drain of transistor 106 is electrically connected to wiring 352.

[0037] Wiring 126, 127, 128 can function as signal lines for controlling the conduction of each transistor . Wiring 352 can function as an output line.

[0038] Wiring 121, 122, 123 can function as power supply lines. In the configuration shown in FIG. 1(B ), the cathode side of the photoelectric conversion device 240 is electrically connected to transistor 103 , and since it is a configuration in which node FD is reset to a high potential and operated, wiring 122 is set to a high potential (a potential higher than that of wiring 121).

[0039] ​ Since the transistor 103 has a function of controlling the potential of the node FD, it can be called a transfer transistor. Since the transistor 104 has a function of resetting the potential of the node FD, it can be called a reset transistor. The transistor 105 functions as an element of a source follower circuit and can output the potential of the node FD as image data to the wiring 352, so it can be called a source follower transistor. Since the transistor 106 has a function of selecting a pixel that outputs image data, it can be called a selection transistor. Here, it is preferable that at least a part of the photoelectric conversion device 240 overlaps with the transistor 104, the transistor 105, and the transistor 106. For example, a configuration in which a part of the photoelectric conversion device 240 overlaps with a part of the transistor 104 and a part of the transistor 105 may be adopted. For example, a configuration in which a part of the photoelectric conversion device 240 overlaps with a part of the transistor 104 and a part of the transistor 106 may be adopted. For example, a configuration in which a part of the photoelectric conversion device 240 overlaps with a part of the transistor 105 and a part of the transistor 106 may be adopted.

[0040] For example, a configuration in which a part of the photoelectric conversion device 240 overlaps with a part of the transistor 104 may be adopted. For example, a configuration in which a part of the photoelectric conversion device 240 overlaps with a part of the transistor 105 may be adopted. For example, a configuration in which a part of the photoelectric conversion device 240 overlaps with a part of the transistor 106 may be adopted. The larger the overlapping area of the photoelectric conversion device 240 with the transistor 104, the transistor 105, and the transistor 106, the more the occupied area of the photoelectric conversion device 240 can be increased in each pixel. ​ Therefore, even if the pixel size is reduced, the occupancy of the photoelectric conversion device 240 in each pixel Since the area ratio can be increased, it is possible to provide an imaging device with high resolution and high sensitivity. This can be done.

[0041] In FIG. 1B, the cathode of the photoelectric conversion device 240 is electrically connected to the node FD. 2, the anode side of the photoelectric conversion device 240 is a transistor. It may be configured to be electrically connected to one of the source and drain of 103 .

[0042] In this configuration, the node FD is reset to a low potential and is operated. 22 is set to a low potential (a potential lower than that of the wiring 121). In both cases, the transistor 103 is preferably a p-channel transistor. More preferably, transistor 106 is a p-channel type.

[0043] <Operation method of imaging device> An imaging device according to one aspect of the present invention is a rolling shutter type or a global shutter type. Figure 3(A) shows the operation of the rolling shutter method. FIG. 3(A) is a schematic diagram of the global shutter method, and FIG. 3(B) is a schematic diagram of the global shutter method. En represents the exposure (storage operation) of the nth column (n is a natural number), and Rn represents the readout operation of the nth column. Figure 3(A) and (B) show the operations from the 1st line to the Mth line (M is a natural number). do.

[0044] The rolling shutter method shown in Figure 3(A) is an operation in which exposure and data readout are performed sequentially. This is a method in which the readout period of one row overlaps with the exposure period of another row. To perform a read operation, imaging can be relatively easily performed even in a circuit configuration with a relatively short data retention period. Note that in the rolling shutter method, since one frame of an image is composed of data without simultaneity in imaging, there are cases where distortion occurs in the image when imaging a moving object. In the rolling shutter method, since one frame of an image is composed of data without simultaneity in imaging, there are cases where distortion occurs in the image when imaging a moving object. In the rolling shutter method, since one frame of an image is composed of data without simultaneity in imaging, there are cases where distortion occurs in the image when imaging a moving object. In the rolling shutter method, since one frame of an image is composed of data without simultaneity in imaging, there are cases where distortion occurs in the image when imaging a moving object.

[0045] As shown in FIG. 3(B), the global shutter method is an operation method in which all pixels are exposed simultaneously to hold data in each pixel and the data is read out row by row. Therefore, even when imaging a moving object, an image without distortion can be obtained. Note that when performing the global shutter method, since the read operation is performed after holding the data in each pixel, a separate memory circuit may be provided to store the data of each pixel. As shown in FIG. 3(B), the global shutter method is an operation method in which all pixels are exposed simultaneously to hold data in each pixel and the data is read out row by row. Therefore, even when imaging a moving object, an image without distortion can be obtained. Note that when performing the global shutter method, since the read operation is performed after holding the data in each pixel, a separate memory circuit may be provided to store the data of each pixel. As shown in FIG. 3(B), the global shutter method is an operation method in which all pixels are exposed simultaneously to hold data in each pixel and the data is read out row by row. Therefore, even when imaging a moving object, an image without distortion can be obtained. Note that when performing the global shutter method, since the read operation is performed after holding the data in each pixel, a separate memory circuit may be provided to store the data of each pixel. As shown in FIG. 3(B), the global shutter method is an operation method in which all pixels are exposed simultaneously to hold data in each pixel and the data is read out row by row. Therefore, even when imaging a moving object, an image without distortion can be obtained. Note that when performing the global shutter method, since the read operation is performed after holding the data in each pixel, a separate memory circuit may be provided to store the data of each pixel. As shown in FIG. 3(B), the global shutter method is an operation method in which all pixels are exposed simultaneously to hold data in each pixel and the data is read out row by row. Therefore, even when imaging a moving object, an image without distortion can be obtained. Note that when performing the global shutter method, since the read operation is performed after holding the data in each pixel, a separate memory circuit may be provided to store the data of each pixel.

[0046] <Operation of Pixel Circuit> Next, an example of the operation of the pixel circuit shown in FIG. 1(B) will be described using the timing chart of FIG. 4. In the description of the timing chart in this specification, the high potential is represented by “H” and the low potential is represented by “L”. A constant “L” is supplied to wiring 121, and a constant “H” is supplied to wirings 122 and 123. Next, an example of the operation of the pixel circuit shown in FIG. 1(B) will be described using the timing chart of FIG. 4. In the description of the timing chart in this specification, the high potential is represented by “H” and the low potential is represented by “L”. A constant “L” is supplied to wiring 121, and a constant “H” is supplied to wirings 122 and 123. Next, an example of the operation of the pixel circuit shown in FIG. 1(B) will be described using the timing chart of FIG. 4. In the description of the timing chart in this specification, the high potential is represented by “H” and the low potential is represented by “L”. A constant “L” is supplied to wiring 121, and a constant “H” is supplied to wirings 122 and 123. Next, an example of the operation of the pixel circuit shown in FIG. 1(B) will be described using the timing chart of FIG. 4. In the description of the timing chart in this specification, the high potential is represented by “H” and the low potential is represented by “L”. A constant “L” is supplied to wiring 121, and a constant “H” is supplied to wirings 122 and 123.

[0047] In period T1, when the potential of wiring 126 is “H”, the potential of wiring 127 is “H”, and the potential of wiring 128 is “L”, transistors 103 and 104 conduct. At this time, the potential “H” of wiring 122 is supplied to node FD (reset operation). In period T1, when the potential of wiring 126 is “H”, the potential of wiring 127 is “H”, and the potential of wiring 128 is “L”, transistors 103 and 104 conduct. At this time, the potential “H” of wiring 122 is supplied to node FD (reset operation). In period T1, when the potential of wiring 126 is “H”, the potential of wiring 127 is “H”, and the potential of wiring 128 is “L”, transistors 103 and 104 conduct. At this time, the potential “H” of wiring 122 is supplied to node FD (reset operation).

[0048] In period T2, when the potential of wiring 126 is “L”, the potential of wiring 127 is “H”, and the potential of wiring 128 is “L”, transistor 104 becomes non-conductive and the supply of the reset potential stops. In period T2, when the potential of wiring 126 is “L”, the potential of wiring 127 is “H”, and the potential of wiring 128 is “L”, transistor 104 becomes non-conductive and the supply of the reset potential stops. It is blocked. Also, the potential of node FD decreases according to the operation of the photoelectric conversion device 240. (Accumulation operation).

[0049] During period T3, when the potential of wiring 126 is “L”, the potential of wiring 127 is “L”, and the potential of wiring 12 8 is “L”, transistor 103 becomes non-conductive, and the potential of node FD is determined and held (holding operation). During period T3, the amount of charge flowing out from node FD depends on the capacitance of capacitor 108 connected to node FD, etc. Therefore, depending on the capacitance of capacitor 108, etc., the length of period T3 of the data holding operation can be set appropriately.

[0050] During period T4, when the potential of wiring 126 is “L”, the potential of wiring 127 is “L”, and the potential of wiring 12 8 is “H”, transistor 106 becomes conductive, and the potential of node FD is read out to wiring 352 by the source follower operation (readout operation). The above is an example of the operation of the pixel circuit shown in FIG. 1(B). The above is an example of the operation of the pixel circuit shown in FIG. 1(B).

[0051] <Readout circuit> FIG. 5 is a diagram for explaining an example of a readout circuit included in a drive circuit 333 connected to a pixel circuit 331, and shows a circuit diagram of a CDS circuit 400 and a block diagram of an A / D converter 410 electrically connected to the CDS circuit 400. Note that the CDS circuit and the A / D converter shown in FIG. 5 are examples, and other configurations may be used. FIG. 5 is a diagram for explaining an example of a readout circuit included in a drive circuit 333 connected to a pixel circuit 331, and shows a circuit diagram of a CDS circuit 400 and a block diagram of an A / D converter 410 electrically connected to the CDS circuit 400. Note that the CDS circuit and the A / D converter shown in FIG. 5 are examples, and other configurations may be used. The CDS circuit 400 and the A / D converter shown in FIG. 5 are examples, and other configurations may be used. The CDS circuit 400 and the A / D converter shown in FIG. 5 are examples, and other configurations may be used.

[0052] The CDS circuit 400 includes a capacitor 402 for capacitive coupling, a transistor 403 for supplying a potential V0, a transistor 404 for holding the potential supplied to the A / D converter 410, and a transistor 404 for holding the potential supplied to the A / D converter 410, and The CDS circuit 400 may be configured to include a capacitor 405 for holding potential. The input is electrically connected to the pixel circuit 331 and the transistor 401 that functions as a current source. The output is electrically connected to the comparator circuit (COMP) of the A / D converter 410. can be.

[0053] The potential of the wiring 352 is V res When the pixel circuit 331 is in a reset state, the node N The potential at the connection point between the transistors 403 and 404 and the capacitor 402 is V0. The node N is set to a floating state, and the potential of the wiring 352 is set to V data (Pixel circuit 331 When the image data is output, the potential of node N becomes V0 + V data -V res becomes Therefore, in the CDS circuit 400, the potential of the imaging data output from the pixel circuit 331 is The potential in the reset state can be subtracted, and the noise component can be reduced.

[0054] The A / D converter 410 includes a comparator circuit (COMP) and a counter circuit (C The A / D converter 410 can be configured to have a CDS The signal potential input from the circuit 400 to the comparator circuit (COMP) and the reference potential to be swept The potential (RAMP) is compared with the output of the comparator circuit (COMP). The counter circuit (COUNTER) operates and digital signals are output to multiple wires. .

[0055] <Image capture device structure 1> Next, the pixel structure of the imaging device will be described with reference to a cross-sectional view.

[0056] FIG. 6 is an example of a cross-sectional view of a pixel structure having an element layer 101 and an element layer 100 with a bonding surface therebetween. It is an example of a cross-sectional view of the structure.

[0057] <Element layer 101> The element layer 101 has a transistor 104, a transistor 10 5, a transistor 106, and a capacitor 108 that constitute a pixel circuit 331. The transistor 104, the tra nsistor 105, and the transistor 106 are provided on a semiconductor substrate 211.

[0058] The element layer 101 is provided with an insulating layer 212, an insulating layer 213, an insulating layer 214, an insulating layer 215, an insulating layer 216, an insulating layer 217, an insulating layer 228, and an insulating layer 229. Further, a conductive layer 13 1 is provided. Here, the conductive layer 131 functions as a part of the wiring 125.

[0059] The insulating layer 212 has a function as a protective film. The insulating layers 213, 214, 2 15, 217, and 228 have functions as an interlayer insulating film and a planarizing film. The insulating layer 216 has a function as a dielectric layer of the capacitor 108.

[0060] As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the interlayer insulating film and the planarizing film, for example, an inorganic insulating film such as a silicon oxide film, an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As for the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide

[0061] The insulating layer 229 and the conductive layer 131 have functions as a bonding layer. That is, the ins The insulating layer 229 and the conductive layer 131 are the layers in the element layer 101 that are closest to the element layer 100. Therefore, the transistors 104, 105, 106, and the capacitor 108 are disposed between the semiconductor substrate 211 and the insulating layer 229 and the conductive layer 131.

[0062] The conductive layer 131 is electrically connected to one of the source and drain of the transistor 104, the gate of the transistor 105, and one of the electrodes of the capacitor 108. Also, one of the source and drain of the transistor 105 is electrically connected to one of the source and drain of the transistor 106. Also, the other of the source and drain of the transistor 104 is electrically connected to the wiring 122. Also, the other of the source and drain of the transistor 106 is electrically connected to the wiring 352. Also, the other electrode of the capacitor 108 is electrically connected to a GND wiring or the like.

[0063] The transistors 104, 105, 106 shown in FIG. 6 are provided on the semiconductor substrate 211 and have a conductive layer 280 that functions as a gate, an insulating layer 282 that functions as a gate insulating layer, and an n-type region 284 that functions as a source region or a drain region. As the semiconductor substrate 211, a semiconductor such as a silicon-based semiconductor may be used. For example, single-crystalline silicon may be used. It is preferable to use a p-type substrate for the semiconductor substrate 211, which contains an element that imparts p-type conductivity such as boron. However, in the n-type region 284,

[0064] it preferably contains an element that imparts n-type conductivity such as arsenic or phosphorus and exhibits n-type conductivity. ​​​​

[0065] Also, the transistors 104, 105, and 106 shown in FIG. 6 are fin-type having a channel formation region on the semiconductor substrate 211, and a cross-section in the channel width direction (the cross-section of A1-A2 shown in FIG. 6 ) is shown in FIG. 7(A).

[0066] Note that the structures of the transistors 104, 105, and 106 are not limited to the structures shown in FIG. 6 and can be set as appropriate. For example, the transistors 104, 105, and 106 may be planar-type as shown in FIG. 7(B).

[0067] Also, for example, the transistors 104, 105, and 106 may be transistors having a semiconductor layer 545 of a silicon thin film as shown in FIG. 7(C). The semiconductor layer 545 can be, for example, single-crystalline silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on the semiconductor substrate 211.

[0068] Note that as conductors that can be used for wirings, electrodes, and plugs used for electrical connection between devices, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel , titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium , zirconium, beryllium, indium, ruthenium, iridium, strontium , lanthanum, etc., metal elements selected from these, or alloys containing the above-described metal elements as components, or alloys combining the above-described metal elements can be appropriately selected and used. The conductor is not limited to a single layer and may be a plurality of layers composed of different materials.

[0069] <Element layer 100> The element layer 100 includes a photoelectric conversion device 240 and a transistor 103 that constitute a pixel circuit 331. The photoelectric conversion device 240 and the transistor 103 are provided on a semiconductor substrate 243.

[0070] The element layer 100 is provided with an insulating layer 241, an insulating layer 242, an insulating layer 245, an insulating layer 246, an insulating layer 232, an insulating layer 231, and a conductive layer 132. Here, the conductive layer 132 functions as a part of the wiring 124.

[0071] The photoelectric conversion device 240 is a pn junction type photodiode formed on a p-type semiconductor substrate 243, and has a p-type region 248 and an n-type region 244. Here, the semiconductor substrate 243 and the n-type region 244 can have the same structure as the semiconductor substrate 211 and the n-type region 284. Also, it is preferable that the p-type region 248 has a higher concentration of impurities that impart p-type than other regions of the semiconductor substrate 243.

[0072] The photoelectric conversion device 240 is an embedded type photodiode, and the n-type region 244 functions as one of the electrodes of the photoelectric conversion device 240. Further, the dark current can be suppressed and the noise can be reduced by a thin p-type region 248 provided on the surface side (current extraction side) of the n-type region 244.

[0073] The insulating layer 241 has a function as a protective film. The insulating layer 242 has a function as an element isolation layer. The insulating layer 245 has a function of suppressing the outflow of carriers. Also, the insulating layers 246 and 232 have functions as an interlayer insulating film and a planarization film.

[0074] ​​​​​​​​​​​​The insulating layer 231 and the conductive layer 132 function as a bonding layer. That is, the insu lating layer 231 and the conductive layer 132 are the layers closest to the element layer 101 within the element layer 100 . Therefore, the transistor 103 and the photoelectric conversion device 240 are disposed between the insulating layer 245 and the insulating layer 231 and the conductive layer 132.

[0075] The semiconductor substrate 243 is provided with grooves for separating pixels, and the insulating layer 245 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 245, carriers generated within the photoelectric conversion device 2 40 can be suppressed from flowing out to adjacent pixels. Also, the insulating layer 245 also has a function of suppressing the intrusion of stray light. Therefore, by the insulating layer 245 , color mixing can be suppressed. Note that an antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 245 .

[0076] The insulating layer 242 can be formed by using a method such as the LOCOS (LOCal Oxidation of Silico n) method or the STI (Shallow Trench Isolation) method. As the insulating layer 245, for example, an inorganic insulating film such as silicon oxide or silicon nitride , or an organic insulating film such as polyimide or acrylic can be used. Also , the insulating layer 245 may have a multilayer structure.

[0077] The transistor 103 can have the same configuration as the transistor 104 and the like. Thus , the n-type region 244 functions as the source region and the drain region of the transistor 103 .

[0078] Here, as shown in FIG. 6, one of the electrodes of the photoelectric conversion device 240 (corresponding to the cathode) Further, one of the source and drain of the transistor 103 is formed in the same n-type region 244. With such a configuration, it is not necessary to provide a plug or the like in contact with the cathode of the photoelectric conversion device 240 to extract the current of the photoelectric conversion device 240. Therefore, the surface side of the n-type region 244 that functions as one of the electrodes of the photoelectric conversion device 240 can be covered with the p-type region 248, so that the dark current can be suppressed and the noise can be reduced. For this reason, the transistor 103 is preferably provided in the element layer 100 together with the photoelectric conversion device 240. The other of the source and drain of the transistor 103 is electrically connected to the conductive layer 132. The region corresponding to the anode of the photoelectric conversion device 240 in the semiconductor substrate 243 is electrically connected to the wiring 121 that functions as a power supply line.

[0079]

[0080] <Bonding> Next, the bonding of the element layer 101 and the element layer 100 will be described.

[0081] In the element layer 101, an insulating layer 229 and a conductive layer 131 are provided on the surface of the semiconductor substrate 211 on the side where the transistors 104 to 106 are arranged. The conductive layer 131 has a region embedded in the insulating layer 229. In addition, the surfaces of the insulating layer 229 and the conductive layer 131 are flattened so that their heights are the same.

[0082] In the element layer 100, an insulating layer 231 and a conductive layer 132 are provided on the surface of the semiconductor substrate 243 on the side where the transistor 103 is arranged. The conductive layer 132 is embedded in the insulating layer 231. It has an embedded area. Also, the surfaces of the insulating layer 231 and the conductive layer 132 are flattened so that their heights match.

[0083] Here, it is preferable that the main components of the conductive layer 131 and the conductive layer 132 are the same metal element. Also, it is preferable that the insulating layer 229 and the insulating layer 231 are composed of the same components.

[0084] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au, etc. can be used for the conductive layer 131 and the conductive layer 132. From the ease of bonding, preferably Cu, Al, W, or Au is used. Also, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used for the insulating layer 229 and the insulating layer 231.

[0085] That is, it is preferable to use the same metal material shown above for each of the conductive layer 131 and the conductive layer 132. Also, it is preferable to use the same insulating material shown above for each of the insulating layer 229 and the insulating layer 231. With such a configuration, bonding is performed with the boundary between the element layer 101 and the element layer 100 as the bonding position, and a bonding portion 130 can be formed at the portion where the conductive layer 131 and the conductive layer 132 are in contact.

[0086] Note that the conductive layer 131 and the conductive layer 132 may have a multi-layer structure of a plurality of layers. In that case, it is only necessary that the surface layer (bonding surface) is the same metal material. Also, the insulating layer 229 and the insulating layer 231 may also have a multi-layer structure of a plurality of layers. In that case, it is only necessary that the surface layer (bonding surface) is the same insulating material.

[0087] ​​​​​By this bonding, electrical connection between the conductive layer 131 and the conductive layer 132 can be obtained. Also, a connection having the mechanical strength of the insulating layer 229 and the insulating layer 231 can be obtained.

[0088] For the direct bonding between conductive layers, a surface activation bonding method can be used in which the oxide film on the surface and the adsorbed layer of impurities are removed by sputtering treatment or the like, and the cleaned and activated surfaces are brought into contact with each other for bonding. Or, a diffusion bonding method in which the surfaces are bonded together using a combination of temperature and pressure can be used. Since bonding occurs at the atomic level in both cases, excellent bonding can be obtained both electrically and mechanically.

[0089] Also, for the direct bonding between insulating layers, after obtaining high flatness by polishing or the like, a hydrophilic bonding method can be used in which the surfaces subjected to hydrophilic treatment with oxygen plasma or the like are brought into contact with each other for temporary bonding, and permanent bonding is performed by dehydration by heat treatment. Since the hydrophilic bonding method also involves bonding at the atomic level, excellent mechanical bonding can be obtained.

[0090] When bonding the element layer 101 and the element layer 100, since the insulating layer and the metal layer are mixed on each bonding surface, for example, a combination of the surface activation bonding method and the hydrophilic bonding method can be used.

[0091] For example, a method can be used in which the surface is cleaned after polishing, an antioxidant treatment is performed on the surface of the metal layer, and then a hydrophilic treatment is performed for bonding. Also, the surface of the metal layer can be made of a metal with low oxidation resistance such as Au, and a hydrophilic treatment can be performed. In addition, bonding methods other than those described above may be used.

[0092] ​​​​​​​​​​​​​By the above bonding, a part of the pixel circuit 331 included in the element layer 100 and another part of the pixel circuit included in the element layer 10 1 are connected, and the sources and drains of the transistors 103 On the other hand, a node FD composed of the wiring 124, the junction 130, the wiring 125, one of the sources and drains of the transistor 104, one electrode of the capacitor 108, and the gate of the transistor 105 can be formed. In this way, at least a part of the photoelectric conversion device 240, the transistors 104, 105, and 106 can be configured to overlap. Therefore, even if the pixel size is miniaturized, the ratio of the occupied area of the photoelectric conversion device 240 in each pixel can be increased, so that a high-resolution and high-sensitivity imaging device can be provided. In FIG. 6, an example in which the transistors 105 and 106 overlap the photoelectric conversion device 2 40 is shown, but the present invention is not limited thereto. The layout of the photoelectric conversion device 240, the transistors 103 to 106, the capacitor 108, etc. can be set as appropriate .

[0093] In addition, in the pixel structure shown in FIG. 6, the element layer 101 and the element layer 100 are electrically connected by bonding the conductive layer 131 and the conductive layer 132, but the present invention is not limited thereto . For example, the element layer 101 and the element layer 100 may be configured to be electrically connected using bump bonding .

[0094] Also, in the pixel structure shown in FIG. 6, the element layer 101 and the element layer 100 are electrically connected by bonding the conductive layer 131 and the conductive layer 132, but the present invention is not limited thereto . For example, the element layer 101 and the element layer 100 may be configured to be electrically connected using bump bonding .

[0095] In the above, the configuration in which the components of the pixel circuit 331 are divided into the element layer 100 and the element layer 101 has been described. At this time, the drive circuits 332 and 333 are provided in the element layer 10 ​​It may be formed on 1 or may be formed on the element layer 100. Also, the components of the drive circuits 332 and 333 may be divided into the element layer 100 and the element layer 101. For example, the n-channel transistors of the drive circuits 332 and 333 may be formed on one of the element layer 100 and the element layer 101, and the p-channel transistors of the drive circuits 332 and 333 may be formed on the other of the element layer 100 and the element layer 101. For example, the n-channel transistors of the drive circuits 332 and 333 may be formed on one of the element layer 100 and the element layer 101, and the p-channel transistors of the drive circuits 332 and 333 may be formed on the other of the element layer 100 and the element layer 101. For example, the n-channel transistors of the drive circuits 332 and 333 may be formed on one of the element layer 100 and the element layer 101, and the p-channel transistors of the drive circuits 332 and 333 may be formed on the other of the element layer 100 and the element layer 101. For example, the n-channel transistors of the drive circuits 332 and 333 may be formed on one of the element layer 100 and the element layer 101, and the p-channel transistors of the drive circuits 332 and 333 may be formed on the other of the element layer 100 and the element layer 101. It may be formed on 1 or may be formed on the element layer 100. Also, the components of the drive circuits 332 and 333 may be divided into the element layer 100 and the element layer 101.

[0096] <Configuration 2 of the imaging device> Also, all or part of the drive circuits 332 and 333 may be formed on an element layer different from the element layer 100 or the element layer 101. Here, FIG. 8 shows a perspective view of an imaging device according to an aspect of the present invention. The imaging device includes an element layer 201 including a drive circuit 333, an element layer 101 on the element layer 201, an element layer 100 on the element layer 101, and an element layer 205 on the element layer 100. Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205. Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205. Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205. Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205.

[0097] Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205. Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205. Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205. Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205. Here, the element layer 100 and the element layer 101 are provided with the pixel circuit 331 as described above. Further, a drive circuit 332 may be provided in the element layer 100 and the element layer 101. Also, the element layer 201 is provided with a drive circuit 333. Further, the element layer 205 is provided with an optical conversion layer such as a color filter. Furthermore, a microlens array 255 may be provided in the element layer 205.

[0098] Note that in FIG. 8 and the like, for clarity of explanation, the imaging device is described as being divided into the above four element layers. However, the types, quantities, and positions of the elements included in each element layer are not limited to the description of the present embodiment. For example, an insulating layer, wiring, and plugs in the vicinity of the boundary between the element layers, etc. Note that in FIG. 8 and the like, for clarity of explanation, the imaging device is described as being divided into the above four element layers. However, the types, quantities, and positions of the elements included in each element layer are not limited to the description of the present embodiment. For example, an insulating layer, wiring, and plugs in the vicinity of the boundary between the element layers, etc. Note that in FIG. 8 and the like, for clarity of explanation, the imaging device is described as being divided into the above four element layers. However, the types, quantities, and positions of the elements included in each element layer are not limited to the description of the present embodiment. For example, an insulating layer, wiring, and plugs in the vicinity of the boundary between the element layers, etc. The elements may belong to element layers different from those described in this embodiment. Or, there may be included elements different from insulating layers, wirings, plugs, etc. in the vicinity of the boundary between element layers. It may be.

[0099] <Structure 2 of Imaging Device> Next, the stacked structure of the imaging device shown in FIG. 8 will be described with reference to a cross-sectional view.

[0100] FIG. 9 is an example of a cross-sectional view of a stacked structure in which element layer 201, element layer 101, element layer 100, and element layer 205 are stacked in this order. Element layer 201 and element layer 101 are bonded by bump bonding. Therefore, element layer 201 is disposed on the back side of semiconductor substrate 211 (the side where transistors 104 to 106 are not formed). to 106).

[0101] Note that element layer 101 and element layer 100 have the same structure as the structure shown in FIG. 6 and the like. Therefore, for details, the description related to FIG. 6 and the like can be referred to. However, in FIG. 9, the layout of a part of element layer 101 and element layer 100 is shown with a change from FIG. 6. For example, in FIG. 9, since transistor 104 is arranged in the channel width direction of transistors 105 and 106, it is not shown. Hereinafter, the details of the configuration of element layer 201 and element layer 205 will be described. 6, it is not shown. Hereinafter, the details of the configuration of element layer 201 and element layer 205 will be described. 6, it is not shown. Hereinafter, the details of the configuration of element layer 201 and element layer 205 will be described.

[0102] <Element Layer 201> Element layer 201 has a drive circuit 333 provided on semiconductor substrate 261. The drive circuit 333 includes, as shown in FIG. 5, a CDS circuit 400, an A / D converter 410, and the like. In FIG. 9, as a part of the above circuits, capacitor 402 included in CDS circuit 400 ​​​​​​​Shows the transistor 403 and the transistor 115 included in the A / D converter 410. Here, one electrode of the capacitor 402 and one of the source and drain of the transistor 403 are electrically connected.

[0103] The element layer 201 is provided with an insulating layer 262, an insulating layer 263, an insulating layer 264, an insulating layer 265, an insulating layer 266, and an insulating layer 267. Further, a conductive layer 273 is provided on the insulating layer 267.

[0104] The insulating layer 262 has a function as a protective film. The insulating layers 263, 264, 265, and 267 have functions as an interlayer insulating film and a planarization film. The insulating layer 266 has a function as a dielectric layer of the capacitor 108.

[0105] The semiconductor substrate 261 may have the same configuration as the above-described semiconductor substrate 211. Further, the transistors 403 and 115 may have the same configuration as the above-described transistor 105 and the like. Further, the capacitor 402 may have the same configuration as the above-described capacitor 108. Further, the insulating layers 262, 263, 264, 265, 266, and 267 may have the same configuration as the above-described insulating layers 212, 213, 214, and 215, insulating layer 216, and insulating layer 217.

[0106] The conductive layer 273 is electrically connected to the other electrode of the capacitor 108, and the element layer 201 is in conduction with the element layer 101 through the conductive layer 273. ·

[0107] Here, the element layer 101 has a conductive layer 270 that is electrically connected to the wiring 352. ​​​​, it is electrically connected to the element layer 201 via the conductive layer 270. The conductive layer 270 is disposed within openings formed in the semiconductor substrate 211 , the insulating layer 212, the insulating layer 213, the insulating layer 214, and the insulating layer 215. The upper surface of the conductive layer 270 is exposed from the insulating layer 215 and contacts the wiring 352, and the lower surface of the conductive layer 270 is exposed from the semiconductor substrate 211. Further, an insulating layer 271 is preferably disposed in contact with the side surface of the conductive layer 270. The insulating layer 271 functions as a protective film . .

[0108] The conductive layer 270 and the insulating layer 271 may be formed using a silicon through - via (TSV) technology. At this time, the semiconductor substrate 211 is preferably thinned by polishing .

[0109] As shown in FIG. 9, a bump 272 is provided between the conductive layer 273 and the conductive layer 270 . The bump 272 can be formed using a conductive material containing gold (Au), nickel (Ni), indium (In), tin (Sn), or the like. For example, solder may be used as the bump 272 .

[0110] By providing the bump 272, the conductive layer 270 and the conductive layer 273 can be electrically connected, and the element layer 101 and the element layer 201 can be electrically and mechanically joined. Thereby, the other source and drain of the transistor 106 can be electrically connected to one of the source and drain of the transistor 403 via the capacitor 402. In this way, the pixel circuit 331 provided in the element layer 100 and the element layer 101 can be electrically connected to the driving circuit 333 provided in the element layer 201 . .

[0111] ​​​​​​In the laminated structure shown in FIG. 9, the element layer 201 and the element layer 101 are bonded together using bumps 272, but the present invention is not limited thereto. For example, bumps may be provided on the conductive layer 270 side and the conductive layer 273 side, respectively, to bond the element layer 201 and the element layer 101. Further, for example, the element layer 201 and the element layer 101 may be bonded together using the same method as the bonding of the conductive layer 131 and the insulating layer 229, and the conductive layer 132 and the insulating layer 231 described above. However, the present invention is not limited to this. For example, bumps may be provided on the conductive layer 270 side and the conductive layer 273 side, respectively, to bond the element layer 201 and the element layer 101. Further, for example, the element layer 201 and the element layer 101 may be bonded together using the same method as the bonding of the conductive layer 131 and the insulating layer 229, and the conductive layer 132 and the insulating layer 231 described above. That is, they may be bonded together.

[0112] <Element layer 205> The element layer 205 is formed on the element layer 100. The element layer 205 includes a light-shielding layer 251, an optical conversion layer 250, and a microlens array 255.

[0113] The light-shielding layer 251 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 251. Further, a dielectric film having a function as an antireflection film may be laminated on the metal layer. The light-shielding layer 251 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 251. Further, a dielectric film having a function as an antireflection film may be laminated on the metal layer. A dielectric film having a function as an antireflection film may be laminated on the metal layer.

[0114] A color filter or the like can be used for the optical conversion layer 250. By assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the pixels separately, a color image can be obtained. A color filter or the like can be used for the optical conversion layer 250. By assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the pixels separately, a color image can be obtained. A color image can be obtained.

[0115] Further, if a wavelength cut filter is used for the optical conversion layer 250, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0116] For example, if a filter that blocks light having a wavelength equal to or less than the wavelength of visible light is used for the optical conversion layer 250, an infrared imaging device can be obtained. Further, if a filter that blocks light having a wavelength equal to or less than the wavelength of near-infrared light is used for the optical conversion layer 250, If a filter is used, an infrared imaging device can be obtained. Also, for the optical conversion layer 250 if a filter that blocks light with a wavelength equal to or longer than that of visible light is used, an ultraviolet imaging device can be obtained .

[0117] Also, if a scintillator is used for the optical conversion layer 250, an imaging device can be obtained that visualizes the intensity of radiation such as X-rays used in an X-ray imaging device or the like. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, the image data is acquired by detecting the light with the photoelectric conversion device 240. Also, an imaging device having such a configuration may be used for a radiation detector or the like . When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, the image data is acquired by detecting the light with the photoelectric conversion device 240. Also, an imaging device having such a configuration may be used for a radiation detector or the like . .

[0118] The scintillator contains a substance that emits visible light or ultraviolet light by absorbing the energy when irradiated with radiation such as X-rays or gamma rays. For example, substances such as Gd2O2S:Tb, Gd2O2S: Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used .

[0119] A microlens array 255 is provided on the optical conversion layer 250. The light passing through each lens of the microlens array 255 passes through the optical conversion layer 250 directly below and is irradiated onto the photoelectric conversion device 240. By providing the microlens array 255, the condensed light can be incident on the photoelectric conversion device 240, so that photoelectric conversion can be performed efficiently. The microlens array 255 is made of a resin with high transparency to visible light . . . . ​​It is preferably formed of glass or the like.

[0120] <Configuration 3 of the imaging device> Also, an element layer having a memory circuit may be formed between the element layer 201 and the element layer 101. Yes.

[0121] For the memory circuit, it is preferable to use a transistor (hereinafter referred to as an OS transistor) using a metal oxide in the channel formation region. The OS transistor has an extremely small off-current and can suppress unnecessary outflow of data from the pixel circuit. Therefore, by using the OS transistor for the select transistor of the memory circuit, unnecessary outflow of data can be suppressed, and the refresh frequency can be suppressed. Therefore, power consumption can be suppressed. The OS transistor has an extremely small off-current and can suppress unnecessary outflow of data from the pixel circuit. Therefore, by using the OS transistor for the select transistor of the memory circuit, unnecessary outflow of data can be suppressed, and the refresh frequency can be suppressed. Therefore, power consumption can be suppressed. Yes. Yes.

[0122] Also, the OS transistor can be formed on a silicon device via an insulating layer without using complicated processes such as bonding or bump bonding. Therefore, a memory circuit using the OS transistor can be manufactured while keeping the manufacturing cost relatively low. Therefore, the OS transistor can be formed on a silicon device via an insulating layer without using complicated processes such as bonding or bump bonding. Therefore, a memory circuit using the OS transistor can be manufactured while keeping the manufacturing cost relatively low.

[0123] Figure 10(A) is a simplified block diagram for explaining the electrical connection of the elements included in the element layer 201, the element layer 202, the element layer 101, and the element layer 100. Yes.

[0124] The element layer 202 includes a memory circuit 321 (MEM) having the above OS transistor. The element layer 201, the element layer 101, and the element layer 100 have the same configuration as described above. That is, the element layer 101 and the element layer 100 have a pixel circuit 331 (PIX) and a drive circuit 332 (Driver), and the element layer 201 has a function as a readout circuit. That is, the element layer 101 and the element layer 100 have a pixel circuit 331 (PIX) and a drive circuit 332 (Driver), and the element layer 201 has a function as a readout circuit. The element layer 201 includes a driver circuit 333 (RC). The row driver 312 (RD) and the column driver 313 (CD) function as The element layer 205 is not shown here.

[0125] The pixel circuits 331 are arranged in a matrix and connected to a driving circuit 332 via wiring 351. The driving circuit 332 controls the data acquisition operation and selection of the pixel circuit 331. The driving circuit 332 can control the operation of the device. can be used.

[0126] In addition, the pixel circuit 331 is electrically connected to a driver circuit 333 via a wiring 352 . The drive circuit 333 functions as a readout circuit and includes a correlated double readout circuit for reducing noise. Sampling circuit (CDS circuit) and A / D converter that converts analog data into digital data The drive circuit 333 includes a drive circuit for controlling the operation of the readout circuit. It may also have an operating circuit.

[0127] The driver circuit 333 is electrically connected to the memory circuit 321 via a wiring 353. The relay circuit 321 can hold the digital data output from the driver circuit 333. Alternatively, the driver circuit 333 can output digital data directly to the outside.

[0128] The memory circuit 321 is electrically connected to the row driver 312 via a wiring 354 . The memory circuit 321 is electrically connected to the column driver 313 via wiring 355. The row driver 312 is a drive circuit for the memory circuit 321, and is used for writing and reading data. It can control reading. The column driver 313 is a drive circuit of the memory circuit 321 and can control data reading. The connection details of the pixel circuit 331, the drive circuit 333, and the memory circuit 321 will be described using the block diagram of FIG. 10 (

[0129] B). The number of read circuits included in the drive circuit 333 can be the same as that of the pixel circuit 331. For each pixel circuit 331, one read circuit is electrically connected via the wiring 352. Also, the read circuit of the drive circuit 333 is connected to a plurality of wirings 353, and each of the wirings 353 is electrically connected to one memory cell 321a. Note that a data holding circuit may be provided between the read circuit of the drive circuit 333 and the memory circuit 321. The A / D converter included in the read circuit of the drive circuit 333 outputs parallel binary data for a predetermined number of bits. Therefore, the A / D converter is connected to the memory cells 321a for the number of bits. For example, when the output of the A / D converter is 8 bits, it is connected to 8 memory cells 321a. With the above configuration, in the imaging device according to one aspect of the present invention, A / D conversion of analog data acquired by all pixel circuits 331 can be performed in parallel, and the converted digital data can be directly written into the memory circuit 321. That is, the storage from imaging to the memory circuit can be performed at high speed. Also, it is possible to perform the imaging operation, the A / D conversion operation, and the read operation in parallel. By adopting such a configuration, it is possible to relatively easily apply the global shutter method in which the charge accumulation operation is performed simultaneously for all pixels. The read circuit of the drive circuit 333 is connected to a plurality of wirings 353, and each of the wirings 353 is electrically connected to one memory cell 321a. The read circuit of the drive circuit 333 is connected to a plurality of wirings 353, and each of the wirings 353 is electrically connected to one memory cell 321a. Note that a data holding circuit may be provided between the read circuit of the drive circuit 333 and the memory circuit 321. Note that a data holding circuit may be provided between the read circuit of the drive circuit 333 and the memory circuit 321.

[0130] The A / D converter included in the read circuit of the drive circuit 333 outputs parallel binary data for a predetermined number of bits. Therefore, the A / D converter is connected to the memory cells 321a for the number of bits. For example, when the output of the A / D converter is 8 bits, it is connected to 8 memory cells 321a. For example, when the output of the A / D converter is 8 bits, it is connected to 8 memory cells 321a.

[0131] With the above configuration, in the imaging device according to one aspect of the present invention, A / D conversion of analog data acquired by all pixel circuits 331 can be performed in parallel, and the converted digital data can be directly written into the memory circuit 321. That is, the storage from imaging to the memory circuit can be performed at high speed. That is, the storage from imaging to the memory circuit can be performed at high speed. Also, it is possible to perform the imaging operation, the A / D conversion operation, and the read operation in parallel. By adopting such a configuration, it is possible to relatively easily apply the global shutter method in which the charge accumulation operation is performed simultaneously for all pixels.

[0132] <Memory circuit> FIG. 11(A) is a diagram showing the connection relationship between the memory cell 321a included in the memory circuit 321, the load driver 31 2, and the column driver 313. As the transistor constituting the memory cell 321a, an OS transistor can be used.

[0133] The memory circuit 321 has m (m is an integer of 1 or more) memory cells 321a in one column and n (n is an integer of 1 or more ) memory cells 321a in one row, for a total of m × n memory cells 321a, and the memory cells 321a are arranged in a matrix. In FIG. 11(A), the addresses of the memory cells 321a are also shown. For example, [1,1] indicates the memory cell 321a located at the address of the first row and first column, , and [i, j] (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) indicates the memory cell 321a located at the address of the i-th row and j-th column. Note that the number of wirings connecting the memory circuit 321 and the load driver 312 is determined by the configuration of the memory cell 321a, the number of memory cells 321a included in one column, etc. Also, the number of wirings connecting the memory circuit 321 and the column driver 313 is determined by the configuration of the memory cell 321a, the number of memory cells 321a included in one row, etc.

[0134] FIGS. 11(B) to (E) are diagrams for explaining the memory cells 321aA to memory cells 321aD applicable to the memory cell 321a. In the following description, the bit lines can be connected to the column driver 313. Also, the word lines can be connected to the load driver 3 12. Note that the bit lines are also electrically connected to the read circuit of the drive circuit 333, but are not shown here. ​

[0135] For the load driver 312 and the column driver 313, for example, a decoder or a shift register can be used. Note that a plurality of load drivers 312 and column drivers 31 3 may be provided.

[0136] [DOSRAM] FIG. 11(B) shows a circuit configuration example of the DRAM type memory cell 321aA. In this specification etc. the DRAM using an OS transistor is called DOSRAM (Dynamic Ox ide Semiconductor Random Access Memory). The memory cell 321aA includes a transistor M11 and a capacitor Cs.

[0137] The first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, and the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring W L, and the back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the capacitor Cs is connected to the wiring GNDL. The wiring GNDL is a wiring that supplies a low level potential (reference potential).

[0138] The wiring BIL functions as a bit line. The wiring WL functions as a word line. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0139] For writing and reading data, a high level potential is applied to the wiring WL and the transistor Turn on M11 and electrically connect the wiring BIL and the first terminal of the capacitor Cs. This is done by.

[0140] It is preferable to use an OS transistor for the transistor M11. Also, for the semiconductor layer of the OS transistor, an oxide semiconductor having at least one of indium, element M (element M is one or more of aluminum, gallium, yttrium, or tin), and zinc is preferably used. In particular, it is preferable to use an oxide semiconductor having indium, gallium, and zinc. is preferably used.

[0141] The OS transistor to which an oxide semiconductor containing indium, gallium, and zinc is applied has the characteristic that the off-current is extremely small. By using the OS transistor as the transistor M11, the leakage current of the transistor M11 can be made very low. That is, the written data can be held by the transistor M11 for a long time, so the frequency of refreshing the memory cell can be reduced. Also, the refresh operation of the memory cell can be made unnecessary.

[0142] [NOSRAM] Fig. 11(C) shows a circuit configuration example of a gain cell type (also referred to as "2Tr1C type") memory cell 321aB having two transistors and one capacitor. The memory cell 321 aB has a transistor M11, a transistor M3, and a capacitor Cs.

[0143] The first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring WBL, and the gate of the transistor M11 is connected to the wiring W. It is connected to L, and the back gate of transistor M11 is connected to wiring BGL. The second terminal of capacitor Cs is connected to wiring RL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first

[0144] terminal of capacitor Cs. Wiring WBL functions as a write bit line. Wiring RBL functions as a read bit line. Wiring WL functions as a word line. Wiring RL functions as a wiring for applying a predetermined potential to the second terminal of capacitor Cs. During data writing and data retention, it is

[0145] preferable to apply a reference potential to wiring RL. Wiring BGL functions as a wiring for applying a potential to the back gate of transistor M11. By applying an arbitrary potential to wiring BGL, the threshold voltage of

[0146] transistor M11 can be increased or decreased. Data writing is performed by applying a high-level potential to wiring WL to turn transistor M11 on and electrically connecting wiring WBL and the first terminal of capacitor Cs. Specifically, when transistor M11 is on, a potential corresponding to the information to be recorded is applied to wiring WBL, and this potential is written to the first terminal of capacitor Cs and the gate of transistor M3. Thereafter, a low-level potential is applied to wiring WL to turn transistor

[0147] Data reading is performed by applying a predetermined potential to wiring RL and wiring SL. The current flowing between the source and drain of transistor M3, and the potential at the first terminal of transistor M3 are determined by the potential at the gate of transistor M3 and the potential at the second terminal of transistor M3. Therefore, by reading the potential of wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of capacitor Cs (or the gate of transistor M3) can be read. That is, the information written into this memory cell can be read from the potential held at the first terminal of capacitor Cs (or the gate of transistor M3). Or, the presence or absence of the information written into this memory cell can be determined. Or, the presence or absence of the information written into this memory cell can be known.

[0148] Also, as shown in FIG. 11(D), a configuration in which wiring WBL and wiring RBL are combined into a single wiring BIL may be used. The memory cell 321aC shown in FIG. 11(D) has a configuration in which the wiring WBL and wiring RBL of the memory cell 321aB are combined into a single wiring BIL, and the second terminal of transistor M11 and the first terminal of transistor M3 are electrically connected to wiring BIL. That is, the memory cell 321aC has a configuration that operates with a single wiring BIL as both the write bit line and the read bit line.

[0149] Note that it is also preferable to use an OS transistor for transistor M 11 in memory cells 321aB and 321aC. By using an OS transistor for transistor M11, a 2Tr1C type such as memory cells 321aB and 321aC ​A memory device using a memory cell is called NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).

[0150] Also, FIG. 11(E) shows a circuit configuration example of a gain cell type (also referred to as "3Tr1C type" ) memory cell 321aD. The memory cell 321aD includes transistors M11, M5, and M6, and a capacitor Cs, and has. .

[0151] The first terminal of transistor M11 is connected to the first terminal of capacitor Cs, and the second terminal of transistor M11 is connected to wiring BIL. The gate of transistor M11 is connected to wiring WL , and the back gate of transistor M11 is electrically connected to wiring BGL. The second terminal of capacitor Cs is electrically connected to the first terminal of transistor M5, wiring GNDL, and. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor Cs. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6

[0152] is connected to wiring RL. Wiring BIL functions as a bit line, wiring WL functions as a write word line,

[0153] and wiring RL functions as a read word line. Wiring BGL functions as a wiring for applying a potential to the back gate of transistor M11. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M11 can be increased or decreased.

[0154] Data writing is performed by applying a high-level potential to the wiring WL, turning on the transistor M11, and electrically connecting the wiring BIL and the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in the on state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the first terminal of the capacitor Cs and the gate of the transistor M5. Thereafter, a low-level potential is applied to the wiring WL to turn off the transistor M11, thereby holding the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M5.

[0155] Data reading is performed by pre-charging a predetermined potential to the wiring BIL, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RL. Since the wiring RL becomes a high-level potential, the transistor M6 turns on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, but the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change according to the potential held at the first terminal of the capacitor Cs (or the gate of the transistor M5). Here, by reading the potential of the wiring BIL, the potential held at the first terminal of the capacitor Cs (or the gate of the transistor M5) can be read. That is, the information written in this memory cell can be read from the potential held at the first terminal of the capacitor Cs (or the gate of the transistor M5). Or, it is possible to know whether the information written in this memory cell is present or not. ​

[0156] In the memory cell 321aD as well, it is preferable to use an OS transistor for the transistor M11. Applying an OS transistor as the transistor M11, the 3Tr1C type memory cell 321aD is one aspect of the aforementioned NOSRAM. The configuration of the memory cell can be appropriately changed. type memory cell 321aD is one aspect of the aforementioned NOSRAM. The memory cell can appropriately change the circuit configuration. The circuit configuration can be changed as appropriate.

[0157] <Structure 3 of the imaging device> Next, the stacked structure of the imaging device shown in FIG. 10(A) will be described using a cross-sectional view.

[0158] FIG. 12 is an example of a cross-sectional view of a stacked structure in which the element layer 201, element layer 202, element layer 101, element layer 100, and element layer 205 are stacked in this order. The element layer 202 is formed on the element layer 201 using a film forming process, and the element layer 202 and the element layer 101 are joined by bump bonding. using a film forming process, and the element layer 202 and the element layer 101 are joined by bump bonding. formed using a film forming process, and the element layer 202 and the element layer 101 are joined by bump bonding. joined.

[0159] Note that, except for the element layer 202, the element layers 201, 101, 100, and element layer 205 have substantially the same structure as the structure shown in FIG. 9. Therefore, for details, the description related to FIG. 9 and the like can be referred to. However, in FIG. 12, since the element layer 201 has a load driver 312 and a column driver 313, some of the configurations are different from those of FIG. 9. Note that, except for the element layer 202, the element layers 201, 101, 100, and element layer 205 have substantially the same structure as the structure shown in FIG. 9. Therefore, for details, the description related to FIG. 9 and the like can be referred to. However, in FIG. 12, since the element layer 201 has a load driver 312 and a column driver 313, some of the configurations are different from those of FIG. 9. For example, in FIG. 12, the transistor 116 included in the load driver 312 is shown in the element layer 201. The transistor 116 has the same configuration as the transistor 115. For example, in FIG. 12, the transistor 116 included in the load driver 312 is shown in the element layer 201. The transistor 116 has the same configuration as the transistor 115. For example, in FIG. 12, the transistor 116 included in the load driver 312 is shown in the element layer 201. The transistor 116 has the same configuration as the transistor 115. For example, in FIG. 12, the transistor 116 included in the load driver 312 is shown in the element layer 201. The transistor 116 has the same configuration as the transistor 115. has.

[0160] Also, in the element layer 201, an insulating layer 218 is provided on the insulating layer 267. The insulating layer 218 has the function as a blocking film. As the blocking film, it is preferable to use a film having a function of preventing the diffusion of hydrogen.

[0161] In a Si device, hydrogen is required to terminate dangling bonds, but hydrogen near the OS transistor becomes one of the factors generating carriers in the oxide semiconductor layer and reduces the reliability. Therefore, it is preferable to provide a hydrogen blocking film between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0162] As the blocking film, for example, silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0163] Hereinafter, the details of the configuration of the element layer 202 will be described.

[0164] <Element layer 202> The element layer 202 is formed on the element layer 201. The element layer 202 has a memory circuit 321 having an OS transistor. Here, as a part of the memory circuit 321, the transistor 111 and the capacitor 112 included in the memory cell 321a are shown.

[0165] The element layer 202 is provided with an insulating layer 221, an insulating layer 222, an insulating layer 223, an insulating layer 224, an insulating layer 225, an insulating layer 226, an insulating layer 227, and an insulating layer 268. Further, a conductive layer 273 is provided on the insulating layer 268.

[0166] ​​​​​​​​​​​The insulating layers 221, 224, 227, and 268 function as interlayer insulating films and planarization films. The insulating layer 222 functions as a gate insulating film. As the gate insulating film, a silicon oxide film or the like can be used. The insulating layer 223 functions as a protective film. The insulating layer 225 functions as a blocking film. The insulating layer 226 functions as a dielectric layer of a capacitor. The conductive layer 273 is electrically connected to the other electrode of the capacitor 402 of the element layer 201 and electrically connected to the conductive layer 270 via the bump 272, similarly to FIG. 9. One of the source or drain of the transistor 111 is electrically connected to one of the source or drain of the transistor 115 of the element layer 201. The gate of the transistor 111 is electrically connected to one of the source or drain of the transistor 116 of the element layer 201. The other of the source or drain of the transistor 111 is electrically connected to one of the electrodes of the capacitor 112. FIG. 13(A) shows the details of the transistor 111. The transistor 111 shown in FIG. 13(A) has a self-aligned structure in which an insulating layer is provided on a stack of an oxide semiconductor layer and a conductive layer, and source electrodes 705 and drain electrodes 706 are formed by providing openings reaching the oxide semiconductor layer. The transistor 111 can be configured to have a channel formation region, a source region 703, a drain region 704, a gate electrode 701, and a gate insulating film 702 formed in the oxide semiconductor layer. At least the gate insulating film 702 and the gate electrode are provided in the opening.

[0167]

[0168]

[0169] ​ An electrode 701 is provided. An oxide semiconductor layer 707 may further be provided in the opening. This is also acceptable.

[0170] Also, as shown in FIG. 13(B), the transistor 111 may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask. This is also acceptable. This is also acceptable.

[0171] Also, as shown in FIG. 13(C), the transistor 111 may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701. This is also acceptable. This is also acceptable.

[0172] Although the transistor 111 is shown having a structure with a back gate 535, it may have a structure without a back gate. The back gate 535 may be electrically connected to the front gate of the transistor 111 provided to face the back gate 535, as in the cross-sectional view in the channel width direction of the transistor 111 shown in FIG. 13(D). Note that FIG. 13(D) is a cross-sectional view corresponding to the dashed-dotted line B1-B2 shown in FIG. 13(A). Here, as a cross-sectional view in the channel width direction, the transistor in FIG. 13(A) is shown as an example, but the same applies to transistors with other structures. Also, the back gate 535 may be configured to supply a fixed potential different from that of the front gate. This is also acceptable. This is also acceptable. This is also acceptable. This is also acceptable. This is also acceptable. As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, may be used. This is also acceptable.

[0173] This is also acceptable. This is also acceptable. A typical example is an oxide semiconductor containing indium, for example, a CAA C-OS or CAC-OS can be used. CAAC-OS is a crystalline The atoms are stable, making it suitable for transistors where reliability is important. exhibits high mobility characteristics and is therefore suitable for transistors that operate at high speed.

[0174] Since the energy gap of the semiconductor layer is large, the OS transistor has a capacitance of several yA / μm (char The OS transistor exhibits extremely low off-state current characteristics (current value per 1 μm of panel width). The transistor is free from impact ionization, avalanche breakdown, and short channel effects. It has characteristics different from Si transistors, such as high voltage resistance, and can form highly reliable circuits. In addition, the electrical characteristics caused by the non-uniformity of the crystallinity, which is a problem in Si transistors, can be improved. OS transistors are also less susceptible to variations in performance.

[0175] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). Titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn containing one or more of the following metals: aluminum, tin, neodymium, or hafnium The In-M-Zn oxide can be a film represented by the following: It can be formed by sputtering or ALD (Atomic Layer Deposition). Alternatively, the insulating film may be formed by a deposition method.

[0176] Sputtering tube used to form In-M-Zn oxide by sputtering method The atomic ratio of the metal elements in the target preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn=1:1: 1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn= 4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. are preferred. The atomic ratio of each layer is the atomic ratio of the metal elements contained in the sputtering target. This includes a variation of plus or minus 40% in numerical ratios.

[0177] The semiconductor layer is made of an oxide semiconductor having a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Below, further Preferably 1 x 10 13 / cm 3 Less than 1×10, more preferably 11 / cm 3 Below, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or The oxide semiconductor has a low density of defect states, It can be said that this is an oxide semiconductor with stable characteristics.

[0178] However, the semiconductor characteristics and electrical characteristics (electric field characteristics) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the characteristics (effective mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be determined. It is preferable that the defect density, the atomic ratio of the metal element to oxygen, the interatomic distance, the density, etc. are appropriate. It is preferable.

[0179] In the oxide semiconductor constituting the semiconductor layer, when silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and it becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10 18 ato ms / cm 3 or less, preferably 2 × 10 17 atoms / cm 3 or less.

[0180] In addition, when an alkali metal and an alkaline earth metal are combined with the oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less.

[0181] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated and the carrier density increases, making it easy to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 × 10 18 atoms / cm 3 or less.

[0182] In addition, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, it reacts with oxygen that binds to metal atoms to form water, and thus oxygen vacancies may be formed in the oxide semiconductor. When the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters oxygen vacancies may function as donors, and electrons, which are carriers, may be generated. Also, part of the hydrogen may bind to oxygen that binds to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Defects in which hydrogen enters oxygen vacancies may function as donors in the oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in the oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, carrier concentration in a state where no electric field is applied may be used as a parameter of the oxide semiconductor instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may sometimes be paraphrased as the "donor concentration". Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 atoms / cm ², preferably less than 1×10 atoms / cm ², more preferably less than 5×10

[0183]

[0184]

[0184] on Mass Spectrometry) is less than 1×10 atoms / cm 20 atoms / cm 3 ², preferably less than 1×10 19 atoms / cm 3 ², more preferably less than 5×10 atoms / cm 18atoms / cm 3 less than, more preferably 1×10 18 atoms / cm 3 less than. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0185] Also, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystall ine Oxide Semiconductor) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CA AC-OS has the lowest density of defect levels. The oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystal components.

[0186] Or, the oxide film with an amorphous structure is, for example, a completely amorphous structure and has no crystal part.

[0187] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA C-OS region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a stacked layer structure including any two or more of the above-described regions.

[0188] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0189] CAC-OS means that, for example, the elements constituting the oxide semiconductor are 0.5 nm or more and 10 nm ​​The following is preferably one of the materials unevenly distributed in a size of 1 nm or more and 2 nm or less, or in the vicinity thereof. This is the structure. In the following, in the oxide semiconductor, one or more metal elements are unevenly distributed, and the region having the metal element is mixed in a state of 0.5 nm or more and 10 nm or less, preferably 1 n m or more and 2 nm or less, or in the vicinity thereof, and is also referred to as a mosaic state or a patch state.

[0190] Note that the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium tantalum, tungsten, or magnesium may be included. For example, in the In-Ga-Zn oxide, CAC-OS (among CAC-OS, the In-Ga-Zn oxide may be particularly referred to as CAC-IGZO.) refers to indium oxide (hereinafter, InO

[0191] (let X1 be a real number greater than 0).), or indium zinc oxide (hereinafter, In O X1 (let X1 be a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (let X2, Y2, and Z2 be real numbers greater than 0 ).), and gallium oxide (hereinafter, GaO X3 (let X3 be a real number greater than 0). ), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (let X4, Y4, and Let Z4 be a real number greater than 0).) etc., and the material separates into a mosaic pattern and becomes a mosaic-like InO X1 or In X2 Zn Y2 O Z2 is uniformly distributed in the film configuration (hereinafter also referred to as a cloud-like configuration).

[0192] That is, CAC-OS is a composite oxide semiconductor X3 having a structure in which a region mainly composed of GaO X2 Zn Y2 O Z2 or InO X1 is mixed with a region mainly composed of In this specification, for example, the atomic number ratio of In to the element M in the first region is greater than the atomic number ratio of In to the element M in the second region. The first region is assumed to have a higher In concentration compared to the second region.

[0193] Note that IGZO is a general term and may refer to a single compound composed of In, Ga, Zn, and O In a typical example, InGaO3(ZnO) m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≤ x0 ≤ 1, m0 is an arbitrary number) represents a crystalline compound.

[0194] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane plane.

[0195] On the other hand, CAC-OS relates to the material composition of the oxide semiconductor. CAC-OS refers to In, In a material composition containing Ga, Zn, and O, a region observed in the form of nanoparticles mainly composed of Ga in part, and a region observed in the form of nanoparticles mainly composed of In in part are each randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0196] Note that CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, a structure composed of two layers, a film mainly composed of In and a film mainly composed of Ga, is not included.

[0197] Note that GaO X3 in the region where it is the main component and In X2 Zn Y2 O Z2 or InO X1 in the region where it is the main component may not have a clear boundary observable.

[0198] Note that when one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. are included instead of gallium, CAC-OS has a structure in which a region observed in the form of nanoparticles mainly composed of the metal element in part and a region observed in the form of nanoparticles mainly composed of In in part are each randomly dispersed in a mosaic pattern.

[0199] CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by a sputtering method, the film-forming gas ​​​​​​ As one or more selected from inert gas (typically argon), oxygen gas, and nitrogen gas may be used. Also, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, more preferably 0% or more and 10% or less. When CAC-OS is measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods, it has the characteristic that no distinct peak is observed. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region. Also, in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high luminance in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction. For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed.

[0200] CAC-OS is measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. When measured, it has the characteristic that no distinct peak is observed, that is, from the X-ray diffraction measurement, it can be seen that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region. Also, CAC-OS has a high-luminance region in a ring shape (ring region) and a plurality of bright spots are observed in the ring region in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam). Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction. For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed.

[0201] Also, for example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. In the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high luminance in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction. For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. In the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high luminance in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0202] Also, for example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. [[ID=3)When CAC-OS is measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods, it has the characteristic that no distinct peak is observed. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region. When measured, it has the characteristic that no distinct peak is observed, that is, from the X-ray diffraction measurement, it can be seen that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region. X3 For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. X2 For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. Y2 For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. Z2 For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. X1 For example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions mainly composed of GaO and regions mainly composed of InZnO or InO are unevenly distributed and mixed. It can be confirmed that the structure is consistent with that of the hydroxyl group.

[0203] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from GZO compounds. X3 The main components are and the region where In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component and the region where is The phases are separated into individual elements, resulting in a mosaic structure of regions each consisting of a different element as the main component.

[0204] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X This is a region with high conductivity compared to the region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The carriers flow through the area where the main component is Therefore, the conductivity of In is exhibited as a semiconductor. X2 Zn Y2 O Z2 , or I nO X1 The regions where the main component is distributed in a cloud-like shape in the oxide semiconductor produce high electric current. Field-effect mobility (μ) can be achieved.

[0205] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 etc. The region that is the main component is distributed in the oxide semiconductor, suppressing the leakage current and achieving good switching operation can be realized.

[0206] Therefore, when CAC-OS is used for a semiconductor device, the insulation X3 due to, for example, GaO and the conductivity due to In X2 Zn Y2 O Z2 or InO X1 act complementarily to achieve a high on-current (I ) and a high field-effect mobility (μ). on This can be achieved.

[0207] In addition, a semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0208] In this modification example, a configuration in which a driving circuit for a readout circuit and a memory circuit of a pixel circuit is provided in the element layer 201 and a memory circuit is provided in the element layer 202 has been described. However, the present invention is not limited to this. For example, a driving circuit for a pixel circuit, a neural network, a communication circuit, a CPU, etc. may be provided in the element layer 201 or the element layer 202. A Noff-CPU can be realized using an OS transistor and an Si transistor. Note that a Noff-CPU is a normally-off type transistor in which the transistor is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.

[0209] It is an integrated circuit including a normally-off transistor.

[0210] The Noff-CPU stops the power supply to circuits unnecessary for the operation in the Noff-CPU, and The circuit can be put into a standby state. In the circuit where the power supply is stopped and it is in the standby state, no power is consumed. Therefore, the Noff-CPU can minimize the power consumption. Also, the Noff-CPU can retain information necessary for operations such as set conditions for a long period even when the power supply is stopped. To resume from the standby state, it is only necessary to restart the power supply to the circuit, and rewriting such as set conditions is not required. That is, a quick resume from the standby state is possible. In this way, the Noff-CPU can significantly reduce the power consumption without substantially reducing the operating speed.

[0211] As described above, according to one aspect of the present invention, a high-sensitivity imaging device can be provided. Or, according to one aspect of the present invention, a high-resolution imaging device can be provided. Or according to one aspect of the present invention, a highly functional imaging device can be provided. Or, according to one aspect of the present invention, a small-sized imaging device can be provided. Or, according to one aspect of the present invention, an imaging device capable of high-speed operation can be provided.

[0212] The configuration described in this embodiment can be appropriately combined with other configurations described in this embodiment or configurations described in other embodiments.

[0213] (Embodiment 2) In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. The configuration of the imaging device according to one aspect of the present invention can be used for the image sensor chip.

[0214] FIG. 14(A1) is an external perspective view of the upper surface side of a package containing an image sensor chip. Yes. The package includes a package substrate 610 that fixes the image sensor chip 650 , a cover glass 620, an adhesive 630 for bonding the two, and the like.

[0215] FIG. 14(A2) is an external perspective view of the lower surface side of the package. On the lower surface of the package has a BGA (Ball grid array) with solder balls as bumps 640 . Note that it may have not only BGA but also LGA (Land grid array), PGA (Pi n Grid Array), etc.

[0216] [[ID=1e]]FIG. 14(A3) is a perspective view of the package shown with a part of the cover glass 620 and the adhesive 630 omitted. On the package substrate 610, electrode pads 660 are formed, and the electrode pads 660 and the bumps 640 are electrically connected via through holes. The electrode pads 660 are electrically connected to the image sensor chip 650 by wires 670 .

[0217] Also, FIG. 14(B1) is an external perspective view of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 611 that fixes the image sensor chip 651, a lens cover 621, and a lens 6 35, etc. Also, between the package substrate 611 and the image sensor chip 651 an IC chip 690 having functions such as a drive circuit and a signal conversion circuit of the imaging device is also provided, and it has a configuration as a SiP (System in package).

[0218] FIG. 14(B2) is an external perspective view of the lower surface side of the camera module. The package substrate ​​The lower surface and side surfaces of the board 611 have a QFN (Quad flat no-lead package) structure. Note that this structure is an example and a QFP (Quad flat package) or the aforementioned BGA may be provided.

[0219] FIG. 14(B3) is a perspective view of the module with a part of the lens cover 621 and the lens 635 omitted. The land 641 is electrically connected to the electrode pad 661, and the electrode pad 661 is electrically connected to the image sensor chip 651 or the IC chip 690 by the wire 671.

[0220] By housing the image sensor chip in a package of the form described above, it becomes easy to mount on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic equipment.

[0221] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0222] (Embodiment 3) As an electronic device that can use the imaging device according to an aspect of the present invention, a display device, a personal computer, an image storage device or an image playback device equipped with a recording medium, a mobile phone, a mobile game machine including a portable type, a portable data terminal, an e-book terminal, a video camera, a digital still camera such as a camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copier, a facsimile machine, a printer, a printer multifunction machine, an automated teller machine (ATM), ​​​​Examples include vending machines. Specific examples of these electronic devices are shown in FIGS. 15(A) to (F). .

[0223] FIG. 15(A) shows an example of a mobile phone, which includes a housing 981, a display unit 982, operation buttons 983 , an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone is provided with a touch sensor on the display unit 982. All operations such as making a call or entering characters can be performed by touching the display unit 982 with a finger or a stylus. An imaging device according to an aspect of the present invention and its operation method can be applied to the elements for image acquisition in the mobile phone.

[0224] FIG. 15(B) shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913 , a camera 919, etc. Information input and output can be performed by the touch panel function of the display unit 912. Also, characters and the like can be recognized from the image acquired by the camera 919, and the characters can be output as voice by the speaker 9 13. An imaging device according to an aspect of the present invention and its operation method can be applied to the elements for image acquisition in the portable data terminal.

[0225] FIG. 15(C) shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, etc. The camera unit 952 is provided with a rotation mechanism or the like, and can perform imaging of the entire surrounding area by being installed on the ceiling. An imaging device according to an aspect of the present invention and its operation method can be applied to the elements for image acquisition in the camera unit. Note that the surveillance camera is a conventional name and does not limit the use. For example, a device having the function of a surveillance camera is also called a camera or a video camera. ​​​​

[0226] FIG. 15(D) is a video camera, which includes a first housing 971, a second housing 972, a display unit 973 , an operation key 974, a lens 975, a connection part 976, a speaker 977, a microphone 978, etc. . The operation key 974 and the lens 975 are provided on the first housing 971, and the display unit 9 73 is provided on the second housing 972. An imaging device and an operation method thereof according to an aspect of the present invention can be applied to elements for image acquisition in the video camera.

[0227] FIG. 15(E) is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting part 967, a lens 965, etc. An imaging device and an operation method thereof according to an aspect of the present invention can be applied to elements for image acquisition in the digital camera.

[0228] FIG. 15(F) is a wristwatch-type information terminal, which includes a display unit 932, a housing-cum-wristband 933 , a camera 939, etc. The display unit 932 includes a touch panel for operating the information terminal. The display unit 932 and the housing-cum-wristband 933 have flexibility and are excellent in wearing comfort on the body. An imaging device and an operation method thereof according to an aspect of the present invention can be applied to elements for image acquisition in the information terminal.

[0229] This embodiment can be appropriately combined with the descriptions of other embodiments.

Description of Reference Numerals

[0230] BGL wiring BIL wiring Cs capacitor GNDL wiring M3 transistor M5 transistor M6 Transistor M11 Transistor RBL Wiring RL Wiring SL Wiring WBL Wiring WL Wiring 100 Element Layer 101 Element Layer 103 Transistor 104 Transistor 105 Transistor 106 Transistor 108 Capacitor 111 Transistor 112 Capacitor 115 Transistor 116 Transistor 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 126 Wiring 127 Wiring 128 Wiring 130 Junction 131 Conductive Layer 132 Conductive Layer 201 Element Layer 202 Element Layer 205 Element Layer 211 Semiconductor Substrate 212 Insulating Layer 213 Insulating Layer 214 Insulating Layer 215 Insulating Layer 216 Insulating Layer 217 Insulating Layer 218 Insulating Layer 221 Insulating Layer 222 Insulating Layer 223 Insulating Layer 224 Insulating Layer 225 Insulating Layer 226 Insulating Layer 227 Insulating Layer 228 Insulating Layer 229 Insulating Layer 231 Insulating layer 232 Insulating layer 240 Photoelectric conversion device 241 Insulating layer 242 Insulating layer 243 Semiconductor substrate 244 n-type region 245 Insulating layer 246 Insulating layer 248 p-type region 250 Optical conversion layer 251 Light-shielding layer 255 Microlens array 261 Semiconductor substrate 262 Insulating layer 263 Insulating layer 264 Insulating layer 265 Insulating layer 266 Insulating layer 267 Insulating layer 268 Insulating layer 270 Conductive layer 271 Insulating layer 272 Bump 273 Conductive layer 280 Conductive layer 282 Insulating layer 284 n-type region 312 Load driver 313 Column driver 321 Memory circuit 321a Memory cell 321aA Memory cell 321aB Memory cell 321aC Memory cell 321aD Memory cell 330 Pixel section 331 Pixel circuit 332 Driving circuit 333 Driving circuit 351 Wiring 352 Wiring 353 Wiring 354 Wiring 355 Wiring 400 CDS circuit 401 Transistor 402 Capacitor 403 Transistor 404 Transistor 405 Capacitor 410 A / D Converter 535 Back Gate 545 Semiconductor Layer 546 Insulating Layer 610 package substrate 611 Package Substrate 620 Cover Glass 621 Lens cover 630 Adhesive 635 Lens 640 Bump 641 rand 650 image sensor chip 651 Image Sensor Chip 660 electrode pads 661 Electrode Pads 670 Wire 671 Wire 690 IC chips 701 Gate electrode 702 Gate insulating film 703 Source Region 704 Drain Region 705 Source Electrode 706 Drain electrode 707 Oxide semiconductor layer 911 chassis 912 Display section 913 Speaker 919 Camera 932 Display section 933 Case and Wristband 939 Camera 951 Support stand 952 Camera Unit 953 Protective Cover 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light-emitting part 971 Case 972 housing 973 display unit 974 operation key 975 lens 976 connection part 977 speaker 978 microphone 981 housing 982 display unit 983 operation button 984 external connection port 985 speaker 986 microphone 987 camera

Claims

【Claim 1】 comprising a first semiconductor substrate and a second semiconductor substrate; wherein the first semiconductor substrate includes a photoelectric conversion device and a first transistor; wherein the second semiconductor substrate includes a second transistor, a third transistor, and a fourth transistor; wherein one of the electrodes of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor; wherein the other of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor; wherein one of the source and drain of the second transistor is electrically connected to the gate of the third transistor; wherein one of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor; an imaging device, wherein at least a part of the photoelectric conversion device, the second transistor, the third transistor, and the fourth transistor overlap each other.

Images