Transferring method for silicon foil layer

Abstract

To provide a method of transferring a thin silicon layer from a donor substrate to a handle substrate.SOLUTION: A method includes the steps of: injecting He+ ions through a silicon dioxide layer 120 in contact with a surface 102 of a single-crystal silicon donor substrate 100; annealing the ion-injected single-crystal silicon donor substrate at sufficient temperature for sufficient time for forming a damage layer in the single-crystal silicon donor substrate; bonding the silicon dioxide layer in contact with the surface of the single-crystal silicon donor substrate to a dielectric layer in contact with a handle substrate 200, thereby preparing a multilayer substrate; annealing the multilayer substrate; and cleaving the annealed multilayer substrate at the damage layer 130 in the single-crystal silicon donor substrate, thereby transferring a silicon layer with a thickness from about 500 angstroms to about 2500 angstroms from the single-crystal silicon donor substrate to the handle substrate.SELECTED DRAWING: Figure 1E

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of priority to U.S. Provisional Application No. 62 / 682,228, filed on June 8, 2018, the disclosure of which is incorporated by reference in its entirety as if fully set forth herein.

[0002] The present invention generally relates to the field of semiconductor wafer manufacturing. More specifically, the present invention relates to a method of transferring a thin silicon layer from a donor substrate to a handle substrate in the fabrication of a silicon - on - insulator structure.

Background Art

[0003] Semiconductor wafers are generally prepared from single - crystal ingots (e.g., silicon ingots) that are trimmed and polished to have one or more flats or notches for proper wafer orientation in subsequent procedures. Subsequently, the ingot is sliced into individual wafers. Here, reference is made to semiconductor wafers formed from silicon, although other materials may be used in the fabrication of semiconductor wafers, for example, germanium, silicon carbide, silicon germanium, gallium arsenide, and other alloys of group III and group V elements such as gallium nitride or indium phosphide, or alloys of group II and group VI elements such as cadmium sulfide or zinc oxide may also be used.

[0004] A semiconductor wafer (e.g., a silicon wafer) may be used to fabricate a composite layer structure. A composite layer structure (e.g., a semiconductor-on-insulator, more specifically, a silicon-on-insulator (SOI) structure) generally consists of a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, the thickness of the device layer is between 0.01 and 20 micrometers, for example, between 0.05 and 20 micrometers. A thick film device layer may have a device layer thickness between about 1.5 micrometers and about 20 micrometers. A thin film device layer may have a thickness between about 0.01 micrometer and about 0.20 micrometer. Generally, composite layer structures such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz are manufactured by placing two wafers in intimate contact, initiating bonding by van der Waals forces therebetween, and then performing a heat treatment to strengthen the bond. Annealing converts terminal silanol groups to siloxane bonds between the two interfaces, thereby strengthening the bond.

[0005] After annealing, the joined structure is further processed to remove a substantial portion of the donor wafer, achieving layer transfer. For example, wafer thinning techniques such as etching and polishing, often referred to as back-etched SOI (i.e., BESOI), are used, where a silicon wafer is bonded to a handle wafer and then slowly etched until a thin silicon layer remains on the handle wafer. See, for example, U.S. Patent No. 5,189,500. The disclosure thereof is incorporated herein by reference as if fully set forth. This method is time-consuming and costly, wastes one of the substrates, and generally does not provide adequate thickness uniformity for layers thinner than a few microns.

[0006] Another common method to achieve layer transfer utilizes hydrogen implantation followed by thermally induced layer splitting. Particles (atoms or ionized atoms, e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted downward from the surface of the donor wafer to a predetermined depth.

[0007] Subsequently, the surface of the donor wafer is bonded to the handle wafer, and a bonded wafer is formed through a hydrophilic bonding process. Prior to bonding, the donor wafer and / or the handle wafer are activated by exposing the surface of the wafer to a plasma containing, for example, oxygen or nitrogen. Exposure to the plasma changes the surface structure in a process often called surface activation, and this activation process makes the surface of one or both of the donor wafer and the handle wafer hydrophilic. The surface of the wafer can be further chemically activated by wet treatments such as SC1 cleaning or hydrofluoric acid. The wet treatment and the plasma activation can be performed in either order, or the wafer can be subjected to only one treatment. Subsequently, the wafers are pressed together, and a bond is formed there. This bond is a relatively weak bond due to van der Waals forces and must be strengthened before further processing can occur.

[0008] In some processes, the hydrophilic bond between the donor wafer and the handle wafer (i.e., the bonded wafers) is strengthened by heating or annealing the bonded wafer pair. In some processes, the wafer bond may occur at a low temperature, such as between about 300 °C and about 500 °C. In some processes, the wafer bond may occur at a high temperature, such as between about 800 °C and about 1100 °C. At high temperatures, a covalent bond is formed between the adjacent surfaces of the donor wafer and the handle wafer, and the bond between the donor wafer and the handle wafer is solidified. Simultaneously with the heating or annealing of the bonded wafers, the particles previously implanted in the donor wafer weaken the cleavage plane.

[0009] Subsequently, from the bonded wafer, a portion of the donor wafer is separated (i.e., cleaved) along the cleavage plane, and an SOI wafer is formed. Cleavage may be performed by placing the bonded wafer in a fixture where a mechanical force is applied perpendicularly to the opposite side of the bonded wafer to pull a portion of the donor wafer away from the bonded wafer. According to some methods, a suction cup is utilized to apply the mechanical force. Separation of a portion of the donor wafer is initiated by applying a mechanical wedge to the edge of the bonded wafer at the cleavage plane to start the propagation of a crack along the cleavage plane. Thereafter, a portion of the donor wafer is pulled away from the bonded wafer by the mechanical force applied by the suction cup, and an SOI wafer is formed.

[0010] According to another method, instead, the bonded pair may be exposed to a high temperature for a certain period of time to separate a portion of the donor wafer from the bonded wafer. Exposure to high temperature causes the initiation and propagation of cracks along the cleavage plane, whereby a portion of the donor wafer is separated. The cracks are formed by the formation of voids from the implanted ions and grow by Ostwald ripening. The voids are filled with hydrogen and helium. These voids become platelets. The pressurized gas within the platelets propagates through microcavities and microcracks, weakening the silicon at the implantation surface. If annealing is stopped at the appropriate timing, the weakened bonded wafer will be cut by a mechanical process. However, if the heat treatment is continued for a longer period and / or at a higher temperature, the propagation of the microcracks reaches a level where all the cracks coalesce along the cleavage plane, whereby a portion of the donor wafer is separated. This method makes the transferred layer more uniform and enables the reuse of the donor wafer, but typically, it is necessary to heat the implanted and bonded pair to a temperature of about 500°C.

SUMMARY OF THE INVENTION

[0011] The present invention relates to a method for transferring a silicon layer from a single-crystalline silicon donor substrate to a handle substrate, the method comprising the following steps: (a) passing through a silicon dioxide layer in contact with the surface of the single-crystalline silicon donor substrate and through the surface of the single-crystalline silicon donor substrate and via the silicon dioxide layer, H2 + ions, H + ions, or H2 + ions and H + ions in a combination injection step, the single-crystalline silicon donor substrate having two major parallel faces, one being the front surface and the other being the back surface, a peripheral portion connecting the front surface and the back surface, a central plane between the front surface and the back surface, a central axis perpendicular to the front surface, and a bulk region between the front surface and the back surface; (b) passing through a silicon dioxide layer in contact with the surface of the single-crystalline silicon donor substrate and through the surface of the single-crystalline silicon donor substrate, He + ion injection step; (c) annealing the ion-implanted single-crystalline silicon donor substrate at a temperature and for a time sufficient to form a damaged layer in the single-crystalline silicon donor substrate; (d) bonding the silicon dioxide layer in contact with the surface of the single-crystalline silicon donor substrate to a dielectric layer in contact with the handle substrate, thereby preparing a multilayer substrate; (e) annealing the multilayer substrate; and (f) cleaving the annealed multilayer substrate at the damaged layer in the single-crystalline silicon donor substrate, thereby transferring a silicon layer having a thickness between about 500 angstroms and about 2500 angstroms from the single-crystalline silicon donor substrate to the handle substrate, characterized by comprising.

[0012] Other objects and features will become in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0013]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 1E

Figure 1F

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0014] The fully depleted silicon-on-insulator (FD-SOI) structure relies on an ultrathin layer of silicon on a buried oxide layer (BOX). The buried oxide layer may be of a conventional thickness (on the order of 100 - 200 nanometers) or may be ultrathin, for example, between 10 - 25 nanometers. A very thin silicon layer can completely eliminate charge from the silicon under the transistor gate (the body of the transistor) of a CMOS device. Thus, the present invention relates to a method of transferring a very thin silicon layer from a donor substrate to a handle substrate.

[0015] According to the present invention, there is provided a method for fabricating a semiconductor-on-insulator composite structure (SOI, e.g., a silicon-on-insulator composite structure) having a relatively thin silicon device layer. In some specific examples, the SOI structure further includes a relatively thin dielectric layer, e.g., a buried oxide layer. In some specific examples, therefore, the present invention relates to a method of transferring a thin silicon layer having a thickness between about 500 angstroms and about 2500 angstroms from a donor substrate onto a handle substrate. According to some specific examples of the present invention, hydrogen (H2 + and / or H + ) ions and helium (He + ) ions are co-implanted into the donor substrate at a low ion energy. By annealing the co-implanted donor substrate, a damaged layer is formed in the donor substrate. The depth of the damaged layer determines the thickness of the silicon layer transferred onto the handle substrate.

[0016] To achieve the transfer of the thin layer, the implantation energy of the gaseous ions is kept low, especially when the oxide layer on the donor wafer is thin (e.g., several hundred angstroms). Transferring the thin silicon device layer enables the fabrication of a fully depleted SOI structure (FD-SOI). In low-power, high-performance CMOS applications based on FD-SOI, it is necessary to limit the thickness of the silicon device layer and the thickness of the buried oxide layer. The thin layer may be transferred by restricting the beam energy during ion implantation. Further, in some specific examples, the manufacturing cost is further reduced by reducing the implantation dose.

[0017] I. Semiconductor Donor Substrate and Semiconductor Handle Substrate The substrates used in the present invention include a semiconductor donor substrate, e.g., a single-crystalline semiconductor donor wafer, and a semiconductor handle substrate, e.g., a single-crystalline semiconductor handle wafer. The semiconductor device layer in the semiconductor-on-insulator composite structure is derived from the semiconductor donor substrate.

[0018] Figures 1A - 1F illustrate process flows according to some specific examples of the present invention. Referring to Figure 1A, an exemplary and non - limiting semiconductor donor substrate 100, such as a single - crystal semiconductor donor wafer, is depicted. Generally, the single - crystal semiconductor donor substrate 100 includes two main, generally parallel surfaces. One of the parallel surfaces is the surface 102 of the single - crystal semiconductor donor substrate 100, and the other parallel surface is the back surface 104 of the single - crystal semiconductor donor substrate 100. The single - crystal semiconductor donor substrate 100 includes a peripheral portion 106 that joins the surface 102 and the back surface 104. The single - crystal semiconductor donor substrate 100 includes a central axis 108 that is perpendicular to the two main, generally parallel surfaces 102 and 104 and also perpendicular to a central plane 110 defined by an intermediate point between the surface 102 and the back surface 104. The single - crystal semiconductor donor substrate 100 includes a bulk region between the two main, generally parallel surfaces 102 and 104. Since semiconductor wafers, such as silicon wafers, typically have some total thickness variation (TTV), warp, and bow, the intermediate point that defines the central plane 110 between all points on the surface 102 and all points on the back surface 104 may not lie exactly in a plane. However, as a practical matter, TTV, warp, and bow are typically very small, and approximately, it can be said that the intermediate point falls within an imaginary central plane 110 that is approximately equidistant between the surface 102 and the surface 104.

[0019] Prior to the operations as described herein, the front surface 102 and the back surface 104 of the single-crystalline semiconductor donor substrate 100 may be substantially the same. For simplicity and generality only, in order to distinguish the surface on which the operations of the method of the present invention are performed, the surface is referred to as the "front surface" or the "back surface". In the context of the present invention, the "front surface" of the single-crystalline semiconductor donor substrate 100 refers to the major surface of the substrate through which ions are implanted. The front surface becomes the inner surface of the bonded structure. Thus, the "back surface" of the single-crystalline semiconductor donor substrate 100 refers to the major surface that becomes the outer surface of the bonded structure. Similarly, the "front surface" of the handle substrate refers to the major surface that becomes the inner surface of the bonded structure, and the "back surface" of the handle substrate refers to the major surface that becomes the outer surface of the bonded structure. When the conventional bonding and cleaving processes are completed, the single-crystalline semiconductor donor substrate forms the semiconductor device layer of a semiconductor-on-insulator (e.g., silicon-on-insulator) composite structure.

[0020] The handle substrate and the single-crystalline semiconductor donor substrate may be single-crystalline semiconductor wafers. In a preferred specific example, the semiconductor wafer includes a material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. The handle wafer may further include sapphire, quartz, or glass. The single-crystalline semiconductor wafers of the present invention, e.g., single-crystalline silicon handle wafers and single-crystalline silicon donor wafers, typically have a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. The thickness of the wafer can vary between about 100 micrometers and about 5000 micrometers, e.g., between about 100 micrometers and about 1500 micrometers, e.g., between about 250 micrometers and about 1500 micrometers, e.g., between about 300 micrometers and about 1000 micrometers, preferably within the range of about 500 micrometers and about 1000 micrometers. In some specific examples, the thickness of the wafer may be about 725 micrometers. In some specific examples, the thickness of the wafer may be about 775 micrometers.

[0021] In particularly preferred embodiments, the single crystal semiconductor wafer includes a single crystal silicon wafer sliced from a single crystal ingot grown according to the conventional Czochralski crystal growth method or the float zone growth method. Such methods, as well as standard silicon slicing, lapping, etching, and polishing techniques, are disclosed, for example, in F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989, and Silicon Chemical Etching, (J. Grabmaier ed.) Springer-Verlag, N.Y., 1982, which are incorporated herein by reference. Preferably, the wafer is polished and cleaned by standard methods known to those skilled in the art. See, for example, W.C. O’Mara et al., Handbook of Semiconductor Silicon Technology, Noyes Publications. If desired, the wafer can be cleaned, for example, with standard SC1 (5 parts water: 1 part aqueous ammonium hydroxide solution (29 wt%): 1 part aqueous hydrogen peroxide solution (30 wt%)) / SC2 solution (6 parts water: 1 part aqueous hydrochloric acid (37 wt%): 1 part aqueous hydrogen peroxide (30 wt%)). In some embodiments, the single crystal silicon wafer of the present invention is a single crystal silicon wafer sliced from a single crystal ingot grown according to the conventional Czochralski (“Cz”) crystal growth method, and typically has a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. Preferably, both the single crystal silicon handle wafer and the single crystal silicon donor wafer have a mirror-polished surface finish that is free of surface defects such as scratches and large particles. The thickness of the wafer may vary within a range from about 250 micrometers to about 1500 micrometers, for example from about 300 micrometers to about 1000 micrometers, and preferably from about 500 micrometers to about 1000 micrometers.In some specific examples, the thickness of the wafer may be in the range between about 725 micrometers and about 800 micrometers, for example, between about 750 micrometers and about 800 micrometers. In some specific examples, the thickness of the wafer may be about 725 micrometers. In some specific examples, the thickness of the wafer may be about 775 micrometers.

[0022] In some specific examples, single-crystalline semiconductor wafers, i.e., single-crystalline semiconductor handle wafers and single-crystalline semiconductor donor wafers, contain interstitial oxygen at a concentration generally achieved by the Czochralski growth method. In some specific examples, single-crystalline semiconductor wafers contain oxygen at a concentration between about 4 PPMA and about 18 PPMA. In some specific examples, semiconductor wafers contain oxygen at a concentration between about 10 PPMA and about 35 PPMA. In some specific examples, single-crystalline silicon wafers contain oxygen at a concentration not exceeding about 10 PPMA. Interstitial oxygen may be measured in accordance with SEMI MF 1188-1105.

[0023] The single-crystalline semiconductor donor substrate 100 and the handle substrate may have any resistivity obtained by the Czochralski method or the float zone method. Thus, the resistivity of the single-crystalline semiconductor donor substrate 100 and the handle substrate is based on the requirements of the end use / application of the structure of the present invention. Therefore, the resistivity may vary from less than milliohms to more than megaohms. In some specific examples, the single-crystalline semiconductor donor substrate 100 is undoped. In some specific examples, the handle substrate 100 is undoped. In some specific examples, the single-crystalline semiconductor donor substrate 100 contains a p-type or n-type dopant. In some specific examples, the handle substrate 100 contains a p-type or n-type dopant. Suitable dopants include boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type). The dopant concentration is selected based on the desired resistivity of the single-crystalline semiconductor donor substrate.

[0024] In some specific examples, the single-crystalline semiconductor donor substrate 100 has a relatively low minimum bulk resistivity, such as less than about 100 ohm·cm, less than about 50 ohm·cm, less than about 1 ohm·cm, less than about 0.1 ohm·cm, or even less than about 0.01 ohm·cm. In some specific examples, the single-crystalline semiconductor donor substrate 100 has a relatively low minimum bulk resistivity, such as less than about 100 ohm·cm, or between about 1 ohm·cm and about 100 ohm·cm. The low-resistance wafer may contain electrically active dopants such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type).

[0025] In some specific examples, the single-crystalline semiconductor donor substrate 100 has a relatively high minimum bulk resistivity. High-resistance wafers are generally sliced from single-crystalline ingots grown by the Czochralski method or the float zone method. High-resistance wafers may generally contain electrically active dopants such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), arsenic (n-type), etc. at very low concentrations. The Cz-grown silicon wafers may be thermally annealed at a temperature of about 600 °C to about 1000 °C to completely eliminate the thermal donors caused by the oxygen incorporated during crystal growth. In some specific examples, the single-crystalline semiconductor handle wafer has a minimum bulk resistivity of at least about 100 ohm·cm or at least about 500 ohm·cm, for example, between about 100 ohm·cm and about 100,000 ohm·cm, or between about 500 ohm·cm and about 100,000 ohm·cm, or between about 1000 ohm·cm and about 100,000 ohm·cm, or between about 500 ohm·cm and about 10,000 ohm·cm, or between about 750 ohm·cm and about 10,000 ohm·cm, between about 1000 ohm·cm and about 10,000 ohm·cm, between about 1000 ohm·cm and about 6000 ohm·cm, between about 2000 ohm·cm and about 10,000 ohm·cm, between about 3000 ohm·cm and about 10,000 ohm·cm, or between about 3000 ohm·cm and about 5000 ohm·cm. In some preferred specific examples, the single-crystalline semiconductor handle wafer has a bulk resistivity between about 1000 ohm·cm and about 6000 ohm·cm. Methods for preparing high-resistance wafers are known in the art, and such high-resistance wafers can be obtained from commercial suppliers such as SunEdison Semiconductor Ltd. (St. Peters, MO; formerly MEMC Electronic Materials, Inc.).

[0026] The single-crystalline semiconductor donor substrate 100 may include single-crystalline silicon. The single-crystalline semiconductor donor substrate 100 may have a crystal orientation of either (100), (110), or (111), and the selection of the crystal orientation may be determined by the end use of the structure.

[0027] Optionally, the front surface 102, back surface 104, or both surfaces of the single-crystalline semiconductor donor substrate 100 may be oxidized according to methods known in the art. Oxidation may be achieved by methods known in the art such as thermal oxidation (in which case a portion of the deposited semiconductor material film is consumed), CVD oxide deposition, or exposure to standard cleaning solutions such as SC1 / SC2 cleaning solutions. The single-crystalline semiconductor donor substrate 100 may be thermally oxidized in a furnace such as an ASM A400 or ASM A400XT. The temperature may be in an oxidation atmosphere in the range of about 750 °C to about 1100 °C, for example, between about 800 °C and about 1200 °C. The oxidation atmosphere may be a mixture of an inert gas such as Ar or N2 and O2. The oxygen content may vary in the range of 1 to 10% or more. In some specific examples, the oxidation ambient atmosphere may be up to 100% ( "dry oxidation"). In some specific examples, the ambient atmosphere may include a mixture of an inert gas such as Ar or N2 and an oxidizing gas such as O2 and water vapor ( "wet oxidation"). In an exemplary specific example, the donor wafer may be loaded into a vertical furnace such as an ASM A400 or ASM A400XT. The temperature is ramped to the oxidation temperature with a mixture of N2 and O2. Water vapor is introduced into the gas stream at the desired temperature. After the desired oxide thickness is obtained, the water vapor and O2 are turned off, the temperature of the furnace is lowered, and the wafer is removed from the furnace. In a specific example where the single-crystalline semiconductor donor substrate 100 is a single-crystalline silicon donor substrate, the oxide layer 120 includes silicon dioxide. Refer to FIG. 1B. The oxide layer 120 on the front surface 102, back surface 104, or both may be between about 100 angstroms and about 1000 angstroms, for example, between about 100 angstroms and about 700 angstroms, or between about 100 angstroms and about 500 angstroms, or between about 100 angstroms and about 250 angstroms.

[0028] In some specific examples, the oxide layer 120 is relatively thin, for example, between about 5 angstroms and about 25 angstroms, such as between about 10 angstroms and about 15 angstroms. The thin oxide layer can be obtained on both sides of the semiconductor wafer by exposure to a standard cleaning solution such as an SC1 / SC2 cleaning solution. In some specific examples, the SC1 solution contains 5 parts deionized water, 1 part aqueous NH4OH (ammonium hydroxide, 29 wt% NH3), and 1 part aqueous H2O2 (hydrogen peroxide, 30 wt%). In some specific examples, the handle wafer may be oxidized by exposure to an aqueous solution containing an oxidizing agent, such as an SC2 aqueous solution. In some specific examples, the SC2 solution contains 5 parts deionized water, 1 part aqueous HCl (hydrochloric acid, 39 wt%), and 1 part aqueous H2O2 (hydrogen peroxide, 30%).

[0029] II. Ion Implantation Ion implantation may be carried out using a commercially available apparatus such as Applied Materials Quantum II, Quantum LEAP, or Quantum X. According to some specific examples, the ions to be implanted include H + and / or H2 + ions and He + ions. The H + and / or H2 + ions may be implanted before the He + ions are implanted, after the He + ions are implanted, or the H + ions and / or H2 + ions may be implanted simultaneously with the He + ions. Ion implantation is performed with a density and time sufficient to form a damaged layer in the semiconductor donor substrate. Referring to FIG. 1C, ion implantation is performed through the oxide layer 120 and the surface 102 of the single-crystalline semiconductor donor substrate 100, and the single-crystalline semiconductor donor substrate 100 contains H + and / or H2 + ions at a peak depth (D1) and He +It contains ions. Note that the peak depths (D1) and (D2) are for illustrative purposes and are not considered as scales. The lengths of the peak depths (D1) and (D2) are measured along the central axis 108 from the surface 102 of the single-crystal silicon donor substrate 100. The implantation depth determines the thickness of the single-crystal semiconductor device layer in the final SOI structure.

[0030] In some specific examples, this method includes the step of implanting hydrogen ions (e.g., H2 + ions, H + ions, or a combination of H2 + ions and H + ions) through the surface of the single-crystal donor substrate to an average depth (D1) measured from the surface of the single-crystal donor substrate towards the central plane. The average depth (D1) of the implanted hydrogen ions may range between about 100 angstroms and about 4000 angstroms, between about 100 angstroms and about 3000 angstroms, or between about 500 angstroms and about 3000 angstroms, or between about 500 angstroms and about 2500 angstroms when measured along the central axis from the surface of the single-crystal silicon donor substrate. In some specific examples, the H2 + ion implantation dose is between about 4.3×10 15 ions / cm 2 and about 1.1×10 16 ions / cm 2 or between about 6.8×10 15 ions / cm 2 and about 1.1×10 16 ions / cm 2 and the implantation energy is between about 10 Kev and about 40 Kev, for example between about 20 Kev and about 40 Kev, or between about 25 Kev and about 35 Kev, for example about 16 Kev or about 32 Kev. In some specific examples, the H2 + ion implantation dose is between about 4.3×10 15 ions / cm 2 and about 1.1×10 16 ions / cm 2 or between about 6×10 15 ions / cm 2and about 1.1×10 16 ions / cm 2 It may also be in the range between, and the implantation melting energy may be between about 20 Kev and about 40 Kev, or between about 25 Kev and about 35 Kev, for example about 16 Kev or about 32 Kev. In some specific examples, H2 + The ion implantation dose may be from about 5.9×10 15 ions / cm 2 to about 6.7×10 15 ions / cm 2 It may also be in the range, and with the implantation energy, between about 10 Kev and about 30 Kev, for example between about 15 Kev and about 20 Kev, for example about 16 Kev. In some specific examples, H + The ion implantation dose may be about 5×10 15 ions / cm 2 and about 2×10 16 ions / cm 2 between, and the implantation energy may be between about 5 KeV and about 20 KeV, for example between about 10 KeV and about 20 KeV, for example about 16 KeV. In some specific examples, H + The ion implantation dose may be from about 1.1×10 16 ions / cm 2 to about 2×10 16 ions / cm 2 It may also be in the range, and the implantation energy may be between about 5 Kev and about 20 Kev, for example between about 10 Kev and about 20 Kev, for example about 16 Kev. In some specific examples, H + The ion implantation dose may be from about 6.1×10 15 ions / cm 2 to about 6.8×10 15 ions / cm 2 It may also be in the range, and the implantation energy may be between about 5 Kev and about 20 Kev, for example between about 10 Kev and about 20 Kev, for example about 16 Kev. In some specific examples, H2 + ions and H + ions in combination are implanted at an average depth (D1) measured from the surface towards the center plane within the above-described implantation range and energy range.

[0031] In some specific examples, this method includes the step of injecting helium ions (e.g., He + ions) through the surface of a single-crystal donor substrate to an average depth (D2) measured along the central axis 108 from the surface 102 of the single-crystal donor substrate. The average depth (D2) of the implanted helium ions may range from about 100 angstroms to about 4000 angstroms, from about 100 angstroms to about 3000 angstroms, or between about 500 angstroms and about 3000 angstroms, or between about 500 angstroms and about 2500 angstroms when measured along the central axis from the surface of the single-crystal silicon donor substrate. In some specific examples, the total helium ion implantation dose is between about 6×10 15 ions / cm 2 and about 2×10 16 ions / cm 2 ; between about 6×10 15 ions / cm 2 and about 1.3×10 16 ions / cm 2 ; about 6.3×10 15 ions / cm 2 to about 1.1×10 16 ions / cm 2 ; about 6.6×10 15 ions / cm 2 to about 8×10 15 ions / cm 2 ; and the implantation energy may be between about 5 keV and about 30 keV, for example, between about 10 keV and about 25 keV, or between about 15 keV and about 25 keV, such as about 22 keV. In some specific examples, the total helium ion implantation dose is between about 6×10 15 ions / cm 2 and about 2×10 16 ions / cm 2 ; between about 6×10 15 ions / cm 2 and about 1.3×10 16 ions / cm 2 ; for example, between about 6.3×10 15 ions / cm 2 and about 1.1×10 16 ions / cm2 , about 6.6×10 15 ions / cm 2 to about 8×10 15 ions / cm 2 may be, and the implantation energy may be between about 5 keV and about 30 keV, for example, between about 10 keV and about 25 keV, or between about 15 keV and about 25 keV, for example, about 22 keV. In some specific examples, the total helium ion implantation amount is about 6×10 15 ions / cm 2 to about 2×10 16 ions / cm 2 , about 6×10 15 ions / cm 2 to about 1.3×10 16 ions / cm 2 , for example, about 6.3×10 15 ions / cm 2 to about 1.1×10 16 ions / cm 2 , about 6.6×10 15 ions / cm 2 to about 8×10 15 ions / cm 2 , or about 6.6×10 15 ions / cm 2 to about 7×10 15 ions / cm 2 may be, and the implantation energy may be between about 5 keV and about 20 keV, for example, between about 5 keV and about 15 keV, for example, about 11 keV.

[0032] Preferably, the peak density (D1) of a combination of H2 + ions, H + ions, or H2 + ions and H + ions and the peak density (D2) of He + ions are within about 1000 angstroms of each other, within about 600 angstroms of each other, or within about 500 angstroms of each other, within about 450 angstroms of each other, within about 400 angstroms of each other, within about 300 angstroms of each other, or within about 200 angstroms of each other.

[0033]

[0033] In some specific examples, it is preferable to wash a single-crystalline semiconductor donor wafer, for example, a single-crystalline silicon donor wafer, after implantation. In some preferred specific examples, the washing can include a Piranha wash (a mixture of sulfuric acid and hydrogen peroxide), followed by a DI water rinse and washes using SC1 (a mixture of water: aqueous ammonium hydroxide solution: aqueous hydrogen peroxide solution in a ratio of 5:1:1) and SC2 (a mixture of water: aqueous ammonium hydroxide solution: aqueous hydrogen peroxide solution in a ratio of 6:1:1).

[0034] III. Annealing In some specific examples of the present invention, the ion-implanted single-crystalline semiconductor donor substrate 100 is annealed at a temperature sufficient to form a thermally activated damage layer or cleavage plane 130 in the single-crystalline semiconductor donor substrate. This annealing is performed before bonding. By using a low implantation energy, the damage layer 130 is generated at a depth that enables the transfer of a thin silicon layer, such as having a thickness between about 500 angstroms and about 2500 angstroms, to the handle substrate.

[0035] An example of a suitable tool may be a simple box furnace such as a Blue M model. In some preferred specific examples, the ion-implanted single-crystalline semiconductor donor substrate is annealed at a temperature between about 200°C and about 350°C, between about 225°C and about 350°C, for example, between about 250°C and about 300°C. The thermal annealing may be performed for between about 10 minutes and about 10 hours, for example, between about 10 minutes and about 2 hours, or between about 10 minutes and about 60 minutes. Thermal annealing within these temperature ranges is sufficient to form the thermally activated cleavage plane 130. After the thermal annealing to activate the cleavage plane 130, the surface of the single-crystalline semiconductor donor substrate is preferably washed. In some preferred specific examples, the washing can include a Piranha wash (a mixture of sulfuric acid and hydrogen peroxide), followed by a DI water rinse and washes using SC1 (a mixture of water: aqueous ammonium hydroxide solution: aqueous hydrogen peroxide solution mixed in a ratio of 5:1:1) and SC2 (a mixture of water: aqueous hydrochloric acid solution: aqueous hydrogen peroxide solution mixed in a ratio of 6:1:1).

[0036] IV. Plasma Activation In some specific examples, the ion-implanted and annealed single-crystalline semiconductor donor substrate undergoes oxygen plasma and / or nitrogen plasma surface activation. In some specific examples, the oxygen plasma surface activation tool is a commercially available tool obtainable from EV Group such as the EVG®810LT Low Temp Plasma Activation System. The ion-implanted and optionally cleaned single-crystalline semiconductor donor wafer is loaded into the chamber. The chamber is evacuated, and an oxygen gas source and / or a nitrogen gas source are returned to a pressure below atmospheric pressure in a carrier gas such as argon, thereby generating plasma. Oxygen and / or water are source gases suitable for plasma oxide treatment. Ammonia and / or nitrogen and / or nitric oxide (NO) and / or nitrous oxide (N2O) gas are suitable source gases for plasma nitride treatment. Oxynitride plasma activation may include an oxygen gas source and a nitrogen gas source in the ambient atmosphere. The single-crystalline semiconductor donor wafer is exposed to this plasma for a desired time, which may range from about 1 second to about 120 seconds. Oxygen or nitrogen plasma surface oxidation is performed to make the surface of the single-crystalline semiconductor donor substrate hydrophilic and compatible with bonding to the handle substrate. After plasma activation, the activated surface is washed with deionized water. Thereafter, the wafer is spin-dried before bonding.

[0037] V. Preparation of the Bonding Structure Referring to FIG. 1E, an oxide layer 120 on the surface 102 of a single-crystalline semiconductor donor substrate 100 having a cleavage plane or damage layer 130 is then bonded to the major surface of a semiconductor handle substrate 200 by intimately contacting these surfaces. In some specific examples, the semiconductor handle substrate 200 includes a dielectric layer. The dielectric layer may include an insulating material selected from silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof. In some specific examples, the dielectric layer has a thickness of at least about 1 nanometer, or at least about 10 nanometers, for example, between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between about 50 nanometers and about 500 nanometers, or between about 100 nanometers and about 400 nanometers, for example, a thickness such as about 50 nanometers, about 75 nanometers, about 85 nanometers, about 100 nanometers, about 150 nanometers, about 175 nanometers, or about 200 nanometers. The dielectric layer may be between about 100 angstroms and about 1000 angstroms, for example, between about 100 angstroms and about 700 angstroms, or between about 100 angstroms and about 500 angstroms, or between about 100 angstroms and about 250 angstroms. In some specific examples, the dielectric layer is much thinner, such as between about 5 angstroms and about 25 angstroms, for example, between about 10 angstroms and about 15 angstroms.

[0038] In some specific examples, the dielectric layer may include one or more insulating layers, for example, two insulating layers, three insulating layers, or more insulating layers. Each insulating layer may include a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride. Each insulating layer may have a thickness of at least about 1 nanometer, or at least about 10 nanometers, for example, between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between about 50 nanometers and about 500 nanometers, or between about 100 nanometers and about 400 nanometers, for example, a thickness between about 50 nanometers, about 75 nanometers, about 85 nanometers, about 100 nanometers, about 150 nanometers, about 175 nanometers, or about 200 nanometers.

[0039] Since the mechanical bond is relatively weak, in some specific examples, the bonding structure may be further annealed to strengthen the bond between the single-crystalline semiconductor donor substrate 100 and the handle substrate 200. In some specific examples of the present invention, the bonding structure is annealed at a temperature sufficient to form a thermally activated cleavage plane on the single-crystalline semiconductor donor substrate. An example of a suitable tool may be a simple box furnace such as a Blue M type. In some preferred specific examples, the bonding structure is annealed at a temperature of about 200°C to about 400°C, for example, at a temperature of about 300°C to about 400°C. The thermal annealing may be performed for a duration between about 10 minutes and about 10 hours, for example, between about 10 minutes and about 60 minutes.

[0040] In some specific examples, annealing may be performed at a relatively high pressure, such as between about 0.5 MPa and about 200 MPa, between about 0.5 MPa and about 100 MPa, between about 0.5 MPa and about 50 MPa, or between about 0.5 MPa and about 10 MPa, or between about 0.5 MPa and about 5 MPa. In conventional bonding methods, the temperature is likely to be limited by the "autoclave". This occurs when the pressure of the platelets in the injection plane exceeds the external isotonic pressure. Therefore, in conventional annealing, due to the autoclave, the bonding temperature may be limited to between about 350 °C and about 400 °C. The wafers after injection and bonding are weakly held. However, the gap between the wafers is sufficient to prevent the intrusion and escape of gas. The weak bond can be strengthened by heat treatment, but the cavities formed during injection are filled with gas. During heating, the gas in the cavity is pressurized. The pressure is estimated to reach 0.2 - 1 GPa depending on the dose amount (Cherkashin et al., J. Appl. Phys. 118, 245301 (2015)). When the pressure exceeds the critical value, the layer peels off. This is called an autoclave or a thermal clavicle. This prevents higher temperatures or longer times during annealing. According to some specific examples of the present invention, the bonding is performed at a high pressure, such as between about 0.5 MPa and about 200 MPa, for example, between about 0.5 MPa and about 100 MPa, for example between about 0.5 MPa and about 50 MPa, or between about 0.5 MPa and about 10 MPa, or between about 0.5 MPa and about 5 MPa, thereby enabling bonding at a high temperature. In some specific examples, the bonded structure is annealed at a temperature between about 300 °C and about 700 °C, between about 400 °C and about 600 °C, for example between about 400 °C and about 450 °C, or even between about 450 °C and about 600 °C, or between about 350 °C and about 450 °C. Increasing the thermal budget has a positive effect on the bonding strength. Thermal annealing may be performed for a time between about 0.5 hours and about 10 hours, for example between about 0.5 hours and about 3 hours, preferably for about 2 hours. Thermal annealing within these temperature ranges is sufficient to form thermally activated cleavage planes.In conventional annealing, due to roll off, the edges of both the handle wafer and the donor wafer may be located far apart. In this region, layer transfer does not occur. This is called a terrace. In pressure bonding, it is expected to reduce this terrace and extend the SOI layer further towards the edge. This mechanism is based on the fact that pockets of trapped air are compressed and "zippered" outwards. After thermal annealing to activate the bonding surface, the bonded structure may be cleaved.

[0041] After thermal annealing, the bond between the single crystal semiconductor donor substrate 100 and the handle substrate 200 is strong enough to initiate layer transfer through cleavage of the bonded structure at the cleavage plane. Cleavage may be performed according to techniques known in the art. In some specific examples, the bonded structure may be placed within a conventional cleavage station, adhered to a suction cup stationary on one side, and adhered by an additional suction cup on a hinge arm on the other side. A crack occurs near the attachment part of the suction cup, and the movable arm rotates around the hinge part to cleave the wafer. Cleavage removes a part of the semiconductor donor wafer, thereby leaving a single crystal semiconductor device layer 300, preferably a silicon device layer, on the semiconductor - on - insulator composite structure. Refer to FIG. 1F. The method of the present invention enables the transfer of a thin layer of silicon from the donor substrate to the handle substrate. Thus, in some specific examples, the silicon layer has a thickness between about 500 angstroms and about 2500 angstroms.

[0042] After cleavage, to further strengthen the bond between the transferred device layer 300 and the handle substrate, the cleaved structure may be further subjected to high - temperature annealing. An example of a suitable tool may be a vertical furnace such as an ASM A400. In some preferred specific examples, the bonded structure is annealed at a temperature from about 1000 °C to about 1200 °C, preferably at a temperature of about 1000 °C. The thermal annealing may be performed for about 0.5 hours to about 8 hours, preferably for about 2 hours to about 4 hours. Thermal annealing within these temperature ranges is sufficient to strengthen the bond between the transferred device layer and the single crystal semiconductor handle substrate.

[0043] After cleavage and high-temperature annealing, the bonded structure may undergo a cleaning process designed to remove thin thermal oxide and clean particles from the surface. In some specific examples, the single-crystalline semiconductor device layer may be subjected to a vapor-phase HCl etching process in a horizontal-flow single-wafer epitaxial reactor using H2 as the carrier gas to achieve the desired thickness and smoothness.

[0044] In some specific examples, an epitaxial layer may be deposited on the transferred single-crystalline semiconductor device layer 300. The deposited epitaxial layer may include substantially the same electrical properties as the underlying single-crystalline semiconductor device layer 300. Alternatively, the epitaxial layer may include electrical properties different from those of the underlying single-crystalline semiconductor device layer 300. The epitaxial layer may include a material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Depending on the desired properties of the final integrated circuit device, the epitaxial layer may include a dopant selected from boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type). The resistivity of the epitaxial layer may be in the range of 1 to 50 ohm·cm, typically 5 to 25 ohm·cm. In some specific examples, the epitaxial layer may have a thickness between about 10 nanometers and about 20 micrometers, between about 20 nanometers and about 3 micrometers, such as between about 20 nanometers and about 2 micrometers, such as between about 20 nanometers and about 1.5 micrometers, or between about 1.5 micrometers and about 3 micrometers.

[0045] The completed SOI wafer may then undergo end-of-line metrology inspection and may be finally cleaned using a typical SC1-SC2 process.

[0046] The present invention may be further illustrated by the following non-limiting examples.

[0047] Example 1 A single crystal silicon donor substrate was subjected to ion implantation. First, the wafer was implanted with 7×10 15 cm -2 A dose of He + Ion implantation was performed. The implantation energy was 22 KeV. After that, the wafer was + Ion implantation or H + Ion implantation was performed. H2 + The ion implantation energy was 32 KeV. + The ion implantation energy was 16 Kev. The dose was varied according to Table 1.

[0048] Calculation of stopping and range of ions in materials (SRIM) is done by H + and He + The difference in the depth profile peaks is approximately 450 Å. See Figure 1. The ion-implanted donor substrate was bonded to a handle substrate, annealed, and cleaved. Table 1 further provides the cleavage results.

[0049] Table 1: Various H2 + and H + Results of mechanical cleavage operations on doses TIFF2025111769000002.tif120161

[0050] According to the results shown in Table 1, He + Ion implant dose of 7 x 10 at 22 Kev 15 cm -2 When fixed at H2 + Ion implantation dose: 4.3 x 10 15 cm -2 Less than or H + Ion implantation dose: 6.8×10 15 cm -2 No cleavage was observed below this.

[0051] After cleavage, the variation range of the thickness of the transferred silicon device layer is H2 + was measured as a function of the ion implantation dose. For various H2 + See FIG. 3 showing the post-cleavage thickness variation range (·) of the transferred silicon device layer with respect to various dose amounts. The data shown in FIGS. 2 and 3 are for a fixed He 15 cm -2 ion implantation dose of 7×10 + at an energy of 22 keV in combination with H2 + It can be determined that when the ion implantation dose is at least 6×10 15 cm -2 the minimum variation in the thickness of the transferred silicon device layer is obtained. Notably, the H2 + ion implantation dose to minimize the thickness variation of the transferred silicon device layer is significantly greater than the amount required to obtain cleavage by a mechanical cleavage operation.

[0052] Example 2 Single crystal silicon donor substrates were subjected to ion implantation. Each wafer was implanted with He + ions and either H2 + or H + ions. The ion implantation doses of He + , H2 + and H + were each varied. The implantation dose of He + ions was varied between 6.6×10 15 cm -2 and 7×10 15 cm -2 . The implantation energy of the He + ion implantation was 11 keV. The implantation energy of the H2 + ion implantation was sixteen keV, and the implantation energy of the H + ion implantation was 8 keV. The SRIM calculations indicate that the difference in the peak depth profiles of H + and He + is about 200 angstroms. See FIG. 4.

[0053] The ion-implanted donor substrate was bonded to the handle substrate, annealed, and cleaved. Table 2 further provides the results of the cleavage.

[0054] Table 2: Various H2 + and H + Results of mechanical cleavage operations for various doses TIFF2025111769000003.tif141169

[0055] At very low He + energies, i.e., 11 Kev, co-implantation with H at 8 Kev and 5.9×10 15 cm -2 results in a low H + co-implantation that can give successful mechanical cleavage.

[0056] Having described the invention in detail, it will be apparent that modifications and variations are possible without departing from the scope of the invention as defined in the appended claims.

[0057] When introducing elements of the present invention or preferred embodiments thereof, the articles "a", "an", "the", and "said" are intended to mean that there are one or more of the elements. The terms "comprising", "including", and "having" are intended to be inclusive and mean that additional elements other than the recited elements may exist.

[0058] From the above, it will be seen that several objects of the present invention are achieved and other advantageous results are obtained.

[0059] Since various changes can be made in the above-described products and methods without departing from the scope of the present invention, all matter contained in the above description and shown in the accompanying drawings is intended to be interpreted in an illustrative, and not a limiting, sense.

Claims

1. 1. A method for transferring a silicon layer from a single crystal silicon donor substrate to a handle substrate, comprising: (a) H through a silicon dioxide layer in contact with the surface of the single crystal silicon donor substrate and further through the surface of the single crystal silicon donor substrate. ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ The method includes implanting a combination of ions into a single crystal silicon donor substrate, the single crystal silicon donor substrate having two major parallel surfaces, one of which is a front surface and the other of which is a back surface, a peripheral edge joining the front surface and the back surface, a central plane between the front surface and the back surface, a central axis perpendicular to the front surface, and a bulk region between the front surface and the back surface, the method comprising: ２ ＋ The ions are implanted at an implant energy of about 10 KeV to about 30 KeV, and H ＋ The ions are implanted with an implant energy of about 5 KeV to about 20 KeV, and H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ a peak density (D1) of the combined ions is from about 100 Angstroms to about 3000 Angstroms, measured along a central axis from the surface of the single crystal silicon donor substrate; (b) He through a silicon dioxide layer in contact with the surface of the single crystal silicon donor substrate and further through the surface of the single crystal silicon donor substrate. ＋ ion implantation, ＋ The ions are implanted at an implant energy of about 5 KeV to about 30 KeV, and He ＋ The peak density of ions (D2) is from about 100 Å to about 3000 Å measured along the central axis from the surface of the single crystal silicon donor substrate, and further includes H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ The peak density of the ion combination (D1) and He ＋ the peak densities (D2) of the ions are within about 450 Angstroms of each other; (c) annealing the ion-implanted single crystal silicon donor substrate at a temperature and for a time sufficient to form a damage layer in the single crystal silicon donor substrate; (d) bonding a silicon dioxide layer to the handle substrate in contact with the surface of the single crystal silicon donor substrate, thereby providing a multi-layer substrate; (e) annealing the multilayer substrate at a temperature and for a time sufficient to thermally activate the damaged layer; and (f) cleaving the annealed multilayer substrate at the damaged layer in the single crystal silicon donor substrate, thereby transferring a silicon layer having a thickness of about 500 angstroms to about 2500 angstroms from the single crystal silicon donor substrate to the handle substrate.

2. 10. The method of claim 1, wherein step (a) is performed before step (b).

3. 10. The method of claim 1, wherein step (b) is performed before step (a).

4. 10. The method of claim 1, wherein steps (a) and (b) are carried out simultaneously.

5. Step (a) is (i) H ２ ＋ Ions are approximately 4.3 × 10 １５ ions / cm ２ to about 1.1 × 10 １６ ions / cm ２ at a dose of about 10 KeV to about 30 KeV and an implant energy of about 10 KeV to about 30 KeV; (ii) H ＋ Ions are approximately 5 × 10 １５ ions / cm ２ From about 2 x 10 １６ ions / cm ２ at a dose of about 1000 keV to about 200 keV and an implant energy of about 5 Kev to about 20 Kev; or (iii) H ２ ＋ Ions are approximately 4.3 × 10 １５ ions / cm ２ to about 1.1 × 10 １６ ions / cm ２ at a dose of about 10 KeV to about 30 KeV, and further at a dose of about 10 KeV to about 30 KeV. ＋ ions, 5 × 10 １５ ions / cm ２ From about 2 x 10 １６ ions / cm ２ 10. The method of claim 1, further comprising implanting at a dose of about 100 .mu.m to about 100 .mu.m at an ion implantation energy of about 5 KeV to about 20 KeV.

6. Step (a) is (i) H ＋ Ions are approximately 1.1 × 10 １６ ions / cm ２ From about 2 x 10 １６ ions / cm ２ at a dose of about 100 .mu.m and an implant energy of about 5 KeV to about 20 KeV; or (ii) H ２ ＋ Ions are approximately 4.3 × 10 １５ ions / cm ２ to about 1.1 × 10 １６ ions / cm ２ at a dose of about 10 KeV to about 30 KeV, and further at a dose of about 10 KeV to about 30 KeV. ＋ Ions are approximately 1.1 × 10 １６ ions / cm ２ From about 2 x 10 １６ ions / cm ２ 10. The method of claim 1, comprising implanting at a dose of about 100 .mu.m to about 100 .mu.m at an implant energy of about 5 KeV to about 20 KeV.

7. Step (a) is (i) H ２ ＋ Ions are approximately 5.9 × 10 １５ ions / cm ２ to approximately 6.7 x 10 １５ ions / cm ２ at a dose of about 10 KeV to about 30 KeV and an implant energy of about 10 KeV to about 30 KeV; (ii) H ＋ Ions are approximately 6.1 × 10 １５ ions / cm ２ to approximately 6.8 x 10 １５ ions / cm ２ at a dose of about 100 .mu.m and an implant energy of about 5 KeV to about 20 KeV; or (iii) H ２ ＋ Ions are approximately 5.9 × 10 １５ ions / cm ２ to approximately 6.7 x 10 １５ ions / cm ２ at a dose of about 10 KeV to about 30 KeV, and further at a dose of about 10 KeV to about 30 KeV. ＋ Ions are approximately 6.1 × 10 １５ ions / cm ２ to approximately 6.8 x 10 １５ ions / cm ２ 10. The method of claim 1, comprising implanting at a dose of about 100 .mu.m to about 100 .mu.m at an implant energy of about 5 KeV to about 20 KeV.

8. Step (b) is ＋ Ions are approximately 6 × 10 １５ ions / cm ２ From about 8 x 10 １５ ions / cm ２ 10. The method of claim 1, comprising implanting at a dose of about 100 .mu.m at an implant energy of about 5 KeV to about 30 KeV.

9. Step (b) is ＋ Ions are approximately 6 × 10 １５ ions / cm ２ From about 8 x 10 １５ ions / cm ２ 10. The method of claim 1, comprising implanting at a dose of about 10 keV to about 30 keV and an implant energy of about 10 keV to about 30 keV.

10. Step (b) is ＋ Ions are approximately 6.6 × 10 １５ ions / cm ２ From about 7 x 10 １５ ions / cm ２ 10. The method of claim 1, comprising implanting at a dose of about 100 .mu.m at an implant energy of about 5 KeV to about 20 KeV.

11. H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ 10. The method of claim 1, wherein the peak density (D1) of the ions combined is in the range of about 500 Angstroms to about 2500 Angstroms, measured along the central axis from the surface of the single crystal silicon donor substrate.

12. He ＋ 10. The method of claim 1, wherein the peak density (D2) of ions ranges from about 500 Angstroms to about 3000 Angstroms, measured along a central axis from the surface of the single crystal silicon donor substrate.

13. H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ The peak density of the ion combination (D1) and He ＋ 2. The method of claim 1, wherein the peak densities (D2) of the ions are within about 400 Angstroms of each other.

14. H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ The peak density of the ion combination (D1) and He ＋ 2. The method of claim 1, wherein the peak densities (D2) of the ions are within about 200 Angstroms of each other.

15. 10. The method of claim 1, wherein step (c) comprises annealing the ion-implanted single crystal silicon donor substrate at a temperature of about 250°C to about 300°C for a time period of 10 to 60 minutes.

16. 10. The method of claim 1, wherein step (e) comprises annealing the multilayer substrate at a temperature of about 300°C to about 400°C for a period of 10 to 60 minutes.

17. 10. The method of claim 1, wherein the silicon layer having a thickness of about 500 angstroms to about 2500 angstroms transferred from the single crystal silicon donor substrate to the handle substrate has a thickness variation of less than about 10 angstroms.

18. 1. A method for transferring a silicon layer from a single crystal silicon donor substrate to a handle substrate, comprising: (a) H through the surface of a single crystal silicon donor substrate ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ The method includes implanting a combination of ions into a single crystal silicon donor substrate, the single crystal silicon donor substrate having two major parallel surfaces, one of which is a front surface and the other of which is a back surface, a peripheral edge joining the front surface and the back surface, a central plane between the front surface and the back surface, a central axis perpendicular to the front surface, and a bulk region between the front surface and the back surface, the method comprising: ２ ＋ The ions are implanted at an implant energy of about 10 KeV to about 30 KeV, and H ＋ The ions are implanted with an implant energy of about 5 KeV to about 20 KeV, and H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ a peak density (D1) of the combined ions is from about 100 Angstroms to about 3000 Angstroms, measured along a central axis from the surface of the single crystal silicon donor substrate; (b) He through the surface of a single-crystal silicon donor substrate. ＋ ion implantation, ＋ The ions are implanted at an implant energy of about 5 KeV to about 30 KeV, and He ＋ The peak density of ions (D2) is from about 100 Angstroms to about 3000 Angstroms measured along the central axis from the surface of the single crystal silicon donor substrate, and further includes H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ The peak density of the ion combination (D1) and He ＋ the peak densities (D2) of the ions are within about 450 Angstroms of each other; (c) bonding a single crystal silicon donor substrate to a handle substrate, thereby preparing a multilayer substrate; (d) annealing the ion-implanted single crystal silicon donor substrate at a temperature and for a time sufficient to form a damage layer in the single crystal silicon donor substrate; and (e) cleaving the multilayer substrate at the damaged layer of the single crystal silicon donor substrate, thereby transferring a silicon layer having a thickness of about 500 angstroms to about 2500 angstroms from the single crystal silicon donor substrate to the handle substrate.

19. 20. The method of claim 18, wherein step (a) is performed before step (b).

20. 20. The method of claim 18, wherein step (b) is performed before step (a).

21. 20. The method of claim 18, wherein steps (a) and (b) are carried out simultaneously.

22. Step (a) is (i) H ２ ＋ Ions are approximately 4.3 × 10 １５ ions / cm ２ to about 1.1 × 10 １６ ions / cm ２ at a dose of about 10 KeV to about 30 KeV and an implant energy of about 10 KeV to about 30 KeV; (ii) H ＋ Ions are approximately 5 × 10 １５ ions / cm ２ From about 2 x 10 １６ ions / cm ２ at a dose of about 100 .mu.m and an implant energy of about 5 KeV to about 20 KeV; or (iii) H ２ ＋ Ions are approximately 4.3 × 10 １５ ions / cm ２ to about 1.1 × 10 １６ ions / cm ２ at a dose of about 10 KeV to about 30 KeV, and further at a dose of about 10 KeV to about 30 KeV. ＋ Ions are approximately 5 × 10 １５ ions / cm ２ From about 2 x 10 １６ ions / cm ２ 20. The method of claim 18, wherein the step of implanting is at a dose of about 100 .mu.m to about 100 .mu.m and at an implant energy of about 5 KeV to about 20 KeV.

23. Step (a) is (i) H ＋ Ions are approximately 1.1 × 10 １６ ions / cm ２ From about 2 x 10 １６ ions / cm ２ at a dose of about 100 .mu.m and an implant energy of about 5 KeV to about 20 KeV; or (ii) H ２ ＋ Ions are approximately 4.3 × 10 １５ ions / cm ２ to about 1.1 × 10 １６ ions / cm ２ at a dose of about 10 KeV to about 30 KeV, and further at a dose of about 10 KeV to about 30 KeV. ＋ Ions are approximately 1.1 × 10 １６ ions / cm ２ From about 2 x 10 １６ ions / cm ２ 20. The method of claim 18, comprising implanting at a dose of about 100 .mu.m to about 100 .mu.m at an implant energy of about 5 KeV to about 20 KeV.

24. Step (a) is (i) H ２ ＋ Ions are approximately 5.9 × 10 １５ ions / cm ２ to approximately 6.7 x 10 １５ ions / cm ２ at a dose of about 10 KeV to about 30 KeV and an implant energy of about 10 KeV to about 30 KeV; (ii) H ＋ Ions are approximately 6.1 × 10 １５ ions / cm ２ to approximately 6.8 x 10 １５ ions / cm ２ at a dose of about 100 keV to about 20 keV and an ion implantation energy of about 5 keV to about 20 keV; or (iii) H ２ ＋ Ions are approximately 5.9 × 10 １５ ions / cm ２ to approximately 6.7 x 10 １５ ions / cm ２ and implanted at an implant energy of about 10 KeV to about 30 KeV. ＋ Ions are approximately 6.1 × 10 １５ ions / cm ２ to approximately 6.8 x 10 １５ ions / cm ２ 20. The method of claim 18, comprising implanting at a dose of about 100 .mu.m to about 100 .mu.m and at an implant energy of about 5 keV to about 20 keV.

25. Step (b) is ＋ Ions are approximately 6 × 10 １５ ions / cm ２ From about 8 x 10 １５ ions / cm ２ 20. The method of claim 18, comprising implanting at a dose of about 100 .mu.m and at an implant energy of about 5 KeV to about 30 KeV.

26. Step (b) is ＋ Ions are approximately 6 × 10 １５ ions / cm ２ From about 8 x 10 １５ ions / cm ２ 20. The method of claim 18, comprising implanting at a dose of about 10 KeV to about 30 KeV and an implant energy of about 10 KeV to about 30 KeV.

27. Step (b) is ＋ Ions are approximately 6.6 × 10 １５ ions / cm ２ From about 7 x 10 １５ ions / cm ２ 20. The method of claim 18, comprising implanting at a dose of about 100 .mu.m at an energy of about 5 KeV to about 20 KeV.

28. H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ 20. The method of claim 18, wherein the peak density (D1) of the combination of ions is about 500 Angstroms to about 2500 Angstroms measured along a central axis from the surface of the single crystal silicon donor substrate.

29. He ＋ 20. The method of claim 18, wherein the peak density (D2) of ions is about 500 Angstroms to about 3000 Angstroms measured along a central axis from the surface of the single crystal silicon donor substrate.

30. H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ The peak density of the ion combination (D1) and He ＋ 19. The method of claim 18, wherein the peak densities (D2) of ions are within about 400 Angstroms of each other.

31. H ２ ＋ Ion, H ＋ ions, or H ２ ＋ Ions and H ＋ The peak density of the ion combination (D1) and He ＋ 19. The method of claim 18, wherein the peak densities (D2) of ions are within about 200 Angstroms of each other.

32. 20. The method of claim 18, wherein step (c) comprises bonding a silicon dioxide layer to the handle substrate in contact with the surface of the single crystal silicon donor substrate.

33. 20. The method of claim 18, wherein step (c) comprises bonding a single crystal silicon donor substrate to the insulating layer of the handle substrate.

34. 20. The method of claim 18, wherein step (d) comprises annealing the ion-implanted single crystal silicon donor substrate at a temperature of about 200°C to about 350°C.

35. 20. The method of claim 18, wherein step (d) comprises annealing the ion-implanted single crystal silicon donor substrate at a temperature of about 250°C to about 300°C for a time period of 10 to 60 minutes.

36. 20. The method of claim 18, wherein the silicon layer having a thickness of about 500 angstroms to about 2500 angstroms transferred from the single crystal silicon donor substrate to the handle substrate has a thickness variation of less than about 10 angstroms.

37. 20. The method of claim 18, wherein step (e) comprises cleaving the multilayer substrate at the damage layer by thermal cleaving.

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