Detection device and detection system

Abstract

To provide a technique advantageous for detecting signals generated by pixels with low noise.SOLUTION: A detection device comprises: pixels each including a photodiode, an amplification transistor having its gate connected to an output node of the photodiode, a reset transistor resetting the photodiode, and a selection transistor; signal lines that are connected to the pixels, and a read-out circuit that reads out the signals from the pixels through the signal lines. The read-out circuit includes an AD converter that performs AD conversion for the signals input from the pixels through the signal lines. The AD converter performs an offset cancellation operation of maintaining a signal level according to the signals generated by the photodiode while cancelling the offset of the AD converter, and performs first AD conversion for a changed portion of the signal level after the offset cancellation operation.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a detection device and a detection system.

Background Art

[0002] There is a technique for converting an analog signal output from a pixel into a digital signal by an analog-to-digital converter (hereinafter, referred to as an AD converter). Patent Document 1 describes that after reading a signal from a pixel, the pixel is reset and AD conversion is performed. Further, Patent Document 1 describes canceling the offset of a comparator during the period when the pixel is being reset.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the configuration described in Patent Document 1, AD conversion is performed after resetting the pixel. Therefore, noise of the AD converter, for example, noise in the offset cancellation operation of the comparator, is AD-converted as an overlapping signal. Thus, there was room for further noise reduction in Patent Document 1.

[0005] An object of the present invention is to provide a technique advantageous for detecting a signal generated by a pixel with low noise.

Means for Solving the Problems

[0006] One aspect of the present invention relates to a detection device, the detection device includes a photodiode, an amplification transistor having a gate connected to an output node of the photodiode, a reset transistor for resetting the photodiode, and a pixel including a selection transistor, a signal line connected to the pixel, and a readout circuit for reading a signal from the pixel via the signal line. The readout circuit includes an AD converter for performing AD conversion on a signal input from the pixel via the signal line. The AD converter performs an offset cancellation operation of holding a signal level corresponding to a signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on a change amount of the signal level after the offset cancellation operation.

[0007] Another aspect of the present invention relates to a detection device, the detection device includes a photodiode to which radiation is incident, an amplification transistor having a gate connected to an output node of the photodiode, a reset transistor for resetting the photodiode, and a pixel including a selection transistor, a signal line connected to the pixel, and a readout circuit for reading a signal from the pixel via the signal line. The readout circuit includes an AD converter for performing AD conversion on a signal input from the pixel via the signal line. The AD converter includes a differential amplification circuit having an input node and an output node, a capacitive element having one terminal connected to the input node and the other terminal connected to the signal line, and a switch connected to the one terminal. During a period when a first signal, which is a signal level corresponding to the amount of radiation received by the photodiode, is output to the one terminal, the switch transitions from an on state to an off state. During a period from when the switch is in the off state until the next on state, a second signal, which is a signal level corresponding to the reset level of the gate, is output to the one terminal. The AD converter performs AD conversion during a period when the second signal is output to the one terminal.

Advantages of the Invention

[0008] According to the present invention, a technique advantageous for detecting a signal generated by a pixel with low noise is provided.

Brief Description of Drawings

[0009] [Figure 1] A block diagram showing a configuration example of a detection device configured as a solid-state imaging device. [Figure 2] A diagram showing a configuration example of a pixel and a readout circuit in the detection device of the first embodiment. [Figure 3A] A timing chart showing a first operation example of the detection device of the first embodiment. [Figure 3B] A timing chart showing a second operation example of the detection device of the first embodiment. [Figure 4] A timing chart showing an operation example of a clip circuit. [Figure 5] A diagram showing a configuration example of a pixel and a readout circuit in the detection device of the second embodiment. [Figure 6] A timing chart showing an operation example of the detection device of the second embodiment. [Figure 7] A diagram showing a detection system in the third embodiment. [Figure 8] A diagram showing a detection system in the fourth embodiment.

Modes for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, all of these plurality of features are not necessarily essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0011] FIG. 1 shows the configuration of the detection device 1 according to an embodiment. Although FIG. 1 illustrates the detection device 1 configured as a solid-state imaging device having a plurality of pixels, the detection device 1 can be configured as a device having at least one pixel (or detection element). The detection device 1 is a direct conversion type detection device including a photodiode that directly converts incident radiation into electric charge. In the following description, "radiation" is a concept including non-ionizing radiation (such as infrared rays, visible light, ultraviolet rays, etc.) and ionizing radiation (electromagnetic radiation and particle radiation). Electromagnetic radiation includes, for example, X-rays and gamma rays, and particle radiation includes, for example, electron beams, proton beams, neutron beams, alpha rays, etc. "Detection system" generally refers to a system that uses radiation to acquire an image of an imaging target (subject, patient in the case of a medical detection system, etc.) as electronic data. The "image" may be a still image or a moving image.

[0012] The detection device 1 can include, for example, a pixel array 10, a readout circuit 110, a horizontal scanning circuit 40, a vertical scanning circuit 50, a lamp signal generation circuit 60, a counter 70, a timing control unit 80, and a signal processing unit 90. The detection device 1 can further include a plurality of row control line groups 11, a plurality of signal lines 12, a lamp signal line 61, and a count signal line 71.

[0013] The pixel array 10 has a plurality of pixels 100 arranged to form a plurality of rows and a plurality of columns. The vertical scanning circuit 50 is electrically connected to the plurality of pixels 100 in row units via the plurality of row control line groups 11. One row control line group 11 is commonly provided corresponding to one row of pixels 100. One row control line group 11 can include a selection signal line for transmitting a selection signal and a reset signal line for transmitting a reset signal. The vertical scanning circuit 50 is electrically connected to the timing control unit 80.

[0014] The vertical scanning circuit 50 controls a plurality of pixels 100 in row units based on a timing signal supplied from the timing control unit 80. Each pixel 100 in a column of the row selected by the vertical scanning circuit 50 outputs a signal PIXSIG to the corresponding signal line 12 among the plurality of signal lines 12. Each of the plurality of signal lines 12 is connected to a plurality of rows of pixels 100 located in the corresponding column.

[0015] The ramp signal generation circuit 60 generates a ramp signal RAMP and supplies it to the plurality of AD converters 21 via the ramp signal line 61. The ramp signal generation circuit 60 can start an operation of changing the signal level of the ramp signal RAMP according to the passage of time based on a timing signal supplied from the timing control unit 80.

[0016] The readout circuit 110 includes a plurality of column circuits 20 respectively corresponding to a plurality of columns composed of a plurality of pixels 100. The column circuit 20 may include an AD converter 21, a column memory 30, a clip circuit 140, and a latch signal line 22. The column circuit 20 may include, for example, a sample hold circuit, an amplifier circuit, etc. in front of the AD converter 21.

[0017] The clip circuit 140 clips the voltage of the signal line 12. The AD converter 21 may be connected to the column memory 30 by the latch signal line 22. Each signal line 12 outputs a signal PIXSIG (first signal) having a signal level corresponding to a signal generated by a photodiode from the pixel 100 connected thereto. The AD converter 21 can output a comparison result signal LATCH indicating a result of comparing the signal level of the signal PIXSIG output from the pixel 100 in the corresponding column to the signal line 12 with the ramp signal RAMP to the corresponding column memory 30.

[0018] The counter 70 counts the clock signal CLK supplied from the timing control unit 80 to generate a count signal COUNT. The counter 70 supplies the count signal COUNT to the plurality of column memories 30 via count signal lines 71. The count signal COUNT is a digital signal of multiple bits. The count signal lines 71 typically have multiple bit lines that transmit a 1-bit signal, and transmit the multiple-bit signals of the count signal COUNT in parallel.

[0019] The horizontal scanning circuit 40 sequentially selects the column memories 30 of each of the multiple columns. The column memories 30 selected by the horizontal scanning circuit 40 output a digital signal corresponding to the voltage of the signal level of the signal PIXSIG to the signal processing unit 90. The signal processing unit 90 performs various processes, such as correction, amplification, and level shifting, on the digital signal input from the column memories 30 and outputs the result to the outside of the detection device 1.

[0020] FIG. 2 shows an example configuration of one pixel 100 and a portion (AD converter 21, clipping circuit 140) of the readout circuit 110 (more specifically, the column circuit 20 connected to the pixel 100) of the detection device 1 of the first embodiment. The pixel 100 may include a photodiode PD, an amplification transistor M102 whose gate is connected to the output node of the photodiode PD, a reset transistor M101 that resets the photodiode PD, and a selection transistor M103. The amplification transistor M102, the reset transistor M101, and the selection transistor M103 may be configured by MOS transistors. A row control line group 11 and a signal line 12 may be connected to the pixel 100. The row control line group 11 may include a reset signal line that transmits a reset signal PRES and a selection signal line that transmits a selection signal PSEL. The signal line 12 is connected to a current source 130 and supplies a signal PIXSIG having a signal level corresponding to the signal generated by the photodiode PD (the amount of radiation received by the photodiode PD) to the column circuit 20 of the readout circuit 110, more specifically to the AD converter 21.

[0021] The amplification transistor M102 may have its drain connected to the power supply VDD, its gate connected to the cathode of the photodiode PD, and its source connected to the signal line 12. The selection transistor M103 may have its source connected to the signal line 12, its drain connected to the source of the amplification transistor M102, and its gate connected to the selection signal line that transmits the selection signal PSEL. Alternatively, the selection transistor M103 may be arranged in the path connecting the power supply VDD and the amplification transistor M102.

[0022] The reset transistor M101 may have its drain connected to the power supply VDD, its source connected to the cathode of the photodiode PD, and its gate connected to the reset signal line that transmits the reset signal PRES. The anode of the photodiode PD is connected to the reference voltage (GND). The amplification transistor M102 outputs a signal PIXSIG having a signal level corresponding to the signal generated by the photodiode PD, that is, the signal (potential) appearing at the output node (cathode) of the photodiode PD, to the signal line 12. The amplification transistor M102 performs a source follower operation by the current supplied from the current source 130 connected to the signal line 12 and the voltage VDD connected to the drain.

[0023] The detection device 1 is not limited to a CMOS sensor or a solid-state imaging device in which the pixel 100 is irradiated with light. For example, it may be configured as an electron beam direct detection device in which the pixel 100 is irradiated with an electron beam. It is known that the characteristics of each MOS transistor of the pixel 100, such as threshold variation, deteriorate in proportion to the irradiation time of the electron beam. Therefore, it is desirable that the number of MOS transistors constituting the pixel 100 is small. Thus, in one example, the pixel 100 may be composed of the above three MOS transistors.

[0024] The AD converter 21 may be configured, for example, by a comparator. The comparator configured as the AD converter 21 may include, for example, a differential amplifier circuit 200, capacitors C201 (capacitance elements) and C202, and switches SW201 and SW202. The differential amplifier circuit 200 has a non-inverting input node (I+) as a first input node, an inverting input node (I-) as a second input node, a non-inverting output node (O+) as a first output node, and an inverting output node (O-) as a second output node. The first input node and the first output node are in phase, and the second input node and the second output node are in phase. The first input node and the second input node form a differential input pair, and the first output node and the second output node form a differential output pair. The differential amplifier circuit 200 may be a fully differential amplifier circuit. The differential amplifier circuit 200 further has an output node (O) that outputs the result of comparing the voltage applied to the first input node with the voltage applied to the second input node.

[0025] A non-inverting input node (I+) of the differential amplifier circuit 200 is connected to a second terminal (one terminal) of the first capacitor C201 and a first terminal of the switch SW201 via a signal line INP. A first terminal (the other terminal) of the first capacitor C201 is connected to a signal line 12. A second terminal of the first switch SW201 is connected to an inverting output node (−) of the differential amplifier circuit 200. The first switch SW201 can be understood as a switch that short-circuits the non-inverting input node (I+) as a first input node of the differential amplifier circuit 200 and an inverting output node (O−) as a second output node of the differential amplifier circuit 200. The first switch SW201 is controlled by a control signal FB from the timing control unit 80.

[0026] The inverting input node (-) of the differential amplifier circuit 200 is connected to the second terminal of the second capacitor C202 and the second terminal of the second switch SW202 via the signal line INN. The first terminal of the second capacitor C202 is connected to the ramp signal line 61, and the ramp signal RAMP is input thereto. The second terminal of the second switch SW202 is connected to the non-inverting output node (+) of the differential amplifier circuit 200. The second switch SW202 can be understood as a switch that short-circuits the inverting input node (I―+) as the second input node of the differential amplifier circuit 200 and the non-inverting output node (O+) as the first output node of the differential amplifier circuit 200. The second switch SW202 is controlled by the control signal FB from the timing control unit 80.

[0027] Offset cancellation can be performed by controlling the switches SW201 and SW202. The offset cancellation operation is an operation of holding the signal level of the signal PIXSIG output to the signal line 12 in accordance with the signal generated by the photodiode PD of the pixel 100 while canceling the offset of the AD converter 21. After performing the offset cancellation operation, the AD converter 21 AD-converts the change amount of the signal level after the offset cancellation operation. The output node (O) of the differential amplifier circuit 200 is connected to the latch signal line 22 and outputs a comparison result signal LATCH. The comparison result signal LATCH indicates the comparison result between the signal level of the signal PIXSIG output to the signal line 12 and the ramp signal RAMP.

[0028] Note that the differential amplifier circuit 200 may have an inverting input node (I-) as the first input node, a non-inverting input node (IO) as the second input node, an inverting output node (O-) as the first output node, and a non-inverting output node (O+) as the second output node.

[0029] Also, the AD converter 21 only needs to be able to hold the voltage of the level of the signal PIXSIG (and the ramp signal RAMP) while canceling the offset of the AD converter 21, and is not limited to the above configuration.

[0030] The clipping circuit 140 may be configured, for example, with a clipping transistor M141 configured as a MOS transistor, switches SW141 and SW142, and a capacitor C141. The clipping circuit 140 is not limited to the configuration illustrated in FIG. 2, as long as it has a configuration capable of performing a clipping operation that limits the amplitude of the signal PIXSIG within a predetermined range. In this description, it is assumed that the voltage drop due to the threshold voltage of the clipping transistor M141 is negligible. The clipping circuit 140 clips or limits the voltage of the signal line 12 according to the gate voltage of the clipping transistor M141.

[0031] The clipping transistor M141 has a source connected to the signal line 12 and the switch SW141, and a drain connected to a power supply VDD. The gate of the clipping transistor M141 is connected to a first terminal of the switch SW141, a second terminal of the switch SW142, and a second terminal of the capacitor C141. A first voltage VCLIPSH is supplied to a first terminal of the capacitor C141. A second voltage VCLIP is supplied to a first terminal of the switch SW142. The first voltage VCLIPSH and the second voltage VCLI may be supplied from outside the detection device 1 or may be generated inside the detection device 1. A first signal PCLIP is supplied from the timing control unit 80 to a control terminal of the switch SW142. A second signal PCLIPSH is supplied from the timing control unit 80 to a control terminal of the switch SW141.

[0032] The switch SW141 is conductive when the second signal PCLIPSH is at a high level and samples the signal PIXSIG onto the capacitor C141. When the second signal PCLIPSH transitions from a high level to a low level, the switch SW141 transitions from a conductive state to a non-conductive state and holds the signal PIXSIG sampled onto the capacitor C141. By varying the first voltage CLIPSH, which is the first voltage V, when the switch SW141 is in a non-conductive state, the gate voltage of the clip transistor M141 can be controlled. The switch SW142 is conductive when the second voltage PCLIP is at a high level and supplies the second voltage VCLIP to the gate of the clip transistor M141. The switch SW142 must be conductive when the switch SW141 is in a non-conductive state.

[0033] An operation example of the detection device 1 of the first embodiment will be described below with reference to FIGS. 3A and 3B. FIG. 3A shows a first operation example of the detection device 1 of the first embodiment, and FIG. 3B shows a second operation example of the detection device 1 of the first embodiment. The first and second operation examples differ in the timing of the signal FB. FIGS. 3A and 3B show an operation example of two rows of pixels 100. Period T1 is a signal readout period for the pixels 100 in the first row (or nth row), and period T2 is a signal readout period for the pixels 100 in the second row (or n+1th row).

[0034] First, a first operation example will be described with reference to Figure 3A. Period T1 shows the operation in a state where there is no accumulated charge in the photodiode PD of the selected pixel 100. Period T2 shows the operation in a state where there is accumulated charge in the photodiode PD of the selected pixel 100. After the operations of periods T1 and T2, the operations of periods T1 and T2 are performed for the selected pixels 10 in the next row, and thereafter, similar operations are repeated for the subsequent rows.

[0035] First, the period T2 will be described. At time t20, the timing control unit 80 sets the signal FB supplied to each column circuit 20 of the readout circuit 110 to a high level. This causes the first switch SW201 and second switch SW202 of the AD converter 21 to be conductive. The signal lines INP and INN of the AD converter 21 are reset to the voltages of the non-inverting output node (O+) and the inverting output node (O-) of the differential amplifier circuit 200, respectively. The AD converter 21 is reset to a state in which the offset voltage of the differential amplifier circuit 200 is held (as an initial value) so that it is canceled. This enables the offset cancellation operation. For ease of explanation, FIGS. 3A and 3B show the operation when there is no offset voltage of the differential amplifier circuit 200.

[0036] At time t21, the vertical scanning circuit 50 sets the selection signal PSEL supplied to a selected row in the pixel array 10 to high level. This causes the selection transistor M103 of that row to become conductive. The amplification transistor M102 of each pixel 100 in that row outputs a signal generated by the photodiode PD, in other words, a signal PIXSIG having a signal level corresponding to the potential (accumulated charge) of the photodiode PD, to the signal line 12. This changes the signal level of the signal PIXSIG.

[0037] At time t22, the timing control unit 80 sets the signal FB supplied to the column circuit 20 of the readout circuit 110 to low level. This causes the first switch SW201 and the second switch SW202 of the AD converter 21 to become non-conductive. This indicates the end of the offset cancellation operation. A signal PIXSIG is supplied to the first terminal of the first capacitor C201 of the AD converter 21. The second terminal of the first capacitor C201 of the AD converter 21 completes holding the voltage reset by the voltage of the inverting output node (O-) of the differential amplifier circuit 200. A ramp signal RAMP is supplied to the first terminal of the second capacitor C202 of the AD converter 21. At this time, the ramp signal generation circuit 60 sets the ramp signal RAMP to a predetermined reference voltage. The second terminal of the second capacitor C202 of the AD converter 21 completes holding the voltage reset at the non-inverting output node (O+) of the differential amplifier circuit 200. This series of operations enables the offset cancellation operation of the differential amplifier circuit 200 (AD converter 21). However, the reset voltage of the differential amplifier circuit 200 includes noise from the AD converter 21, such as noise generated when the first switch SW201 and the second switch SW202 are turned off.

[0038] At time t23, the ramp signal generating circuit 60 starts the slope operation of the ramp signal RAMP. When the voltage (signal level) of the signal line INP and the voltage of the signal line INN become the same, the differential amplifier circuit 200 outputs a pulse lt21 to the comparison result signal LATCH. Then, by the AD conversion operation described above, a digital signal is stored in the column memory 30. This is the first AD conversion, and a digital signal corresponding to the reset voltage of the differential amplifier circuit 200 containing noise from the AD converter 21 can be obtained.

[0039] At time t24, the vertical scanning circuit 50 sets the reset signal PRES to high level, which turns on the reset transistor M101 and resets the photodiode PD. The signal PIXSIG then changes to a signal level that corresponds to the reset voltage of the photodiode PD.

[0040] At time t25, the vertical scanning circuit 50 sets the reset signal PRES to low level. This causes the reset transistor M101 to become non-conductive, and the reset of the photodiode PD is released. The difference (potential difference) between the signal level of the signal PIXSIG before the reset of the photodiode PD and the signal level of the signal PIXSIG after the reset of the photodiode PD, i.e., the change in signal level, is the pixel signal voltage Vpix that corresponds to the accumulated charge of the photodiode PD.

[0041] At time t26, the ramp signal generation circuit 60 starts the slope operation of the ramp signal RAMP, and a second AD conversion is performed. The second AD conversion is performed after the first AD conversion in response to a change in the signal level of the pixel signal PIXSIG caused by the reset transistor M101 resetting the photodiode PD. The differential amplifier circuit 200 outputs a pulse lt22 to the comparison result signal LATCH at a timing corresponding to the value of the pixel signal voltage Vpix, and the digital signal is stored in the column memory 30. By subtracting the first AD conversion result from the second AD conversion result, a digital signal corresponding to the pixel signal voltage Vpix can be obtained, with noise from the AD converter removed. The AD converter 21 may be configured to output a value obtained by subtracting the first AD conversion result from the second AD conversion result.

[0042] Next, the operation during period T1 will be described. The operation during period T1 differs from the operation during period T2 only in that there is no accumulated charge in the photodiode PD. Therefore, only the differences will be described here, and descriptions of other operations will be omitted.

[0043] At time t11, the signal level of the signal PIXSIG remains unchanged because there is no charge stored in the photodiode PD.

[0044] At time t12, as in period T2, the offset cancellation operation of the differential amplifier circuit 200 is performed. The signal level of the signal PIXSIG at this time depends on the accumulated charge of the photodiode PD. The subsequent operation is the same as the operation in period T2.

[0045] Next, a second operation example shown in Fig. 3B will be described. The second operation example in Fig. 3B differs from the first operation example in Fig. 3A only in the timing at which the signal FB is set to high level. The other timings and operations are the same, so detailed description thereof will be omitted.

[0046] The operation during period T2 will be described. At time t20, the timing control unit 80 does not set the signal FB supplied to each column circuit 20 of the readout circuit 110 to high level. Then, at time t200, the timing control unit 80 sets the signal FB to high level. In this respect, the second operation example differs from the first operation example shown in FIG. 3A.

[0047] At time t21, the vertical scanning circuit 50 sets the selection signal PSEL to high level. In the second operation example, the signal FB is low level at this time, so the signal line INP of the AD converter 21 is not reset. Therefore, the voltage of the signal line INP changes following the signal level of the signal PIXSIG via the first capacitor C201. If the voltage fluctuation of the signal line INP is large, an error may occur in the offset cancellation operation due to fluctuations in the power supply voltage VDD, etc. In that case, an error will also occur in the result of the first AD conversion. Therefore, as in the first operation example, it is desirable to set the signal FB to high level before the signal level of the signal PIXSIG changes.

[0048] Next, the operation of the clipping circuit 140 in Fig. 2 will be described with reference to Fig. 4. In period T2 in Fig. 4, the same timing as in period T2 in Fig. 3A and Fig. 3B is indicated by the same reference numerals.

[0049] Voltage Vg_M141 (dashed line) indicates the gate voltage of clipping transistor M141 of clipping circuit 140. As described above, clipping circuit 140 clips the voltage of signal line 12 so that it does not fall below voltage Vg_M141.

[0050] At time t20, the first signal PCLIP is set to high level. The switch SW142 of the clipping circuit 140 becomes conductive, and the voltage Vg_M141 changes to the second voltage VCLIP. The second voltage VCLIP is a voltage higher than the lower limit voltage at which the current source 130 operates.

[0051] At time t24, the first signal PCLIP is set to low level. This causes the switch SW142 of the clip circuit 140 to become non-conductive. Next, the second signal PCLIPSH is set to high level. This causes the switch SW141 of the clip circuit 140 to become conductive, and the voltage Vg_M141 changes to the signal level of the signal PIXSIG. Next, the first voltage VCLIPSH is changed to the first reference voltage.

[0052] At time t27, the second signal PCLIPSH is set to low level. This causes the switch SW141 to become non-conductive, and the voltage Vg_M141 becomes a value obtained by sampling and holding the signal level of the signal PIXSIG. At time t25, the first voltage VCLIPSH is changed to the second reference voltage. The difference between the first reference voltage and the second reference voltage is the voltage ΔVCLIPSH. The voltage Vg_M141 changes to a voltage lower by the voltage ΔVCLIPSH via the capacitor C141. The voltage ΔVCLIPSH is set so that the voltage Vg_M141 becomes a voltage lower than the signal PIXSIG.

[0053] At time t25, the reset signal PRES goes low. This puts the photodiode PD into an accumulation state. Consider a case where the photodiode PD is irradiated with radiation during the second AD conversion in period T2. Without the clipping circuit 140, the signal level of the signal PIXSIG would change during the second AD conversion, potentially making it impossible to perform AD conversion according to the pixel signal voltage Vpix. However, by providing the clipping circuit 140, the signal level of the signal PIXSIG is clipped according to the voltage Vg_M141 obtained by sampling and holding the signal level of the signal PIXSIG at time t27. This makes it possible to perform AD conversion according to the voltage Vpix'. For example, in applications such as electron beam detection, the presence or absence of an electron beam may be determined. In this case, there is no problem as long as the voltage Vpix' is a voltage value sufficient to determine the presence or absence of an electron beam.

[0054] The signal PIXSIG' (dash line) shows a state in which a threshold voltage shift occurs due to an electron beam in the pixel 100. The signal PIXSIG' is an example in which a voltage value that is ΔVth lower than the signal PIXSIG is assumed due to a threshold voltage shift of the amplification transistor M102.

[0055] Even when the output of pixel 100 changes, as in the case of signal PIXSIG', clipping circuit 140 performs clipping based on the signal level of signal PIXSIG' at time t24. Therefore, even if the threshold of pixel 100 changes, appropriate clipping can be performed on the output after the change.

[0056] According to the first embodiment, for example, it is possible to reduce deterioration in image quality due to noise in an AD converter, and to improve image quality.

[0057] In the above example, the readout circuit 110 is arranged on one side of the pixel array 10. However, this is merely an example, and the present invention is not limited to this. For example, multiple readout circuits 110 may be provided, such as by arranging the readout circuits 110 on both sides of the pixel array 10. Furthermore, multiple ramp signal generation circuits 60 and ramp signal lines 61 may be arranged. When multiple ramp signal generation circuits 60 and ramp signal lines 61 are arranged, gain adjustment may be performed for each column circuit 20 to which the ramp signal line 61 is connected. Gain adjustment for each column circuit 20 can be performed by gain adjustment within the ramp signal generation circuit 60, gain adjustment in the signal processing unit 90, gain adjustment in an external system, or the like. Furthermore, as in Patent Document 1, the first switch SW201 may be connected to the second terminal of the first capacitor C201 and a node to which the power supply voltage is supplied.

[0058] The second embodiment will be described below. Matters not mentioned in the second embodiment may follow the first embodiment. FIG. 5 shows an example configuration of one pixel 100 and a readout circuit 110 (more specifically, a part of the column circuit 20 connected to the pixel 100) as the configuration of a detection device 1 of the second embodiment. In the second embodiment, the readout circuit 110 includes a sample-and-hold circuit 210 arranged between the signal line 12 and the AD converter 21. The sample-and-hold circuit 210 may include, for example, a buffer circuit 211, a capacitor C211, and a switch SW211.

[0059] A first terminal of a capacitor C211 and a second terminal of a switch SW211 are connected to an input node of the buffer circuit 211. An output node of the buffer circuit 211 is connected to a first terminal of a first capacitor C201 of the AD converter 21. A second terminal of the capacitor C211 is connected to a reference voltage (GND). A first terminal of the switch SW211 is connected to a signal line 12. The switch SW211 is controlled by a signal SH from the timing control unit 80. The other configurations are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0060] Hereinafter, an operation example of the detection device 1 according to the second embodiment will be described with reference to FIG. 6. In FIG. 6, the operation of the pixels 100 in two rows will be described. Period T3 is the signal readout period of the pixels 100 in the first row (n-th row plane), and period T4 is the signal readout period of the pixels 100 in the second row ((n + 1)-th row).

[0061] Period T3 shows the operation in a state where there is no accumulated charge in the photodiode PD of the selected pixel 100. Period T4 shows the operation in a state where there is accumulated charge in the photodiode PD of the selected pixel 100.

[0062] With reference to period T4 in FIG. 6, the operation of the sample hold circuit 210 in FIG. 5 will be described. Since period T3 in FIG. 6 only has a different accumulation state of the photodiode PD and has the same drive as period T4, the description thereof will be omitted. Also, the operations described in the description of the first embodiment will be omitted.

[0063] At time t41, the vertical scanning circuit 50 sets the selection signal PSEL supplied to the selected row in the pixel array 10 to a high level. As a result, similar to the first embodiment, the signal level of the signal PIXSIG changes. However, in the second embodiment, since there is a sample hold circuit 210, during the period when the signal SH is at a low level, the change in the signal PIXSIG is not transmitted to the signal line INP.

[0064] At time t410, the timing control unit 80 sets the signal FB supplied to the column circuit 20 to a high level. As described in the first embodiment, it is desirable that the signal FB be set to a high level before the voltage of the signal line INP changes.

[0065] At time t411, the timing control unit 80 sets the signal SH supplied to the column circuit 20 of the readout circuit 110 to a high level. As a result, the switch SW211 of the sample hold circuit 210 conducts, and the signal level of the signal PIXSIG is sampled in the capacitor C211.

[0066] At time t42, the timing control unit 80 sets the signal FB supplied to the column circuit 20 of the readout circuit 110 to low level. As a result, the offset cancellation operation of the differential amplifier circuit 200 (AD converter 21) is performed as described in the first embodiment.

[0067] At time t412, the timing control unit 80 sets the signal SH supplied to the column circuit 20 of the readout circuit 110 to low level. This causes the switch SW211 of the sample-and-hold circuit 210 to become non-conductive, and the voltage of the signal PIXSIG is held in the capacitor C211.

[0068] At time t43, the ramp signal generation circuit 60 starts the slope operation of the ramp signal RAMP, and a first AD conversion is performed. At time t44, the vertical scanning circuit 50 sets the reset signal PRES to high level. At time t45, the vertical scanning circuit 50 sets the reset signal PRES to low level. At time t413, the timing control unit 80 sets the signal SH to high level. This causes the signal level of the signal PIXSIG to be sampled by the capacitor C211. At time t414, the timing control unit 80 sets the signal SH to low level. This causes the signal level of the signal PIXSIG to be held (retained) by the capacitor C211. At time t46, the ramp signal generation circuit 60 starts the slope operation of the ramp signal RAMP, and a second AD conversion is performed.

[0069] As in the first embodiment, the result of the first AD conversion is subtracted from the result of the second AD conversion to remove noise from the AD converter 21. The operation of the clip circuit 140 is the same as in the first embodiment, and therefore a description thereof will be omitted.

[0070] As described above, in the second embodiment, the AD converter 21 starts the offset cancellation operation before the signal level of the pixel signal PIXSIG is supplied to the AD converter 21 via the sample and hold circuit 210. The AD converter 21 starts the offset cancellation operation after a predetermined time (for example, the predetermined period is a set accumulation period) has elapsed since the photodiode PD was last reset by the reset transistor M101 and before the signal level of the pixel signal PIXSIG is supplied to the AD converter 21 via the sample and hold circuit 210.

[0071] In the second embodiment, the second AD conversion can be overlapped with the readout operation of the pixels 100 in the next row. As illustrated in FIG. 6, the second AD conversion in the period T3 is performed in the period T4. This allows the periods T3 and T4 to be shortened, thereby achieving a high frame rate.

[0072] The detector 1 can be used in various systems, such as the detector 1. Such a system can be, for example, a camera (imaging device) or an electron beam detection system. The system can include, for example, the detector 1 and a processing unit that processes an image detected using multiple pixels of the detector 1.

[0073] The third embodiment will be described below. Matters not mentioned in the third embodiment may follow the first or second embodiment. Fig. 7 shows a detection system incorporating the detection device 1.

[0074] 7 includes an imaging device 1101, an exposure control unit 1102, a radiation source 1103, and a computer 1104. The imaging device 1101 can be the detection device 1 described in the first or second embodiment.

[0075] The radiation source 1103 starts irradiating radiation in accordance with an exposure command from the exposure control unit 1102. The radiation emitted from the radiation source 1103 passes through the imaging target (subject) and enters the image sensor 1001 of the imaging device 1101. The radiation source 1103 stops emitting radiation in accordance with a stop command from the exposure control unit 1102.

[0076] The imaging device 1101 is, for example, a flat panel detector used for radiography in medical image diagnosis, non-destructive testing, and the like. The imaging device 1101 includes an imaging panel 100P that includes a direct conversion type imaging element 100 as a detection device. The imaging panel 100P can be a plate-shaped element sized to match the size of the object to be imaged. For example, the imaging element 100 has 3300 x 2800 pixels arranged on a 550 mm x 445 mm substrate.

[0077] The imaging device 1101 includes the imaging panel 100P described above, a control unit 1105 for controlling the imaging panel 100P, and a signal processing unit 1106 for processing signals output from the imaging panel 100P. The signal processing unit 1106 may calculate background components of pixel signals output from the imaging panel 100P and subtract the background components from the pixel signals. The signal processing unit 1106 may include the functions of the signal processing unit 90 of the first and second embodiments and may output digital image data to a computer 1104. The signal processing unit 1106 may also generate a stop signal for stopping radiation irradiation from the radiation source 1103, for example, based on the signal output from the imaging panel 100P. The stop signal is supplied to an exposure control unit 1102 via the computer 1104, and the exposure control unit 1102 sends a stop command to the radiation source 1103 in response to the stop signal.

[0078] The control unit 1105 can be configured, for example, by a PLD (abbreviation for Programmable Logic Device) such as an FPGA (abbreviation for Field Programmable Gate Array), or an ASIC (abbreviation for Application Specific Integrated Circuit), or a general-purpose computer with a built-in program, or a combination of all or part of these.

[0079] In the present embodiment, the signal processing unit 1106 is shown as being arranged in the control unit 1105 or as a part of the function of the control unit 1105, but this is not limiting. The control unit 1105 and the signal processing unit 1106 may be configured separately. Furthermore, the signal processing unit 1106 may be arranged separately from the imaging device 1101. For example, the computer 1104 may have the function of the signal processing unit 1106. Therefore, the signal processing unit 1106 may be included in the detection system 1100 as a signal processing device that processes signals output from the imaging device 1101.

[0080] The computer 1104 can control the imaging device 1101 and the exposure control unit 1102, receive radiation image data from the imaging device 1101, and perform processing to display the data as a radiation image. The computer 1104 can also function as an input unit for the user to input conditions for capturing a radiation image.

[0081] As an example, the exposure control unit 1102 has an exposure switch, and when the user turns on the exposure switch, it sends an exposure command to the radiation source 1103 and also sends a start notification indicating the start of radiation emission to the computer 1104. In response to the start notification, the computer 1104 notifies the control unit 1105 of the imaging device 1101 of the start of radiation irradiation. In response to this, the control unit 1105 causes the imaging panel 100P to generate a signal corresponding to the incident radiation.

[0082] Hereinafter, a fourth embodiment will be described. FIG. 8 shows another example of a detection system incorporating a detection device.

[0083] FIG. 8(a) shows an equipment EQP as a detection system including a detection device 1. The detection device 1 includes, in addition to an image sensor 100 which is a semiconductor device, a package PKG for mounting the image sensor 100.

[0084] The package PKG may include a substrate to which the image sensor 1001 is fixed, a lid such as glass facing the image sensor 1001, and connection members such as bonding wires and bumps for connecting terminals provided on the substrate and terminals provided on the image sensor 1001. The image sensor 1001 has a pixel region 100 in which pixels are arranged in a matrix and a peripheral region PR around it.

[0085] The equipment EQP may further include at least any one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a storage device MMRY, and a mechanical device MCHN. The optical system OPT forms an image of radiation on the detection device 1 and is, for example, a lens, a shutter, or a mirror. The optical system OPT may form an image of a particle beam such as an electron beam or a proton beam on the detection device 1 according to the type of radiation to be handled. The control device CTRL controls the detection device 1 and is, for example, an ASIC. The processing device PRCS processes signals output from the detection device 1 and is a device such as a CPU or an ASIC for constituting an AFE (analog front end) or a DFE (digital front end). The display device DSPL is an EL display device or a liquid crystal display device that displays information obtained by the detection device 1 in a form such as a visible image. The storage device MMRY is a magnetic device or a semiconductor device that stores information obtained by the detection device 1. The storage device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a movable part or a propulsion part such as a motor or an engine.

[0086] The equipment EQP displays the signal output from the detection device 1 on the display device DSPL or transmits it externally through a communication device (not shown) provided in the equipment EQP. For this purpose, it is preferable that the equipment EQP further includes a storage device MMRY and a processing device PRCS separately from the storage circuit and arithmetic circuit of the detection device 1. The mechanical device MCHN may be controlled based on the signal output from the detection device 1.

[0087] The equipment EQP shown in Fig. 8(a) may be a medical device such as an endoscope or a radiation diagnostic device, a measuring device such as a distance measuring sensor, or an analytical device such as an electron microscope.

[0088] Fig. 8(b) is a schematic diagram showing the configuration of a transmission electron microscope (TEM) as an example of the equipment EQP. The equipment EQP as an electron microscope includes an electron beam source 1202 (electron gun), an irradiation lens 1204, a vacuum chamber 1201 (column), an objective lens 1206, a magnifying lens system 1207, and a camera 1209 as the detection device 1.

[0089] The electron beam 1203, which is an energy ray emitted from the electron beam source 1202, is focused by the irradiation lens 1204 and irradiated onto the sample S as the analysis target held by the sample holder. The space through which the electron beam 1203 passes is formed by the vacuum chamber 1201 (column), and this space is maintained in a vacuum. The detection device 1 is arranged so as to face the vacuum space through which the electron beam 1203 passes. The electron beam 1203 that has passed through the sample S is magnified by the objective lens 1206 and the magnifying lens system 1207 and projected onto the detection device 1. The electron optical system for irradiating the sample S with an electron beam is called an irradiation optical system, and the electron optical system for forming an image of the electron beam that has passed through the sample S on the detection device 1 is called an imaging optical system.

[0090] The electron beam source 1202 is controlled by an electron beam source controller 1211. The illumination lens 1204 is controlled by an illumination lens controller 1212. The objective lens 1206 is controlled by an objective lens controller 1213. The magnifying lens system 1207 is controlled by a magnifying lens system controller 1214. The sample holder control mechanism 1205 is controlled by a holder controller 1215, which controls the drive mechanism of the sample holder.

[0091] An electron beam 1203 transmitted through the sample S is detected by a direct detector 1200 of a camera 1209. An output signal from the direct detector 1200 is processed by a signal processing device 1216 and an image processing device 1218 serving as a processing device PRCS, and an image signal is generated. The generated image signal (transmitted electron image) is displayed on an image display monitor 1220 and an analysis monitor 1221, which correspond to a display device DSPL.

[0092] The camera 1209 is provided at the bottom of the device EQP. The camera 1209 has a direct electron detector 1200. The direct detector 1200 corresponds to the image sensor 100. The camera 1209 is provided inside the camera 1209 so that at least a part of the camera 1209 is exposed to the vacuum space formed by the vacuum chamber 1201.

[0093] The electron beam source controller 1211, the irradiation lens controller 1212, the objective lens controller 1213, the magnifying lens system controller 1214, and the holder controller 1215 are each connected to an image processor 1218. This allows mutual data exchange to set the imaging conditions of the electron microscope. For example, the electron beam irradiation rate can be set to 0.5 electron / pix / frm or less. In this case, the electron beam source controller 1211 and the image processor 1218 function as control means for controlling the radiation irradiation rate. Drive control of the sample holder and setting of the observation conditions for each lens can be performed using signals from the image processor 1218.

[0094] The operator prepares a sample S to be photographed and sets the photographing conditions using an input device 1219 connected to the image processing device 1218. Predetermined data is input to the electron beam source control device 1211, the illumination lens control device 1212, the objective lens control device 1213, and the magnifying lens system control device 1214, respectively, to obtain the desired acceleration voltage, magnification, and observation mode. The operator also inputs conditions such as the number of consecutive field-of-view images, the photographing start position, and the specimen holder movement speed into the image processing device 1218 using the input device 1219 such as a mouse, keyboard, or touch panel. The image processing device 1218 may be designed to automatically set the conditions without relying on operator input.

[0095] The detection systems described in the third and fourth embodiments above are merely examples, and the detection devices described in the first and second embodiments may be applied to other systems.

[0096] The present specification and accompanying drawings include the following disclosure: (Item 1) a pixel including a photodiode, an amplifying transistor having a gate connected to an output node of the photodiode, a reset transistor that resets the photodiode, and a selection transistor; signal lines connected to the pixels; a readout circuit that reads out signals from the pixels via the signal lines; the readout circuit includes an AD converter that performs AD conversion on a signal input from the pixel via the signal line, the AD converter performs an offset cancellation operation to hold a signal level corresponding to the signal generated by the photodiode while canceling an offset of the AD converter, and performs a first AD conversion on a change in the signal level after the offset cancellation operation; A detection device characterized by: (Item 2) After the first AD conversion, the AD converter performs a second AD conversion on the change in the signal level due to the reset of the photodiode by the reset transistor. The detection device according to item 1, characterized in that. (Item 3) The AD converter starts the offset cancellation operation before the signal level is supplied to the AD converter. The detection device according to item 1 or 2, characterized in that. (Item 4) After a predetermined time has elapsed since the photodiode was last reset by the reset transistor, and before the signal level is supplied to the AD converter, the AD converter starts the offset cancellation operation. The detection device according to item 1 or 2, characterized in that. (Item 5) The readout circuit further includes a sample-and-hold circuit disposed between the signal line and the AD converter. The detection device according to item 1 or 2, characterized in that. (Item 6) The AD converter starts the offset cancellation operation before the signal level is supplied to the AD converter via the sample-and-hold circuit. The detection device according to item 5, characterized in that. (Item 7) After a predetermined time has elapsed since the photodiode was last reset by the reset transistor, and before the signal level is supplied to the AD converter via the sample-and-hold circuit, the AD converter starts the offset cancellation operation. The detection device according to item 5, characterized in that. (Item 8) The AD converter has a differential amplifier circuit having a first input node to which the signal level is applied, a second input node to which a ramp signal is applied, a first output node in phase with the first input node, and a second output node in phase with the second input node. A first capacitor disposed between the signal line and the first input node; A second capacitor disposed between the signal line and the second input node; A first switch that shorts the first input node and the second output node; A second switch that shorts the second input node and the first output node; The detection device according to any one of items 3 to 7, characterized by including the above. (Item 9) The offset cancellation operation is an operation of turning the first switch and the second switch into a non-conductive state after turning them into a conductive state. The detection device according to item 8, characterized by the above. (Item 10) The start of the offset cancellation operation is to turn the first switch and the second switch into a conductive state. The detection device according to item 9, characterized by the above. (Item 11) The end of the offset cancellation operation is to turn the first switch and the second switch from a conductive state to a non-conductive state. The detection device according to item 10, characterized by the above. (Item 12) The first input node is a non-inverting input node, The second input node is an inverting input node, The first output node is a non-inverting output node, The second output node is an inverting output node. The detection device according to any one of items 8 to 11, characterized by the above. (Item 13) The photodiode detects an electron beam. The detection device according to any one of items 1 to 12, characterized by the above. (Item 14) The readout circuit further includes a clip circuit that clips the voltage of the signal line. The detection device according to item 13, characterized by the above. (Item 15) The clip circuit clips the voltage of the signal line according to the voltage obtained by sampling and holding the voltage of the signal line. The detection device according to item 14, characterized in that. (Item 16) A pixel including a photodiode on which radiation is incident, an amplification transistor having a gate connected to an output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, A signal line connected to the pixel, A readout circuit for reading a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on a signal input from the pixel via the signal line. The AD converter includes a differential amplification circuit having an input node and an output node, a capacitive element having one terminal connected to the input node and the other terminal connected to the signal line, and a switch connected to the one terminal. During a period in which a first signal, which is a signal level corresponding to the amount of radiation received by the photodiode, is output to the one terminal, the switch transitions from an on state to an off state. During a period until the switch transitions from the off state to the next on state, a second signal, which is a signal level corresponding to the reset level of the gate, is output to the one terminal. The AD converter performs AD conversion during a period in which the second signal is output to the one terminal. The detection device, characterized in that. (Item 17) The detection device according to item 16, characterized in that the switch is a switch that connects the one terminal and the output node. (Item 18) The detection device according to item 16, characterized in that the switch is a switch that connects the one terminal and a node to which a power supply voltage is supplied. (Item 19) Comprising a plurality of the pixels arranged in a plurality of rows. After the selection transistor of the pixel arranged in the first row transitions from the off state to the on state, the switch transitions from the on state to the off state, In the period before the selection transistor transitions from the on state to the off state, after the reset transistor transitions from the off state to the on state, it transitions from the on state to the off state, and the detection device according to any one of items 16 to 18, characterized in that the AD conversion is performed. (Item 20) A radiation source that irradiates the imaging target with radiation, The detection device according to any one of items 1 to 19, A processing unit that processes an image detected using a plurality of pixels of the detection device, A detection system, characterized by comprising:

[0097] The invention is not limited to the above embodiments, and various changes and modifications are possible without departing from the spirit and scope of the invention. Therefore, claims are attached to disclose the scope of the invention.

Description of Reference Numerals

[0098] PD: Photodiode, M101: Reset transistor, M102: Amplification transistor, M103: Selection transistor, 1: Detection device, 10: Pixel array, 100: Pixel, 12: Signal line, 21: AD converter, 110: Readout circuit

Claims

1. A pixel including a photodiode, an amplification transistor having a gate connected to an output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor; A signal line connected to the pixel; A readout circuit for reading a signal from the pixel via the signal line, comprising: The readout circuit includes an AD converter that performs AD conversion on a signal input from the pixel via the signal line. The AD converter performs an offset cancellation operation of holding a signal level corresponding to a signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on a change in the signal level after the offset cancellation operation. A detection device characterized by the above.

2. After the first AD conversion, the AD converter performs a second AD conversion on a change in the signal level due to the reset of the photodiode by the reset transistor. The detection device according to claim 1, characterized by the above.

3. The AD converter starts the offset cancellation operation before the signal level is supplied to the AD converter. The detection device according to claim 1, characterized by the above.

4. The AD converter starts the offset cancellation operation after a predetermined time has elapsed since the photodiode was last reset by the reset transistor and before the signal level is supplied to the AD converter. The detection device according to claim 1, characterized by the above.

5. The readout circuit further includes a sample and hold circuit disposed between the signal line and the AD converter. The detection device according to claim 1, characterized by the above.

6. The AD converter starts the offset cancellation operation before the signal level is supplied to the AD converter via the sample and hold circuit. The detection device according to claim 5, characterized by the above.

7. The AD converter starts the offset cancellation operation after a predetermined time has elapsed since the photodiode was last reset by the reset transistor and before the signal level is supplied to the AD converter via the sample and hold circuit. The detection device according to claim 5, characterized by the above.

8. The AD converter A differential amplification circuit having a first input node to which the signal level is applied, a second input node to which a lamp signal is applied, a first output node in phase with the first input node, and a second output node in phase with the second input node; A first capacitor disposed between the signal line and the first input node; A second capacitor disposed between the signal line and the second input node; A first switch for short-circuiting the first input node and the second output node; A second switch for short-circuiting the second input node and the first output node; The detection device according to claim 3, comprising the above.

9. The offset cancellation operation is an operation of turning off the first switch and the second switch after turning them on. The detection device according to claim 8, characterized by the above.

10. The start of the offset cancellation operation is to turn on the first switch and the second switch. The detection device according to claim 9, characterized by the above.

11. The end of the offset cancellation operation is to turn the first switch and the second switch from the on state to the off state. The detection device according to claim 10, characterized by the above.

12. The first input node is a non-inverting input node; The second input node is an inverting input node; The first output node is a non-inverting output node; The second output node is an inverting output node. The detection device according to claim 8, characterized by the above.

13. The photodiode detects ionizing radiation. The detection device according to claim 1, characterized by the above.

14. The readout circuit further includes a clip circuit for clipping the voltage of the signal line. The detection device according to claim 13, characterized by the above.

15. The clip circuit clips the voltage of the signal line according to the voltage obtained by sampling and holding the voltage of the signal line. The detection device according to claim 14, characterized by the above.

16. A pixel including a photodiode irradiated with radiation, an amplification transistor having a gate connected to an output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor; A signal line connected to the pixel; A readout circuit for reading a signal from the pixel via the signal line. The readout circuit includes an analog-to-digital (AD) converter that performs AD conversion on a signal input from the pixel via the signal line. The AD converter includes a differential amplification circuit having an input node and an output node, a capacitive element having one terminal connected to the input node and the other terminal connected to the signal line, and a switch connected to the one terminal. During a period in which a first signal, which is a signal level corresponding to the amount of radiation received by the photodiode, is output to the one terminal, the switch transitions from an on state to an off state. During a period from when the switch is in the off state until the next on state, a second signal, which is a signal level corresponding to the reset level of the gate, is output to the one terminal. The AD converter performs AD conversion during a period in which the second signal is output to the one terminal. A detection device characterized by the above.

17. The detection device according to claim 16, wherein the switch is a switch that connects the one terminal and the output node.

18. The detection device according to claim 16, wherein the switch is a switch that connects the one terminal and a node to which a power supply voltage is supplied.

19. Comprising a plurality of the pixels arranged in a plurality of rows, after the selection transistor of the pixel arranged in the first row transitions from an off state to an on state, the switch transitions from an on state to an off state, During a period before the selection transistor transitions from an on state to an off state, after the reset transistor transitions from an off state to an on state and then transitions from an on state to an off state, the AD conversion is performed. The detection device according to claim 16, characterized by the above.

20. A radiation source that irradiates a radiation imaging target, The detection device according to any one of claims 1 to 19, A processing unit that processes an image detected using a plurality of pixels of the detection device, A detection system characterized by comprising the above.

Images