Vertical HEMT and manufacturing method for vertical HEMT

Abstract

To provide a vertical type high electron mobility transistor (HEMT) with reduced size, and a manufacturing method for the vertical type HEMT.SOLUTION: A HEMT 100 includes a drain contact 410, a nanowire layer 500 including at least one vertical type nanowire 510 and a supporting material 520 that surrounds the at least one vertical type nanowire 510 in a lateral direction, a hetero structure 600 disposed on the nanowire layer and including an AlGaN layer 610 and a GaN layer 620 that form a hetero junction together, at least one source contact 420a, 420b in contact with the hetero structure 600, and a gate contact 430 disposed over the at least one vertical type nanowire 510 and in contact with the hetero structure 600. The at least one vertical type nanowire 510 forms an electron transport channel between the drain contact and the hetero structure.SELECTED DRAWING: Figure 1a

Description

[Technical Field]

[0001] The present invention relates to vertical high electron mobility transistors, HEMTs, and methods for fabricating such transistors. In particular, the present invention relates to vertical HEMTs, meaning that the main current flow is directed vertically, or perpendicular to the surface. [Background technology]

[0002] A HEMT is a type of field-effect transistor that contains a heterojunction of materials with different bandgaps, such as GaN and AlGaN. The transistor orientation can be lateral or vertical, meaning that current flow between the transistor's source and drain contacts can be either perpendicular or parallel to the surface of the transistor or the substrate on which the transistor is based. In a vertical HEMT, the drain contact can be located at the bottom of the device, and the source contact can be located at the top. Transistor operation, i.e., whether current is conducted between the source and drain contacts, is controlled by the application of a voltage to the gate contact. In more traditional lateral HEMTs, current flows horizontally through the transistor, mediated primarily by a two-dimensional electron gas (2DEG) formed at the interface between the heterojunction of materials with different bandgaps. In vertical HEMTs, as the name suggests, current flow also includes a significant vertical component. The main vertical conducting portion of a vertical HEMT is often referred to as the vertical HEMT aperture. Vertical HEMTs generally allow for improved transistor area reduction, due in part to the potential for more effective use of the bottom / backside contacts. However, further improvements are needed to continue scaling vertical HEMTs, and new modes of HEMTs must be considered. Summary of the Invention [Problem to be solved by the invention]

[0003] The purpose of the present disclosure is to at least address the above concerns. [Means for solving the problem]

[0004] According to a first aspect, there is provided a vertical high electron mobility transistor (HEMT). The vertical HEMT comprises a drain contact. The vertical HEMT comprises a nanowire layer. The nanowire layer is disposed on the drain contact. The nanowire layer comprises at least one vertical nanowire. The nanowire layer comprises a support material laterally surrounding the at least one vertical nanowire. The vertical HEMT comprises a heterostructure disposed on the nanowire layer. The heterostructure comprises an AlGaN layer and a GaN layer that together form a heterojunction. The vertical HEMT comprises at least one source contact in contact with the heterostructure. The vertical HEMT comprises a gate contact in contact with the heterostructure. The gate contact is disposed above the at least one vertical nanowire. The at least one vertical nanowire forms an electron transport channel between the drain contact and the heterostructure.

[0005] A layer or structure disposed on another layer or structure should be understood as being located substantially above the other layer or structure when viewed from a side / cross-sectional view of the device with the substrate at the bottom of the figure. A layer or structure may or may not be in direct contact with the other layer or structure, so long as it is substantially above it. However, this should not be construed as limiting two layers or structures from being vertically overlaid on each other when viewed from the same side / cross-sectional view. Directional terms such as vertical and horizontal should be understood in this same context.

[0006] The term heterostructure should be understood as a single monolithic structure consisting essentially of two different structures with a well-defined interface / transition between the two.

[0007] The inventors have recognized that further scaling of vertical HEMTs may be possible by utilizing vertical nanowire structures as the vertical HEMT aperture. In the extreme case, a truly ultra-small HEMT can be created by using just a single nanowire as the electron transport channel.

[0008] Furthermore, vertical nanowires should be considered beneficial in vertical HEMTs due to their substantially one-dimensional electron transport properties. This feature may be due to the material structure and the way it is formed into nanowires, and should not be interpreted as a similar dimensional structure of bulk material of the same or similar elemental composition.

[0009] Nanowires can be characterized by significantly fewer material defects compared to bulk materials, further adding to the benefits of their incorporation: fewer defects generally result in improved electrical conduction properties.

[0010] Vertical nanowires may also be less complex to fabricate than high-quality apertures on a similar scale in bulk material because the nanowires are essentially self-aligned during epitaxial formation.

[0011] Gallium nitride, GaN-based semiconductors, i.e., compounds containing (but not exclusively including) gallium and nitrogen, offer many advantages over silicon. Electronic devices such as HEMTs and vertical HEMTs offer promising candidates to replace many silicon-based devices.

[0012] GaN-based HEMTs may offer faster switching speeds, increased electron mobility, lower resistance, larger breakdown voltage, etc. Compared to silicon-based transistors, GaN-based devices may offer lower on-state resistance and lower switching losses when used as power switching transistors for voltage converter applications.

[0013] Furthermore, GaN can exhibit ballistic transport at room temperature, especially when the GaN is in the form of one-dimensional structures such as nanowires. Ballistic transport can be attributed to GaN's high optical phonon energy, which can be approximately four times higher than that of other III-V semiconductors. Ballistic transport and / or high optical phonon energy can result in high electron mobility and lower on-resistance, Rds(on), which can be beneficial for power chips. Ballistic transport in GaN is discussed by Matioli et al. in "Room-temperature ballistic transport in III-nitride heterostructures," Nano Letters, (2015) 15(2), pp. 1070-1075.

[0014] The at least one vertical nanowire may be in direct contact with the drain contact at a first end of the at least one vertical nanowire and in direct contact with the heterostructure at a second end of the at least one vertical nanowire.

[0015] The material of one vertical nanowire can be different from the support material.

[0016] The material difference between the at least one vertical nanowire and the support material allows the support material to provide a current blocking layer while the at least one vertical nanowire establishes an electron transport channel. This creates the possibility of in situ growth and efficient fabrication of a key feature of HEMTs. The structure of the support layer surrounding the at least one nanowire may eliminate the need for cumbersome fabrication methods such as ion implantation.

[0017] At least one vertical nanowire can include GaN.

[0018] GaN nanowires generally form predictably with a wurtzite crystal structure and can form good one-dimensional current-carrying channels.

[0019] At least one vertical nanowire can comprise n-doped GaN, and the support material comprises p-doped GaN.

[0020] Thus, the nanowire layer can be formed using at least one vertical nanowire and a support material having substantially the same lattice constant, which can result in reduced defects and improved structural integrity of the vertical HEMT. The different doped materials can further ensure that the support layer acts as a current blocking layer around the at least one vertical nanowire.

[0021] The support material may be configured to be a current blocking layer.

[0022] The term current blocking layer should be understood as a layer that prevents current from exiting the electron transport channel. By acting as a current blocking layer, the support material may reduce leakage current to / from the at least one vertical nanowire electron transport channel, which may result in reduced losses and more efficient operation of the transistor.

[0023] At least one vertical nanowire may be laterally aligned with the gate contact.

[0024] By laterally aligned, it is understood that at least one vertical nanowire at least overlaps the area of the gate contact when viewed in a top view.

[0025] The gate may form a 2DEG at the heterojunction interface from the source contact to at least one vertical nanowire. For this reason, it may be more efficient to place the gate laterally aligned with the gate contact.

[0026] The length of the at least one vertical nanowire may be in the range of 50 nm to 500 nm, preferably in the range of 150 nm to 250 nm.

[0027] Shorter vertical nanowires may correspond to thinner material overall, and vice versa. Thinner material may generally result in a thinner vertical HEMT, requiring less material to fabricate. Thicker material may help space the source and drain contacts further apart, improving high-voltage performance by reducing the risk of breakdown current completely bypassing at least one vertical nanowire and heterojunction.

[0028] In general, this can be an advantage of vertical HEMTs over lateral HEMTs due to the inherent isolation of the source and drain contacts compared to when both contacts are located on the same side of the device and are laterally closely spaced.

[0029] The nanowire layer can include a plurality of vertical nanowires.

[0030] Several additional vertical nanowires can be placed parallel to at least one vertical nanowire. More nanowires can provide options for modular device design. By adding more nanowires, the potential current density through the vertical HEMT can be increased incrementally due to the increase in the total aperture cross-sectional area. Using multiple nanowires can be more beneficial than using a single bulk material aperture of the same total cross-sectional area due to the improved conduction properties of the nanowires.

[0031] A GaN layer may be disposed on the AlGaN layer.

[0032] Alternatively, an AlGaN layer may be disposed on a GaN layer, as long as both layers form a common heterojunction.

[0033] According to a second aspect, a method for fabricating a vertical HEMT is provided. The method includes providing a base layer, the base layer comprising a substrate. The method includes forming a nanowire layer on the base layer. The nanowire layer includes at least one vertical nanowire and a support material laterally surrounding the at least one vertical nanowire. The method includes depositing a heterostructure on the nanowire layer in contact with the at least one vertical nanowire. The method includes forming at least one source contact in contact with the heterostructure. The method includes forming a gate contact in contact with the heterostructure. The method includes forming a drain contact in contact with the at least one vertical nanowire.

[0034] The term forming may be understood as forming the specified layers and structures by any applicable method, such as deposition, epitaxial growth, etching, or integrated lithography-based pattern transfer processes, to name just a few.

[0035] The method provides an efficient, low complexity / easily available method for forming a vertical HEMT according to the first aspect, so that similar advantages to the first aspect may also be applied to the second aspect.

[0036] The substrate may be a silicon substrate, and the base layer may comprise an AlN layer disposed on the substrate.

[0037] Silicon substrates are inexpensive and readily available. Vertical nanowires of lattice-mismatched materials to silicon, such as GaN, can be grown directly on the silicon substrate, resulting in better material quality than bulk GaN materials. An AlN layer can act as a transition layer between the silicon substrate and the nanowire layer.

[0038] The method may further include separating the substrate from the AlN layer. The method may further include forming a trench in the AlN layer. The method may further include exposing the at least one vertical nanowire. The step of forming a drain contact may include forming a drain contact in the trench.

[0039] Such a method can be performed using existing equipment and provides access for forming the drain contact below the nanowire layer.

[0040] The method may further include bonding the substrate or another substrate to the AlN layer and / or the drain contact. Once the drain contact is formed, the substrate or another substrate may be rebonded to the composite structure. Thus, closer co-integration with devices, structures, and circuits on the substrate may be achieved.

[0041] The step of depositing the heterostructure can include depositing an AlGaN layer. The step of depositing the heterostructure can include depositing a GaN layer. The AlGaN layer and the GaN layer can together form a heterojunction.

[0042] It should be understood that it may not be necessary to rebond the substrate or another substrate to the AlN layer and / or the drain contact. Alternatively, the vertical HEMT may remain without a substrate bonded to the AlN layer and / or without a substrate bonded to the drain contact. As one example, the vertical HEMT may remain without a substrate. As another example, a substrate with a trench may be bonded to the AlN layer, and the trench may be the same size as and aligned with the drain contact so that the drain contact is not bonded to the substrate. As another example, a substrate with a trench may be bonded to the AlN layer, and the trench may be similar in size to and aligned with the drain contact, e.g., 1 to 5 times the size of the drain contact, so that the drain contact and surrounding area are not bonded to the substrate. In the above example, the trench in the substrate may be replaced with a hole through the substrate.

[0043] The absence of a substrate at and / or near the drain contact may improve the operating voltage capability of the vertical HEMT. Such devices may potentially operate at over 1000 V. The absence of a substrate at and / or near the drain contact may ensure that there are no charge traps at and / or near the drain contact. As a result, there are no charge traps near the gate contact. Additionally, the AlN layer may be a layer of sputtered AlN. Such a layer may further improve the operating voltage capability of the vertical HEMT. Sputtered AlN may have fewer charge traps than epitaxially grown AlN.

[0044] In general, all terms used in the claims should be interpreted according to their ordinary meaning in the art unless otherwise expressly defined herein. All references to "a / an / the [element, device, component, means, step, etc.]" should be interpreted broadly as referring to at least one instance of the element, device, component, means, step, etc., unless otherwise specified. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless otherwise specified.

[0045] Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the scope of the invention will become apparent to those skilled in the art from this detailed description.

[0046] Therefore, it is to be understood that this invention is not limited to the specific components of the devices or acts of the methods described, as such devices and methods may vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.

[0047] It should be noted that, as used in this specification and the appended claims, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of an element, unless the context clearly dictates otherwise. Thus, for example, reference to "a unit" or "the unit" may include several devices, etc. Furthermore, the words "comprise," "include," "contain," and similar expressions do not exclude other elements or steps.

[0048] These and other aspects of the present invention will now be described in more detail with reference to the accompanying figures, which should not be considered limiting, but instead should be considered for purposes of illustration and understanding.

[0049] As shown in the figures, the sizes of layers and regions may be exaggerated for illustrative purposes and, therefore, are provided to show the general structure. Like reference numerals refer to like elements throughout. [Brief explanation of the drawings]

[0050] [Figure 1a] A side view of a vertical HEMT is shown. [Figure 1b] A side view of a vertical HEMT is shown. [Figure 2] 1 shows a flowchart of a method for manufacturing a vertical HEMT. DETAILED DESCRIPTION OF THE INVENTION

[0051] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which presently preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness, and to fully convey the scope of the invention to those skilled in the art.

[0052] 1a shows a vertical HEMT 100. The vertical HEMT 100 includes a drain contact 410.

[0053] The drain contact 410 may be disposed on the substrate 310 as shown. The substrate 310 may be a silicon, Si, substrate. <111> may have Miller indices of

[0054] The drain contact 410 may also be laterally surrounded by an AlN layer 320 .

[0055] The vertical HEMT 100 comprises a nanowire layer 500 disposed on the drain contact 410. The nanowire layer 500 may comprise at least one vertical nanowire 510 and a support material 520 laterally surrounding the at least one vertical nanowire 510.

[0056] At least one vertical nanowire 510 forms an electron transport channel between the drain contact 410 and the heterostructure 600 .

[0057] At least one vertical nanowire 510 may have a first end 511 and a second end 512 at two opposing vertical boundaries of the vertical nanowire. The first end 511 may be in direct contact with the drain contact 410. The second end 512 may be in direct contact with the heterostructure 600.

[0058] At least one vertical nanowire 510 may be laterally aligned with the gate contact 430, as shown in the case of FIG. 1a.

[0059] The length L of the at least one vertical nanowire 510 may be in the range of 50 nm to 500 nm, preferably in the range of 150 nm to 250 nm.

[0060] The at least one vertical nanowire 510 may have a hexagonal or circular radial cross section. The at least one vertical nanowire 510 may have a diameter in the range of 10 to 500 nm due to radial density of state confinement. The diameter of the at least one vertical nanowire 510 may preferably be in the range of 10 to 100 nm. The diameter may be fixed along the length of the at least one nanowire 510. The diameter, and indeed the radial cross-sectional shape, may also vary along the length of the at least one nanowire 510.

[0061] At least one vertical nanowire 510 can include GaN.

[0062] The material of the at least one vertical nanowire 510 can be different from the support material 520 .

[0063] At least one vertical nanowire 510 may comprise n-doped GaN. The GaN may be n-doped by doping with C or Si impurity atoms. The support material 520 may comprise p-doped GaN. The GaN may be p-doped by doping with Mg impurity atoms.

[0064] The support material 520 may be configured as a current blocking layer.

[0065] The nanowire layer 500 may comprise a plurality of vertical nanowires 510. The plurality of vertical nanowires 510 may be laterally arranged in a square array or a hexagonal array.

[0066] The vertical HEMT 100 comprises a heterostructure 600 disposed on the nanowire layer. The heterostructure 600 may comprise an AlGaN layer 610 and a GaN layer 620 that together form a heterojunction.

[0067] A GaN layer 620 may be disposed on the AlGaN layer 610 .

[0068] The GaN layer 620 can comprise or consist essentially of GaN. The AlGaN layer 610 can comprise or consist essentially of AlGaN. AlGaN can be characterized by many different elemental composition ratios. Generally, AlGaN is a thin film of Al x Ga 1-x N, where 0 <x<1である。

[0069] The vertical HEMT 100 includes at least one source contact 420a, 420b in contact with the heterostructure 600. However, the at least one source contact 420a, 420b should be laterally offset from the at least one vertical nanowire 510.

[0070] The vertical HEMT 100 may include multiple source contacts 420 a, 420 b, as shown in FIG. 1 a. Alternatively, the illustrated configuration may be understood as having multiple source contact fingers 420 a, 420 b that are essentially unitary and correspond to the same electrical node. Positioning the multiple source contact fingers 420 a, 420 b equidistant laterally about the center of the at least one vertical nanowire 510 may be preferable for more uniform deployment across the heterostructure 600 and the at least one nanowire 510.

[0071] For the same reason, the source contacts 420 a , 420 b may alternatively be circular in shape centered on the extended centerline of the at least one vertical nanowire 510 .

[0072] When having multiple vertical nanowires 510, the source contacts 420a, 420b can be configured as a grid where replaceable grid elements are consistent across the grid in how they correspond to each individual vertical nanowire 510. For example, the closest distance between any point on the vertical nanowire 510 and any point on the source contacts 420a, 420b should preferably be equal for each individual vertical nanowire 510.

[0073] The vertical HEMT 100 comprises a gate contact 430 disposed above at least one vertical nanowire 510 and in contact with the heterostructure 600 .

[0074] The gate contact 430, the at least one source contact 420a, 420b, and the drain contact 410 may comprise or consist essentially of a metallic material. Examples of metallic materials available for use alone or in alloys / compounds may include Cu, Al, Pd, Au, Ag, Ni, Ti, and W.

[0075] Referring to FIG. 1a, the operation of a vertical HEMT can be described as the gate contact 430 receiving a voltage. The voltage can be positive. If the voltage is large enough, a 2DEG can form at the heterojunction, i.e., the interface between the AlGaN layer 610 and the GaN layer 620, opening the transistor to conduct current between the source contacts 420a, 420b and the drain contact 410 through the at least one nanowire 510. The current path can follow the heterojunction until it approaches the portion of the heterojunction closest to the at least one vertical nanowire 510. The current then transitions to the at least one vertical nanowire 510 and continues to flow toward the drain contact 430. The interfaces between different structures and layers in the current path can be optimized to feature substantially ohmic conduction across each interface.

[0076] 1b shows a slightly modified version of the vertical HEMT 100 that also includes a top oxide layer 700. Such an oxide layer 700 may advantageously reduce leakage current between, for example, the gate contact 430 and the source contacts 420a, 420b, and may better insulate and passivate the vertical HEMT.

[0077] 1b also shows an example of a nanowire layer 500 comprising multiple vertical nanowires 510. In the figure, two similar nanowires are shown parallel to each other. In this case, the gate contact 430 is aligned with the center point between two vertical nanowires 510 instead of at least one vertical nanowire as shown in FIG. 1a.

[0078] 2 shows a flowchart of a method for manufacturing a vertical HEMT 100. Optional steps are indicated in the flowchart by dashed boxes.

[0079] The method includes S2020 providing a base layer 300, the base layer 300 comprising a substrate 310.

[0080] The substrate 310 may be a silicon substrate. The base layer 300 may include an AlN layer 320 disposed on the substrate 310. The AlN layer 320 may be formed on the substrate 310 by a suitable deposition technique, such as sputtering or chemical vapor deposition (CVD). Sputtered AlN may be beneficial because it may provide a low density of charge traps, for example, at the interface between the AlN layer 320 and the substrate.

[0081] The method includes S2030 forming a nanowire layer 500 on the base layer 300. The nanowire layer 500 includes at least one vertical nanowire 510 and a support material 520 laterally surrounding the at least one vertical nanowire 510.

[0082] The at least one vertical nanowire 510 may be formed by selective area growth epitaxial techniques, for example using metal organic chemical vapor deposition, MOVPE, or by selectively etching the vertical nanowire 510 from a bulk layer of semiconductor material, for example by plasma etching using chloride chemistry Ar / Cl. The step of forming the at least one vertical nanowire 510 may include defining the intended position and geometry of the at least one nanowire 510 using lithography-based pattern transfer techniques.

[0083] The support material 520 may be formed by a deposition technique such as MOVPE or CVD, and may surround at least one vertical nanowire 510 or fill the spaces between multiple nanowires 510 if multiple nanowires 510 are present.

[0084] The method includes S2040 depositing a heterostructure 600 on the nanowire layer 500 in contact with at least one vertical nanowire 510.

[0085] The heterostructure 600 can be deposited by a similar technique to the at least one vertical nanowire 510, namely MOVPE.

[0086] The step S2040 of depositing the heterostructure 600 may include depositing an AlGaN layer 610 and depositing a GaN layer 620. The AlGaN layer 610 and the GaN layer 620 may together form a heterojunction.

[0087] A first layer of a heterostructure 600, for example, an AlGaN layer 610, can be deposited on the nanowire layer 500. A second layer of the heterostructure, in this case a GaN layer 620, can then be deposited on the AlGaN layer 610.

[0088] The method includes S2050 forming at least one source contact 420a, 420b in contact with the heterostructure 600.

[0089] The source contacts 420a, 420b can be formed by deposition techniques such as evaporation or sputtering. The source contacts 420a, 420b can be formed vertically through the heterostructure 600 and onto the nanowire layer 500, as shown in Figure 1a. This result can be achieved by pattern transfer and selective area etching through the heterostructure prior to deposition of the source contacts 420a, 420b.

[0090] The method includes S2060 forming a gate contact 430 in contact with the heterostructure. The gate contact 430 may be formed using deposition techniques similar to those proposed for the source contacts 410a, 410b. The gate contact 430 may be formed on the heterostructure 600 as shown in FIG. 1a. In FIG. 1b, where an oxide layer 700 is present, etching may first be used to create a trench for the gate contact 430 through the oxide layer.

[0091] The method may further include S3020 separating the substrate 310 from the AlN layer 320 using a substrate removal or separation technique.

[0092] The method may further include S3030 forming a trench in the AlN layer 320 to expose at least one vertical nanowire 510. The step of forming the drain contact 410, in this case, may include forming the drain contact 410 in the trench. The trench may function as a mold for the drain contact 410. Thus, the trench shares its geometric shape with the drain contact 410 of FIGS. 1a-1b.

[0093] The trenches may be formed by selective area etching through the AlN layer 320 from below, as can be seen in the figure.

[0094] The method includes S2070 forming a drain contact 410 in contact with the at least one vertical nanowire 510. The drain contact 410 can be formed using deposition techniques similar to those proposed for the source contacts 410a, 410b and the gate contact 430.

[0095] Formation of the drain contact 410 may also include the aforementioned etching through the substrate 310 from the bottom. The trench may be selectively etched through the oxide layer on the bottom surface of the substrate. The remaining bottom substrate oxide layer may then be used as a mask layer for a dry reactive ion etch of the substrate 310.

[0096] The method may further include S4020, bonding the substrate 310 or another substrate to the AlN layer 320 and / or the drain contact 410. The bonding step S4020 may involve bonding a previously used substrate 310 that was separated from the remainder of the structure in step S3020, or it may involve bonding an entirely different substrate. If precise alignment is desired in the bonding, an automated stepper machine may be employed to assist during the step. The bonding step S4020 may involve bonding a substrate having a trench to the AlN layer. The trench may be the same size as and aligned with the drain contact 410. Thus, the substrate may be bonded to the AlN layer but not to the drain contact 410 because the trench in the substrate may prevent contact between the substrate and the drain contact 410. Alternatively, the trench may be similar in size to and aligned with the drain contact 410, e.g., 1 to 5 times the size of the drain contact 410. Thus, the substrate may be bonded to the AlN layer, but may not be bonded to the AlN layer in the area surrounding the drain contact 410 .

[0097] Additionally, variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A vertical high electron mobility transistor, HEMT (100), comprising: a drain contact (410); a nanowire layer (500) disposed on the drain contact (410) and comprising at least one vertical nanowire (510) that is a wire having a diameter in the range of 10 to 500 nm, and a support material (520) that laterally surrounds the at least one vertical nanowire (510); a hetero-structure (600) disposed on the nanowire layer and comprising an AlGaN layer (610) and a GaN layer (620) that together form a hetero-junction; at least one source contact (420a, 420b) in contact with the hetero-structure (600), wherein the at least one source contact (420a, 420b) is laterally offset from the at least one vertical nanowire (510); a gate contact (430) disposed above the at least one vertical nanowire (510) and in contact with the hetero-structure (600); wherein: the at least one vertical nanowire (510) forms an electron transport channel between the drain contact and the hetero-structure; a vertical high electron mobility transistor, HEMT (100).

2. The vertical HEMT according to claim 1, wherein the at least one vertical nanowire (510) is in direct contact with the drain contact (410) at a first end (511) of the at least one vertical nanowire (510) and is in direct contact with the hetero-structure (600) at a second end (512) of the at least one vertical nanowire (510). The vertical HEMT according to claim 1.

3. The vertical HEMT according to claim 1 or 2, wherein the material of the at least one vertical nanowire (510) is different from the support material (520). The vertical HEMT according to claim 1 or 2.

4. The vertical HEMT according to any one of claims 1 to 3, wherein the at least one vertical nanowire (510) comprises GaN. The vertical HEMT according to any one of claims 1 to 3.

5. The vertical HEMT according to claim 1 or 2, wherein the at least one vertical nanowire (510) comprises n-doped GaN and the support material (520) comprises p-doped GaN. The vertical HEMT according to claim 1 or 2.

6. The vertical HEMT according to claim 1 or 2, wherein the support material (520) is configured to be a current blocking layer. The vertical HEMT according to any one of claims 1 to 5.

7. The at least one vertical nanowire (510) is laterally aligned with the gate contact (430). The vertical HEMT according to any one of claims 1 to 6.

8. The length (L) of the at least one vertical nanowire (510) is in the range of 50 nm to 500 nm, preferably in the range of 150 nm to 250 nm. The vertical HEMT according to any one of claims 1 to 7.

9. The nanowire layer (500) includes a plurality of vertical nanowires (510). The vertical HEMT according to any one of claims 1 to 8.

10. The GaN layer (620) is disposed on the AlGaN layer (610). The vertical HEMT according to any one of claims 1 to 9.

11. A method for manufacturing a vertical HEMT (100), the method comprising: Providing a base layer (300) (S2020), the base layer (300) comprising a substrate (310); Forming a nanowire layer (500) on the base layer (300) (S2030), the nanowire layer (500) comprising at least one vertical nanowire (510) having a diameter in the range of 10 to 500 nm and a support material (520) laterally surrounding the at least one vertical nanowire (510); Depositing a heterostructure (600) in contact with the at least one vertical nanowire (510) on the nanowire layer (500) (S2040), the heterostructure (600) comprising an AlGaN layer (610) and a GaN layer (620) that together form a heterojunction; Forming at least one source contact (420a, 420b) in contact with the heterostructure (600) (S2050), the at least one source contact (420a, 420b) being laterally offset from the at least one vertical nanowire (510); Forming a gate contact (430) in contact with the heterostructure and disposed above the at least one vertical nanowire (510). forming a drain contact (410) in contact with the at least one vertical nanowire (510) (S2070); comprising; wherein the at least one vertical nanowire (510) forms an electron transport channel between the drain contact and the heterostructure; method.

12. wherein the substrate (310) is a silicon substrate, and the base layer (300) comprises an AlN layer (320) disposed on the substrate (310); The method according to claim 11.

13. The method further comprises: separating the substrate (310) from the AlN layer (320) (S3020); forming a trench in the AlN layer (320) (S3030) to expose the at least one vertical nanowire (510); further comprising; wherein the step of forming the drain contact (410) comprises: forming the drain contact (410) in the trench; The method according to claim 12.

14. The method further comprises: bonding the substrate (310) or another substrate to the AlN layer (320) and / or the drain contact (410) (S4020); The method according to claim 13.

15. wherein the step of depositing the heterostructure (600) (S2040) comprises: depositing an AlGaN layer (610); depositing a GaN layer (620); comprising; wherein the AlGaN layer (610) and the GaN layer (620) together form a heterojunction; The method according to any one of claims 11 to 14.

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