Display device

Abstract

To provide a display device capable of performing viewing angle control.SOLUTION: A display device includes: a display panel that includes a display area, and a non-display area disposed so as to surround the display area, and includes multiple pixels and multiple selection signal generation sections disposed on the display area; and a timing controller for controlling the display panel. Each of the multiple pixels includes a first light-emitting element, a first optical member for refracting light from the first light-emitting element, a second light-emitting element for emitting the same color as that of the first light-emitting element, and a second optical member that refracts light from the second light-emitting element and is in a shape different from that of the first optical member. Each of the multiple selection signal generation sections performs control such that either one of the first light-emitting element and the second light-emitting element included in at least one corresponding pixel from among the multiple pixels emits light.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This specification relates to a display device, and more particularly, to a display device capable of controlling a viewing angle.

Background Art

[0002] As technology in modern society develops, display devices are widely used to provide information to users. Display devices include not only electro-optical panels that simply transmit visual information in one direction, but also various electronic devices that require higher technologies to check user input and provide information corresponding to the confirmed input.

[0003] For example, a display device can be included in a vehicle to provide various information to the driver and passengers of the vehicle. However, the display device in the vehicle needs to appropriately display content so as not to interfere with the operation of the vehicle. For example, the display device needs to limit the display of content that can reduce the driver's concentration during vehicle operation.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by this specification is to provide a display device that can divide a display panel into regions and independently control the driving mode of each region.

[0005] Another problem to be solved by this specification is to provide a display device that can minimize the number of wirings and pixel layout arranged on the display panel.

[0006] Another problem to be solved by this specification is to provide a display device capable of realizing high resolution.

[0007] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned may be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0008] The display device according to an embodiment of the present specification includes a display area and a non-display area arranged so as to surround the display area, and may include a display panel including a plurality of pixels and a plurality of selection signal generation units arranged on the display area, and a timing controller for controlling the display panel. Each of the plurality of pixels may include a first light-emitting element, a first optical member for refracting light from the first light-emitting element, a second light-emitting element that emits the same color as the first light-emitting element, and a second optical member for refracting light from the second light-emitting element and having a shape different from that of the first optical member. Each of the plurality of selection signal generation units can control at least one corresponding pixel among the plurality of pixels so that either the first light-emitting element or the second light-emitting element included therein emits light.

[0009] Specific matters of other embodiments are included in the detailed description and the drawings.

Advantages of the Invention

[0010] The embodiments of the present specification can divide the display panel into regions and independently control the driving modes of the respective regions, so as to drive in a first mode that provides content with a wide viewing angle or in a second mode that provides content with a narrow viewing angle for each region.

[0011] The embodiments of the present specification can divide the display panel into regions and independently control the driving modes of the respective regions without increasing the number of wirings and the pixel layout arranged on the display panel, so that the display panel can be configured with high resolution.

[0012] The effects according to the embodiments of the present specification are not limited by the content illustrated above, and more various effects are included in the present specification.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3a

Figure 3b

Figure 3c

Figure 3d

Figure 3e

Figure 4

Figure 5a

Figure 5b

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10a

Figure 10b

Figure 10c

Figure 10d

Figure 11

Figure 12

Figure 13

Figure 14a

Figure 14b

Figure 14c

Figure 14d

Figure 15

Figure 16

Figure 17a

Figure 17b

Figure 17c

Figure 17d

Embodiments for Carrying Out the Invention

[0014] The advantages and features of this specification, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but is embodied in various different forms. Merely, these embodiments are provided so that the disclosure of this specification becomes complete and that those with ordinary knowledge in the technical field to which this specification pertains are fully informed of the scope of this specification.

[0015] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, and thus this specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, in explaining this specification, when it is determined that a detailed description of related known technologies may obscure the gist of this specification, the detailed description thereof is omitted. When terms such as "including", "having", "being made" as referred to in this specification are used, other parts may be added as long as "only" is not used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0016] In interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0017] In the case of an explanation regarding a positional relationship, for example, when a positional relationship between two parts is described such as "on ~", "above ~", "below ~", "next to ~", etc., one or more other parts may be located between the two parts as long as "immediately" or "directly" is not used.

[0018] An element or layer referred to as "on" another element or layer includes both the case where it is immediately above the other element and the case where another layer or another element is interposed in the middle.

[0019] Also, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of this specification.

[0020] Throughout the specification, the same reference numerals refer to the same components.

[0021] The areas and thicknesses of the respective components shown in the drawings are shown for convenience of explanation, and this specification is not necessarily limited to the areas and thicknesses of the components shown.

[0022] The respective features of the various embodiments of this specification can be partially or wholly combined or combined with each other, enabling various technical linkages and drives, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0023] In the following, this specification will be described with reference to the drawings.

[0024] FIG. 1 is an exemplary view of a display device according to an embodiment of this specification.

[0025] Referring to FIG. 1, the display device 100 can be disposed on at least a part of the dashboard of a vehicle. The dashboard of the vehicle can include a configuration disposed in front of the front seats (e.g., driver's seat, passenger seat) of the vehicle. For example, the dashboard of the vehicle can have input configurations for operating various functions inside the vehicle (e.g., air conditioner, audio system, navigation system).

[0026] The display device 100 is disposed on the dashboard of the vehicle and can operate as an input unit for operating at least a part of various functions of the vehicle. The display device 100 can provide various information related to the vehicle, such as the driving information of the vehicle (e.g., current speed of the vehicle, remaining fuel amount, driving distance), information on vehicle parts (e.g., damage degree of vehicle tires), etc.

[0027] The display device 100 can be disposed so as to cross the driver's seat and the passenger seat disposed in front of the vehicle. The users of the display device 100 can include the driver of the vehicle and passengers boarding the passenger seat. Any of the driver and passengers of the vehicle can use the display device 100.

[0028] The display device 100 shown in FIG. 1 may show only a part thereof. The display device 100 shown in FIG. 1 may show a display panel among various configurations included in the display device 100. Specifically, for example, the display device 100 shown in FIG. 1 may show at least a part of the display area and the non-display area of the display panel. Configurations other than the part shown in FIG. 1 among the configurations of the display device 100 may be mounted inside the vehicle (or at least a part thereof).

[0029] FIG. 2 is a functional block diagram of a display device according to an embodiment of the present specification.

[0030] An electroluminescent display device may be applied to the display device according to an embodiment of the present specification. As the electroluminescent display device, an organic light emitting diode (OLED) display device, a quantum dot light emitting diode (QLED) display device, or an inorganic light emitting diode (ILED) display device may be used.

[0031] Referring to FIG. 2, the display device 100 may include a display panel PN, a data driving circuit DD, a gate driving circuit GD, and a timing controller TD.

[0032] The display panel PN can generate an image provided to the user. For example, the display panel PN can generate and display an image provided to the user through a plurality of pixels PX in which pixel circuits are respectively arranged.

[0033] The data driving circuit DD, the gate driving circuit GD, and the timing controller TD can provide signals for the operation of each pixel PX through signal wirings. For example, the signal wirings for providing signals for the operation of each pixel PX may include a plurality of data wirings DL and a plurality of gate wirings GL.

[0034] The plurality of data wirings DL are arranged in the column direction and can include a plurality of wirings connected to the pixels PX arranged in one column direction. The plurality of gate wirings GL are arranged in the row direction and can include a plurality of wirings connected to the pixels PX arranged in one row direction.

[0035] In some cases, the display device 100 can further include a power supply unit. In such a case, signals for the operation of the pixels PX can be provided through the power supply wiring connecting the power supply unit and the display panel PN. According to an embodiment, the power supply unit can supply power to the data driving circuit DD and the gate driving circuit GD. The data driving circuit DD and the gate driving circuit GD can be driven based on the power supplied from the power supply unit.

[0036] As an example, the data driving circuit DD can apply data signals to each pixel PX through a plurality of data wirings DL, the gate driving circuit GD can apply gate signals to each pixel PX through a plurality of gate wirings GL, and the power supply unit can supply a power supply voltage to each pixel PX through a power supply voltage supply wiring.

[0037] The timing controller TD can control the data driving circuit DD and the gate driving circuit GD. For example, the timing controller TD can re-align the digital video data input from the outside to match the resolution of the display panel PN and supply it to the data driving circuit DD.

[0038] The data driving circuit DD can convert the digital video data input from the timing controller TD based on a data control signal into an analog data voltage and supply it to a plurality of data wirings DL.

[0039] The gate driving circuit GD can generate a scan signal and a light emission signal based on a gate control signal. For example, the gate driving circuit GD can include a scan driving unit and a light emission signal driving unit. The scan driving unit can generate a scan signal in a row sequential manner to drive at least one or more scan wirings connected to each row of pixels and supply the scan signal to the scan wirings. The light emission signal driving unit can generate a light emission signal in a row sequential manner to drive at least one or more light emission signal wirings connected to each row of pixels and supply the light emission signal to the light emission signal wirings.

[0040] According to an embodiment, the gate driving circuit GD can be arranged on the display panel PN in a GIP (Gate-driver In Panel) manner. For example, the gate driving circuit GD can be divided into a plurality of parts and arranged on at least two sides of the display panel PN respectively.

[0041] The display panel PN can include a display area and a non-display area surrounding the display area.

[0042] The display area of the display panel PN can include a plurality of pixels PX arranged in a row direction and a column direction. For example, the plurality of pixels PX can be arranged in an area where a plurality of data wirings DL and a plurality of gate wirings GL intersect.

[0043] One pixel PX can include a plurality of sub-pixels that emit different colors. For example, one pixel PX can use three sub-pixels to represent blue, red, and green. However, it is not limited thereto, and in some cases, the pixel PX can further include a sub-pixel for further representing a specific color, for example, white.

[0044] The area representing blue in the pixel PX can be referred to as a blue sub-pixel, the area representing red can be referred to as a red sub-pixel, and the area representing green can be referred to as a green sub-pixel.

[0045] Each of the plurality of pixels PX can include a first light emitting element and a second light emitting element that emit the same color.

[0046] Each of the plurality of pixels PX may include a first optical member that refracts light from the first light-emitting element in a specific direction and a second optical member that refracts light from the second light-emitting element in a specific direction. For example, the first optical member and the second optical member may each be configured as a lens, but the embodiments of this specification are not limited thereto.

[0047] For example, the first optical member may be disposed in an optical region that provides light to a first range to form a first viewing angle, and the second optical member may be disposed in an optical region that provides light to a second range to form a second viewing angle. The first range may correspond to a wider range than the second range. Therefore, the first optical member and the second optical member can limit the viewing angle of each of the plurality of pixels PX.

[0048] A detailed description of the first optical member and the second optical member will be described later with reference to FIGS. 6 and 7.

[0049] The non-display area may be arranged along the periphery of the display area. Various components for driving the pixel circuit arranged in the pixel PX may be arranged in the non-display area. For example, at least a part of the gate drive circuit GD may be arranged in the non-display area. The non-display area may be referred to as a bezel area.

[0050] When the display panel PN is used in the vehicle described with reference to FIG. 1, it is necessary to limit the viewing field of at least a part of the area of the display panel PN according to the user's request. For example, in the case of a video displayed in an area that provides entertainment functions and seat information for a passenger sitting in the passenger seat in the display area of the display panel PN, it may interfere with the driver's vehicle operation, so it may be necessary to limit the viewing field of the video displayed in the corresponding area according to the user's request.

[0051] Therefore, each pixel PX included in the display panel PN can be driven in a first mode or a second mode according to a driving mode. For example, when the pixel PX is driven in the first mode, a first light-emitting element included in the pixel PX emits light based on a selection signal, and the light from the first light-emitting element is provided to a first range through a first optical member to form a first viewing angle, for example, a wide viewing angle. Also, when the pixel PX is driven in the second mode, a second light-emitting element included in the pixel PX emits light based on a selection signal, and the light from the second light-emitting element is provided to a second range through a second optical member to form a second viewing angle, for example, a narrow viewing angle. Here, the first mode corresponds to a mode in which the corresponding pixel PX is controlled in a wide viewing mode (Share mode), and the second mode may correspond to a mode in which the corresponding pixel PX is driven in a narrow viewing mode (Private mode).

[0052] On the other hand, when controlling the driving mode, it is necessary to divide the display panel PN into regions and independently control the driving mode of each region. At this time, when generating a selection signal for controlling the driving mode of the pixel PX arranged in each region from a driving circuit such as a D-IC and providing it to the pixel PX in the corresponding region, since the selection signal wiring for providing the selection signal from the driving circuit to the pixel PX in the corresponding region is arranged over the entire display panel PN, the number of regions to be divided may be limited. For example, as the number of regions to be divided increases, the selection signal wiring arranged over the entire display panel PN increases, so there may be a problem that the wiring arranged over the entire display panel PN and the area occupied by the wiring increase. Also, when changing the pixel circuit so that the selection signal is received in a matrix form within each pixel PX to reduce the number of selection signal wirings, transistors are added within the pixel PX and the pixel layout becomes complicated, so there may be a problem that it is difficult to achieve high resolution.

[0053] Therefore, the display device 100 according to the embodiments of the present specification can further include at least one selection signal generation unit for controlling the driving mode of the pixels PX in the corresponding area for each divided area. The selection signal generation unit can be arranged on the display panel PN, and one selection signal generation unit for commonly controlling the driving mode of the pixels PX arranged in the corresponding area for each area can be arranged.

[0054] The selection signal generation unit can control the driving mode of the pixel PX. For example, the selection signal generation unit generates a selection signal and provides it to the pixel PX. As described above, based on the selection signal, the pixel PX can be driven in the first mode or the second mode.

[0055] In this way, the selection signal generation unit for controlling the driving mode of the pixel PX can be arranged on the display panel PN. For example, the selection signal generation unit can be arranged in an area where the pixel PX is not arranged among the display areas of the display panel PN, and / or can be arranged in a layer different from the configuration included in the pixel PX. As a result, without increasing the number of selection signal wirings connected from the driving circuit to the pixel PX or changing the pixel circuit as described above, the display panel PN can be divided into areas and the driving mode of each area can be independently controlled. Therefore, when dividing the display panel PN into areas and independently controlling the driving mode of each area, the number of wirings arranged on the display panel PN and the pixel layout can be minimized, and high resolution can be achieved.

[0056] A detailed description of the selection signal generation unit will be given later with reference to FIGS. 3a to 3e, FIGS. 8 to 10d, and FIGS. 12 to 17d.

[0057] FIGS. 3a to 3e are diagrams showing examples of the display panel included in the display device of FIG. 2.

[0058] On the other hand, each of the first display panel PN1, the second display panel PN2, the third display panel PN3, the fourth display panel PN4, and the fifth display panel PN5 shown in FIGS. 3a to 3e shows various embodiments of the display panel PN described with reference to FIG. 2.

[0059] Referring to FIG. 3a, the first display panel PN1 can include a plurality of selection signal generation units SLG and a plurality of pixels PX.

[0060] Each of the plurality of selection signal generation units SLG is arranged for each one pixel PX and can control the driving mode of the corresponding pixel PX. For example, as shown in FIG. 3a, each of the plurality of selection signal generation units SLG can be arranged on one side of each pixel PX. As an example, on the first display panel PN1, the selection signal generation unit SLG and the pixel PX can be arranged at a ratio of 1:1.

[0061] Each of the plurality of selection signal generation units SLG can provide a selection signal to the corresponding one pixel PX to control the driving mode of the corresponding pixel PX. Therefore, the driving mode of each pixel PX included in the first display panel PN1 can be independently controlled. For example, the first display panel PN1 includes a plurality of regions defined in units of one pixel PX, and the driving mode of the corresponding plurality of regions can be independently controlled. That is, in the case of the plurality of pixels PX included in the first display panel PN1, the driving mode of each individual pixel PX can be independently controlled. On the other hand, in such a case, one selection signal generation unit SLG and the corresponding one pixel PX can be defined as a pixel block or a pixel unit.

[0062] Referring to FIG. 3b, the second display panel PN2 can include a plurality of selection signal generation units SLG and a plurality of pixels PX.

[0063] Each of the plurality of selection signal generation units SLG is arranged for every two pixels PX and can control the driving modes of the corresponding two pixels PX. For example, as shown in FIG. 3b, each of the plurality of selection signal generation units SLG can be arranged on one side along one of the two pixels PX arranged in the row direction. As an example, on the second display panel PN2, the selection signal generation unit SLG and the pixel PX can be arranged at a ratio of 1:2. However, it is not limited thereto, and each of the plurality of selection signal generation units SLG may be arranged on one side along one of the two pixels PX arranged in the column direction.

[0064] Each of the plurality of selection signal generation units SLG can provide a selection signal to the corresponding two pixels PX and commonly control the driving modes of the corresponding two pixels PX. Therefore, the driving modes of the two pixels PX included in the second display panel PN2 can be independently controlled for each pixel. For example, the second display panel PN2 includes a plurality of regions defined in units of two pixels PX, and the driving modes of the corresponding plurality of regions can be independently controlled. That is, in the case of the plurality of pixels PX included in the second display panel PN2, the driving modes can be independently controlled for every two pixels PX. On the other hand, in such a case, one selection signal generation unit SLG and the corresponding two pixels PX can be defined as a pixel block or a pixel unit.

[0065] Referring to FIG. 3c, the third display panel PN3 can include a plurality of selection signal generation units SLG and a plurality of pixels PX.

[0066] Each of the plurality of selection signal generation units SLG is arranged for every three pixels PX and can control the driving modes of the corresponding three pixels PX. For example, as shown in FIG. 3c, each of the plurality of selection signal generation units SLG can be arranged on one side along the row direction of any one of the three pixels PX arranged in the row direction. As an example, on the third display panel PN3, the selection signal generation unit SLG and the pixel PX can be arranged at a ratio of 1:3. However, it is not limited thereto, and each of the plurality of selection signal generation units SLG may be arranged on one side along the column direction of any one of the three pixels PX arranged in the column direction.

[0067] Each of the plurality of selection signal generation units SLG can provide a selection signal to the corresponding three pixels PX and commonly control the driving modes of the corresponding three pixels PX. Therefore, the driving modes of the three pixels PX included in the third display panel PN3 can be independently controlled for each pixel. For example, the third display panel PN3 includes a plurality of regions defined in units of three pixels PX, and the driving modes of the corresponding plurality of regions can be independently controlled. That is, in the case of the plurality of pixels PX included in the third display panel PN3, the driving modes can be independently controlled for every three pixels PX. On the other hand, in such a case, one selection signal generation unit SLG and the corresponding three pixels PX can be defined as a pixel block or a pixel unit.

[0068] Referring to FIG. 3d, the fourth display panel PN4 can include a plurality of selection signal generation units SLG and a plurality of pixels PX.

[0069] Each of the plurality of selection signal generation units SLG is arranged for every six pixels PX and can control the driving modes of the corresponding six pixels PX. For example, as shown in FIG. 3d, each of the plurality of selection signal generation units SLG can be arranged on one side along one of the row directions of any one of the six pixels PX arranged in the row direction. As an example, on the fourth display panel PN4, the selection signal generation unit SLG and the pixel PX can be arranged at a ratio of 1:6. However, it is not limited thereto, and each of the plurality of selection signal generation units SLG may be arranged on one side along one of the column directions of any one of the six pixels PX arranged in the column direction.

[0070] Each of the plurality of selection signal generation units SLG can provide a selection signal to the corresponding six pixels PX and commonly control the driving modes of the corresponding six pixels PX. Therefore, the driving modes of the six pixels PX included in the fourth display panel PN4 can be independently controlled for each pixel. For example, the fourth display panel PN4 includes a plurality of regions defined in units of six pixels PX, and the driving modes of the corresponding plurality of regions can be independently controlled. That is, in the case of the plurality of pixels PX included in the fourth display panel PN4, the driving modes can be independently controlled for every six pixels PX. On the other hand, in such a case, one selection signal generation unit SLG and the corresponding six pixels PX can be defined as a pixel block or a pixel unit.

[0071] Referring to FIG. 3e, the fifth display panel PN5 can include a plurality of selection signal generation units SLG and a plurality of pixels PX.

[0072] Each of the plurality of selection signal generation units SLG is arranged for every six pixels PX and can control the driving modes of the corresponding six pixels PX. For example, as shown in FIG. 3e, each of the plurality of selection signal generation units SLG can be arranged on one side along the row direction of two pixels PX arranged in the same column among the six pixels PX arranged three by three in two rows respectively. As an example, on the fifth display panel PN5, the selection signal generation unit SLG and the pixel PX can be arranged at a ratio of 1:6. However, it is not limited thereto, and each of the plurality of selection signal generation units SLG may be arranged on one side along the column direction of two pixels PX arranged in the same row among the six pixels PX arranged three by three in two columns respectively.

[0073] Each of the plurality of selection signal generation units SLG can provide a selection signal to the corresponding six pixels PX and commonly control the driving modes of the corresponding six pixels PX. Therefore, the driving mode of each of the six pixels PX included in the fifth display panel PN5 can be independently controlled. For example, the fifth display panel PN5 includes a plurality of regions defined in units of six pixels PX, and the driving modes of the corresponding plurality of regions can be independently controlled. That is, in the case of a plurality of pixels PX included in the fifth display panel PN5, the driving mode of each six pixels PX can be independently controlled.

[0074] In this way, the arrangement relationship between the selection signal generation unit SLG and the pixel PX included in the display panel PN of the display device 100 according to the embodiments of the present specification can be designed in various ways. Here, as described above, the region of the display panel PN is divided according to each pixel PX commonly controlled by one selection signal generation unit SLG, and the driving mode can be independently controlled for each region. Accordingly, the display panel PN is divided into various regions according to the design of the display device 100, and the corresponding regions can be independently controlled. On the other hand, in such a case, one selection signal generation unit SLG and the corresponding six pixels PX can be defined as a pixel block or a pixel unit.

[0075] FIG. 4 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. 2.

[0076] On the one hand, the first pixel circuit PC1 shown in FIG. 4 shows an embodiment of a pixel circuit corresponding to each of the plurality of pixels PX included in the display device 100 described with reference to FIG. 2.

[0077] Referring to FIG. 4, at least some of the plurality of transistors included in the first pixel circuit PC1 may be n-type transistors or p-type transistors. In the case of p-type transistors, the low level voltage of each drive signal may mean a voltage for turning on the TFT, and the high level voltage of each drive signal may mean a voltage for turning off the TFT.

[0078] Here, the low level voltage may correspond to a predetermined voltage lower than the high level voltage. For example, the low level voltage may include a voltage corresponding to a range of -8V to -12V. The high level voltage may correspond to a predetermined voltage higher than the low level voltage. For example, the high level voltage may include a voltage corresponding to a range of the high level voltage may include a voltage corresponding to a range of 12V to 16V. Depending on the embodiment, the low level voltage may be referred to as the first voltage, and the high level voltage may be referred to as the second voltage. In such a case, the first voltage may be a value lower than the second voltage.

[0079] The first pixel circuit PC1 may include a driving transistor DT, a plurality of switching transistors ST1 to ST6, a plurality of selection transistors TP1, TP2, a storage capacitor Cst, and a plurality of light emitting elements ED1, ED2.

[0080] The driving transistor DT can control the driving current applied to the plurality of light emitting elements ED1, ED2 by a source-gate voltage. The driving transistor DT may include a source electrode connected to a high potential power supply wiring that provides a high potential power supply voltage VDD, a gate electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0081] The first switching transistor ST1 can apply the data voltage Vdata from the data wiring DL to the first node N1. The first switching transistor ST1 can include a source electrode connected to the data wiring DL, a drain electrode connected to the first node N1, and a gate electrode connected to a first scan signal wiring to which the first scan signal SCAN1 is applied. The first switching transistor ST1 can be turned on or off by the first scan signal SCAN1. Therefore, the first switching transistor ST1 can apply the data voltage Vdata from the data wiring DL to the first node N1 in response to the first scan signal SCAN1 at a turn-on level, which is a low level.

[0082] The second switching transistor ST2 can diode-connect the gate electrode and the drain electrode of the driving transistor DT. The second switching transistor ST2 can include a drain electrode connected to the second node N2, a source electrode connected to the third node N3, and a gate electrode connected to a second scan signal wiring to which the second scan signal SCAN2 is applied. The second switching transistor ST2 can be turned on or off by the second scan signal SCAN2. Therefore, the second switching transistor ST2 can diode-connect the gate electrode and the drain electrode of the driving transistor DT in response to the second scan signal SCAN2 at a turn-on level, which is a low level.

[0083] The third switching transistor ST3 can apply a reference voltage Vref to the first node N1. The third switching transistor ST3 can include a source electrode connected to a reference voltage wiring that provides the reference voltage Vref, a drain electrode connected to the first node N1, and a gate electrode connected to a light emission signal wiring to which a light emission signal EM is applied. The third switching transistor ST3 can be turned on or off by the light emission signal EM. Therefore, the third switching transistor ST3 can transmit the reference voltage Vref to the first node N1 in response to the light emission signal EM at a turn-on level, which is a low level.

[0084] The fourth switching transistor ST4 can apply the reference voltage Vref to the anode electrode of the first light emitting element ED1. The fourth switching transistor ST4 can include a source electrode connected to a reference voltage wiring that provides the reference voltage Vref, a drain electrode connected to the anode electrode of the first light emitting element ED1, and a gate electrode connected to a second scan signal wiring to which a second scan signal SCAN2 is applied. The fourth switching transistor ST4 can be turned on or off by the second scan signal SCAN2. Therefore, the fourth switching transistor ST4 can apply the reference voltage Vref to the anode electrode of the first light emitting element ED1 in response to the second scan signal SCAN2 at a turn-on level, which is a low level.

[0085] The fifth switching transistor ST5 can apply a reference voltage Vref to the anode electrode of the second light-emitting element ED2. The fifth switching transistor ST5 can include a source electrode connected to a reference voltage wiring that provides the reference voltage Vref, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to a second scan signal wiring to which a second scan signal SCAN2 is applied. The fifth switching transistor ST5 can be turned on or off by the second scan signal SCAN2. Therefore, the fifth switching transistor ST5 can apply the reference voltage Vref to the anode electrode of the second light-emitting element ED2 in response to the second scan signal SCAN2 at a turn-on level, which is a low level.

[0086] The sixth switching transistor ST6 can form a current path between the driving transistor DT and any one of the plurality of light-emitting elements ED1, ED2. The sixth switching transistor ST6 can include a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to a light-emitting signal wiring to which a light-emitting signal EM is applied. The sixth switching transistor ST6 can be turned on or off by the light-emitting signal EM. Therefore, the sixth switching transistor ST6 can electrically connect the third node N3 and the fourth node N4 in response to the light-emitting signal EM at a turn-on level, which is a low level, and can form a current path between the driving transistor DT and any one of the plurality of light-emitting elements ED1, ED2.

[0087] The storage capacitor Cst can include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. One electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst can be connected to the first switching transistor ST1. The storage capacitor Cst can store a constant voltage and maintain the voltage of the gate electrode of the driving transistor DT constant while any one of the plurality of light-emitting elements ED1, ED2 emits light.

[0088] The plurality of selection transistors TP1, TP2 can include a first selection transistor TP1 for generating a current path of a first drive current via the first light-emitting element ED1 and a second selection transistor TP2 for generating a current path of a second drive current via the second light-emitting element ED2.

[0089] The first selection transistor TP1 is connected between the fourth node N4 and the first light-emitting element ED1, and the gate electrode of the first selection transistor TP1 can be connected to a first selection signal wiring that provides a first selection signal Ss. When the pixel PX to which the first pixel circuit PC1 is applied is driven in a first mode which is a wide viewing angle mode, the first selection signal Ss is supplied to the gate electrode of the first selection transistor TP1 so that the first selection transistor TP1 can be turned on. Thus, a current path of the first drive current via the first light-emitting element ED1 is formed, and the first light-emitting element ED1 can emit light. On the other hand, the first selection transistor TP1 can also be referred to as a first light emission control transistor that controls the light emission of the first light-emitting element ED1.

[0090] The second selection transistor TP2 is connected between the fourth node N4 and the second light-emitting element ED2, and the gate electrode of the second selection transistor TP2 can be connected to a second selection signal wiring that provides a second selection signal Ps. When the pixel PX to which the first pixel circuit PC1 is applied is driven in a second mode which is a narrow viewing angle mode, the second selection signal Ps is supplied to the gate electrode of the second selection transistor TP2 so that the second selection transistor TP2 can be turned on. Thus, a current path of the second drive current via the second light-emitting element ED2 is formed, and the second light-emitting element ED2 can emit light. On the other hand, the second selection transistor TP2 can also be referred to as a second light emission control transistor that controls the light emission of the second light-emitting element ED2.

[0091] The first light-emitting element ED1 can be connected between a first selection transistor TP1 that is turned on or off by a first selection signal Ss and a low-potential power supply wiring that provides a low-potential power supply voltage VSS. The second light-emitting element ED2 can be connected between a second selection transistor TP2 that is turned on or off by a second selection signal Ps and the low-potential power supply wiring that provides the low-potential power supply voltage VSS.

[0092] In such a case, the first light-emitting element ED1 or the second light-emitting element ED2 can be connected to other components of the first pixel circuit PC1, such as a driving transistor DT, by the first selection transistor TP1 or the second selection transistor TP2 that is turned on according to a driving mode. For example, the first light-emitting element ED1 is connected to the driving transistor DT via the first selection transistor TP1 turned on in the first mode, and can provide light at a first viewing angle, that is, a wide viewing angle in the first mode, i.e., the wide viewing field mode, by a first driving current. Also, the second light-emitting element ED2 is connected to the driving transistor DT via the second selection transistor TP2 turned on in the second mode, and can provide light at a second viewing angle, that is, a narrow viewing angle in the second mode, i.e., the narrow viewing field mode, by a second driving current. Here, the driving mode can be specified by a user input or determined when a pre-specified condition is satisfied.

[0093] FIG. 5A and FIG. 5B are waveform diagrams for explaining the pixel circuit of FIG. 4.

[0094] On the other hand, FIG. 5A shows a waveform diagram for explaining an example when a pixel PX to which the first pixel circuit PC1 is applied is driven in the first mode, and FIG. 5B shows a waveform diagram for explaining an example when the pixel PX to which the first pixel circuit PC1 is applied is driven in the second mode.

[0095] Referring to FIGS. 4 to 5b, in the first mode, only the first light-emitting element ED1 emits light, and in the second mode, only the second light-emitting element ED2 can emit light. Here, as shown in FIG. 5a, a second selection signal Ps for controlling the light emission of the second light-emitting element ED2 so that only the first light-emitting element ED1 emits light in the first mode can be output only at a high level which is a turn-off level. Also, as shown in FIG. 5b, a first selection signal Ss for controlling the light emission of the first light-emitting element ED1 so that only the second light-emitting element ED2 emits light in the second mode can be output only at a high level (or a first level) which is a turn-off level.

[0096] Specifically, first, referring to FIGS. 4 and 5a, considering the first mode which is a wide viewing angle mode, a low-level second scan signal SCAN2, a low-level first selection signal Ss, and a low-level light emission signal EM can be output during an initialization period P1. The low-level second scan signal SCAN2 turns on the second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5, the low-level first selection signal Ss turns on the first selection transistor TP1, and the low-level light emission signal EM can turn on the third switching transistor ST3 and the sixth switching transistor ST6.

[0097] The first node N1 can be initialized to a reference voltage Vref through the turned-on third switching transistor ST3. The voltage of the anode electrode of the first light-emitting element ED1 is initialized to the reference voltage Vref through the turned-on fourth switching transistor ST4, and the voltage of the anode electrode of the second light-emitting element ED2 can be initialized to the reference voltage Vref through the turned-on fifth switching transistor ST5. The driving transistor DT is diode-connected through the turned-on second switching transistor ST2, and by shorting the gate electrode and the drain electrode of the driving transistor DT, the driving transistor DT can operate like a diode. The reference voltage Vref transmitted to the anode electrode of the first light-emitting element ED1 through the turned-on fourth switching transistor ST4 is transmitted to the third node N3 and the second node N2 through the turned-on first selection transistor TP1 and the turned-on sixth switching transistor ST6, and the third node N3 and the second node N2 can be initialized to the reference voltage Vref.

[0098] Next, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 are output during the sampling period P2, and the first selection signal Ss can be output at a high level. When a high-level light-emitting signal EM is output and the third switching transistor ST3 is turned off, at the same time, the first switching transistor ST1 is turned on by the low-level (or second level, the second level has a value lower than the first level) first scan signal SCAN1, and the data voltage Vdata can be transmitted to the first node N1. Then, the driving transistor DT is diode-connected by the turned-on second switching transistor ST2, and the differential voltage between the high-potential power supply voltage VDD and the threshold voltage can be sampled and supplied to the second node N2.

[0099] On the other hand, during the sampling period P2, the sixth switching transistor ST6 can be turned off by the high-level emission signal EM, and the first selection transistor TP1 can be turned off by the high-level first selection signal Ss.

[0100] Then, during the holding period P3, the first scan signal SCAN1 and the second scan signal SCAN2 are output at a high level, and the first switching transistor ST1, the second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 can all be turned off. However, even if the first switching transistor ST1 is turned off, the data voltage Vdata input in the previous period (e.g., the sampling period P2) can be maintained by the storage capacitor Cst.

[0101] Finally, during the emission period P4, the low-level first selection signal Ss and the low-level emission signal EM are output, and the high-level second selection signal Ps can be output. The reference voltage Vref is applied to the first node N1 through the third switching transistor ST3 turned on by the low-level emission signal EM, and the voltage of the first node N1 can become the differential voltage between the reference voltage Vref and the data voltage Vdata, and such voltage fluctuations can also be reflected in the second node N2. The gate-source voltage of the drive transistor DT is set to the value obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata (Vdata - Vref + Vth), and the first drive current can be controlled.

[0102] Then, a first drive current is supplied from a drive transistor DT to a first light-emitting element ED1 through a sixth switching transistor ST6 turned on by a low-level light-emission signal EM and a first selection transistor TP1 turned on by a low-level first selection signal Ss, and the first light-emitting element ED1 can emit light. However, since a second selection signal Ps is output at a high level and a second selection transistor TP2 is turned off, a second drive current cannot be transmitted from the drive transistor DT to a second light-emitting element ED2. Therefore, when a first pixel circuit PC1 is driven in a first mode, only the first drive current is applied to the first light-emitting element ED1, and only the first light-emitting element ED1 can emit light.

[0103] Next, referring to FIGS. 4 and 5B, when considering a second mode which is a narrow viewing angle mode, the first pixel circuit PC1 can be driven in the second mode in substantially the same manner as in the first mode, except that a first selection signal Ss and a second selection signal Ps are output opposite to those in the first mode which is a wide viewing angle mode. That is, the first selection signal Ss is output only at a high level which is a turn-off level, and the second selection signal Ps can be output at a low level which is a turn-on level during a light-emission period P4 in which the second light-emitting element ED2 emits light.

[0104] Specifically, during an initialization period P1, a first scan signal SCAN1 can be output at a high level, and a second scan signal SCAN2 can be output at a low level. Then, the first selection signal Ss can be output at a high level, and the second selection signal Ps and the light-emission signal EM can be output at a low level. Therefore, the second scan signal SCAN2 turns on a second switching transistor ST2, a fourth switching transistor ST4, and a fifth switching transistor ST5, the second selection signal Ps turns on a second selection transistor TP2, and the light-emission signal EM can turn on a third switching transistor ST3 and a sixth switching transistor ST6.

[0105] The first node N1 is initialized to a reference voltage Vref through a third switching transistor ST3 turned on by a light emission signal EM, and the anode electrodes of a first light emitting element ED1 and a second light emitting element ED2 can be initialized to the reference voltage Vref by a fourth switching transistor ST4 and a fifth switching transistor ST5 turned on by a second scan signal SCAN2, respectively. Then, the driving transistor DT is diode-connected through the turned-on second switching transistor ST2 and can operate like a diode. Finally, the reference voltage Vref transmitted to the anode electrode of the second light emitting element ED2 through the turned-on fifth switching transistor ST5 is transmitted to a third node N3 and a second node N2 through the turned-on second selection transistor TP2 and the turned-on sixth switching transistor ST6, and the third node N3 and the second node N2 can be initialized to the reference voltage Vref.

[0106] Next, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 are output during a sampling period P2, and a second selection signal Ps and a light emission signal EM can be output from a low level to a high level. When the high-level light emission signal EM is output and the third switching transistor ST3 is turned off, the first switching transistor ST1 can be turned on by the low-level first scan signal SCAN1 and a data voltage Vdata can be transmitted to the first node N1. Then, the driving transistor DT is diode-connected by the turned-on second switching transistor ST2, and a differential voltage between a high-potential power supply voltage VDD and a threshold voltage can be sampled and supplied to the second node N2.

[0107] On the other hand, during the sampling period P2, the sixth switching transistor ST6 can be turned off by the high-level light emission signal EM, and the second selection transistor TP2 can be turned off by the high-level second selection signal Ps.

[0108] Finally, a low-level second selection signal Ps and a low-level emission signal EM may be output during the emission period P4, and a high-level first selection signal Ss may be output. A reference voltage Vref is applied to the first node N1 through a third switching transistor ST3 turned on by the low-level emission signal EM, and the voltage of the first node N1 may become a differential voltage between the reference voltage Vref and the data voltage Vdata, and such voltage fluctuations may also be reflected in the second node N2. The gate-source voltage of the driving transistor DT is set to a value obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata (Vdata - Vref + Vth), and the second driving current may be controlled.

[0109] Then, a second driving current is supplied from the driving transistor DT to the second light-emitting element ED2 through a sixth switching transistor ST6 turned on by the low-level emission signal EM and a second selection transistor TP2 turned on by the low-level second selection signal Ps, and the second light-emitting element ED2 can emit light. However, since the first selection signal Ss is output at a high level and the first selection transistor TP1 is turned off, the first driving current cannot be transmitted from the driving transistor DT to the first light-emitting element ED1. Therefore, when the first pixel circuit PC1 is driven in the second mode, only the second driving current is applied to the second light-emitting element ED2, and only the second light-emitting element ED2 can emit light.

[0110] FIG. 6 and FIG. 7 are cross-sectional views of a part of a display device according to an embodiment of the present specification.

[0111] FIG. 6 shows a pixel in which a first optical member 161 is arranged, and FIG. 7 shows a pixel in which a second optical member 162 is arranged.

[0112] Referring to FIGS. 6 and 7, the display device 100 according to the embodiments of the present specification may include a substrate 110, a buffer film 111, a gate insulating film 112, an interlayer insulating film 113, a lower protective film 114, an overcoat layer 115, a bank insulating film 116, a first selection transistor TP1, a second selection transistor TP2, a first light-emitting element ED1, a second light-emitting element ED2, a first optical member 161, a second optical member 162, an optical member protective film 170, and a sealing member 180.

[0113] The substrate 110 may include an insulating material. The substrate 110 may include a transparent material. For example, the substrate 110 may include glass or plastic.

[0114] A buffer film 111 may be disposed on the substrate 110. The buffer film 111 may include an insulating material. For example, the buffer film 111 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer film 111 may have a multilayer structure. For example, the buffer film 111 may have a laminated structure of a film made of silicon nitride (SiNx) and a film made of silicon oxide (SiOx).

[0115] The buffer film 111 may be located between the substrate 110 and the driving portion of each pixel PX. The buffer film 111 can prevent contamination of the substrate 110 during the formation process of the driving portion. For example, the upper surface of the substrate 110 facing the driving portion of each pixel PX may be covered by the buffer film 111. The driving portion of each pixel PX may be located on the buffer film 111.

[0116] A gate insulating film 112 may be disposed on the buffer film 111. The gate insulating film 112 may include an insulating material. For example, the gate insulating film 112 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The gate insulating film 112 may include a material having a high dielectric constant. For example, the gate insulating film 112 may include a High-K material such as hafnium oxide (HfO). The gate insulating film 112 may have a multilayer structure.

[0117] The gate insulating film 112 can extend between the semiconductor layers 121 and 221 and the gate electrodes 122 and 223 of the selection transistors TP1 and TP2. For example, the gate electrodes of the driving transistor and the switching transistor can be insulated from the semiconductor layers of the driving transistor and the switching transistor by the gate insulating film 112. The gate insulating film 112 can cover the semiconductor layer of each pixel PX. The gate electrodes of the driving transistor and the switching transistor can be located on the gate insulating film 112.

[0118] An interlayer insulating film 113 can be disposed on the gate insulating film 112. The interlayer insulating film 113 can contain an insulating material. For example, the interlayer insulating film 113 can contain an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The interlayer insulating film 113 can extend between the gate electrode and the source electrode and between the gate electrode and the drain electrode of each of the driving transistor and the switching transistor. For example, the source electrodes and the drain electrodes of the driving transistor and the switching transistor can be insulated from the gate electrode by the interlayer insulating film 113. The interlayer insulating film 113 can cover the gate electrodes of the driving transistor and the switching transistor. The source electrodes and the drain electrodes of each pixel PX can be located on the interlayer insulating film 113. The gate insulating film 112 and the interlayer insulating film 113 can expose the source region and the drain region of each semiconductor pattern located within each pixel PX.

[0119] A lower protective film 114 can be disposed on the interlayer insulating film 113. The lower protective film 114 can contain an insulating material. For example, the lower protective film 114 can contain an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The lower protective film 114 can prevent damage to the driving portion due to external moisture and impact. The lower protective film 114 can extend along the surfaces of the driving transistor and the switching transistor facing the substrate 110. The lower protective film 114 can contact the interlayer insulating film 113 outside the driving portion located within each pixel PX.

[0120] An overcoat layer 115 may be disposed on the lower protective film 114. The overcoat layer 115 may contain an insulating material. The overcoat layer 115 may contain a material different from that of the lower protective film 114. For example, the overcoat layer 115 may contain an organic insulating material. The overcoat layer 115 can remove the step caused by the driving portion of each pixel PX. For example, the upper surface of the overcoat layer 115 facing the substrate 110 may be a flat surface.

[0121] The first selection transistor TP1 and the second selection transistor TP2 may be disposed on the substrate 110. The first selection transistor TP1 may be electrically connected between the drain electrode of the driving transistor DT and the first lower electrode 141 of the first light-emitting element ED1. The second selection transistor TP2 may be electrically connected between the drain electrode of the driving transistor DT and the second lower electrode 151 of the second light-emitting element ED2.

[0122] The first selection transistor TP1 may include a first semiconductor layer 121, a first gate electrode 122, a first source electrode 123, and a first drain electrode 124. The first selection transistor TP1 may have the same structure as the switching transistor and the driving transistor. For example, the first semiconductor layer 121 may be located between the buffer film 111 and the gate insulating film 112, and the first gate electrode 122 may be located between the gate insulating film 112 and the interlayer insulating film 113. The first source electrode 123 and the first drain electrode 124 may be located between the interlayer insulating film 113 and the lower protective film 114. The first gate electrode 122 may overlap with the channel region of the first semiconductor layer 121. The first source electrode 123 may be electrically connected to the source region of the first semiconductor layer 121. The first drain electrode 124 may be electrically connected to the drain region of the first semiconductor layer 121.

[0123] The second selection transistor TP2 can include a second semiconductor layer 221, a second gate electrode 223, a second source electrode 225, and a second drain electrode 227. For example, the second semiconductor layer 221 can be located in the same layer as the first semiconductor layer 121, the second gate electrode 223 can be located in the same layer as the first gate electrode 122, and the second source electrode 225 and the second drain electrode 227 can be located in the same layer as the first source electrode 123 and the first drain electrode 124.

[0124] The first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX can be disposed on the overcoat layer 115 of the corresponding pixel PX.

[0125] The first light-emitting element ED1 can emit light indicating a specific color. For example, the first light-emitting element ED1 can include a first lower electrode 141, a first light-emitting layer 142, and a first upper electrode 143 that are sequentially stacked on the substrate 110.

[0126] The first lower electrode 141 can include a conductive material. The first lower electrode 141 can include a material having a high reflectivity. For example, the first lower electrode 141 can include a metal such as aluminum (Al) and silver (Ag). The first lower electrode 141 can have a multilayer structure. For example, the first lower electrode 141 can have a structure in which a reflective electrode made of a metal is located between transparent electrodes made of transparent conductive materials such as ITO and IZO. The first lower electrode 141 can be electrically connected to the first drain electrode 124 of the first selection transistor TP1 through a contact hole that penetrates the lower protection film 114 and the overcoat layer 115.

[0127] The first light-emitting layer 142 can generate light having a luminance corresponding to the voltage difference between the first lower electrode 141 and the first upper electrode 143. For example, the first light-emitting layer 142 can include an emission material layer (EML) containing an emission material. The emission material can include an organic material, an inorganic material, or a hybrid material.

[0128] The first light-emitting layer 142 may have a multilayer structure. For example, the first light-emitting layer 142 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0129] The first upper electrode 143 may include a conductive material. The first upper electrode 143 may include a material different from that of the first lower electrode 141. The transmittance of the first upper electrode 143 may be higher than that of the first lower electrode 141. For example, the first upper electrode 143 may be a transparent electrode made of a transparent conductive material such as ITO and IZO. Accordingly, in the display device 100 according to the embodiments of the present specification, the light generated by the first light-emitting layer 142 may be emitted through the first upper electrode 143.

[0130] The second light-emitting element ED2 may express the same color as the first light-emitting element ED1. The second light-emitting element ED2 may have the same structure as the first light-emitting element ED1. For example, the second light-emitting element ED2 may include a second lower electrode 151, a second light-emitting layer 152, and a second upper electrode 153 sequentially stacked on the substrate 110.

[0131] The second lower electrode 151 may correspond to the first lower electrode 141, the second light-emitting layer 152 may correspond to the first light-emitting layer 142, and the second upper electrode 153 may correspond to the first upper electrode 143. For example, the second lower electrode 151 may be formed with the same structure as the first lower electrode 141 for the second light-emitting element ED2, which is also the same for the second light-emitting layer 152 and the second upper electrode 153. For example, the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to have the same structure. However, it is not limited thereto, and in some cases, at least some of the configurations of the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to be different.

[0132] The second light-emitting layer 152 may be spaced apart from the first light-emitting layer 142. Accordingly, in the display device according to the embodiments of the present specification, light emission due to leakage current may be prevented.

[0133] According to the embodiments of the present specification, in the display device, light may be generated only in one of the first light-emitting layer 142 and the second light-emitting layer 152 according to a user's selection or a preset condition.

[0134] The second lower electrode 151 of each pixel PX may be spaced apart from the first lower electrode 141 of the corresponding pixel PX. For example, a bank insulating film 116 may be disposed between the first lower electrode 141 and the second lower electrode 151 of each pixel PX. The bank insulating film 116 may include an insulating material. For example, the bank insulating film 116 may include an organic insulating material. The bank insulating film 116 may include a material different from that of the overcoat layer 115.

[0135] The second lower electrode 151 of each pixel PX may be insulated from the first lower electrode 141 of the corresponding pixel PX by the bank insulating film 116. For example, the bank insulating film 116 may cover the edges of the first lower electrode 141 and the second lower electrode 151 located within each pixel PX. Accordingly, in the display device 100, an image by the first optical region of each pixel PX where the first light-emitting element ED1 is located or an image by the second optical region of each pixel PX where the second light-emitting element ED2 is located may be provided to the user.

[0136] The first light-emitting layer 142 and the first upper electrode 143 of the first light-emitting element ED1 located within each pixel PX can be laminated on a partial region of the corresponding first lower electrode 141 exposed by the bank insulating film 116. The second light-emitting layer 152 and the second upper electrode 153 of the second light-emitting element ED2 located within each pixel PX can be laminated on a partial region of the corresponding second lower electrode 151 exposed by the bank insulating film 116. For example, the bank insulating film 116 can demarcate a first light-emitting region where light is emitted by the first light-emitting element ED1 and a second light-emitting region where light is emitted by the second light-emitting element ED2 within each pixel PX. The size of the second light-emitting region demarcated within each pixel PX may be smaller than the size of the first light-emitting region.

[0137] The second upper electrode 153 of each pixel PX can be electrically connected to the first upper electrode 143 of the corresponding pixel PX. For example, the voltage applied to the second upper electrode 153 of the second light-emitting element ED2 located within each pixel PX may be the same as the voltage applied to the first upper electrode 143 of the first light-emitting element ED1 located within the corresponding pixel PX. The second upper electrode 153 of each pixel PX can contain the same material as the first upper electrode 143 of the corresponding pixel PX. For example, the second upper electrode 153 of each pixel PX can be formed simultaneously with the first upper electrode 143 of the corresponding pixel PX. The second upper electrode 153 of each pixel PX can extend on the bank insulating film 116 and directly contact the first upper electrode 143 of the corresponding pixel PX. The luminance of the first optical region and the luminance of the second optical region located within each pixel PX can be controlled by the drive current generated in the corresponding pixel PX.

[0138] On the first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX, a sealing member 180 may be located. The sealing member 180 can prevent damage to the light-emitting elements ED1 and ED2 due to moisture and impact from the outside. The sealing member 180 may have a multilayer structure. For example, the sealing member 180 may include, but is not limited to, a first sealing layer 181, a second sealing layer 182, and a third sealing layer 183 laminated in order. The first sealing layer 181, the second sealing layer 182, and the third sealing layer 183 may include an insulating material. The second sealing layer 182 may include a material different from that of the first sealing layer 181 and the third sealing layer 183. For example, the first sealing layer 181 and the third sealing layer 183 are inorganic sealing layers including an inorganic insulating material, and the second sealing layer 182 may include an organic sealing layer including an organic insulating material. Thereby, damage to the light-emitting elements ED1 and ED2 of the display device 100 due to moisture and impact from the outside can be more effectively prevented.

[0139] On the sealing member 180, a first optical member 161 and a second optical member 162 may be arranged.

[0140] The first optical member 161 may be arranged on the first light-emitting element ED1. The light generated by the first light-emitting element ED1 of each pixel PX may be emitted through the first optical member 161 arranged in the first optical region of the corresponding pixel PX. The first optical member 161 may have a shape in which light in at least one side direction does not need to be restricted. For example, the planar shape of the first optical member 161 located within each pixel PX may have a bar shape extending in one direction.

[0141] In such a case, the traveling direction of the corresponding light emitted in the first optical region of each pixel PX does not have to be restricted to one direction. For example, the content (or image) provided through the first optical region of each pixel PX can be shared with people in the surrounding area adjacent to the user in one direction. As a result, the content provided by the light emitted through the first optical member 161 can be provided within a first viewing angle range that has a wider viewing angle than the content provided by the light emitted through the second optical member 162. For example, the content provided by the light emitted through the first optical member 161 can be provided in a wide viewing angle mode (Share mode).

[0142] The second optical member 162 can be disposed on the second light emitting element ED2. The light generated by the second light emitting element ED2 of each pixel PX can be emitted through the second optical member 162 disposed in the second optical region of the corresponding pixel PX. The second optical member 162 can restrict the traveling direction of the passing light to one direction and / or another one direction. For example, the planar shape of the second optical member 162 located within each pixel PX can have a circular shape.

[0143] In such a case, the traveling direction of the light emitted in the second optical region of each pixel PX can be restricted to one direction and / or another one direction. For example, the content (or image) provided by the second optical region of each pixel PX does not have to be shared with people around the user. As a result, the content provided by the light emitted through the second optical member 162 can be provided within a second viewing angle range that has a narrower viewing angle than the content provided by the light emitted through the first optical member 161. For example, the content provided by the light emitted through the second optical member 162 can be provided in a narrow viewing angle mode (Private mode).

[0144] The first light-emitting region of each pixel PX may have a shape corresponding to the first optical member 161 of the corresponding pixel PX. For example, the planar shape of the first light-emitting region of each pixel PX may have a bar shape extending in one direction. The first optical member 161 may have a size larger than that of the first light-emitting region of the corresponding pixel PX. Thereby, the efficiency of the light emitted from the first light-emitting region of the pixel PX can be improved.

[0145] The second light-emitting region of each pixel PX may have a shape corresponding to the second optical member 162 of the corresponding pixel PX. For example, the planar shape of the second light-emitting region of each pixel PX may have a circular shape. The second optical member 162 may have a size larger than that of the second light-emitting region of the corresponding pixel PX. Thereby, the efficiency of the light emitted from the second light-emitting region of the pixel PX can be improved.

[0146] An optical member protective film 170 may be located on the first optical member 161 and the second optical member 162 of the pixel PX. The optical member protective film 170 may include an insulating material. For example, the optical member protective film 170 may include an organic insulating material. The refractive index of the optical member protective film 170 may be smaller than the refractive indices of the first optical member 161 and the second optical member 162 located within each pixel PX. Thereby, in the display device 100 according to the embodiments of the present specification, the light that has passed through the first optical member 161 and the second optical member 162 of each pixel PX does not need to be reflected in the direction of the substrate 110 due to the refractive index difference with the optical member protective film 170.

[0147] FIG. 8 is a circuit diagram showing an example of a selection signal generation circuit included in the display device of FIG. 2.

[0148] On the other hand, the first selection signal generation circuit SLC1 shown in FIG. 8 shows an embodiment of a selection signal generation circuit corresponding to each of the plurality of selection signal generation units SLG included in the display device 100 described with reference to FIGS. 2 to 3e. The selection signal generation unit SLG including the first selection signal generation circuit SLC1 can provide a selection signal to the pixel PX including the first pixel circuit PC1 described with reference to FIG. 4.

[0149] Referring to FIG. 8, the plurality of transistors included in the first selection signal generation circuit SLC1 may be n-type transistors or p-type transistors. In the case of p-type transistors, the low level voltage of each control signal means the voltage for turning on the TFT, and the high level voltage of each control signal may mean the voltage for turning off the TFT. In the following, for convenience of explanation, it will be described on the basis that the plurality of transistors T1 to T8 included in the first selection signal generation circuit SLC1 are p-type transistors, but at least a part of the plurality of transistors T1 to T8 included in the first selection signal generation circuit SLC1 can be modified to n-type transistors.

[0150] Hereinafter, the first electrode or the second electrode of the transistor to be described later may mean the source electrode or the drain electrode. However, the terms "first electrode" and "second electrode" are only terms for distinguishing each electrode, and do not limit what each electrode corresponds to. Also, the first electrode may not refer to the same electrode for each electrode.

[0151] The first selection signal generation circuit SLC1 can include a first selection signal output unit SGL1 that generates a first selection signal Ss based on the first to fourth control signals S_V, S_H, P_V, P_H, the first power supply voltage VGH, and the second power supply voltage VGL, and a second selection signal output unit SGL2 that generates a second selection signal Ps based on the first to fourth control signals S_V, S_H, P_V, P_H, the first power supply voltage VGH, and the second power supply voltage VGL.

[0152] The first power supply voltage VGH and the second power supply voltage VGL are drive voltages for driving the first selection signal generation circuit SLC1, and the voltage level of the second power supply voltage VGL may be lower than the voltage level of the first power supply voltage VGH. For example, the first power supply voltage VGH may be a positive voltage, and the second power supply voltage VGL may be a negative voltage.

[0153] The first selection signal output unit SGL1 can output a high-level or low-level first selection signal Ss, that is, a first selection signal Ss at a turn-off level or a turn-on level, through the first output node NC1 by controlling the voltage of the first output node NC1 to the high-level first power supply voltage VGH or the low-level second power supply voltage VGL. For this purpose, the first selection signal output unit SGL1 can include first to fourth transistors T1 to T4.

[0154] The first transistor T1 can be connected between the second power supply voltage wiring that provides the second power supply voltage VGL and the first output node NC1. For example, the first electrode of the first transistor T1 can be connected to the second power supply voltage wiring, and the second electrode of the first transistor T1 can be connected to the first output node NC1. The gate electrode of the first transistor T1 can be connected to the first control signal wiring that provides the first control signal S_V. The first transistor T1 can be turned on when a turn-on level, for example, a low-level first control signal S_V is supplied, and can electrically connect the first output node NC1 and the second power supply voltage wiring. In this case, the second power supply voltage VGL is provided to the first output node NC1, and the first selection signal output unit SGL1 can output a low-level first selection signal Ss.

[0155] The second transistor T2 can be connected between the second power supply voltage wiring that provides the second power supply voltage VGL and the first output node NC1. For example, the first electrode of the second transistor T2 can be connected to the second power supply voltage wiring, and the second electrode of the second transistor T2 can be connected to the first output node NC1. The gate electrode of the second transistor T2 can be connected to the second control signal wiring that provides the second control signal S_H. The second transistor T2 can be turned on when a turn-on level, for example, a low-level second control signal S_H is supplied, and can electrically connect the first output node NC1 and the second power supply voltage wiring. In this case, the second power supply voltage VGL is provided to the first output node NC1, and the first selection signal output unit SGL1 can output a low-level first selection signal Ss.

[0156] The third transistor T3 can be connected between a first power supply voltage wiring that provides a first power supply voltage VGH and a first output node NC1. For example, a first electrode of the third transistor T3 can be connected to the fourth transistor T4, and a second electrode of the third transistor T3 can be connected to the first output node NC1. A gate electrode of the third transistor T3 can be connected to a third control signal wiring that provides a third control signal P_V. The third transistor T3 can be turned on when a turn-on level, for example, a low-level third control signal P_V is supplied, and the first output node NC1 and the fourth transistor T4 can be electrically connected.

[0157] The fourth transistor T4 can be connected between the third transistor T3 and a first power supply voltage wiring that provides a first power supply voltage VGH. For example, a first electrode of the fourth transistor T4 can be connected to the first power supply voltage wiring, and a second electrode of the fourth transistor T4 can be connected to a first electrode of the third transistor T3. A gate electrode of the fourth transistor T4 can be connected to a fourth control signal wiring that provides a fourth control signal P_H. The fourth transistor T4 can be turned on when a turn-on level, for example, a low-level fourth control signal P_H is supplied, and the third transistor T3 and a second power supply voltage wiring can be electrically connected.

[0158] The first transistor T1 and the second transistor T2 can be connected in parallel between a second power supply voltage wiring that provides a second power supply voltage VGL and the first output node NC1. Thereby, when at least one of the first transistor T1 and the second transistor T2 is turned on, the first output node NC1 and the second power supply voltage wiring that provides the second power supply voltage VGL are electrically connected, and a low-level first selection signal Ss can be output through the first output node NC1.

[0159] Further, the third transistor T3 and the fourth transistor T4 can be connected in series between a first power supply voltage wiring that provides a first power supply voltage VGH and a first output node NC1. Thus, when both the third transistor T3 and the fourth transistor T4 are turned on, the first output node NC1 and the first power supply voltage wiring that provides the first power supply voltage VGH are electrically connected, and a high-level first selection signal Ss can be output through the first output node NC1.

[0160] In this way, the first transistor T1 and the second transistor T2 can function as a pull-up part of the first selection signal output unit SGL1, and the third transistor T3 and the fourth transistor T4 can function as a pull-down part of the first selection signal output unit SGL1. For example, the first transistor T1 and the second transistor T2 can be defined as a first pull-up part, and the third transistor T3 and the fourth transistor T4 can be defined as a first pull-down part.

[0161] The second selection signal output unit SGL2 controls the voltage of the second output node NC2 to the high-level first power supply voltage VGH or the low-level second power supply voltage VGL, so that a high-level or low-level second selection signal Ps, that is, a turn-off level or turn-on level second selection signal Ps can be output through the second output node NC2. For this purpose, the second selection signal output unit SGL2 can include fifth to eighth transistors T5 to T8.

[0162] The fifth transistor T5 can be connected between a second power supply voltage wiring that provides a second power supply voltage VGL and the second output node NC2. For example, a first electrode of the fifth transistor T5 can be connected to the second power supply voltage wiring, and a second electrode of the fifth transistor T5 can be connected to the sixth transistor T6. A gate electrode of the fifth transistor T5 can be connected to a fourth control signal wiring that provides a fourth control signal P_H. The fifth transistor T5 can be turned on when a turn-on level, for example, a low-level fourth control signal P_H is supplied, and the second power supply voltage wiring and the sixth transistor T6 can be electrically connected.

[0163] The sixth transistor T6 can be connected between the fifth transistor T5 and the second output node NC2. For example, the first electrode of the sixth transistor T6 can be connected to the second electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6 can be connected to the second output node NC2. The gate electrode of the sixth transistor T6 can be connected to a third control signal wiring that provides a third control signal P_V. The sixth transistor T6 can be turned on when a turn-on level, for example, a low-level third control signal P_V is supplied, and can electrically connect the fifth transistor T5 and the second output node NC2.

[0164] The seventh transistor T7 can be connected between a first power supply voltage wiring that provides a first power supply voltage VGH and the second output node NC2. For example, the first electrode of the seventh transistor T7 can be connected to the first power supply voltage wiring, and the second electrode of the seventh transistor T7 can be connected to the second output node NC2. The gate electrode of the seventh transistor T7 can be connected to a first control signal wiring that provides a first control signal S_V. The seventh transistor T7 can be turned on when a turn-on level, for example, a low-level first control signal S_V is supplied, and can electrically connect the second output node NC2 and the first power supply voltage wiring. In this case, the first power supply voltage VGH is provided to the second output node NC2, and the second selection signal output unit SGL2 can output a high-level second selection signal Ps.

[0165] The eighth transistor T8 can be connected between a first power supply voltage wiring that provides a first power supply voltage VGH and a second output node NC2. For example, a first electrode of the eighth transistor T8 can be connected to the first power supply voltage wiring, and a second electrode of the eighth transistor T8 can be connected to the second output node NC2. A gate electrode of the eighth transistor T8 can be connected to a second control signal wiring that provides a second control signal S_H. The eighth transistor T8 can be turned on when a turn-on level, for example, a low-level second control signal S_H is supplied, and the second output node NC2 and the first power supply voltage wiring can be electrically connected. In this case, the first power supply voltage VGH is provided to the second output node NC2, and the second selection signal output unit SGL2 can output a high-level second selection signal Ps.

[0166] The fifth transistor T5 and the sixth transistor T6 can be connected in series between a second power supply voltage wiring that provides a second power supply voltage VGL and the second output node NC2. Accordingly, when both the fifth transistor T5 and the sixth transistor T6 are turned on, the second output node NC2 and the second power supply voltage wiring that provides the second power supply voltage VGL are electrically connected, and a low-level second selection signal Ps can be output through the second output node NC2.

[0167] Also, the seventh transistor T7 and the eighth transistor T8 can be connected in parallel between a first power supply voltage wiring that provides a first power supply voltage VGH and the second output node NC2. Accordingly, when at least one of the seventh transistor T7 and the eighth transistor T8 is turned on, the second output node NC2 and the first power supply voltage wiring that provides the first power supply voltage VGH are electrically connected, and a high-level second selection signal Ps can be output through the second output node NC2.

[0168] Thus, the fifth transistor T5 and the sixth transistor T6 can function as a pull-up part of the second selection signal output unit SGL2, and the seventh transistor T7 and the eighth transistor T8 can function as a pull-down part of the second selection signal output unit SGL2. For example, the fifth transistor T5 and the sixth transistor T6 can be defined as a second pull-up part, and the seventh transistor T7 and the eighth transistor T8 can be defined as a second pull-down part.

[0169] FIG. 9 is a diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 8.

[0170] FIGS. 10A to 10D are equivalent circuit diagrams for explaining an example of the operation of the selection signal generation circuit of FIG. 8.

[0171] Referring to FIGS. 8 and 9, the first selection signal generation circuit SLC1 can output a low-level first selection signal Ss and a high-level second selection signal Ps, or a high-level first selection signal Ss and a low-level second selection signal Ps based on the first to fourth control signals S_V, S_H, P_V, and P_H. That is, the first selection signal generation circuit SLC1 can output the first selection signal Ss and the second selection signal Ps having voltage levels opposite to each other.

[0172] For example, further referring to FIG. 10A, when the first control signal S_V and the second control signal S_H are at a low level, that is, at a turn-on level, and the third control signal P_V and the fourth control signal P_H are at a high level, that is, at a turn-off level, the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned off.

[0173] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is provided to the first output node NC1 through the turned-on first transistor T1 or the turned-on second transistor T2, and a first selection signal Ss having a low level of the second power supply voltage VGL, that is, a turn-on level, can be output. Also, the first power supply voltage VGH provided from the first power supply voltage wiring is provided to the second output node NC2 through the turned-on seventh transistor T7 or the turned-on eighth transistor T8, and a second selection signal Ps having a high level of the first power supply voltage VGH, that is, a turn-off level, can be output.

[0174] Next, referring further to FIG. 10b, when the second control signal S_H and the third control signal P_V are at a low level, that is, a turn-on level, and the first control signal S_V and the fourth control signal P_H are at a high level, that is, a turn-off level, the second transistor T2, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 can be turned off.

[0175] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is provided to the first output node NC1 through the turned-on second transistor T2, and a first selection signal Ss having a low level of the second power supply voltage VGL, that is, a turn-on level, can be output. Also, the first power supply voltage VGH provided from the first power supply voltage wiring is provided to the second output node NC2 through the turned-on eighth transistor T8, and a second selection signal Ps having a high level of the first power supply voltage VGH, that is, a turn-off level, can be output.

[0176] On the other hand, even if the third transistor T3 is turned on, the fourth transistor T4 connected in series with the third transistor T3 is turned off, so that the first power supply voltage VGH cannot be provided to the first output node NC1. Similarly, even if the sixth transistor T6 is turned on, the fifth transistor T5 connected in series with the sixth transistor T6 is turned off, so that the second power supply voltage VGL cannot be provided to the second output node NC2.

[0177] Next, referring further to FIG. 10c, when the second control signal S_H and the third control signal P_V are at a high level, i.e., a turn-off level, and the first control signal S_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the second transistor T2, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are turned off, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 can be turned on.

[0178] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is provided to the first output node NC1 through the turned-on first transistor T1, and the first selection signal Ss having a low level of the second power supply voltage VGL, i.e., a turn-on level, can be output. Also, the first power supply voltage VGH provided from the first power supply voltage wiring is provided to the second output node NC2 through the turned-on seventh transistor T7, and the second selection signal Ps having a high level of the first power supply voltage VGH, i.e., a turn-off level, can be output.

[0179] On the other hand, even if the fourth transistor T4 is turned on, the third transistor T3 connected in series with the fourth transistor T4 is turned off, so that the first power supply voltage VGH cannot be provided to the first output node NC1. Similarly, even if the fifth transistor T5 is turned on, the sixth transistor T6 connected in series with the fifth transistor T5 is turned off, so that the second power supply voltage VGL cannot be provided to the second output node NC2.

[0180] Finally, referring further to FIG. 10d, when the first control signal S_V and the second control signal S_H are at a high level, i.e., the turn-off level, and the third control signal P_V and the fourth control signal P_H are at a low level, i.e., the turn-on level, the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned on.

[0181] In this case, the first power supply voltage VGH provided from the first power supply voltage wiring is connected in series with each other and provided to the first output node NC1 through the turned-on third transistor T3 and the turned-on fourth transistor T4, and a first selection signal Ss having a high level of the first power supply voltage VGH, i.e., the turn-off level, can be output. Also, the second power supply voltage VGL provided from the second power supply voltage wiring is connected in series with each other and provided to the second output node NC2 through the turned-on fifth transistor T5 and the turned-on sixth transistor T6, and a second selection signal Ps having a low level of the second power supply voltage VGL, i.e., the turn-on level, can be output.

[0182] In this way, the first selection signal generation circuit SLC1 can provide the first selection signal Ss and the second selection signal Ps having mutually opposite voltage levels to the pixel PX to control the driving mode of the pixel PX.

[0183] For example, when a low-level first selection signal Ss and a high-level second selection signal Ps are provided to the pixel PX, the first selection transistor TP1 is turned on, the second selection transistor TP2 is turned off, and a first driving current can be provided to the first light-emitting element ED1. In this case, the first light-emitting element ED1 can provide light at a wide viewing angle, which is the first viewing angle, through the first optical member 161.

[0184] Also, when a high-level first selection signal Ss and a low-level second selection signal Ps are provided to the pixel PX, the first selection transistor TP1 is turned off, and the second selection transistor TP2 is turned on, so that a second drive current can be provided to the second light-emitting element ED2. In this case, the second light-emitting element ED2 can provide light through the second optical member 162 at a narrow viewing angle which is the second viewing angle.

[0185] In this way, the selection signal generation unit SLG to which the first selection signal generation circuit SLC1 is applied provides the first selection signal Ss and the second selection signal Ps having mutually opposite voltage levels to the pixel PX, and can control at least one corresponding pixel PX in the first mode or the second mode.

[0186] FIG. 11 is a circuit diagram showing another example of the pixel circuit included in the display device of FIG. 2.

[0187] On the other hand, the second pixel circuit PC2 shown in FIG. 11 shows another embodiment of the pixel circuit corresponding to each of the plurality of pixels PX included in the display device 100 described with reference to FIG. 2. For example, FIG. 11 shows a modified embodiment with respect to the embodiment of FIG. 4 in relation to the selection transistors TP3 and TP4. Here, in FIG. 11, in order to avoid redundant description, the description will be centered on the differences from the embodiment of FIG. 4.

[0188] Referring to FIG. 11, the second pixel circuit PC2 can include a drive transistor DT, a plurality of switching transistors ST1 to ST6, a plurality of selection transistors TP3 and TP4, a storage capacitor Cst, and a plurality of light-emitting elements ED1 and ED2.

[0189] The plurality of selection transistors TP3 and TP4 can include a third selection transistor TP3 for generating a current path of the first drive current passing through the first light-emitting element ED1, and a fourth selection transistor TP4 for generating a current path of the second drive current passing through the second light-emitting element ED2.

[0190] The third selection transistor TP3 is connected between the fourth node N4 and the first light-emitting element ED1, and the gate electrode of the third selection transistor TP3 can be connected to a selection signal wiring that provides a selection signal MS.

[0191] The fourth selection transistor TP4 is connected between the fourth node N4 and the second light-emitting element ED2, and the gate electrode of the fourth selection transistor TP4 can be connected to a selection signal wiring that provides a selection signal MS.

[0192] The third selection transistor TP3 may be an n-type transistor, and the fourth selection transistor TP4 may be a p-type transistor. Thus, when a low-level selection signal MS is supplied to the selection signal wiring, the third selection transistor TP3 can be turned off and the fourth selection transistor TP4 can be turned on in response to the low-level selection signal MS. Also, when a high-level selection signal MS is supplied to the selection signal wiring, the third selection transistor TP3 can be turned on and the fourth selection transistor TP4 can be turned off in response to the high-level selection signal MS.

[0193] Therefore, when the pixel PX to which the second pixel circuit PC2 is applied is driven in a first mode which is a wide-view mode, a high-level selection signal MS is supplied to the gate electrode of the third selection transistor TP3 and the gate electrode of the fourth selection transistor TP4, respectively, so that the third selection transistor TP3 can be turned on and the fourth selection transistor TP4 can be turned off. Therefore, a current path of the first drive current through the first light-emitting element ED1 is formed, and the first light-emitting element ED1 can emit light. On the other hand, since the second drive current is not formed by the turned-off fourth selection transistor TP4, the second light-emitting element ED2 can be non-luminous.

[0194] Also, when the pixel PX to which the second pixel circuit PC2 is applied is driven in a second mode which is a narrow viewing angle mode, a low-level selection signal MS is supplied to the gate electrode of the third selection transistor TP3 and the gate electrode of the fourth selection transistor TP4 respectively, so that the third selection transistor TP3 is turned off and the fourth selection transistor TP4 can be turned on. Therefore, a current path of the second drive current through the second light-emitting element ED2 is formed, and the second light-emitting element ED2 can emit light. On the other hand, since the first drive current is not formed by the turned-off third selection transistor TP3, the first light-emitting element ED1 cannot emit light.

[0195] The first light-emitting element ED1 can be connected between the third selection transistor TP3 which is turned on or off by the selection signal MS and the low-potential power supply wiring that provides the low-potential power supply voltage VSS. The second light-emitting element ED2 can be connected between the fourth selection transistor TP4 which is turned on or off by the selection signal MS and the low-potential power supply wiring that provides the low-potential power supply voltage VSS.

[0196] In such a case, the first light-emitting element ED1 or the second light-emitting element ED2 can be connected to other components of the second pixel circuit PC2, such as the drive transistor DT, by the third selection transistor TP3 or the fourth selection transistor TP4 that is turned on according to the drive mode. For example, the first light-emitting element ED1 is connected to the drive transistor DT via the third selection transistor TP3 that is turned on in the first mode, and the first drive current can provide light at a wide viewing angle which is the first viewing angle in the first mode, i.e., the wide viewing angle mode. Also, the second light-emitting element ED2 is connected to the drive transistor DT via the fourth selection transistor TP4 that is turned on in the second mode, and the second drive current can provide light at a narrow viewing angle which is the second viewing angle in the second mode, i.e., the narrow viewing angle mode. Here, the drive mode can be determined when specified by the user's input or when meeting a pre-specified condition.

[0197] FIG. 12 is a circuit diagram showing another example of the selection signal generation circuit included in the display device of FIG. 2.

[0198] On the other hand, the second selection signal generation circuit SLC2 shown in FIG. 12 shows another embodiment of the selection signal generation circuit corresponding to each of the plurality of selection signal generation units SLG included in the display device 100 described with reference to FIGS. 2 to 3e. The selection signal generation unit SLG including the second selection signal generation circuit SLC2 can provide a selection signal to the pixel PX including the second pixel circuit PC2 described with reference to FIG. 11.

[0199] Referring to FIG. 12, the plurality of transistors included in the second selection signal generation circuit SLC2 may be n-type transistors or p-type transistors. In the following, for the sake of convenience of explanation, it is described on the basis that the plurality of transistors T9 to T12 included in the second selection signal generation circuit SLC2 are p-type transistors, but at least a part of the plurality of transistors T9 to T12 included in the second selection signal generation circuit SLC2 can be modified to n-type transistors.

[0200] The second selection signal generation circuit SLC2 can generate a selection signal MS based on the first to fourth control signals S_V, S_H, P_V, P_H, the first power supply voltage VGH, and the second power supply voltage VGL.

[0201] The second selection signal generation circuit SLC2 can output a high-level or low-level selection signal MS through the third output node NC3 by controlling the voltage of the third output node NC3 to the high-level first power supply voltage VGH or the low-level second power supply voltage VGL. For this purpose, the second selection signal generation circuit SLC2 can include the ninth to twelfth transistors T9 to T12.

[0202] The ninth transistor T9 can be connected between a second power supply voltage wiring that provides a second power supply voltage VGL and a third output node NC3. For example, a first electrode of the ninth transistor T9 can be connected to the second power supply voltage wiring, and a second electrode of the ninth transistor T9 can be connected to the third output node NC3. A gate electrode of the ninth transistor T9 can be connected to a first control signal wiring that provides a first control signal S_V. The ninth transistor T9 can be turned on when a turn-on level, for example, a low-level first control signal S_V is supplied, and the third output node NC3 and the second power supply voltage wiring can be electrically connected. In this case, the second power supply voltage VGL is provided to the third output node NC3, and the second selection signal generation circuit SLC2 can output a low-level selection signal MS.

[0203] The tenth transistor T10 can be connected between a second power supply voltage wiring that provides a second power supply voltage VGL and a third output node NC3. For example, a first electrode of the tenth transistor T10 can be connected to the second power supply voltage wiring, and a second electrode of the tenth transistor T10 can be connected to the third output node NC3. A gate electrode of the tenth transistor T10 can be connected to a second control signal wiring that provides a second control signal S_H. The tenth transistor T10 can be turned on when a turn-on level, for example, a low-level second control signal S_H is supplied, and the third output node NC3 and the second power supply voltage wiring can be electrically connected. In this case, the second power supply voltage VGL is provided to the third output node NC3, and the second selection signal generation circuit SLC2 can output a low-level selection signal MS.

[0204] The 11th transistor T11 can be connected between a first power supply voltage wiring that provides a first power supply voltage VGH and a third output node NC3. For example, a first electrode of the 11th transistor T11 can be connected to the 12th transistor T12, and a second electrode of the 11th transistor T11 can be connected to the third output node NC3. A gate electrode of the 11th transistor T11 can be connected to a third control signal wiring that provides a third control signal P_V. The 11th transistor T11 can be turned on when a turn-on level, for example, a low-level third control signal P_V is supplied, and can electrically connect the third output node NC3 and the 12th transistor T12.

[0205] The 12th transistor T12 can be connected between the 11th transistor T11 and a first power supply voltage wiring that provides a first power supply voltage VGH. For example, a first electrode of the 12th transistor T12 can be connected to the first power supply voltage wiring, and a second electrode of the 12th transistor T12 can be connected to a first electrode of the 11th transistor T11. A gate electrode of the 12th transistor T12 can be connected to a fourth control signal wiring that provides a fourth control signal P_H. The 12th transistor T12 can be turned on when a turn-on level, for example, a low-level fourth control signal P_H is supplied, and can electrically connect the 11th transistor T11 and a second power supply voltage wiring.

[0206] The 9th transistor T9 and the 10th transistor T10 can be connected in parallel between a second power supply voltage wiring that provides a second power supply voltage VGL and a third output node NC3. Thereby, when at least one of the 9th transistor T9 and the 10th transistor T10 is turned on, the third output node NC3 and the second power supply voltage wiring that provides the second power supply voltage VGL are electrically connected, and a low-level selection signal MS can be output through the third output node NC3.

[0207] Also, the 11th transistor T11 and the 12th transistor T12 can be connected in series between a first power supply voltage wiring that provides a first power supply voltage VGH and a third output node NC3. Thus, when both the 11th transistor T11 and the 12th transistor T12 are turned on, the third output node NC3 and the first power supply voltage wiring that provides the first power supply voltage VGH are electrically connected, and a high-level selection signal MS can be output through the third output node NC3.

[0208] In this way, the 9th transistor T9 and the 10th transistor T10 can function as a pull-up part of the second selection signal generation circuit SLC2, and the 11th transistor T11 and the 12th transistor T12 can function as a pull-down part of the second selection signal generation circuit SLC2. For example, the 9th transistor T9 and the 10th transistor T10 can be defined as a third pull-up part, and the 11th transistor T11 and the 12th transistor T12 can be defined as a third pull-down part.

[0209] FIG. 13 is a diagram for explaining an example of the operation of the selection signal generation circuit in FIG. 12.

[0210] FIGS. 14a to 14d are equivalent circuit diagrams for explaining an example of the operation of the selection signal generation circuit in FIG. 12.

[0211] Referring to FIGS. 12 and 13, the second selection signal generation circuit SLC2 can output a low-level selection signal MS or a high-level selection signal MS based on the first to fourth control signals S_V, S_H, P_V, and P_H.

[0212] For example, further referring to FIG. 14a, when the first control signal S_V and the second control signal S_H are at a low level, that is, at a turn-on level, and the third control signal P_V and the fourth control signal P_H are at a high level, that is, at a turn-off level, the 9th transistor T9 and the 10th transistor T10 can be turned on, and the 11th transistor T11 and the 12th transistor T12 can be turned off.

[0213] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is provided to the third output node NC3 through the turned-on ninth transistor T9 or the turned-on tenth transistor T10, and a selection signal MS having a low level of the second power supply voltage VGL can be output.

[0214] Next, referring further to FIG. 14b, when the second control signal S_H and the third control signal P_V are at a low level, i.e., the turn-on level, and the first control signal S_V and the fourth control signal P_H are at a high level, i.e., the turn-off level, the tenth transistor T10 and the eleventh transistor T11 can be turned on, and the ninth transistor T9 and the twelfth transistor T12 can be turned off.

[0215] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is provided to the third output node NC3 through the turned-on tenth transistor T10, and a selection signal MS having a low level of the second power supply voltage VGL can be output.

[0216] On the other hand, even if the eleventh transistor T11 is turned on, the twelfth transistor T12 connected in series with the eleventh transistor T11 is turned off, so that the first power supply voltage VGH cannot be provided to the third output node NC3.

[0217] Next, referring further to FIG. 14c, when the second control signal S_H and the third control signal P_V are at a high level, i.e., the turn-off level, and the first control signal S_V and the fourth control signal P_H are at a low level, i.e., the turn-on level, the ninth transistor T9 and the twelfth transistor T12 can be turned off, and the tenth transistor T10 and the eleventh transistor T11 can be turned on.

[0218] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is provided to the third output node NC3 through the turned-on ninth transistor T9, and a selection signal MS having a low level of the second power supply voltage VGL can be output.

[0219] On the other hand, even if the 12th transistor T12 is turned on, the 11th transistor T11 connected in series with the 12th transistor T12 is turned off, so that the first power supply voltage VGH cannot be provided to the third output node NC3.

[0220] Finally, referring further to FIG. 14d, when the first control signal S_V and the second control signal S_H are at a high level, i.e., a turn-off level, and the third control signal P_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the 9th transistor T9 and the 10th transistor T10 are turned off, and the 11th transistor T11 and the 12th transistor T12 can be turned on.

[0221] In this case, the first power supply voltage VGH provided from the first power supply voltage wiring is connected in series with each other and provided to the third output node NC3 through the turned-on 11th transistor T11 and the turned-on 12th transistor T12, and a selection signal MS having a high level of the first power supply voltage VGH can be output.

[0222] In this way, the second selection signal generation circuit SLC2 can provide a selection signal MS having a high level to the pixel PX in the first mode and provide a selection signal MS having a low level to the pixel PX in the second mode to control the driving mode of the pixel PX.

[0223] For example, when a high-level selection signal MS is provided to the pixel PX, the third selection transistor TP3 is turned on and the fourth selection transistor TP4 is turned off, so that a first driving current can be provided to the first light-emitting element ED1. In this case, the first light-emitting element ED1 can provide light through the first optical member 161 at a wide viewing angle which is the first viewing angle.

[0224] Also, when a low-level selection signal MS is provided to the pixel PX, the third selection transistor TP3 is turned off, and the fourth selection transistor TP4 is turned on, so that the second drive current can be provided to the second light-emitting element ED2. In this case, the second light-emitting element ED2 can provide light through the second optical member 162 at a narrow viewing angle which is the second viewing angle.

[0225] In this way, the selection signal generation unit SLG to which the second selection signal generation circuit SLC2 is applied provides the selection signal MS having different voltage levels in each mode to the pixel PX, and can control at least one corresponding pixel PX in the first mode or the second mode.

[0226] Also, as described with reference to FIGS. 11 to 14d, by commonly connecting the gate electrodes of the selection transistors TP3 and TP4 included in the pixel circuit of the pixel PX to the same selection signal MS and controlling the voltage level of the selection signal MS according to the driving mode, the number of selection signal wirings for controlling the selection transistors TP3 and TP4 can be reduced, and the number of transistors in the selection signal generation circuit of the selection signal generation unit SLG is reduced, so that the selection signal generation circuit for generating the selection signal can be simplified.

[0227] FIG. 15 is a circuit diagram showing still another example of the selection signal generation circuit included in the display device of FIG. 2.

[0228] On the other hand, the third selection signal generation circuit SLC3 shown in FIG. 15 shows still another embodiment of the selection signal generation circuit corresponding to each of the plurality of selection signal generation units SLG included in the display device 100 described with reference to FIGS. 2 to 3e. The selection signal generation unit SLG including the third selection signal generation circuit SLC3 can provide a selection signal to the pixel PX including the second pixel circuit PC2 described with reference to FIG. 11.

[0229] Referring to FIG. 15, the plurality of transistors included in the third selection signal generation circuit SLC3 may be n-type transistors or p-type transistors. In the following, for convenience of explanation, it will be described on the basis that the plurality of transistors T13 to T16 included in the third selection signal generation circuit SLC3 are p-type transistors. However, at least a part of the plurality of transistors T13 to T16 included in the third selection signal generation circuit SLC3 can be modified to n-type transistors.

[0230] The third selection signal generation circuit SLC3 can generate a selection signal MS based on the first to fourth control signals S_V, S_H, P_V, P_H, the first power supply voltage VGH, and the second power supply voltage VGL.

[0231] The third selection signal generation circuit SLC3 can output a high-level or low-level selection signal MS through the fourth output node NC4 by controlling the voltage of the fourth output node NC4 to the high-level first power supply voltage VGH or the low-level second power supply voltage VGL. For this purpose, the third selection signal generation circuit SLC3 can include the 13th to 16th transistors T13 to T16.

[0232] The 13th transistor T13 can be connected between the second power supply voltage wiring that provides the second power supply voltage VGL and the fourth output node NC4. For example, the first electrode of the 13th transistor T13 can be connected to the second power supply voltage wiring, and the second electrode of the 13th transistor T13 can be connected to the 14th transistor T14. The gate electrode of the 13th transistor T13 can be connected to the fourth control signal wiring that provides the fourth control signal P_H. The 13th transistor T13 can be turned on when a turn-on level, for example, a low-level fourth control signal P_H is supplied, and the second power supply voltage wiring and the 14th transistor T14 can be electrically connected.

[0233] The 14th transistor T14 can be connected between the 13th transistor T13 and the 4th output node NC4. For example, the first electrode of the 14th transistor T14 can be connected to the second electrode of the 13th transistor T13, and the second electrode of the 14th transistor T14 can be connected to the 4th output node NC4. The gate electrode of the 14th transistor T14 can be connected to a third control signal wiring that provides a third control signal P_V. The 14th transistor T14 can be turned on when a turn-on level, for example, a low-level third control signal P_V is supplied, and the 13th transistor T13 and the 4th output node NC4 can be electrically connected.

[0234] The 15th transistor T15 can be connected between a first power supply voltage wiring that provides a first power supply voltage VGH and the 4th output node NC4. For example, the first electrode of the 15th transistor T15 can be connected to the first power supply voltage wiring, and the second electrode of the 15th transistor T15 can be connected to the 4th output node NC4. The gate electrode of the 15th transistor T15 can be connected to a first control signal wiring that provides a first control signal S_V. The 15th transistor T15 can be turned on when a turn-on level, for example, a low-level first control signal S_V is supplied, and the 4th output node NC4 and the first power supply voltage wiring can be electrically connected. In this case, the first power supply voltage VGH is provided to the 4th output node NC4, and the 3rd selection signal generation circuit SLC3 can output a high-level selection signal MS.

[0235] The 16th transistor T16 can be connected between a first power supply voltage wiring that provides a first power supply voltage VGH and a fourth output node NC4. For example, a first electrode of the 16th transistor T16 can be connected to the first power supply voltage wiring, and a second electrode of the 16th transistor T16 can be connected to the fourth output node NC4. A gate electrode of the 16th transistor T16 can be connected to a second control signal wiring that provides a second control signal S_H. The 16th transistor T16 can be turned on when a turn-on level, for example, a low-level second control signal S_H is supplied, and the fourth output node NC4 and the first power supply voltage wiring can be electrically connected. In this case, the first power supply voltage VGH is provided to the fourth output node NC4, and the third selection signal generation circuit SLC3 can output a high-level selection signal MS.

[0236] The 13th transistor T13 and the 14th transistor T14 can be connected in series between a second power supply voltage wiring that provides a second power supply voltage VGL and the fourth output node NC4. Thereby, when both the 13th transistor T13 and the 14th transistor T14 are turned on, the fourth output node NC4 and the second power supply voltage wiring that provides the second power supply voltage VGL are electrically connected, and a low-level selection signal MS can be output through the fourth output node NC4.

[0237] Also, the 15th transistor T15 and the 16th transistor T16 can be connected in parallel between a first power supply voltage wiring that provides a first power supply voltage VGH and the fourth output node NC4. Thereby, when at least one of the 15th transistor T15 and the 16th transistor T16 is turned on, the fourth output node NC4 and the first power supply voltage wiring that provides the first power supply voltage VGH are electrically connected, and a high-level selection signal MS can be output through the fourth output node NC4.

[0238] As described above, the 13th transistor T13 and the 14th transistor T14 can function as a pull-up part of the third selection signal generation circuit SLC3, and the 15th transistor T15 and the 16th transistor T16 can function as a pull-down part of the third selection signal generation circuit SLC3. For example, the 13th transistor T13 and the 14th transistor T14 can be defined as a fourth pull-up part, and the 15th transistor T15 and the 16th transistor T16 can be defined as a fourth pull-down part.

[0239] FIG. 16 is a diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 15.

[0240] FIGS. 17A to 17D are equivalent circuit diagrams for explaining an example of the operation of the selection signal generation circuit of FIG. 15.

[0241] Referring to FIGS. 15 and 16, the third selection signal generation circuit SLC3 can output a low-level selection signal MS or a high-level selection signal MS based on the first to fourth control signals S_V, S_H, P_V, and P_H.

[0242] For example, further referring to FIG. 17A, when the first control signal S_V and the second control signal S_H are at a low level, that is, the turn-on level, and the third control signal P_V and the fourth control signal P_H are at a high level, that is, the turn-off level, the 15th transistor T15 and the 16th transistor T16 can be turned on, and the 13th transistor T13 and the 14th transistor T14 can be turned off.

[0243] In this case, the first power supply voltage VGH provided from the first power supply voltage wiring is provided to the fourth output node NC4 through the turned-on 15th transistor T15 or the turned-on 16th transistor T16, and a selection signal MS having a high level of the first power supply voltage VGH can be output.

[0244] Next, referring further to FIG. 17b, when the second control signal S_H and the third control signal P_V are at a low level, i.e., the turn-on level, and the first control signal S_V and the fourth control signal P_H are at a high level, i.e., the turn-off level, the fourteenth transistor T14 and the sixteenth transistor T16 can be turned on, and the thirteenth transistor T13 and the fifteenth transistor T15 can be turned off.

[0245] In this case, the first power supply voltage VGH provided from the first power supply voltage wiring is provided to the fourth output node NC4 through the turned-on sixteenth transistor T16, and a selection signal MS having a high level of the first power supply voltage VGH can be output.

[0246] On the other hand, even if the fourteenth transistor T14 is turned on, since the thirteenth transistor T13 connected in series with the fourteenth transistor T14 is turned off, the second power supply voltage VGL cannot be provided to the fourth output node NC4.

[0247] Next, referring further to FIG. 17c, when the second control signal S_H and the third control signal P_V are at a high level, i.e., the turn-off level, and the first control signal S_V and the fourth control signal P_H are at a low level, i.e., the turn-on level, the fourteenth transistor T14 and the sixteenth transistor T16 can be turned off, and the thirteenth transistor T13 and the fifteenth transistor T15 can be turned on.

[0248] In this case, the first power supply voltage VGH provided from the first power supply voltage wiring is provided to the fourth output node NC4 through the turned-on fifteenth transistor T15, and a selection signal MS having a high level of the first power supply voltage VGH can be output.

[0249] On the other hand, even if the thirteenth transistor T13 is turned on, since the fourteenth transistor T14 connected in series with the thirteenth transistor T13 is turned off, the second power supply voltage VGL cannot be provided to the fourth output node NC4.

[0250] Finally, referring further to FIG. 17d, when the first control signal S_V and the second control signal S_H are at a high level, i.e., a turn-off level, and the third control signal P_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the 15th transistor T15 and the 16th transistor T16 are turned off, and the 13th transistor T13 and the 14th transistor T14 can be turned on.

[0251] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is connected in series with each other and provided to the fourth output node NC4 through the turned-on 13th transistor T13 and the turned-on 14th transistor T14, and a selection signal MS having a low level of the second power supply voltage VGL can be output.

[0252] In this way, the third selection signal generation circuit SLC3 can provide a selection signal MS having a high level in the first mode to the pixel PX, and provide a selection signal MS having a low level in the second mode to the pixel PX to control the driving mode of the pixel PX.

[0253] For example, when a high-level selection signal MS is provided to the pixel PX, the third selection transistor TP3 is turned on, the fourth selection transistor TP4 is turned off, and a first drive current can be provided to the first light-emitting element ED1. In this case, the first light-emitting element ED1 can provide light through the first optical member 161 at a wide viewing angle which is the first viewing angle.

[0254] Also, when a low-level selection signal MS is provided to the pixel PX, the third selection transistor TP3 is turned off, the fourth selection transistor TP4 is turned on, and a second drive current can be provided to the second light-emitting element ED2. In this case, the second light-emitting element ED2 can provide light through the second optical member 162 at a narrow viewing angle which is the second viewing angle.

[0255] In this way, the selection signal generation unit SLG to which the third selection signal generation circuit SLC3 is applied can provide a selection signal MS having different voltage levels in each mode to the pixel PX, thereby controlling at least one corresponding pixel PX to the first mode or the second mode.

[0256] Furthermore, as explained with reference to Figures 11 and 15 to 17d, by commonly connecting the gate electrodes of the selection transistors TP3 and TP4 included in the pixel circuit of the pixel PX to the same selection signal MS and controlling the voltage level of the selection signal MS by the drive mode, the number of selection signal wirings for controlling the selection transistors TP3 and TP4 can be reduced, the number of transistors in the selection signal generation circuit of the selection signal generation unit SLG can be reduced, and the selection signal generation circuit for generating the selection signal can be simplified.

[0257] A display device according to an embodiment of the present specification can be described as follows.

[0258] A display device according to an embodiment of the present specification may include a display panel including a display area and a non-display area surrounding the display area, the display panel including a plurality of pixels arranged on the display area and a plurality of selection signal generators, and a timing controller for controlling the display panel. Each of the plurality of pixels may include a first light-emitting element, a first optical member that refracts light from the first light-emitting element, a second light-emitting element that emits the same color as the first light-emitting element, and a second optical member that refracts light from the second light-emitting element and has a shape different from that of the first optical member. Each of the plurality of selection signal generators may control one of the first light-emitting element and the second light-emitting element included in a corresponding one of the plurality of pixels to emit light.

[0259] According to another feature of the present specification, each of the plurality of pixels may further include a drive transistor that generates a first drive current flowing from a high potential power supply wiring that provides a high potential power supply voltage to a low potential power supply wiring that provides a low potential power supply voltage through a first light-emitting element and a second drive current flowing from the high potential power supply wiring to the low potential power supply wiring through a second light-emitting element, a first selection transistor connected between the drive transistor and the first light-emitting element and turned on in response to a first selection signal supplied to a first selection signal wiring, and a second selection transistor connected between the drive transistor and the second light-emitting element and turned on in response to a second selection signal supplied to a second selection signal wiring.

[0260] According to another feature of the present specification, each of the plurality of selection signal generation units includes a first selection signal output unit that outputs a first selection signal through a first output node based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage, and a second selection signal output unit that outputs a second selection signal through a second output node based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage.

[0261] According to another feature of the present specification, the first selection signal output unit may include a first transistor connected between a second power supply voltage wiring providing a second power supply voltage and a first output node and turned on in response to a first control signal, a second transistor connected between the second power supply voltage wiring and the first output node and turned on in response to the second control signal, a third transistor connected between the first output node and a first power supply voltage wiring providing the first power supply voltage and turned on in response to a third control signal, and a fourth transistor connected between the third transistor and the first power supply voltage wiring and turned on in response to a fourth control signal.

[0262] According to still another feature of the present specification, the first transistor and the second transistor may be connected in parallel between the second power supply voltage wiring and the first output node, and the third transistor and the fourth transistor may be connected in series between the first power supply voltage wiring and the first output node.

[0263] According to another feature of the present specification, the second selection signal output unit may include a fifth transistor connected between a second power supply voltage wiring providing a second power supply voltage and a second output node and turned on in response to a fourth control signal, a sixth transistor connected between the fifth transistor and the second output node and turned on in response to a third control signal, a seventh transistor connected between the second output node and a first power supply voltage wiring providing the first power supply voltage and turned on in response to the first control signal, and an eighth transistor connected between the second output node and the first power supply voltage wiring and turned on in response to the second control signal.

[0264] According to still another feature of the present specification, the fifth transistor and the sixth transistor may be connected in series between the second power supply voltage wiring and the second output node, and the seventh transistor and the eighth transistor may be connected in parallel between the first power supply voltage wiring and the second output node.

[0265] According to another feature of the present specification, each of the plurality of pixels may further include a drive transistor that generates a first drive current flowing from a high potential power supply wiring that provides a high potential power supply voltage to a low potential power supply wiring that provides a low potential power supply voltage through a first light-emitting element and a second drive current flowing from the high potential power supply wiring to the low potential power supply wiring through a second light-emitting element, a third selection transistor connected between the drive transistor and the first light-emitting element and turned on in response to a selection signal supplied to the selection signal wiring, and a fourth selection transistor connected between the drive transistor and the second light-emitting element and turned on in response to the selection signal.

[0266] According to yet another feature of the present disclosure, the third select transistor may be an n-type transistor and the fourth select transistor may be a p-type transistor.

[0267] According to another feature of the present specification, each of the plurality of selection signal generating units can output a selection signal having a high level or a low level based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage.

[0268] According to still other features of the present specification, each of the plurality of selection signal generation units is connected between a second power supply voltage wiring that provides a second power supply voltage and a third output node, and includes a ninth transistor that is turned on in response to a first control signal, a tenth transistor that is connected between the second power supply voltage wiring and the third output node and is turned on in response to a second control signal, an eleventh transistor that is connected between the third output node and a first power supply voltage wiring that provides a first power supply voltage and is turned on in response to a third control signal, and a twelfth transistor that is connected between the eleventh transistor and the first power supply voltage wiring and is turned on in response to a fourth control signal.

[0269] According to still other features of the present specification, the ninth transistor and the tenth transistor may be connected in parallel between the second power supply voltage wiring and the third output node, and the eleventh transistor and the twelfth transistor may be connected in series between the first power supply voltage wiring and the third output node.

[0270] According to still other features of the present specification, each of the plurality of selection signal generation units is connected between a second power supply voltage wiring that provides a second power supply voltage and a fourth output node, and includes a thirteenth transistor that is turned on in response to a fourth control signal, a fourteenth transistor that is connected between the thirteenth transistor and the fourth output node and is turned on in response to a third control signal, a fifteenth transistor that is connected between the fourth output node and a first power supply voltage wiring that provides a first power supply voltage and is turned on in response to a first control signal, and a sixteenth transistor that is connected between the fourth output node and the first power supply voltage wiring and is turned on in response to a second control signal.

[0271] According to still other features of the present specification, the thirteenth transistor and the fourteenth transistor may be connected in series between the second power supply voltage wiring and the fourth output node, and the fifteenth transistor and the sixteenth transistor may be connected in parallel between the first power supply voltage wiring and the fourth output node.

[0272] According to still other features of this specification, each of the plurality of selection signal generation units can control one of the first light emitting element and the second light emitting element included in one pixel among the plurality of pixels to emit light.

[0273] According to still other features of this specification, each of the plurality of selection signal generation units can control one of the first light emitting element and the second light emitting element included in each of at least two pixels among the plurality of pixels to emit light.

[0274] As described above, with reference to the accompanying drawings, the embodiments of this specification have been described in more detail. However, this specification is not necessarily limited to such embodiments, and various modifications can be made within the scope not departing from the technical idea of this specification. Therefore, the embodiments disclosed in this specification are not for limiting the technical idea of this specification, but for explaining it, and the scope of the technical idea of this specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and not restrictive.

Claims

1. A display panel including a display area and a non-display area arranged to surround the display area, the display panel including a plurality of pixels and a plurality of selection signal generation units arranged on the display area; A timing controller for controlling the display panel; Each of the plurality of pixels includes: A first light-emitting element; A first optical member for refracting light from the first light-emitting element; A second light-emitting element that emits the same color as the first light-emitting element; A second optical member for refracting light from the second light-emitting element and having a shape different from that of the first optical member; Each of the plurality of selection signal generation units controls at least one corresponding pixel among the plurality of pixels such that either the first light-emitting element or the second light-emitting element included therein emits light. A display device.

2. Each of the plurality of pixels further includes: A driving transistor for generating a first driving current flowing from a high-potential power supply wiring providing a high-potential power supply voltage, through the first light-emitting element, to a low-potential power supply wiring providing a low-potential power supply voltage, and a second driving current flowing from the high-potential power supply wiring, through the second light-emitting element, to the low-potential power supply wiring; A first selection transistor connected between the driving transistor and the first light-emitting element and turned on in response to a first selection signal supplied to a first selection signal wiring; A second selection transistor connected between the driving transistor and the second light-emitting element and turned on in response to a second selection signal supplied to a second selection signal wiring. The display device according to Claim 1.

3. Each of the plurality of selection signal generation units includes: A first selection signal output unit for outputting the first selection signal through a first output node based on first to fourth control signals, a first power supply voltage, and a second power supply voltage; A second selection signal output unit for outputting the second selection signal through a second output node based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage. The display device according to Claim 2.

4. The first selection signal output unit includes: A first transistor connected between a second power supply voltage wiring providing the second power supply voltage and the first output node and turned on in response to the first control signal; A second transistor connected between the second power supply voltage wiring and the first output node and turned on in response to the second control signal; A third transistor connected between the first output node and a first power supply voltage wiring that provides the first power supply voltage, the third transistor being turned on in response to the third control signal; The display device according to claim 3, further comprising a fourth transistor connected between the third transistor and the first power supply voltage wiring, the fourth transistor being turned on in response to the fourth control signal.

5. The first transistor and the second transistor are connected in parallel between the second power supply voltage wiring and the first output node. The display device according to claim 4, wherein the third transistor and the fourth transistor are connected in series between the first power supply voltage wiring and the first output node.

6. The second selection signal output unit A fifth transistor connected between a second power supply voltage wiring that provides the second power supply voltage and the second output node, the fifth transistor being turned on in response to the fourth control signal; A sixth transistor connected between the fifth transistor and the second output node, the sixth transistor being turned on in response to the third control signal; A seventh transistor connected between the second output node and a first power supply voltage wiring that provides the first power supply voltage, the seventh transistor being turned on in response to the first control signal; The display device according to claim 3, further comprising an eighth transistor connected between the second output node and the first power supply voltage wiring, the eighth transistor being turned on in response to the second control signal.

7. The fifth transistor and the sixth transistor are connected in series between the second power supply voltage wiring and the second output node. The display device according to claim 6, wherein the seventh transistor and the eighth transistor are connected in parallel between the first power supply voltage wiring and the second output node.

8. Each of the plurality of pixels A driving transistor that generates a first driving current flowing from a high-potential power supply wiring that provides a high-potential power supply voltage, through the first light-emitting element, to a low-potential power supply wiring that provides a low-potential power supply voltage, and a second driving current flowing from the high-potential power supply wiring, through the second light-emitting element, to the low-potential power supply wiring; A third selection transistor connected between the driving transistor and the first light-emitting element, the third selection transistor being turned on in response to a selection signal supplied to a selection signal wiring; The display device according to claim 1, further comprising a fourth selection transistor connected between the driving transistor and the second light-emitting element, the fourth selection transistor being turned on in response to the selection signal.

9. The display device according to claim 8, wherein the third selection transistor is an n-type transistor and the fourth selection transistor is a p-type transistor.

10. The display device according to claim 8, wherein each of the plurality of selection signal generation units outputs the selection signal having a high level or a low level based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage.

11. Each of the plurality of selection signal generation units includes a ninth transistor connected between a second power supply voltage wiring that provides the second power supply voltage and a third output node and turned on in response to the first control signal; a tenth transistor connected between the second power supply voltage wiring and the third output node and turned on in response to the second control signal; an eleventh transistor connected between the third output node and a first power supply voltage wiring that provides the first power supply voltage and turned on in response to the third control signal; and a twelfth transistor connected between the eleventh transistor and the first power supply voltage wiring and turned on in response to the fourth control signal, the display device according to claim 10.

12. The ninth transistor and the tenth transistor are connected in parallel between the second power supply voltage wiring and the third output node, and the eleventh transistor and the twelfth transistor are connected in series between the first power supply voltage wiring and the third output node, the display device according to claim 11.

13. Each of the plurality of selection signal generation units includes a thirteenth transistor connected between a second power supply voltage wiring that provides the second power supply voltage and a fourth output node and turned on in response to the fourth control signal; a fourteenth transistor connected between the thirteenth transistor and the fourth output node and turned on in response to the third control signal; a fifteenth transistor connected between the fourth output node and a first power supply voltage wiring that provides the first power supply voltage and turned on in response to the first control signal; and a sixteenth transistor connected between the fourth output node and the first power supply voltage wiring and turned on in response to the second control signal, the display device according to claim 10.

14. The thirteenth transistor and the fourteenth transistor are connected in series between the second power supply voltage wiring and the fourth output node. The display device according to claim 13, wherein the fifteenth transistor and the sixteenth transistor are connected in parallel between the first power supply voltage wiring and the fourth output node.

15. The display device according to claim 1, wherein each of the plurality of selection signal generation units controls any one of the first light-emitting element and the second light-emitting element included in one pixel among the plurality of pixels to emit light.

16. The display device according to claim 1, wherein each of the plurality of selection signal generation units controls any one of the first light-emitting element and the second light-emitting element included in at least two pixels among the plurality of pixels to emit light.

Images