Dual timing circuit

Abstract

To provide a dual timing circuit including a startup circuit set to reset a processor if a failure is detected and to have a first time-out sustention time.SOLUTION: A method for a dual timing circuit to promote automatic correction of a failure includes: allowing a startup circuit set to have a first time-out sustention time to operate in a way to assert a reset signal in response to a fact that no boot loading by a processor could have been completed in the first time-out sustention time after turning on of power. An operation circuit set to have a second time-out sustention time operates in a way to assert a reset signal in response to a fact that no strobe signal could have been received from the processor in a second time-out sustention time.SELECTED DRAWING: Figure 4

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