Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device whose reliability is improved.SOLUTION: A semiconductor device includes: a lamination structure including vertically laminated interlayer insulation layers and gate electrodes; a cell guide structure arranged on the lamination structure to define a first region; a first conductive layer arranged over the lamination structure in the first region; a protective layer arranged over the lamination structure in a second region other than the first region defined by the cell guide structure; and channel structures, each of which includes a first part vertically penetrating the lamination structure in the first region and a second part including a channel layer extending upward from the first part and directly contacting the first conductive layer. At a boundary surface between the first conductive layer and the cell guide structure, a side surface of the first conductive layer and an undersurface of the first conductive layer may form an acute angle.SELECTED DRAWING: Figure 4a

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a data storage system including the same.

Background Art

[0002] In a data storage system that requires data storage, a semiconductor device capable of storing high-capacity data is required. Accordingly, a solution capable of increasing the data storage capacity of the semiconductor device has been studied. For example, as one method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of memory cells arranged two-dimensionally has been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device with improved reliability.

[0004] One of the technical problems to be achieved by the technical idea of the present invention is to provide a data storage system including a semiconductor device with improved reliability.

Means for Solving the Problems

[0005] In an exemplary embodiment, a first semiconductor structure including a first substrate, circuit elements on the first substrate, a lower wiring structure electrically connected to the circuit elements, and a lower bonding structure connected to the lower wiring structure, and a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes, in a first region and a second region, a stacked structure including an interlayer insulating layer and a gate electrode stacked in a vertical direction, an upper wiring structure disposed under the stacked structure, an upper bonding structure connected to the upper wiring structure and bonded to the lower bonding structure, a cell guide structure that divides the first region and the second region above the stacked structure, a channel structure including a first portion that penetrates the stacked structure in the vertical direction in the first region and a second portion that extends upward from the first portion, and a contact plug that penetrates the stacked structure in the vertical direction in the second region and is connected to a contact region of the gate electrode, a first conductive layer that contacts an inner surface of the cell guide structure in the first region, is disposed above the stacked structure, and is connected to the second portion of the channel structure, and a protective layer that contacts an outer surface of the cell guide structure in the second region and is disposed above the stacked structure, a semiconductor device can be provided.

[0006] In an exemplary embodiment, a stacked structure including an interlayer insulating layer and a gate electrode stacked in a vertical direction, a cell guide structure disposed on the stacked structure and defining a first region, a first conductive layer disposed above the stacked structure in the first region, a protective layer disposed above the stacked structure in a second region other than the first region defined by the cell guide structure, and a channel structure including a first portion that penetrates the stacked structure in the vertical direction in the first region and a second portion that extends upward from the first portion and includes a channel layer that is in direct contact with the first conductive layer, a semiconductor device can be provided, wherein a side surface and a bottom surface of the first conductive layer form an acute angle at an interface between the first conductive layer and the cell guide structure.

[0007] In an exemplary embodiment, a first semiconductor structure including a substrate and circuit elements on the substrate, a stacked structure including an interlayer insulating layer and a gate electrode vertically stacked in a first region and a second region, and a second semiconductor structure including a channel structure penetrating the stacked structure, a semiconductor storage device including input / output pads electrically connected to the circuit elements, and a controller electrically connected to the semiconductor storage device via the input / output pads and controlling the semiconductor storage device, wherein the first semiconductor structure further includes a lower wiring structure electrically connected to the circuit elements or a lower bonding structure connected to the lower wiring structure, and the second semiconductor structure includes an upper wiring structure disposed under the stacked structure, an upper bonding structure connected to the upper wiring structure and bonded to the lower bonding structure, a cell guide structure separating the first region and the second region above the stacked structure, a contact plug penetrating the stacked structure in the vertical direction in the second region and connected to a contact region of the gate electrode, a first conductive layer contacting an inner surface of the cell guide structure in the first region, disposed above the stacked structure, and connected to a second portion of the channel structure, and a protective layer contacting an outer surface of the cell guide structure in the second region and disposed above the stacked structure. A data storage system can be provided.

Advantages of the Invention

[0008] In a structure in which two or more substrate structures are joined, a cell guide structure for dividing a cell region and an extension region is formed on a stacked structure exposed from the rear surface of the upper substrate structure, a nitride film as a protective layer is formed on the extension region, and common source lines can be formed on the cell regions respectively. When performing activation by laser annealing on a silicon layer arranged as a common source line on the cell region, the protective layer blocks the energy by laser annealing from reaching the front surface of the extension region, thereby preventing defects due to metal diffusion, particularly copper diffusion, of many wiring structures arranged on the front surface of the extension region. Further, by further forming at least a pair of reflection structures on the protective layer, it is possible to more effectively prevent energy from being transmitted to the underlying wiring structure.

[0009] Also, by applying an H-rich nitride to the protective layer to provide hydrogen to the channel structure, activation of each channel layer can be easily performed.

[0010] By forming the cell guide structure after replacing the gate electrode, by forming the cell guide structure in the base substrate before forming the channel structure, problems such as leakage current generated by the residue of metal substances in the intersection region of the cell guide structure and the isolation region during metal replacement of the gate electrode due to the opening of the isolation region can be prevented.

[0011] Therefore, a semiconductor device with improved reliability and a data storage system including the same can be provided.

[0012] The various beneficial advantages and effects of the present invention are not limited to the above-described content and can be more easily understood during the process of explaining the specific embodiments of the present invention.

Brief Description of the Drawings

[0013]

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DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described as follows. In the following, terms such as "upper", "upper part", "above", "lower", "lower part", "lower surface", "below", "side surface", etc. can be understood to refer to the drawings, unless otherwise indicated by reference numerals and separately mentioned.

[0015] FIG. 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment, and FIG. 2 is a schematic plan view for explaining the mat of FIG. 1. FIG. 2 shows a selection of the second mat, which is one of the four mats in FIG. 1.

[0016] The semiconductor device 10 can include a first semiconductor structure S1 and a second semiconductor structure S2, and the first semiconductor structure S1 can be stacked in the z direction, which is perpendicular to the second semiconductor structure S2. Specifically, the first semiconductor structure S1 may be disposed below the second semiconductor structure S2 in the z direction. In an exemplary embodiment, conversely, the second semiconductor structure S2 may be disposed below the first semiconductor structure S1.

[0017] In an exemplary embodiment, the semiconductor device 10 can include a peripheral circuit structure PERI (see FIG. 4a), which is a first semiconductor structure S1 with a peripheral circuit region formed on a first substrate 101, and a memory cell structure CELL (see FIG. 4a), which is a second semiconductor structure S2 including a common source line CSL.

[0018] In one embodiment, the first semiconductor structure S1 can form a peripheral circuit by forming transistors and metal patterns for wiring the transistors on the first substrate 101. After the peripheral circuit is formed in the first semiconductor structure S1, the second semiconductor structure S2 may be formed, but it is not limited thereto.

[0019] The second semiconductor structure S2 of the semiconductor device 10 can include a plurality of mats MAT1 to MAT4. The mats MAT1 to MAT4 may be arranged in a matrix type along the x direction and the y direction.

[0020] As an example, for one semiconductor device 10, n mats MAT1 to MATn can be arranged, and as an example, 4, 8, or the like mats MAT1 to MATn can be arranged. As an example, when four mats MAT1 to MAT4 are arranged, the bottom left mat is defined as the first mat MAT1, and the second mat MAT2 extending in the y direction from the first mat MAT1, the third mat MAT3 extending in the x direction from the first mat MAT1, and the fourth mat MAT4 extending in the y direction from the third mat MAT3 can be respectively defined. Each of the mats MAT1 to MAT4 can include a memory block BLK that is a set of a plurality of channel structures CH.

[0021] Each of the mats MAT1 to MAT4 can include a first region R1 along the x direction, a first extension region R2a on both sides of the first region R1, and a second extension region R2b.

[0022] The first extension region R2a is an extension region arranged between adjacent mats MAT1 to MAT4, and the second extension region R2b can be defined as an extension region arranged outside the semiconductor device 10. Therefore, the first extension regions R2a of the first mat MAT1 and the third mat MAT3 face each other, the first extension regions R2a of the second mat MAT2 and the fourth mat MAT4 face each other, and the second extension region R2b can be arranged outside each of the two sides (left and right) of the semiconductor device 10. The first region R1 is a memory cell region where memory cells are arranged and is a region where the channel structures CH are arranged. The first extension region R2a and the second extension region R2b can correspond to regions for electrically connecting the memory cells to the peripheral circuit structures PERI. For this purpose, the gate electrode layer may be a region where the gate electrode layers extend with different lengths, but is not limited thereto.

[0023] Referring to FIG. 2, edge regions EA can be arranged on respective sides of mats MAT1 to MAT4. The edge region EA may be arranged outside the first extension region R2a and outside the second extension region R2b, above and below the first region R1, and may be a region where the mold structure remains. The edge region EA can be defined as a region where a pad region connected from the outside is arranged, an external contact via connected to the pad region is arranged, or various through vias connected to the first semiconductor structure S1 are arranged. Although shown as being arranged such that edge regions EA are arranged on respective sides of each of mats MAT1 to MAT4 to have a frame shape, it is not limited thereto.

[0024] Each of mats MAT1 to MAT4 can further include a cell guide structure CD that defines a first region R1 on the stacked structures GS1, GS2 and the mold structures MS1, MS2.

[0025] The cell guide structure CD can define, on each of mats MAT1 to MAT4, a first region R1 which is a memory cell region where a channel structure CH is arranged, and can define a region where a common source line CSL is arranged. Accordingly, a memory cell region is defined inside the cell guide structure CD in the x-y plane, edge regions EA are defined above and below the first region R1 outside the cell guide structure CD, and the first and second extension regions R2a, R2b can be arranged on the left and right of the first region R1. The common source line CSL may be arranged as a plate shape as a whole within the cell guide structure CD, or alternatively, may be arranged as several separated units.

[0026] A common source line CSL is not arranged outside the cell guide structure CD, and a protective layer 251 may be arranged. The protective layer 251 can be an insulating film, specifically, a silicon nitride film, and an H-rich SiN, that is, a nitride film containing a large amount of hydrogen can be applied. Such an H-rich SiN can be applied as PE-SiN (Plasma enhanced-SiN) or the like, and is a material layer with a very low thermal conductivity, a high energy absorption rate, and minimized thermal stress changes, and can function as a buffer layer. During the melting laser annealing process (MLA: Melting laser annealing) of the semiconductor layer constituting the common source line CSL, since a selective process is impossible, energy and heat penetrate into the first and second extension regions R2a, R2b where a large number of lower wirings are formed, and the edge region EA, and there is a possibility of device failure due to unintentional metal diffusion of the copper material forming the lower wiring. Therefore, while proceeding with crystallization and planarization by the melting laser annealing process of the semiconductor layer inside the cell guide structure CD, the protective layer 251 is arranged on the adjacent first and second extension regions R2a, R2b, and the edge region EA to minimize the influence on the lower part and protect the lower wiring.

[0027] The cell guide structure CD can have a frame shape having a predetermined width in the x-y plane, and the predetermined width can have a width 5 to 10 times the upper end width of the channel structure CH. As an example, the cell guide structure CD may have a width of 500 nm to 1000 nm, preferably 800 nm to 1000 nm, but is not limited thereto.

[0028] In this way, a cell guide structure CD that defines a first region R1, which is a memory cell region of each mat MAT1 to MAT4, is arranged on the stacked structure GS1, GS2 or the mold structure MS1, MS2. By arranging the common source line CSL in a plate shape only inside the cell guide structure CD, it is possible to have the same effect as performing selective laser annealing.

[0029] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to FIGS. 3, 4a, 4b, and FIGS. 5a and 5b.

[0030] FIG. 3 is a partially enlarged view of a semiconductor device according to an exemplary embodiment, FIGS. 4a and 4b are schematic cross-sectional views of a semiconductor device according to an exemplary embodiment, and FIGS. 5a and 5b are partially enlarged views of a semiconductor device according to an exemplary embodiment. FIG. 3 is an enlarged view of the “A” portion of FIG. 2, and FIGS. 4a and 4b show cross-sections along the cut lines I-I' and II-II' of FIG. 2, respectively. FIGS. 5a and 5b are enlarged views of the “B” portion and the “C” portion of FIG. 4b, respectively.

[0031] Referring to FIGS. 3 to 5b, the semiconductor device 10 can include a first semiconductor structure S1 defined as a peripheral circuit structure PERI and a second semiconductor structure S2 defined as a memory cell structure CELL on the first semiconductor structure S1. The first semiconductor structure S1 and the second semiconductor structure S2 may be joined to each other via bonding structures 180 and 280.

[0032] The first semiconductor structure S1 can include a first substrate 101, circuit elements 120 on the first substrate 101, a lower wiring structure 130, a lower bonding structure 180, and a lower capping layer 190.

[0033] The first substrate 101 can include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The first substrate 101 may be provided as a bulk wafer or an epitaxial layer. The active region can be defined in the first substrate 101 by an element isolation layer 110. Source / drain regions 105 containing impurities can be arranged in a part of the active region.

[0034] The circuit element 120 can include a transistor. Each circuit element 120 can include a circuit gate dielectric layer 122, a circuit gate electrode 124, a spacer layer 126, and source / drain regions 105. The source / drain regions 105 containing impurities can be disposed in the first substrate 101 on both sides of the circuit gate electrode 124. The spacer layer 126 can be disposed on both sides of the circuit gate electrode 124. The circuit gate dielectric layer 122 can include silicon oxide, silicon nitride, or a high-k (high dielectric constant) material. The circuit gate electrode 124 can include at least one of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), and ruthenium (Ru). For example, the circuit gate electrode 124 can include a doped polycrystalline silicon layer. According to an exemplary embodiment, the circuit gate electrode 124 may be composed of two or more multilayers.

[0035] The lower wiring structure 130 can be electrically connected to the circuit gate electrode 124 and the source / drain region 105 of the circuit element 120. The lower wiring structure 130 can include a lower contact plug 135 and a lower wiring line 137 in which at least one region is linear. A part of the lower contact plug 135 may be connected to the source / drain region 105, and although not shown, another part of the lower contact plug 135 may be connected to the gate electrode 124. The lower contact plug 135 can electrically connect the lower wiring lines 137 arranged at different levels from the upper surface of the first substrate 101 to each other. The lower wiring structure 130 can include a conductive material, for example, it can include tungsten (W), copper (Cu), aluminum (Al), etc., and each configuration can further include a diffusion barrier including at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). According to an exemplary embodiment, the number of layers and the arrangement form of the lower contact plug 135 and the lower wiring line 137 constituting the lower wiring structure 130 can be variously changed.

[0036] The lower bonding structure 180 can be connected to the lower wiring structure 130. The lower bonding structure 180 can include a lower bonding via 182, a lower bonding pad 184, and a lower bonding insulating layer 186. The lower bonding via 182 can be connected to the lower wiring structure 130. The lower bonding pad 184 can be connected to the lower bonding via 182. The lower bonding via 182 and the lower bonding pad 184 can include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each configuration can further include a diffusion barrier. The lower bonding insulating layer 186 can also function as a diffusion prevention layer for the lower bonding pad 184 and can include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. The lower bonding insulating layer 186 can have a thickness thinner than that of the lower bonding pad 184, but is not limited thereto. The lower bonding structure 180 may be directly contacted, joined, or connected to the upper bonding structure 280 by hybrid bonding. For example, the lower bonding pad 184 may be in contact with the upper bonding pad 284 and bonded by copper-to-copper bonding, and the lower bonding insulating layer 186 may be in contact with the upper bonding insulating layer 286 and bonded by dielectric-to-dielectric bonding. The lower bonding structure 180 and the upper bonding structure 280 together can provide an electrical connection path between the peripheral circuit structure PERI(S1) and the memory cell structure CELL(S2).

[0037] The lower capping layer 190 is disposed on the first substrate 101 and can cover the circuit element 120 and the lower wiring structure 130. The lower capping layer 190 can include a plurality of insulating layers. The lower capping layer 190 can include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0038] The second semiconductor structure S2, which is a memory cell structure, includes a first conductive layer 201 in a first region R1 that is a memory cell region, a second conductive layer 202 on the upper surface of the first conductive layer 201, a buffer layer 205 on the upper surface of the second conductive layer 202, a gate electrode 230 laminated on the lower surface of the first conductive layer 201, an interlayer insulating layer 220 laminated alternately with the gate electrode 230 in the first region R1, and in first and second extended regions R2a and R2b, a channel structure CH disposed so as to penetrate the gate electrode 230, a separation region MS extending in one direction through the gate electrode 230, and an insulating region SS penetrating a part of the gate electrode 230. The second semiconductor structure S2 includes an edge region EA surrounding the first region R1, and the first and second extended regions R2a and R2b, and can include a sacrificial insulating layer 218 laminated alternately with the interlayer insulating layer 220 in the edge region EA. In the first and second extended regions R2a and R2b, and the edge region EA, it can further include a protective layer 251 disposed on the lowermost interlayer insulating layer 222 horizontally with respect to the first conductive layer 201, an upper capping layer 290 covering the gate electrode 230 and the buffer layer 205, and an upper insulating structure 210 and a passivation layer 215 on the protective layer 251.

[0039] The second semiconductor structure S2 can include a stud 272 for electrical connection with the first semiconductor structure S1, an upper wiring structure 271 under the stacked structures GS1 and GS2, and an upper bonding structure 280 connected to the upper wiring structure 271.

[0040] The second semiconductor structure S2 can further include support structures 265 in the first extension region R2a and the second extension region R2b, contact plugs 270, and external contact vias 275 in the edge region EA.

[0041] As shown in FIG. 3, the first region R1 may be a region where gate electrodes 230 are stacked spaced apart from each other in the vertical direction, for example, the z direction, and a channel structure CH is disposed. The first extension region R2a and the second extension region R2b may be disposed on both sides of the first region R1 in the x direction, and may be regions where contact plugs 270 are disposed which are respectively connected to the gate electrodes 230 to electrically connect the memory cell to the first semiconductor structure S1. In FIGS. 3 and 4a, the gate electrodes 230 are shown as extending with different lengths from each other so that contact pads GP are formed for connection between each gate electrode 230 and the contact plug 270, but it is not limited thereto.

[0042] Also, the edge region EA is disposed on the outer surfaces of the first extension region R2a and the second extension region R2b and the upper and lower portions of the first region R1, a pad region 258 for transmitting and receiving external signals is disposed, and external contact vias 275 for transmitting external signals to the first semiconductor structure S1 can be disposed. The edge region EA is a region where the gate electrodes 230 do not extend and mold structures MS1, MS2 in which the sacrificial insulating layer 218 and the interlayer insulating layer 220 are stacked on each other remain, and the external contact vias 275 can be connected to the lower first semiconductor structure S1 in a state insulated from the mold structures MS1, MS2.

[0043] In the first region R1, the first extension region R2a and the second extension region R2b, and the edge region EA, an insulating structure 210 may be disposed on the upper part of the stacked structures GS1, GS2, and a passivation layer 215 may be disposed on the upper part of the insulating structure 210.

[0044] The gate electrode 230 is vertically and separately stacked on the lower surfaces of the first conductive layer 201 and the protective layer 251, and can form stacked structures GS1 and GS2 together with the interlayer insulating layer 220. The stacked structures GS1 and GS2 can include a plurality of stacked structures GS1 and GS2 stacked vertically. In FIGS. 4a and 4b, they are shown as including a lower and an upper stacked structure GS1 and GS2, but are not limited thereto, and may include three to five stacked structures GS1 to GSn. However, depending on the embodiment, the stacked structures GS1 to GSn may consist of a single stacked structure.

[0045] The gate electrode 230 can include at least one lower gate electrode 230L that forms the gate of the ground selection transistor, a memory gate electrode 230M that forms a plurality of memory cells, and an upper gate electrode 230U that forms the gate of the string selection transistor. Here, the lower gate electrode 230L and the upper gate electrode 230U may be referred to as "lower" and "upper" based on the direction during the manufacturing process. Depending on the capacitance of the semiconductor device 10, the number of memory gate electrodes 230M that form the memory cells can be determined. Depending on the embodiment, the upper and lower gate electrodes 230U and 230L may each be one to two or more, and may have the same or different structures from the memory gate electrode 230M. In an exemplary embodiment, an erase gate electrode can be further disposed under the upper gate electrode 230U. Also, some gate electrodes 230, for example, the memory gate electrode 230M adjacent to the upper or lower gate electrode 230U or 230L, may be dummy gate electrodes, but are not limited thereto.

[0046] The gate electrodes 230 may be separated from each other in the y direction by a separation region MS that continuously extends within the first region R1 and the first and second extension regions R2a and R2b. The gate electrode 230 between a pair of separation regions MS may form one memory block BLK, but the range of the memory block BLK is not limited thereto. A part of the gate electrode 230, for example, the memory gate electrode 230M, may each form one layer within one memory block BLK.

[0047] The gate electrode 230 is stacked vertically and spaced apart from each other in the first region R1, and the first extension region R2a and the second extension region R2b, and extends from the first region R1 to the first extension region R2a and the second extension region R2b with different lengths from each other, and a part of the first extension region R2a and the second extension region R2b, for example, a stepped structure can be formed in the first extension region R2a and the second extension region R2b. The gate electrodes 230 can be arranged so as to have a stepped structure with each other also in the y direction. Due to the stepped structure, the lower gate electrode 230 can extend longer than the upper gate electrode 230, and each can have a region where the upper surface is exposed from the interlayer insulating layer 120 and other gate electrodes 230, and the region can be called a pad region GP. In each gate electrode 230, the pad region GP may be a region including an end portion of the gate electrode 230 along the x direction. The pad region GP can correspond to a region of the gate electrode 230 located at the uppermost part in each region among the gate electrodes 230 forming the stacked structures GS1 and GS2 in the first extension region R2a and the second extension region R2b. The gate electrode 230 can be connected to the contact plug 270 in the pad region GP respectively. The gate electrode 230 can have an increased thickness in the pad region GP.

[0048] The gate electrode 230 can contain a metal substance, for example, tungsten (W). Depending on the embodiment, the gate electrode 230 can contain polycrystalline silicon or a metal silicide substance. According to an exemplary embodiment, the gate electrode 230 can further include a diffusion prevention layer 231. For example, the diffusion prevention layer 231 can contain tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0049] The interlayer insulating layer 220 can be disposed between the gate electrodes 230 to form stacked structures GS1 and GS2. Similar to the gate electrodes 230, the interlayer insulating layer 220 can also be disposed so as to be spaced apart from each other in a direction perpendicular to the lower surfaces of the first conductive layer 201 and the protective layer 251 and extend in the x direction. The interlayer insulating layer 220 may extend to the edge region EA and be disposed between the sacrificial insulating layers 218, and may form mold structures MS1 and MS2. The interlayer insulating layer 220 can include an insulating material such as silicon oxide or silicon nitride.

[0050] In an embodiment, the thicknesses of the interlayer insulating layers 220 may not all be the same. As an example, among the interlayer insulating layers 220, the uppermost interlayer insulating layer 223, the lowermost interlayer insulating layer 222, and the intermediate interlayer insulating layer 225 may have a greater thickness than the other interlayer insulating layers 220, but are not limited thereto. The intermediate interlayer insulating layer 225 can be defined as the interlayer insulating layer between the stacked structures GS1 and GS2.

[0051] The sacrificial insulating layers 218 may be disposed in the edge region EA so as to be spaced apart from each other in a direction perpendicular to the lower surface of the protective layer 251 and extend in the x direction, similar to the gate electrodes 230. In the edge region EA, the sacrificial insulating layers 218 may be alternately stacked with the interlayer insulating layers 220 to form mold structures MS1 and MS2. When the gate electrodes 230 are replaced, the sacrificial insulating layers 218 are not replaced with the gate electrodes 230 depending on the distance from the separation region MS, and can include a material layer that remains and has an etching selectivity with respect to the interlayer insulating layers 220. For example, the interlayer insulating layer 220 can be composed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 218 can be composed of a material different from the interlayer insulating layer 220, which is selected from silicon, silicon oxide, silicon carbide, and silicon nitride. Also, the thicknesses and the number of films constituting the interlayer insulating layers 220 and the sacrificial insulating layers 218 can be variously changed from those shown.

[0052] The isolation region MS can be arranged to extend along the x-direction through at least a part of the gate electrode 230. The isolation regions MS may be arranged parallel to each other. The isolation region MS can penetrate through the entire stacked gate electrode 230 and be connected to the lower insulating layer 291. The isolation region MS may extend continuously in one along the x-direction, but may extend intermittently in part, and may be arranged only in some regions.

[0053] An isolation insulating layer 264 can be arranged in the isolation region MS. The isolation insulating layer 264 can have a shape in which the width increases toward the first substrate 101 due to a high aspect ratio, but is not limited thereto. The lower surface of the isolation insulating layer 264 can be in contact with the lower insulating layer 291, and the upper surface can be in contact with the lower surface of the first conductive layer 201. The isolation insulating layer 264 does not extend to the edge region EA and is arranged only in the first extension region R2a and the second extension region R2b. In the process of opening the isolation region MS and replacing the sacrificial insulating layer 218 with the gate electrode 230, the sacrificial insulating layer 218 in the edge region EA can remain without being replaced to maintain the mold structures MS1 and MS2.

[0054] As shown in FIG. 3, the isolation region MS can be formed to have a curved surface on the side surface, and can have a structure in which a curved surface having a convex curvature toward the outside is continuously formed. Such a curved surface structure on the side surface can be derived by forming a plurality of separation holes separated from each other simultaneously with the formation of the channel hole, and then expanding the plurality of separation holes to connect to each other by a cleaning process to form the isolation region MS.

[0055] By forming the isolation region MS from the separation holes, it is possible to perform simultaneously when forming the channel holes without further advancing the high aspect ratio etching process for forming a separate isolation region MS, and it can proceed in an all-in-one high aspect ratio etching (All-in-one HARC (High aspect ratio contact) etching) process.

[0056] The insulating region SS can extend in the x direction between the separation regions MS adjacent to each other. The insulating region SS may be disposed in the first region R1 as part of the first extension region R2a and the second extension region R2b. The insulating region SS can penetrate the upper gate electrode 230U disposed at the uppermost stage of the gate electrode 230. As shown in FIG. 3, the insulating region SS can divide the upper gate electrode 230U in the y direction. However, the number of upper gate electrodes 230U separated by the insulating region SS can be variously changed in the embodiment.

[0057] The insulating region SS can be disposed across a part of the channel structure CH. The insulating region SS can have a predetermined width in the y direction and extend across in the x direction between a plurality of channel structures CH arranged in a staggered matrix. Thus, when the plurality of channel structures CH are arranged to have the same separation distance, the insulating region SS can extend across a row of channel structures CH at the same time. The insulating region SS can be recessed into a part of the channel structure CH facing, for example, one upper gate electrode 230U at the upper end of the channel structure CH, whereby a part of the channel structure CH can be removed. At this time, the channel structure CH can be recessed by a length smaller than the radius of the channel structure CH, which is from the central axis of the channel to the inner wall of the channel hole. Therefore, the insulating region SS can be arranged so as not to pass through the central axis of the channel of the channel structure CH and more than 1 / 2 of the channel structure CH remains on the upper surface, but is not limited thereto. The channel structure CH into which the insulating region SS is recessed may be an effective channel structure that actually functions as a memory cell rather than a dummy channel structure. At this time, the insulating region SS disposed at the center of each memory block BLK can be recessed and arranged over the entire channel structure CH, and the recessed channel structure CH may be a dummy channel structure DCH and may not function as an actual memory cell. The insulating region SS can each include an upper isolation insulating layer 266. The upper isolation insulating layer 266 can include an insulating material, for example, can include silicon oxide, silicon nitride, or silicon oxynitride.

[0058] The channel structures CH can be arranged separately from each other in rows and columns on the lower surface of the first conductive layer 201 in the first region R1. The channel structures CH may be arranged in a staggered pattern in one direction in the x-y plane. The channel structures CH can penetrate the gate electrode 230 and extend in a vertical direction perpendicular to the lower surface of the first conductive layer 201, for example, the z direction, have a column shape, and can have inclined side surfaces that become narrower closer to the first conductive layer 201 according to the aspect ratio.

[0059] Each of the channel structures CH can have a form in which a lower channel structure CH1 and an upper channel structure CH2 that penetrate the lower stacked structure GS1 and the upper stacked structure GS2 of the gate electrode 230, respectively, are connected, and can have a bent portion due to a width difference or change in the connection region.

[0060] As shown in the enlarged view of FIG. 5a, each of the channel structures CH can include a first portion in the stacked structures GS1 and GS2 and a second portion protruding above the stacked structures GS1 and GS2.

[0061] The channel layer 240 can be disposed entirely on the first and second portions of the channel structure CH and can be disposed up to the upper end of the second portion. The channel layer 240 can be disposed on the second portion of the channel structure CH and can include a protruding portion 240a that protrudes and is exposed above the stacked structures GS1 and GS2, and a non-protruding portion 240b that is disposed on the first portion of the channel structure CH. In the channel structure CH, the length h1 by which the protruding portion 240a of the channel layer 240 protrudes may not be the same as each other, but is not limited thereto. The channel layer 240 may be formed in an annular shape surrounding the internal embedded insulating layer 247 on the side surface, but depending on the embodiment, may have a column shape such as a cylinder or a prism without the embedded insulating layer 247. The protruding portion 240a of the channel layer 240 can be covered with the first conductive layer 201 and can be in direct contact with the first conductive layer 201. The protruding portion 240a may be formed to have a gentle slope with the non-protruding portion 240b so that the above-mentioned annular shape is maintained as shown in FIG. 5a. The channel layer 240 can include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material containing P-type or N-type impurities.

[0062] In the channel structure CH, a channel pad 249 can be disposed below the channel layer 240. The channel pad 249 may be disposed to cover the lower surface of the buried insulating layer 247 and be electrically connected to the channel layer 240. The channel pad 249 may include, for example, doped polycrystalline silicon.

[0063] The information storage structure 245 can be disposed between the gate electrode 230 and the channel layer 240. The information storage structure 245 can include a tunneling layer 241, a charge storage layer 242, and a blocking layer 243 sequentially stacked from the channel layer 240. The tunneling layer 241 can tunnel charges to the charge storage layer 242 and can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer 242 may be a charge trap layer or a floating gate conductive layer. The blocking layer 243 can include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. According to an exemplary embodiment, at least a portion of the information storage structure 245 can form a channel dielectric layer extending horizontally along the gate electrode 230.

[0064] The information storage structure 245 may be removed from the upper portions of the stacked structures GS1, GS2 such that the protruding portion 240a of the channel layer 240 is exposed to the outside in the second portion. Accordingly, the upper end of the information storage structure 245 can contact the first conductive layer 201, and in the first portion, the side surface of the information storage structure 245 can be disposed to surround the non-protruding portion 240b of the channel layer 240.

[0065] Between the upper channel structure CH2 and the lower channel structure CH1, the channel layer 240, the information storage structure 245, and the embedded insulating layer 247 may be connected to each other. As described above, a relatively thick intermediate interlayer insulating layer 225 may be disposed between the upper channel structure CH2 and the lower channel structure CH1.

[0066] The support structure 265 can be disposed in the first extension region R2a and the second extension region R2b, and can have the same or a similar structure as the channel structure CH, but may not perform a substantial function within the semiconductor device 10. The support structures 265 may be regularly arranged in rows and columns in the first extension region R2a and the second extension region R2b. The support structure 265 can have a diameter equal to or smaller than the maximum diameter of the contact plug 270. The shape, number, and / or interval of the support structures 265 may be different. The channel structure CH and the support structure 265 may have a circular or nearly circular shape, but are not limited thereto, and may have an elliptical shape. The support structure 265 may be a supporter that can prevent deformation such as warping of the stacked structures GS1 and GS2.

[0067] The contact plug 270 can be connected to the contact region of the gate electrode 230 in the gate pad regions GP of the first extension region R2a and the second extension region R2b. The contact plug 270 can penetrate at least a part of the upper capping layer 290 and be connected to each of the contact regions of the gate electrode 230 exposed at the upper part. The contact plug 270 can penetrate the gate electrode 230 under the contact region and be connected to the circuit wiring line 280 in the first semiconductor structure S1. The contact plug 270 can be separated from the gate electrode 230 under the contact region by the contact insulating layer 260. However, in some embodiments, the contact plug 270 may be arranged so as not to penetrate the gate electrode 230, and in this case, the contact plug 270 may be connected to each of the contact regions of the gate electrode 230 exposed at the upper part.

[0068] The contact plug 270 can have a shape corresponding to the channel structure CH or a shape corresponding to the isolation region MS. Each of the contact plugs 270 can include an upper region penetrating through the stacked structures GS1 to GS2 respectively and a lower region extending from and below the upper region. The lower region and the upper region can have inclined side surfaces whose width decreases as they approach the protective layer 251 from each of the stacked structures GS1, GS2 due to the aspect ratio, and can have a cylindrical shape.

[0069] As shown in FIG. 4a, each of the contact plugs 270 can have a horizontally extended form in the contact region. The contact plug 270 can include a vertical extension 270V extending along the z direction and a horizontal extension 270H extending horizontally from the vertical extension 270V and contacting the gate electrode 230. The horizontal extension 270H is arranged along the circumference of the vertical extension 270V and can be entirely surrounded by the gate electrode 230 on the side surface. The length from the side surface of the vertical extension 270V to the end of the horizontal extension 270H may be smaller than the length from the side surface of the vertical extension 270V to the outer surface of the contact insulating layer 260. The contact plug 270 can be separated from the gate electrode 230 below the contact region, that is, the gate electrode 230 not electrically connected, by the contact insulating layer 260.

[0070] The contact plug 270 can include at least one of conductive materials such as tungsten (W), copper (Cu), aluminum (Al), and their alloys. In some embodiments, the contact plug 270 can also include a barrier layer extending along the side surface and the bottom surface or have an air gap inside.

[0071] The contact insulating layer 260 may be disposed to surround respective side surfaces of the contact plug 270 under the contact region. The contact insulating layers 260 may be spaced apart from each other along the z direction around each of the contact plugs 270. The contact insulating layer 260 can be disposed at substantially the same level as the gate electrode 230 respectively. The contact insulating layer 260 can include an insulating material, for example, it can include silicon oxide, silicon nitride, or silicon oxynitride.

[0072] The external contact via 275 can be connected in the edge region EA to transmit an external signal to the first semiconductor structure S1 via the pad region 258 exposed to the outside and the upper wiring structure 272 of the second semiconductor structure S2. The external contact via 275 can penetrate the mold structures MS1, MS2 and be connected via the pad region 258 and the upper stud 257 exposed at the top. The external contact via 275 can penetrate the mold structures MS1, MS2 and be connected to the circuit wiring line 280 in the first semiconductor structure S1.

[0073] The external contact via 275 can have a shape corresponding to the channel structure CH or a shape corresponding to the separation region MS. Each of the external contact vias 275 can include a lower region penetrating the mold structures MS1, MS2 respectively and an upper region extending from the lower region and located below the lower region. The lower region and the upper region can have inclined side surfaces whose width decreases as they approach the protective layer 251 from each of the mold structures MS1, MS2 due to the aspect ratio, and can have a cylindrical shape. The upper end width of the external contact via 275 can be 1.5 to 3 times the upper end width of the channel structure CH, but is not limited thereto. The external contact via 275 can include at least one of conductive materials, for example, tungsten (W), copper (Cu), aluminum (Al), and their alloys.

[0074] A cell guide structure CD can be disposed in a boundary region between the first region R1, the first extended region R2a, and the second extended region R2b, and also in a boundary region between the first region R1 and the edge region EA. The cell guide structure CD can be arranged such that lines having the same width on the x-y plane form a frame shape. In a cross-section in the z direction, it can have a shape where the width W1 of the lower surface is smaller than the width W2 of the upper surface along the z direction perpendicular to the first substrate 101 on the lowermost interlayer insulating layer 222, and can have a shape where the width increases upward. The largest upper surface width W2 of the cell guide structure CD can be 500 nm to 1000 nm, preferably 800 nm to 1000 nm, but is not limited thereto.

[0075] The cell guide structure CD includes a guide insulating layer 250. The guide insulating layer 250 can include a cell guide structure region 250V extending in the z direction and an extended insulating layer region 250H extending from the cell guide structure region 250V onto the protective layer 251. The thickness of the cell guide structure region 250V can satisfy 300 nm to 500 nm, preferably 400 nm to 450 nm, but is not limited thereto. The extended insulating layer region 250H can have a thickness much smaller than the thickness of the cell guide structure region 250V.

[0076] The cell guide structure CD can be defined as a structure including the cell guide structure region 250V and a part of the extended insulating layer region 250H overlapping with the cell guide structure region 250V in the z direction. The extended insulating layer region 250H can extend from the cell guide structure CD onto the protective layer 251.

[0077] The side surface of the cell guide structure CD may have an inclined surface, and the angles of the two inclined surfaces may be the same as each other. The inner surface of the cell guide structure CD can be in direct contact with the first conductive layer 201, and the outer surface can be in direct contact with the protective layer 251. The side surface of the cell guide structure CD is such that up to the same height as the upper surface of the protective layer 251 is the cell guide structure region 250V. The angle formed by the inner surface and the upper surface of the outermost upper layer insulation layer 222 has a first angle Θ1, and the width increases as it rises in the z direction. The extended insulation layer region 250H connected to the protective layer 251 has a second angle Θ2 greater than the first angle Θ1, and the width may not be extended. Therefore, the inner surface of the cell guide structure CD can have an inflection point where the inclination changes between the extended insulation layer region 250H and the cell guide structure region 250V.

[0078] The first conductive layer 201 and the second conductive layer 202 can be arranged inside the frame formed by the cell guide structure CD, that is, on the first region R1.

[0079] The first conductive layer 201 may be arranged between the lower surface of the second conductive layer 202 and the stacked structures GS1, GS2 in the first region R1. The first conductive layer 201 can contain a semiconductor material. For example, the first conductive layer 201 can contain a semiconductor material, such as a group IV semiconductor, a III-V compound semiconductor, or a II-VI compound semiconductor. For example, the group IV semiconductor can include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The first conductive layer 201 can function as a common source line (CSL) of the semiconductor device 10. The first conductive layer 201 can include a silicon layer, for example, a silicon layer having an N-type conductivity type. For example, the first conductive layer 201 may be provided as a single crystal silicon layer doped with impurities, a crystalline semiconductor layer such as a polycrystalline silicon layer, or an epitaxial layer. As shown in the enlarged view of FIG. 5a, the first conductive layer 201 covers the second portion of the channel structure CH and can be in direct contact with the protrusion 240a of the channel layer 240.

[0080] The first conductive layer 201 disposed within the frame of the cell guide structure CD is a plate layer that entirely covers the interior of the frame and can be arranged such that its upper surface has a flat surface. Within the frame, the first conductive layer 201 may be arranged to have a first thickness h2, and the first thickness h2 may be greater than the length h1 of the protrusion 240a of the channel layer 240. As an example, when the length h1 of the protrusion 240a of the channel layer 240 satisfies 150 nm to 180 nm, the first thickness h2 of the first conductive layer 201 satisfies 200 nm to 220 nm, which is greater than the length h1 of the protrusion 240a, and the first conductive layer 201 can remain on the protrusion 240a by a second thickness h3.

[0081] Within the frame, the upper surface of the first conductive layer 201 can be positioned at a lower level than the upper surface of the cell guide structure CD, and the lower surface of the first conductive layer 201 can be positioned at a lower level than the lower surface of the cell guide structure CD. The lower surface of the first conductive layer 201 may be arranged within the frame so as to be recessed by a predetermined length h5 from the lower surface of the cell guide structure CD. Therefore, within the frame, the first conductive layer 201 can be arranged to be recessed downward in a concave shape from the cell guide structure CD.

[0082] The first conductive layer 201 can have an inclined surface on the side surface in contact with the cell guide structure CD. Each inclined surface of the first conductive layer 201 is formed to be in contact with the inclined surface of the cell guide structure CD and can have a first angle Θ1 that is an acute angle with respect to the upper surface of the interlayer insulating layer 222, that is, the lower surface of the first conductive layer 201, as shown in FIG. 5b. Therefore, within the frame, the first conductive layer 201 can form an inclined surface on the side surface while decreasing in width as it rises in the z direction, and the area of the upper surface of the first conductive layer 201 within the frame can be made smaller than the area of the lower surface.

[0083] The second conductive layer 202 can be disposed along the first conductive layer 201. The second conductive layer 202 may have a thickness thinner than that of the first conductive layer 201 and be a conductive layer in contact with the first conductive layer 201. The second conductive layer 202 can include at least one of a metal-semiconductor compound, a metal-nitride, and a metal (e.g., tungsten (W), copper (Cu), aluminum (Al)). The second conductive layer 202 can be aligned in a direction perpendicular to the first conductive layer 201. The second conductive layer 202 can include at least three layers as shown in FIG. 5b and can have a stacked structure of a lower ohmic contact layer 202b, a conductive metal layer 202a, and a diffusion barrier 202c.

[0084] When the lower first conductive layer 201 includes a semiconductor layer, the ohmic contact layer 202b is a low-resistance layer for making an ohmic contact with the conductive metal layer 202a. When the conductive metal layer 202a is a conductive metal such as tungsten (W), the ohmic metal layer 202b may be, for example, titanium (Ti) or tantalum (Ta). The diffusion barrier 202c is disposed on the conductive metal layer 202a and is for preventing the diffusion of the conductive metal layer 202a into the upper insulating layer 205, and can include, but is not limited to, a nitride film, for example, a titanium nitride film (TiN), a tantalum nitride film (TaN), a tungsten nitride film (WN). The thickness of the conductive metal layer 202a is the thickest within the second conductive layer 202, the thicknesses of the ohmic contact layer 202b and the diffusion barrier 202c are very thin, and the thickness of the conductive metal layer 202a can account for 60% or more of the whole, but is not limited thereto.

[0085] Within the frame, the first and second conductive layers 201, 202 are source layers and can together form a source structure. The source structure can function as a common source line CSL of the semiconductor device 10.

[0086] A buffer layer 205 can be further formed on the second conductive layer 202. The buffer layer 205 can protect the first and second conductive layers 201 and 202 during the patterning of the second conductive layer 202 and the first conductive layer 201. It may be an oxide conformally covering along the second conductive layer 202, and may include silicon oxide, silicon oxynitride, etc.

[0087] In the first region R1, the first conductive layer 201, the second conductive layer 202, and the buffer layer 205 can have the same area. The first conductive layer 201, the second conductive layer 202, and the buffer layer 205 cover the inclined surface of the inner side of the cell guide structure CD from the inside of the frame and extend to the upper surface of the cell guide structure CD, an extended region CSL E which can be included. Such an extended region CSL of the common source line CSL E does not extend outside the cell guide structure CD and can be limited to above the upper surface of the cell guide structure CD. The first conductive layer of the extended region CSL E arranged on the side surface and the upper surface of the cell guide structure CD may have a second thickness h4 different from the first thickness h2, and the second thickness h4 may be smaller than the first thickness h2. As an example, the second thickness h4 can satisfy 40 nm to 60 nm, preferably 50 nm to 60 nm, but is not limited thereto. In contrast, the thickness of the second conductive layer 202 in the extended region CSL E can have a range similar to the thickness of the second conductive layer 202 within the frame.

[0088] On one hand, a protective layer 251 may be disposed in a first extended region R2a, a second extended region R2b, and an edge region EA outside the cell guide structure CD. The protective layer 251 is an absorption layer for absorbing energy and heat in order to prevent metal diffusion of the underlying wiring structures 271, 272, 284 during laser annealing of the first conductive layer 201, and may include a substance with an extremely low thermal conductivity. As an example, a nitride film, specifically, a stress-reinforced nitride film specialized for passivation such as SiN, particularly PE-SiN (Plasma enhanced SiN) can be disposed. The protective layer 251 is in direct contact with the outer surface of the cell guide structure CD on the side surface, and the thickness of the protective layer 251 can have a thickness greater than the first thickness h2 of the first conductive layer 201, but the upper surface may be located at a level lower than the upper surface of the cell guide structure CD. The extended guide region 250H of the cell guide structure CD may extend to cover the upper surface of the protective layer 251.

[0089] Thus, when the gate electrode 230 is gradually removed to form a stepped shape or is formed only by the mold structures MS1, MS2, relatively more energy transmission to the wiring structures 271, 272, 284 below the memory cell region R1 can occur. By disposing the protective layer 251 in the first extended region R2a, the second extended region R2b, and the edge region EA, energy transmission downward can be blocked during the progress of the MLA process of the first conductive layer 201. Therefore, defects due to diffusion of the metal forming the underlying wiring structures 271, 272, 284, for example, copper, can be eliminated.

[0090] Also, after forming the protection layer 251 entirely, the cell guide structure CD is formed to define the memory cell region R1 and the other regions R2a, R2b, and EA. Then, only the protection layer 251 in the first region R1 can be selectively removed to form the common source line CSL. By forming the guide structure on the base substrate before forming the channel structure CH according to such a process procedure, when replacing the gate electrode 230 through the isolation region MS in the guide structure that intersects the isolation region MS, defects such as metal substances remaining in a part of the guide structure can be prevented from occurring.

[0091] When applying the protection layer 251 as a nitride film, specifically SiN, especially PE - SiN (Plasma enhanced SiN), H - rich SiN can be applied. That is, by applying a nitride film having a high hydrogen content, a hydrogen path can be formed during the subsequent heat treatment for activating the channel layer 240.

[0092] The upper insulating structure 210 may be disposed to entirely cover the common source line CSL and the protection layer 251.

[0093] The upper insulating structure 210 can include a first insulating layer 211, a second insulating layer 212, and a hydrogen supply layer 213. The first insulating layer 211 is a buffer layer 205 and an extended region CSL EIt can cover and form a flat upper surface, can contain an insulating substance, and can contain, for example, silicon oxide, silicon nitride, or silicon oxynitride. The second insulating layer 212 can contain silicon oxide, silicon nitride, or silicon oxynitride like the first insulating layer 211, but can be formed to have a thickness smaller than that of the first insulating layer 211. The hydrogen supply layer 213 is H-rich SiN and can be formed of a material such as PE-SiN. Annealing can be performed in a state where the hydrogen supply layer 213 is formed, and a hydrogen path to the channel layer 240 can be formed. For this purpose, the first insulating layer 211 can contain TEOS, and the second insulating layer 212 can contain HDP oxide, but is not limited thereto.

[0094] The second semiconductor structure S2 can further include a source contact via 255 on the second conductive layer 202 and a source connection wiring 256 on the source contact via 255, and the source connection wiring 256 on the second conductive layer 202 is disposed on the first insulating layer 211 or the second insulating layer 212. The source contact via 255 can penetrate the underlying insulating layers 205 and 211.

[0095] Also, in the edge region EA, an upper stud 257 connecting the external contact via 275 and the pad region 258 may be disposed, and the pad region 258 may be disposed on the first insulating layer 211. The upper stud 257 may be disposed in a multilayer structure. When the upper stud 257 is disposed in multiple layers, a wiring structure may be further disposed therebetween, but is not limited thereto. The second insulating layer 212 and the hydrogen supply layer 213 may be disposed so as to cover the edge of the pad region 258, and the central region of the pad region 258 may be provided in a state of being exposed to the outside and connectable to a wire or the like.

[0096] The passivation layer 215 can be disposed on the upper surface of the hydrogen supply layer 213. The passivation layer 215 can function as a layer for protecting the semiconductor device 10. In an exemplary embodiment, the passivation layer 215 has openings OI in some regions, thereby defining the pad region 258 connected to the outside. The passivation layer 215 can contain an organic substance, but in contrast, it can contain at least one of silicon oxide and silicon carbide and can function as a capping layer.

[0097] The upper wiring structures 271 and 272 can electrically connect the gate electrode 230 and the channel structure CH to the circuit element 120. The upper wiring structures 271 and 272 can include studs 272 connected to the channel structure CH, studs 272 connected to the contact plug 270, and studs 272 connected to the external contact via 275. The stud 272 connected to the channel structure CH can be connected to the channel pad 249 of the channel structure CH. The stud 272 connected to the channel structure CH can be electrically connected to the channel layer 240 via the channel pad 249 of the channel structure CH in the first region R1. In the first extended region R2a and the second extended region R2b, the stud 272 can be connected to the contact plug 270 connected to the gate electrode 230. The upper wiring line 271 can be connected to the stud 272. The upper wiring structures 271 and 272 can include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each configuration can further include a diffusion barrier layer including at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). According to an exemplary embodiment, the number of layers and the arrangement form of the studs 272 and the upper wiring line 271 constituting the upper wiring structures 271 and 272 can be variously changed, and high energy and heat are blocked by the protective layer 251 disposed on the upper part, and the diffusion of the metal material of the upper wiring structures 271 and 272 does not proceed, and the element reliability can be improved.

[0098] The upper bonding structure 280 can be connected to the upper wiring structures 271 and 272. For example, the stud 272 may be electrically connected to the upper bonding structure 280. The upper bonding structure 280 can include upper bonding vias 282, upper bonding pads 284, and an upper bonding insulating layer 286. The upper bonding vias 282 can be connected to the upper wiring structure 270. The upper bonding pads 284 can be connected to the upper bonding vias 282. The upper bonding vias 282 and the upper bonding pads 284 can include a conductive material, for example, can include tungsten (W), copper (Cu), aluminum (Al), etc., and each configuration can further include a diffusion barrier. The upper bonding insulating layer 286 can also function as a diffusion prevention layer for the upper bonding pad 284 and can include at least one of SiCN, SiO, SiN, SiOC, SiON, and SiOCN. The upper bonding insulating layer 286 can have a thickness thinner than the thickness of the upper bonding pad 284, but is not limited thereto.

[0099] Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6a to 12. FIGS. 6a and 6b are enlarged views of a semiconductor device according to an exemplary embodiment, and are an enlargement of the "C" region in FIG. 4b.

[0100] Referring to FIG. 6a, the semiconductor device 10a is the same as FIG. 5b except that an extended region CSL of the common source line CSL E is formed to have a width W3 smaller than the upper surface width W2 on the upper surface of the cell guide structure CD.

[0101] Specifically, in the semiconductor device 10a, a common source line CSL is disposed in a cell guide structure CD that defines a first region R1 in which a channel structure CH is disposed. The common source line CSL can have a stacked structure of a first conductive layer 201 and a second conductive layer 202 as described above. When the common source line CSL is disposed within the frame formed by the cell guide structure CD, the first conductive layer 201 and the second conductive layer 202 extend along the inner surface of the cell guide structure CD and an extended region CSL that extends above the upper surface of the cell guide structure CD E can be included. The above extended region CSL E can extend by being bent from the inner surface of the cell guide structure CD so as to have a width W3 smaller than the width W2 of the upper surface of the cell guide structure CD. Therefore, side ends of the above extended region CSL E can be exposed above the upper surface of the cell guide structure CD.

[0102] Referring to FIG. 6b, the semiconductor device 10b is the same as FIG. 5b except that the extended region CSL of the common source line CSL E is not bent above the upper surface of the cell guide structure CD.

[0103] Specifically, in the semiconductor device 10b, a common source line CSL is disposed in a cell guide structure CD that defines a first region R1 in which a channel structure CH is disposed. The common source line CSL can have a stacked structure of a first conductive layer 201 and a second conductive layer 202 as described above. When the common source line CSL is disposed within the frame formed by the cell guide structure CD, the first conductive layer 201 and the second conductive layer 202 include an extended region CSL that extends along the inner wall of the cell guide structure CD E can be included. The above extended region CSL EThe first conductive layer 201 and the second conductive layer 202 that form can have upper ends that are not bent on the upper surface of the cell guide structure CD and are coplanar with the upper surface of the cell guide structure CD. The buffer layer 205 can be formed so as to embed within the frame on the upper surface and the side surface of the second conductive layer 202, and the upper surface of the buffer layer 205 can also be coplanar with the upper surface of the cell guide structure CD. In this way, by planarizing so that the upper end of the common source line CSL and the buffer layer 205 are coplanar with the upper surface of the cell guide structure CD, the thickness of the layered structure above the channel structure CH is reduced and miniaturization is possible.

[0104] FIGS. 7 and 8 are schematic cross-sectional views of a semiconductor device according to an exemplary embodiment. FIGS. 7 and 8 show the same region as FIG. 4a.

[0105] Referring to FIG. 7, the semiconductor device 10c is the same as FIG. 4a except that a reflection structure RS is further disposed in a region other than the first region R1, and a dummy channel structure DCH is disposed under the cell guide structure CD.

[0106] Specifically, the semiconductor device 10c can further include a reflection structure RS on an extended guide region 250H of the cell guide structure CD that defines the first region R1 where the channel structure CH is disposed. The reflection structure RS is disposed on the first and second extension regions R2a, R2b and the edge region EA, and can be disposed on the cell guide structure CD that is a part of the first region R1. Therefore, the area of the reflection structure RS may be smaller than the area of the protective layer 251.

[0107] The reflection structure RS can include a stacked structure of a first material layer 261 and a second material layer 262, and the first material layer 261 and the second material layer 262 can extend in contact with the upper surface of the extended guide region 250H on the extended guide region 250H of the cell guide structure CD. Therefore, the reflection structure RS extends to the edge region EA, covers all of the lower protective layer 251, and can have an area larger than the area where the protective layer 251 is disposed.

[0108] The first material layer 261 and the second material layer 262 are different material layers from each other. The first material layer 261 can include an oxide film, preferably a silicon oxide film. The second material layer 262 can include a nitride film, preferably a silicon nitride film, and as an example, can include one of SiN, SiON, SiCN, and SiOCN. The thicknesses of the first material layer 261 and the second material layer 262 may be the same as each other, but are not limited thereto. The reflection structure RS has a structure in which the second material layer 262 of a nitride film is laminated on the first material layer 261, and there is a possibility of absorbing or reflecting the energy and heat incident from the outside and not transmitting them to the lower part. That is, the reflection structure RS performs a function similar to that of the lower protective layer 251, but when the oxide film and the nitride film are laminated so as to cross each other in a similar thickness range, the absorption and reflection performance of energy and heat can be improved. An extended region CSL of a common source line CSL is disposed on such a reflection structure RS E can be bent and partially arranged, but is not limited thereto.

[0109] The reflection structure RS does not extend inside the frame of the cell guide structure CD, and by extending from the upper surface of the cell guide structure CD to the outside, it can effectively block the energy transmission to the lower wiring structures 271 and 272 disposed in the extended regions R2a, R2b and the edge region EA.

[0110] On the other hand, in the semiconductor device 10c of FIG. 7, a dummy channel structure DCH can be further disposed under the cell guide structure CD. When the width of the cell guide structure CD is much larger than the width of the channel structure CH, if there is no vertical structure under the cell guide structure CD, dishing may occur and the reliability may decrease. By disposing the dummy channel structure DCH under the cell guide structure CD, it can function as a vertical structure. The configuration of the dummy channel structure DCH is the same as that of the channel structure CH, but it is not connected to the wiring structures 271 and 272. Also, the dummy channel structure DCH can cover the channel layer 240 while the second portion of the information storage structure 245 protruding on the stacked structures GS1 and GS2 is not removed and is maintained as it is. The number of the dummy channel structures DCH can be determined according to the width of the cell guide structure CD.

[0111] Referring to FIG. 8, the semiconductor device 10d is the same as FIG. 7 except for the multilayer structure form of the reflection structure RS in the region other than the first region R1.

[0112] Specifically, in the semiconductor device 10d, the reflection structure RS may be disposed on the guide insulating layer 250. The reflection structure RS is disposed on the first and second extension regions R2a and R2b and the edge region EA, and can be disposed on the cell guide structure CD which is a part of the first region R1. Therefore, the area of the reflection structure RS may be smaller than the area of the protective layer 251.

[0113] The reflective structure RS can have a plurality of stacked pairs of the first material layer 261 and the second material layer 262. As an example, two pairs of stacked pairs of the first material layers 261, 263 and the second material layers 262, 268 may be arranged. Alternatively, three to four pairs of stacked pairs may be arranged. The plurality of first material layers 261, 263 and the plurality of second material layers 262, 268 have similar ranges of thickness and have a stacked structure in which they are alternately stacked. When arranged so as to extend to the edge region EA, the energy absorption and reflection efficiency can be further improved, and the amount of energy transmitted to the lower wiring structures 271, 272 can be significantly reduced. The reflective structure RS does not extend inside the frame of the cell guide structure CD, and by extending outward from the upper surface of the cell guide structure CD, it can effectively block the energy transmission to the lower wiring structures 271, 272 arranged in the extension regions R2a, R2b and the edge region EA.

[0114] FIG. 9a is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 9b is an enlarged cross-sectional view of the “D” region in FIG. 9a.

[0115] Referring to FIGS. 9a and 9b, the semiconductor device 10e of the present invention is the same as FIG. 4a except that the shape of the protruding portion 240a of each channel structure CH includes a head CH_a as shown in FIG. 9b.

[0116] Specifically, the channel structure CH can further include a head CH_a having a width that is expanded at one end.

[0117] In the exemplary embodiment shown in FIG. 9b, the head CH_a of the channel structure CH can have a width W5 that is larger than the width of the protruding portion 240a of the channel layer 240. The head CH_a of the channel structure CH can be formed by a stopper for maintaining the depth of the channel hole uniform in the manufacturing process, but is not limited thereto.

[0118] The head CH_a can have different widths in the z direction. As an example, it can have a width that decreases towards the upper part, but it is not limited to this. The width W4 at the upper part and the width W5 at the lower part of the head CH_a can be formed to be the same. At this time, the width W5 at the lower part of the largest head CH_a can be formed to be larger than the width of the non-projecting part 240b of the channel layer 240.

[0119] At this time, the width W5 of the head CH_a can satisfy about 1 / 2 to 3 / 5 with respect to the separation distance between the channel structures CH adjacent to the channel structure CH.

[0120] Even if the head CH_a is formed, the laminated structure of the first part of the channel structure CH can be formed in the same manner as in FIG. 5a. The height of the protruding part 240a may be the same as the first height h1, or the head CH_a may be formed with a length smaller than the length h1 of the protruding part 240a. On the outermost surface of the head CH_a, the protruding part 240a of the channel layer 240 may be arranged, the inside may be filled with the embedded insulating layer 247, and depending on the embodiment, all may be formed of the channel layer 240.

[0121] In this way, when the head CH_a is formed on the protruding part 240a, the contact area between the first conductive layer 201 and the channel layer 240 can be expanded by the expanded one end, and the inflow amount of charges can be increased.

[0122] In the exemplary embodiment shown in FIG. 9b, not only the channel structure CH but also other vertical structures such as the contact plug 270 can include a head. The head of the contact plug can also be formed by a stopper for maintaining the depth of the contact hole uniform in the manufacturing process, but is not limited thereto. Further, other vertical structures such as the isolation region MS, the supporter structure 265, the external contact via 275, and the dummy channel structure DCH can also have a shape including a head with a stopper applied for a uniform hole depth when forming the hole by HARC etching, but is not limited thereto.

[0123] FIG. 10 is a schematic partial enlarged plan view of a semiconductor device according to an exemplary embodiment.

[0124] The semiconductor device 10f in FIG. 10 is the same as FIGS. 3 and 4a except that the isolation region MS has a flat side surface and the dummy channel structure DCH is disposed below the cell guide structure CD.

[0125] Specifically, in the semiconductor device 10f, a plurality of isolation regions MS crossing the extension regions R2a and R2b in the x direction from the first region R1 are disposed, and each isolation region MS can penetrate a plurality of gate electrodes 230 while extending in the z direction in the second semiconductor structure S2. Different from FIGS. 3, 4a, and 4b, the isolation region MS can form a sacrificial isolation region that penetrates the plurality of mold structures MS1 and MS2 by etching at once in a separate etching process without proceeding with an extension process of connecting them after forming continuous isolation holes like channel holes. Therefore, the isolation region MS can have a flat side surface instead of a side surface having a curved surface.

[0126] On the one hand, as shown in FIGS. 7 and 8, in the semiconductor device 10f, a dummy channel structure DCH can be disposed below the cell guide structure CD. The layer structure of the dummy channel structure DCH may be the same as that of the channel structure CH, but the information storage structure 245 can surround the channel layer 240 as a whole without exposing the protrusion 240a for direct contact with the common source line CSL. Also, since the dummy channel structure DCH is not connected to the wirings 271 and 272, it does not function as an actual memory cell.

[0127] Five to ten dummy channel structures DCH are disposed below the cell guide structure CD extending in the x direction, and ten to fifteen dummy channel structures DCH can be disposed spaced apart from each other below the cell guide structure CD extending in the y direction. Such a dummy channel structure DCH is a vertical structure and can support so as to prevent dishing of the mold structures MS1, MS2 or the stacked structures GS1, GS2.

[0128] FIGS. 11 and 12 are schematic cross-sectional views of a semiconductor device according to an exemplary embodiment.

[0129] The semiconductor device 10g in FIG. 11 is the same as the embodiment in FIGS. 2 to 5b except that the shapes of the stacked structures GS1, GS2 in the extension regions R2a, R2b and the shapes of the contact plugs 270 connected to the respective gate electrodes 230 are different in the extension regions R2a, R2b.

[0130] Specifically, the semiconductor device 10g in FIG. 11 does not include a stepped structure in which the gate electrode 230 of the stacked structure is gradually etched in the extension regions R2a and R2b to expose the gate pad region GP. That is, even in the extension regions R2a and R2b, the gate electrodes 230 of the stacked structure can extend with the same length as each other and maintain the same length from the first region R1 to the extension regions R2a and R2b. At this time, the contact plugs 270 that are selectively connected to the respective gate electrodes 230 to apply signals can extend to different levels in the z direction and contact different gate electrodes 230 from each other.

[0131] The contact plug 270 connected to the uppermost gate electrode 230U extends in the z direction until it contacts the lower surface (upper surface in terms of the process) of the uppermost gate electrode 230U and can extend to a depth that penetrates the uppermost interlayer insulating layer 223.

[0132] The contact plug 270 connected to the gate electrode 230 in the stage next to the uppermost stage extends from the uppermost interlayer insulating layer 223 until it contacts the lower surface (upper surface in terms of the process) of the gate electrode 230 in the stage next to the uppermost stage and can have a length longer than that of the previous contact plug 270. In this way, the contact plug 270 can extend so as to penetrate the gate electrode 230 above the target gate electrode 230 and the interlayer insulating layer 220 so as to directly contact the lower surface (upper surface in terms of the process) of each stage of the gate electrode 230.

[0133] Each contact plug 270 can include a conductive contact layer 276 that extends from the uppermost interlayer insulating layer 223 to the lower surface (upper surface in terms of the process) of the target gate electrode 230, and can include a plug insulating layer 277 that surrounds the conductive contact layer 276.

[0134] The plug insulating layer 277 is formed on the side surfaces of the contact holes forming the respective contact plugs 270, and the conductive contact layer 276 can be arranged to fill the contact holes in the plug insulating layer 277. At this time, the plug insulating layer 277 is removed from the lower surface of each contact hole, that is, the region in contact with the lower surface (upper surface in the process) of the gate electrode 230, and at the lower surface of each contact hole, the conductive contact layer 276 is exposed and can be in direct contact with the lower surface (upper surface in the process) of the target gate electrode 230. In this way, each contact plug 270 can be in direct contact with the target gate electrode 230 with the insulating layer 277 on the side surface, so that the step etching for the pad regions GP of the plurality of gate electrodes 230 can be omitted, and the process can be very simple.

[0135] The semiconductor device 10h in FIG. 12 is the same as FIGS. 3 to 5b except that the upper channel structure CH3 is arranged on the first and second channel structures CH1 and CH2 to form one channel structure CH.

[0136] The upper channel structure CH3 can extend in the z direction through the upper gate electrode 293 (230U2) and be connected to the channel structures CH1 and CH2 respectively. The upper channel structure CH3 may be arranged on the channel structures CH1 and CH2 respectively and shifted horizontally from the channel structures CH1 and CH2, but is not limited thereto.

[0137] As shown in FIG. 12, each of the upper channel structures CH3 can include an upper channel layer, an upper gate dielectric layer, an upper channel buried insulating layer, and an upper channel pad arranged in the upper channel hole. The upper channel layer can be formed in an annular shape surrounding the internal upper channel buried insulating layer. The upper channel layer is connected to the connection pad 295 at the lower part and can be electrically connected to the channel layers 240 of the lower channel structures CH1 and CH2 through the connection pad 295.

[0138] The descriptions of the materials of the upper channel layer, upper gate dielectric layer, upper channel embedding insulating layer, and upper channel pad can be similarly applied to the descriptions of the lower channel layer 240, information storage structure 245, channel embedding insulating layer 247, and channel pad layer 249 described above, respectively.

[0139] The horizontal insulating layer 292 is disposed between the lower channel structures CH1, CH2 and the upper channel structure CH3 and can extend horizontally. The horizontal insulating layer 292 can be disposed between the upper gate electrode 230U2 and the uppermost interlayer insulating layer 223. The horizontal insulating layer 292 can be used as an etching stop layer during the formation of the upper channel structure CH3 and can also be a layer used during the formation of the connection pad 295.

[0140] The horizontal insulating layer 292 contains an insulating material and can contain a material different from that of the interlayer insulating layer 223. The horizontal insulating layer 292 can be a hydrogen blocking layer and can contain a material that prevents or reduces the diffusion of hydrogen (H). The horizontal insulating layer 292 can contain a nitride, for example, it can contain at least one of SiN, SiON, SiCN, and SiOCN.

[0141] The connection pad 295 penetrates the horizontal insulating layer 292 between the lower channel structures CH1, CH2 and the upper channel structure CH3 and can electrically connect the lower channel layer 240 and the upper channel layer. The connection pad 295 is formed by partially removing the horizontal insulating layer 292 and can have an upper surface coplanar with the upper surface of the horizontal insulating layer 292. The connection pad 295 may be disposed in a form in which a part of the lower channel pad layer is recessed. However, the specific arrangement form of the connection pad 295 can be variously changed in the embodiments. The connection pad 295 can contain a conductive material, for example, it can contain polycrystalline silicon.

[0142] The upper insulating region SS can extend in the x direction between the separation regions MS adjacent to each other. The upper insulating region SS can penetrate the upper gate electrode 293 (230U2) disposed on the uppermost part of the gate electrode 230. The upper insulating region SS can divide the upper gate electrode 293 (230U2) in the y direction. A part of the upper insulating region SS may be disposed on the separation region MS.

[0143] Therefore, as shown in FIG. 4b, the upper insulating region SS is not formed by sinking a part of the channel structure CH, and can be arranged to separate only the upper gate electrode 293 (230U2).

[0144] Each of the upper insulating regions SS can include an upper separation insulating layer 266. The upper separation insulating layer 266 can include an insulating material, for example, can include silicon oxide, silicon nitride, or silicon oxynitride.

[0145] The second horizontal insulating layer 294 may be arranged to cover the upper gate electrode 293 (230U2). The second horizontal region insulating layer 294 is disposed on the horizontal insulating layer 292 and can cover the side surfaces of the upper gate electrode 293 (230U2). The lower insulating layer 291 may be disposed on the second horizontal region insulating layer 294, and the lower insulating layer 291 and the second horizontal region insulating layer 294 may be made of an insulating material or may be made of a plurality of insulating layers.

[0146] FIGS. 13a to 13o are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. FIGS. 13a to 13o show regions corresponding to FIG. 4a.

[0147] Referring to FIG. 13a, a first semiconductor structure (S1: PERI) including a circuit element 120 forming a peripheral circuit region PERI, a lower wiring structure 130, a lower bonding structure 180, and a lower capping layer 190 can be formed on a first substrate 101.

[0148] First, an element isolation layer 110 can be formed in the first substrate 101, and a circuit gate dielectric layer 122 and a circuit gate electrode 124 can be sequentially formed on the first substrate 101. The element isolation layer 110 can be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 122 is formed on the first substrate 101, and the circuit gate electrode 124 can be formed on the circuit gate dielectric layer 122. The circuit gate dielectric layer 122 and the circuit gate electrode 124 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 122 is formed of silicon oxide, and the circuit gate electrode 124 may be formed of at least one of polycrystalline silicon or a metal silicide layer, but is not necessarily limited thereto. Next, a spacer layer 126 can be formed on both sidewalls of the circuit gate dielectric layer 122 and the circuit gate electrode 124, and impurities can be implanted into the active region of the first substrate 101 on both sides of the circuit gate electrode 124 to form the source / drain regions 105.

[0149] Among the lower wiring structures 130, the lower contact plug 135 can be formed by forming a part of the lower capping layer 190, then etching and removing a part thereof, and filling a conductive material. The lower wiring line 137 can be formed, for example, by depositing a conductive material and then patterning it.

[0150] Among the lower bonding structures 180, the lower bonding vias 182 can be formed by forming a part of the lower capping layer 190, then etching and removing a part thereof, and embedding a conductive material. The lower bonding pads 184 can be formed, for example, by depositing a conductive material and then patterning it. The lower bonding structure 180 can be formed, for example, by a vapor deposition process or a plating process. The lower bonding insulating layer 186 can be formed by forming it so as to cover the upper surface and a part of the side surface of the lower bonding pad 184, and then performing a planarization process until the upper surface of the lower bonding pad 184 is exposed.

[0151] The lower capping layer 190 can be composed of a plurality of insulating layers. The lower capping layer 190 may be a part thereof at each stage of forming the lower wiring structure 130 and the lower bonding structure 180. Thereby, the first semiconductor structure S1 which is the peripheral circuit region PERI can be formed.

[0152] Referring to FIG. 13b, the manufacturing process of the second semiconductor structure (S2: CELL) can be started.

[0153] Referring to FIG. 13b, the manufacturing process of the second substrate structure (S2: CELL) can be started. The sacrificial insulating layer 118 and the interlayer insulating layer 220 are alternately laminated on the base substrate 300 (SUB) to form the mold structures MS1 and MS2, and the sacrificial vertical structures 216 and 217 can be formed at the positions where the respective vertical structures are formed.

[0154] The above-mentioned lower mold structure MS1 may be formed on the base substrate 300 at the height where the first channel structure CH1 (see FIG. 4a) is arranged.

[0155] The base substrate 300 can contain a semiconductor material, for example, a group IV semiconductor, a III-V compound semiconductor, or a II-VI compound semiconductor.

[0156] The sacrificial insulating layer 218 can be a layer that is at least partially replaced by a part of the gate electrode 230 (see FIG. 4a) in a subsequent process. The sacrificial insulating layer 218 can be made of a material different from that of the interlayer insulating layer 220. For example, the interlayer insulating layer 220 and the uppermost, middle, and lowermost interlayer insulating layers 222, 223, 225 can be made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 218 can be made of a material different from the interlayer insulating layer 220 selected from among silicon, silicon oxide, silicon carbide, and silicon nitride. In an embodiment, the thicknesses of the interlayer insulating layers 220 may not all be the same. Also, the thicknesses and the number of films constituting the interlayer insulating layer 220 and the sacrificial insulating layer 218 can be variously changed from those shown in the figure.

[0157] The interlayer insulating layer 220 and the sacrificial insulating layer 218 forming the lower mold structure MS1 are alternately laminated on the base substrate 300.

[0158] The gate pad region GP can be formed by repeatedly performing a photolithography process and an etching process on the sacrificial insulating layer 218 and the interlayer insulating layer 220. The gate pad region GP is formed in the second region R2 and can be formed to include a region where the upper sacrificial insulating layer 218 extends shorter than the lower sacrificial insulating layer 218. In the gate pad region GP, an asymmetrical step structure can be formed such that the upper surfaces and ends of the plurality of sacrificial insulating layers 218 are exposed upward. However, in an embodiment, the specific form of the gate pad region GP can be variously changed. A sacrificial insulating layer 218 is further formed on the step structure of the gate pad region GP, and the sacrificial insulating layer 218 located at the uppermost part of each region can be formed to have a relatively large thickness.

[0159] When forming a channel hole for forming the vertical sacrificial structures 216a, 216b, a blocking structure can be formed first to maintain a uniform depth at which the channel hole is recessed into the base substrate 300.

[0160] At the position where the channel hole is formed in the base substrate 300, as a blocking structure (not shown), it can be formed of a material having an etching selectivity with respect to the base substrate 300 for the anisotropic etching. As an example, it may be a metal material such as tungsten (W). When the channel hole is formed in a state where the blocking structure is formed for each channel hole, the blocking structure can prevent the channel hole from being formed below the sacrificial blocking structure. Thereafter, the blocking structure is removed through the channel hole, and a channel structure CH having a head CH_a as shown in FIG. 9b can be formed according to the shape of the blocking structure.

[0161] Next, a lower cell capping layer 290 covering the lower mold structure MS1 can be formed, and a first vertical sacrificial layer 216a penetrating the lower mold structure MS1 can be formed.

[0162] The first vertical sacrificial layer 216a can be formed at a position corresponding to the lower part of the first channel structure CH1 in the first region R1. The first contact sacrificial layer 217a can be formed at positions corresponding to the contact plug 270 (see FIG. 4a) in the first and second extension regions R2a and R2b. The first vertical sacrificial layer 216a and the first contact sacrificial layer 217a may be formed simultaneously. The first vertical sacrificial layer 216a and the first contact sacrificial layer 217a can be formed by forming holes so as to penetrate the lower mold structure MS1, depositing a sacrificial layer material in the holes, and performing a planarization process. The holes can include holes corresponding to the channel structure CH, the support structure 265, the contact plug 270, and the external contact via 275. Further, when forming the holes, a plurality of separation holes spaced apart from each other can be formed in a region corresponding to the separation region MS, and a vertical sacrificial layer (not shown) filling the plurality of separation holes can be formed together. The vertical sacrificial layer including the first vertical sacrificial layer 216a and the first contact sacrificial layer 217a can include at least one of TiN and polycrystalline silicon, for example.

[0163] Next, a sacrificial insulating layer 218 and an interlayer insulating layer 220 forming an upper mold structure MS2 are alternately laminated on a lower mold structure MS1 to form a stepped structure GP, an upper capping layer 290 is formed, and a second vertical sacrificial layer 216b and a second contact sacrificial layer 217b can be formed.

[0164] Each component of the upper mold structure MS2 can be formed in the same manner as the formation method of the lower mold structure MS1.

[0165] The second vertical sacrificial layer 216b can be formed so as to be connected to the first vertical sacrificial layer 216a respectively. The second contact sacrificial layer 217b can be formed so as to be connected to the first contact sacrificial layer 217a respectively. The second vertical sacrificial layer 216b and the second contact sacrificial layer 217b can be formed by depositing the same material as the first vertical sacrificial layer 216a, for example, polycrystalline silicon. Further, the vertical sacrificial layer for the support structure 265, the vertical sacrificial layer for the separation region MS, and the vertical sacrificial layer for the external contact via 275 can all be formed by depositing the same material, for example, polycrystalline silicon.

[0166] Therefore, all the vertical structures in FIGS. 4a and 4b, the external contact via 275, the channel structure CH, the support structure 265, the contact plug 270, and the plurality of vertical sacrificial layers forming the separation region MS can be formed simultaneously. By simultaneously forming holes for vertical structures in such an all-in-one etching (all-in-one HARC etching) method, it is possible to minimize the formation of arcs on the base substrate 300 due to the injection of high energy for etching the mold structures MS1 and MS2.

[0167] As shown in FIG. 13c, a channel structure CH penetrating the mold structures MS1 and MS2 of the sacrificial insulating layer 218 and the interlayer insulating layer 220 can be formed on the base substrate 300.

[0168] The channel structure CH can be formed by forming upper holes on the vertical sacrificial layers 216a and 216b, then removing the vertical sacrificial layers 216a and 216b to form hole-shaped channel holes, and embedding the channel holes with a plurality of layers. The plurality of layers can include an information storage structure 245, a channel layer 240, an embedded insulating layer 247, and a channel pad 249. The upper channel holes of the channel holes can be formed by anisotropically etching the upper stacked structure of the sacrificial insulating layer 218 and the interlayer insulating layer 220 using another mask layer. The lower channel holes of the channel holes can be formed by removing the vertical sacrificial layer exposed through the upper channel holes.

[0169] Due to the heights of the mold structures MS1 and MS2, the sidewalls of the channel structure CH may not be perpendicular to the upper surface of the base substrate 300. The channel structure CH may be formed to recess a part of the base substrate 300 according to the depth of the channel holes.

[0170] The information storage structure 245 can be formed to have a uniform thickness. In this step, all or part of the information storage structure 245 can be formed, and a portion extending perpendicular to the base substrate 300 along the channel structure CH can be formed in this step. The channel layer 240 may be formed on the information storage structure 245 within the channel structure CH. The embedded insulating layer 247 can be formed to fill the channel structure CH and may be an insulating material. The channel pad 249 can be made of a conductive material, for example, polycrystalline silicon. The support structures 265 (see FIG. 3) of the first and second extension regions R2a and R2b can also be formed in a similar manner. Specifically, the support structure 265 can be formed by removing the vertical sacrificial layer to form support holes and then embedding the support holes with a support insulating layer.

[0171] Referring to FIG. 13d, a preliminary contact insulating layer 260P and a vertical sacrificial layer 270P can be formed in a region corresponding to the contact plug 270.

[0172] First, the contact sacrificial layer 217 in the region corresponding to the contact plug 270 can be removed to form a contact hole. A part of the sacrificial insulating layer 218 exposed through the contact hole can be removed. The sacrificial insulating layer 218 can be removed from around the contact hole by a predetermined length to form a contact tunnel portion. The contact tunnel portion can be formed with a relatively short length in the uppermost sacrificial insulating layer 218 and a relatively long length in the lower sacrificial insulating layer 218.

[0173] Specifically, initially, conversely, the contact tunnel portion can be formed relatively long in the uppermost sacrificial insulating layer 218. This may be due to the uppermost sacrificial insulating layer 218 including a region where the etching rate is relatively faster than that of the lower sacrificial insulating layer 218. Next, another sacrificial layer can be formed in the contact hole and the contact tunnel portion. The sacrificial layer can be made of a material with an etching rate slower than that of the sacrificial insulating layer 218. Next, a part of the sacrificial layer and the sacrificial insulating layer 218 can be removed. At this time, at the uppermost part, the sacrificial layer remains, and at the lower part, a part of the sacrificial insulating layer 218 can be removed after the sacrificial layer is removed. Thereby, finally, the contact tunnel portion can be formed with a relatively short length in the uppermost sacrificial insulating layer 218.

[0174] An insulating material can be deposited in the contact hole and the contact tunnel portion to form a preliminary contact insulating layer 260P. The preliminary contact insulating layer 260P is formed on the sidewall of the contact hole and can fill the contact tunnel portion. In the uppermost sacrificial insulating layer 218, the preliminary contact insulating layer 260P does not have to completely fill the contact tunnel portion.

[0175] The vertical sacrificial layer 270P can fill the contact hole and the uppermost contact tunnel portion. The vertical sacrificial layer 270P can contain a substance different from the preliminary contact insulating layer 260P, and can contain, for example, polycrystalline silicon.

[0176] As shown in FIG. 13e, the vertical sacrificial layer filling the isolation hole formed at the position of the isolation region MS is removed, and the isolation hole is expanded by washing or the like and connected to each other, so that openings connected to each other in the x direction can be formed as shown in FIG. 3. By connecting a plurality of isolation holes to each other while expanding in the circumferential direction, the side surface forming the isolation region MS can have a shape in which an outwardly convex curve is continuous. By wet etching in the thus-expanded opening, the sacrificial insulating layer 218 is selectively removed with respect to the interlayer insulating layer 220 and the preliminary contact insulating layer 260P, and the gate electrode 230 can be formed.

[0177] The gate electrode 230 can be formed by depositing a conductive substance in a region where the sacrificial insulating layer 218 has been removed. The conductive substance can include a metal, polycrystalline silicon, or a metal silicide substance. In some embodiments, a part of the gate dielectric layer may be formed first before forming the gate electrode 230.

[0178] After forming the gate electrode 230, the gate isolation insulating layer 264 (see FIG. 4b) can be formed in the opening formed corresponding to the isolation region MS.

[0179] Referring to FIG. 13f, the contact plug 270 can be formed.

[0180] The vertical sacrificial layer 270P corresponding to the contact plug 270 can be removed, and a part of the preliminary contact insulating layer 260P can be removed.

[0181] The vertical sacrificial layer 270P can be selectively removed with respect to the interlayer insulating layer 220 and the gate electrode 230. A part of the preliminary contact insulating layer 260P exposed after the vertical sacrificial layer 270P is removed can also be removed. At this time, in the uppermost gate electrode 230 corresponding to the contact region, all of the preliminary contact insulating layer 260P can be removed, and below it, the contact insulating layer 260 can remain to form. In the contact region, when the gate dielectric layer is exposed after the preliminary contact insulating layer 260P is removed, the gate dielectric layer can also be removed to expose the side surface of the gate electrode 230.

[0182] A contact plug 270 and an external contact via 275 can be formed.

[0183] The contact plug 270 and the external contact via 275 can be formed by depositing a conductive material in the removed contact hole. The contact plug 270 can be formed to have a horizontal extension part 270H (see FIG. 4a) that extends horizontally in the contact region, whereby it can be physically and electrically connected to the gate electrode 230. The external contact via 275 may be deposited together with the contact plug 270 or may be deposited and formed in another process.

[0184] Referring to FIG. 13g, an upper wiring structure 271, 272 including studs 272 and an upper wiring 271 can be formed, and an upper bonding structure 280 can be formed.

[0185] In the first region R1, the stud 272 can be formed to be connected to the channel structure CH. In the first and second extension regions R2a, R2b, the stud 272 can be formed to be connected to the contact plug 270. Also, studs 272 connected to the external contact via 275 can be formed together in the first and second extension regions R2a, R2b. Each stud 272 can be vertically connected to the upper wiring 271 and can be connected in multiple layers via another plug.

[0186] Next, the upper bonding structure 280 can be formed in the same manner as forming the lower bonding structure 180. Thereby, the second semiconductor structure S2 which is the memory cell structure CELL can be formed. However, in the manufacturing process of the semiconductor device 10, the second semiconductor structure S2 may further include the base substrate 300.

[0187] Referring to FIG. 13h, the stacked structures GS1 and GS2 on which the base substrate 300 is formed can be transferred onto the carrier substrate 310 and turned over so that the lower base substrate 300 is exposed upward.

[0188] Specifically, when the stacked structures GS1 and GS2 are turned over so that the upper bonding structure 280 abuts on the carrier substrate 310, the channel structure CH, the isolation region MS, the contact plug 270, and the external contact via 275 can be reversely arranged so that their widths increase as they go downward under the base substrate 300 exposed upward. Next, the base substrate 300 can be removed to form a state in which the lowermost interlayer insulating layer 222 and the lowermost portions of the channel structure CH and the contact plug 270 protrude. At this time, by not forming a separate layer as an etching prevention film for the channel structure CH between the base substrates 300, the base substrate 300 can be removed at a very high speed. Next, a protective layer 251 can be formed on the uppermost surface of the exposed stacked structures GS1 and GS2. The protective layer 251 can be formed to cover the entire mat MAT and have a predetermined thickness, and the predetermined thickness can be formed to have a height corresponding to the height of the cell guide structure CD, and can be 300 to 500 nm. The protective layer 251 can be entirely formed by plasma CVD by applying PE-SiN, and at this time, it can proceed in a hydrogen atmosphere to form an H-rich SiN layer containing a large amount of hydrogen.

[0189] As shown in FIG. 13i, an opening can be formed in a region surrounding the first region R1 within the protective layer 251. The opening can proceed until the upper surface of the lowermost interlayer insulating layer 222 in the lower part is exposed, and can be selectively formed in the region where the cell guide structure CD of FIG. 2 is disposed. The opening can be formed by selectively removing the protective layer 251 with a mask pattern, and can be formed to have an inclined side surface such that the width of the upper part of the opening is larger than the width of the lower part. The opening can be filled, and the cell guide insulating layer 250 can be formed on the protective layer 251. The cell guide insulating layer 250 can form a cell guide structure region 250V that fills the opening, and can be formed with a sufficient thickness to cover the protective layer 251, and an oxide film can be deposited to have a predetermined thickness on the protective layer 251 to form an extended guide region 250H on the protective layer 251. By such deposition, a cell guide structure CD as shown in FIG. 3 can be formed in a frame shape within the opening, and can function as a dam that defines the memory cell region R1 and other regions in the subsequent process.

[0190] Next, as shown in FIG. 13j, the protective layer 251 inside the frame of the cell guide structure CD can be selectively removed to form the first region opening OP.

[0191] The first region opening OP can be formed along the inner side surface of the cell guide structure CD, so that the angle formed by the side surface and the bottom surface can be an acute angle, and can have a shape in which the width becomes narrower toward the upper part.

[0192] The information storage structure 245 on the second portion of the channel structure CH exposed within the first region opening OP can be removed. The information storage structure 245 can be removed by an etching process such as a photolithography process and a wet etching and / or a dry etching. Thereby, within the first region opening OP, the second portion of the channel structure CH protruding on the stacked structures GS1, GS2 can have the channel layer 240 exposed and the protrusion 240a disposed thereon. Thus, when subsequent processes are performed, the channel layer 240 of the second portion can be in direct contact with the first conductive layer 201. At this time, an etching process for continuous removal of an oxide film, a nitride film, and an oxide film is performed, and a part of the uppermost interlayer insulating layer 222 containing an oxide is etched together so that the upper surface of the uppermost interlayer insulating layer 222 within the first region opening OP can be lowered to have a level lower than the lower surfaces of the cell guide structure CD and the protective layer 251. When including the reflection structure RS as shown in FIGS. 7 and 8, each stacked pair for forming the reflection structure RS on the guide insulating layer 250 can be sequentially formed.

[0193] Next, as shown in FIG. 3k, the first conductive layer 201 can be formed so as to cover the entire mat MAT. The first conductive layer 201 can be formed by depositing a semiconductor layer, specifically a crystalline silicon layer, for example, a polycrystalline silicon layer 201a. At this time, the polycrystalline silicon layer 201a formed entirely on the upper surface of the mat MAT may be formed to have a bend along the channel structure CH protruding within the first region opening OP. Thus, the thickness of the polycrystalline silicon layer 201a on the protective layer 251 may be different from the thickness of the polycrystalline silicon layer 201a within the first region opening OP.

[0194] At this time, an MLA (Melting laser annealing) process can be performed to activate the polycrystalline silicon layer 201a. The MLA process is a process in which impurities in the polycrystalline silicon layer 201a diffuse through laser annealing and the crystal is recrystallized. It is performed by a high-temperature and high-energy laser and is performed simultaneously on the entire MAT. In such an MLA process, the first and second extension regions R2a, R2b, and the edge region EA where the protective layer 251 is formed can prevent energy and heat from passing through to the lower part by the protective layer 251 absorbing high energy and heat. Therefore, it is possible to prevent defects such as diffusion of copper metal without affecting the wiring structures 271, 272 containing copper disposed below the stacked structures GS1, GS2. After the polycrystalline silicon layer 201a is melted through such an MLA process, a recrystallization process is performed, and the upper surface of the polycrystalline silicon layer 201a in the first region opening OP having a bend is formed flat, and the first conductive layer 201 can be formed. Thereby, the upper surface of the first conductive layer 201 in the first region R1 is flat, and its thickness h2 can have a value larger than the thickness h4 of the first conductive layer 201 on the cell guide structure CD.

[0195] As shown in FIG. 13l, the second conductive layer 202 can be formed on the first conductive layer 201, and the buffer layer 205 can be continuously formed. Specifically, the second conductive layer 202 can be formed by continuously depositing an ohmic contact layer 202b, a conductive metal layer 202a, and a diffusion barrier 202c, and can be formed such that the thickness of the conductive metal layer 202a has a significantly large value. The second conductive layer 202 can entirely cover, and the buffer layer 205 can be conformally formed. As the buffer layer 205, an oxide film, for example, a silicon oxide film can be formed.

[0196] As shown in FIG. 13m, the first conductive layer 201, the second conductive layer 202, and the buffer layer 205 are located within the first region R1 and can be etched so as not to extend into the first and second extended regions R2a, R2b, and the edge region EA. Such etching of the first conductive layer 201, the second conductive layer 202, and the buffer layer 205 can be performed through a mask pattern, and can be patterned to have an extended region CSL covering the upper surface of the cell guide structure CD as shown in FIG. 4a E but can also be formed as shown in FIG. 6a or FIG. 6b. Next, the first insulating layer 211 can be formed with a predetermined thickness over the entire mat MAT so that the upper surface becomes flat.

[0197] As shown in FIG. 13n, an upper insulating structure 210 can be formed by successively forming a second insulating layer 212 and a hydrogen supply layer 213 over the first insulating layer 211, and the upper structure can be completed by forming a passivation layer 215. Specifically, after further forming the second insulating layer 212 and the hydrogen supply layer 213 over the first insulating layer 211 and opening the first insulating layer 211 to the hydrogen supply layer 213 to form a source contact via 255, a source wiring 256 connected to the source contact via 255 can be formed within the second insulating layer 212 or the hydrogen supply layer 213. A plurality of common contact vias 255 can be formed within one mat MAT and can simultaneously transmit a common source voltage to the common source line CSL, and the source wirings 256 therefor may be connected to each other. The passivation layer 215 can be formed so as to cover the common source line CSL. The passivation layer 215 can be flattened by a polishing process such as a grinding process or a Chemical Mechanical Polishing process. In a subsequent process, a part of the passivation layer 215 can be removed to form an input / output pad region 258, but is not limited thereto.

[0198] As shown in FIG. 13o, the first semiconductor structure S1 which is a peripheral circuit structure PERI and the second semiconductor structure S2 which is a memory cell structure CELL can be joined.

[0199] The first semiconductor structure S1 and the second semiconductor structure S2 separated from the carrier substrate 310 can be connected by bonding the lower bonding pad 184 and the upper bonding pad 284 under pressure. The lower bonding insulating layer 186 and the upper bonding insulating layer 286 can be connected by bonding them under pressure. On the first semiconductor structure S1, the second semiconductor structure S2 can be bonded such that the upper bonding pad 284 faces downward. The first semiconductor structure S1 and the second semiconductor structure S2 can be directly bonded without an intervening adhesive such as a separate adhesive layer.

[0200] FIG. 14 is a diagram schematically showing a data storage system including a semiconductor device according to an exemplary embodiment.

[0201] Referring to FIG. 14, the data storage system 1000 can include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive device (SSD device), a USB (Universal Serial Bus), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0202] The semiconductor device 1100 may be a non-volatile memory device, for example, it may be the NAND flash memory device described above with reference to FIGS. 1 to 5b. The semiconductor device 1100 can include a first semiconductor structure 1100F and a second semiconductor structure 1100S on the first semiconductor structure 1100F. According to an exemplary embodiment, the first semiconductor structure 1100F may be disposed adjacent to the second semiconductor structure 1100S. The first semiconductor structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second semiconductor structure 1100S may be a memory cell structure including bit lines BL, a common source line CSL, word lines WL, first and second upper gate lines UL1, UL2, first and second lower gate lines LL1, LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0203] In the second semiconductor structure 1100S, each memory cell string CSTR can include lower transistors LT1, LT2 adjacent to the common source line CSL, upper transistors UT1, UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1, LT2 and the upper transistors UT1, UT2. The number of the lower transistors LT1, LT2 and the number of the upper transistors UT1, UT2 can be variously deformed according to the embodiment.

[0204] According to an exemplary embodiment, the upper transistors UT1, UT2 can include string selection transistors, and the lower transistors LT1, LT2 can include ground selection transistors. The lower gate lines LL1, LL2 may be gate electrodes of the lower transistors LT1, LT2 respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1, UL2 may be gate electrodes of the upper transistors UT1, UT2 respectively.

[0205] According to an exemplary embodiment, the lower transistors LT1, LT2 can include the grounded selection transistors LT1, LT2 connected in series. The upper transistors UT1, UT2 can include the string selection transistors UT1, UT2 connected in series.

[0206] The common source line CSL, the first and second gate lower lines LL1, LL2, the word line WL, and the first and second gate upper lines UL1, UL2 may be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from within the first semiconductor structure 1100F to the second semiconductor structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from within the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0207] In the first semiconductor structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors. The decoder circuit 1110 and the page buffer 1120 can be controlled by a logic circuit 1130. The semiconductor device 1000 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 via an input / output connection wiring 1135 extending from within the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0208] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the data storage system 1000 can include a plurality of semiconductor devices 1100, in which case the controller 1200 can control the plurality of semiconductor devices 1000.

[0209] Processor 1210 can control the operation of the entire data storage system 1000 including controller 1200. Processor 1210 can operate according to a predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 can include a NAND interface 1221 that processes communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be recorded in memory cell transistors MCT of semiconductor device 1100, data to be read from memory cell transistors MCT of semiconductor device 1100, etc. can be transmitted. Host interface 1230 can provide a communication function between data storage system 1000 and an external host. When a control command is received from the external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0210] FIG. 15 is a perspective view schematically showing a data storage system including a semiconductor device according to an exemplary embodiment.

[0211] Referring to FIG. 15, a data storage system 2000 according to an exemplary embodiment of the present invention can include a main board 2001, a controller 2002 mounted on main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. Semiconductor package 2003 and DRAM 2004 may be connected to each other and to controller 2002 by a wiring pattern 2005 formed on main board 2001.

[0212] The main board 2001 can include a connector 2006 including a plurality of pins for coupling with an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the data storage system 2000 and the external host. According to an exemplary embodiment, the data storage system 2000 can communicate with the external host by any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). According to an exemplary embodiment, the data storage system 2000 can operate by power supplied from the external host via the connector 2006. The data storage system 2000 may further include a PMIC (Power Management Integrated Circuit) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0213] The controller 2002 can record data in the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0214] The DRAM 2004 may be a buffer memory for alleviating the speed difference between the semiconductor package 2003, which is a data storage space, and the external host. The DRAM 2004 included in the data storage system 2000 can also operate as a kind of cache memory and can provide a space for temporarily storing data in the control operation for the semiconductor package 2003. When the DRAM 2004 is included in the data storage system 2000, the controller 2002 can further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0215] The semiconductor package 2003 can include first and second semiconductor packages 2003a and 2003b that are separated from each other. The first and second semiconductor packages 2003a and 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b can include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on each lower surface of the semiconductor chips 2200, a connection structure 2400 that electrically connects the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0216] The package substrate 2100 may be a printed circuit board including package upper pads 2130. Each semiconductor chip 2200 can include input / output pads 2210. The input / output pads 2210 can correspond to the input / output pads 1101 of FIG. 14 and can be an area including the pad region 258 of FIG. 4b. Each of the semiconductor chips 2200 can include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 can include the semiconductor device described above with reference to FIGS. 1 to 12.

[0217] According to an exemplary embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 and the package top pads 2130. Thus, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 can be electrically connected to each other in a bonding wire manner and can be electrically connected to the package top pads 2130 of the package substrate 2100. Depending on the embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including through-silicon vias (TSVs) instead of the bonding wire type connection structure 2400.

[0218] According to an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. According to an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wirings formed on the interposer substrate.

[0219] FIG. 16 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment.

[0220] FIG. 16 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 15 and conceptually shows a region where the semiconductor package 2003 of FIG. 15 is cut along the cutting line III-III'.

[0221] Referring to FIG. 16, in semiconductor package 2003A, package substrate 2100 may be a printed circuit board. Package substrate 2100 includes a main body portion 2120 of the package substrate, package upper pads 2130 (see FIG. 15) disposed on the upper surface of main body portion 2120 of the package substrate, lower pads 2125 disposed on the lower surface of main body portion 2120 of the package substrate or exposed through the lower surface, and internal wiring 2135 electrically connecting upper pads 2130 and lower pads 2125 inside main body portion 2120 of the package substrate. Upper pads 2130 can be electrically connected to connection structure 2400. Lower pads 2125 can be connected to wiring pattern 2005 of main board 2010 of data storage system 2000 through conductive connection portion 2800 as shown in FIG. 15.

[0222] In semiconductor package 2003A, each of semiconductor chips 2200a can include a semiconductor substrate 4010, a first semiconductor structure 4100 on semiconductor substrate 4010, and a second semiconductor structure 4200 bonded to first semiconductor structure 4100 in a wafer bonding manner on first semiconductor structure 4100.

[0223] The first semiconductor structure 4100 can include a peripheral circuit region including peripheral wiring 4110 and a lower bonding structure 4150. The second semiconductor structure 4200 can include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first semiconductor structure 4100, a channel structure 4220 and a separation structure 4230 penetrating the gate stack structure 4210, and an upper bonding structure 4250 electrically connected to the word lines of the channel structure 4220 and the gate stack structure 4210, respectively. For example, the upper bonding structure 4250 may be electrically connected to the channel structure 4220 and the word line via a bit line 4240 electrically connected to the channel structure 4220 and a contact plug 270 electrically connected to the word line, respectively. The lower bonding structure 4150 of the first semiconductor structure 4100 and the upper bonding structure 4250 of the second semiconductor structure 4200 can be bonded while contacting each other. The bonded portion of the lower bonding structure 4150 and the upper bonding structure 4250 may be formed of, for example, copper (Cu).

[0224] As shown in the enlarged view, the second semiconductor structure 4200 includes a cell guide structure CD that defines a first region R1. A protective layer 251, which is a nitride film, is disposed outside the first region R1 and can protect the lower wiring structure during the MLA process of the common source line CSL in the first region R1.

[0225] Each of the semiconductor chips 2200 can further include an input / output pad 2210 and an input / output connection wiring 4235 below the input / output pad 2210. The input / output connection wiring 4235 may be electrically connected to a part of the second bonding structure 4250. The input / output pad 2210 may be a region including a pad region 258.

[0226] The semiconductor chips 2200 in FIG. 16 may be electrically connected to each other by a connecting structure 2400 in the form of bonding wires. However, in an exemplary embodiment, semiconductor chips within one semiconductor package, such as the semiconductor chips 2200 in FIG. 15, may be electrically connected to each other by a connecting structure including through-silicon vias (TSVs).

[0227] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the appended claims. Therefore, within the scope not departing from the technical idea of the present invention described in the claims, various forms of substitution, modification, and change, as well as combinations of embodiments, are possible by those having ordinary knowledge in the art, and it can be said that these also belong to the scope of the present invention.

Explanation of Reference Numerals

[0228] CH: Channel structure DCH: Dummy channel structure GS1, GS2: Stacked structure MS: Separation region MS1, MS2: Mold structure CD: Cell guide structure 101: First substrate 201: First conductive layer 202: Second conductive layer CSL: Common source line 218: Sacrificial insulating layer 220: Interlayer insulating layer 230: Gate electrode 270: Contact plug

Claims

1. A first semiconductor structure including a first substrate, circuit elements on the first substrate, a lower wiring structure electrically connected to the circuit elements, and a lower bonding structure connected to the lower wiring structure, and a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes a stacked structure including an interlayer insulating layer and a gate electrode stacked vertically in a first region and a second region, an upper wiring structure disposed under the stacked structure, an upper bonding structure connected to the upper wiring structure and bonded to the lower bonding structure, a cell guide structure that divides the first region and the second region above the stacked structure, a channel structure including a first portion penetrating the stacked structure and a second portion extending upward from the first portion in the vertical direction in the first region, a contact plug penetrating the stacked structure and connected to a contact region of the gate electrode in the vertical direction in the second region, a first conductive layer in contact with an inner surface of the cell guide structure in the first region, disposed above the stacked structure, and connected to the second portion of the channel structure, a semiconductor device including a protective layer in contact with an outer surface of the cell guide structure in the second region and disposed above the stacked structure.

2. The semiconductor device according to claim 1, wherein the protective layer contains a nitride and the first conductive layer contains a crystalline semiconductor.

3. In the first region, the first conductive layer has a thickness greater than a length of the second portion of the channel structure, and an area of an upper surface of the first conductive layer is smaller than an area of a lower surface, according to the semiconductor device of claim 1.

4. The first conductive layer further includes a source region covering the stacked structure in the first region and an extended region bent from the source region and extending along a side surface of the cell guide structure, and a thickness of the source region of the first conductive layer is greater than a thickness of the extended region, according to the semiconductor device of claim 1.

5. The semiconductor device further includes an extended insulating region extending from an upper portion of the cell guide structure onto the protective layer, wherein a thickness of the extended insulating region is smaller than a thickness of the cell guide structure, according to the semiconductor device of claim 1.

6. A lower surface of the protective layer and a lower surface of the cell guide structure are coplanar. The semiconductor device according to claim 1, wherein a lower surface of the first conductive layer is located at a level lower than a lower surface of the protective layer.

7. The semiconductor device according to claim 1, wherein the second semiconductor structure further includes a second conductive layer disposed on the first conductive layer along the first conductive layer in the first region.

8. The semiconductor device according to claim 1, further including a reflective structure having a layered structure of a first material layer disposed on the protective layer and a second material layer including a material different from the first material layer on the first material layer, wherein the reflective structure does not overlap with the channel structure in the vertical direction.

9. The semiconductor device according to claim 8, wherein the first material layer includes an oxide and the second material layer includes a nitride.

10. The semiconductor device according to claim 8, wherein the reflective structure is formed by alternately laminating a plurality of the first material layers and a plurality of the second material layers.

11. The semiconductor device according to claim 8, wherein the reflective structure overlaps with the cell guide structure in the vertical direction.

12. The semiconductor device according to claim 1, wherein the protective layer includes H-rich SiN and provides a hydrogen path to the channel structure.

13. A stacked structure including an interlayer insulating layer and a gate electrode stacked in a vertical direction, A cell guide structure disposed on the stacked structure and defining a first region, A first conductive layer disposed on the stacked structure within the first region and in contact with the cell guide structure, A protective layer disposed on the stacked structure in a second region other than the first region defined by the cell guide structure, A channel structure including, in the first region, a first portion penetrating the stacked structure in the vertical direction and a second portion extending upward from the first portion and directly contacting the first conductive layer, A semiconductor device, wherein a side surface and a lower surface of the first conductive layer form an acute angle at an interface between the first conductive layer and the cell guide structure.

14. The semiconductor device according to claim 13, wherein the cell guide structure is disposed on the stacked structure to have a frame shape, and the frame-shaped region and the inside of the frame shape are defined as the first region.

15. The semiconductor device according to claim 14, wherein in the first region, the first conductive layer has a thickness greater than the length of the second portion of the channel structure, and the area of the upper surface of the first conductive layer is smaller than the area of the lower surface.

16. The lower surface of the protective layer and the lower surface of the cell guide structure are coplanar. The semiconductor device according to claim 13, wherein the lower surface of the first conductive layer is located at a level lower than the lower surface of the protective layer.

17. The semiconductor device according to claim 13, further comprising a dummy channel structure that penetrates the stacked structure in the vertical direction below the cell guide structure.

18. The semiconductor device according to claim 17, wherein in the dummy channel structure, the channel layer of the portion protruding above the stacked structure is covered by a channel dielectric layer.

19. A first semiconductor structure including a substrate and circuit elements on the substrate, a stacked structure including an interlayer insulating layer and a gate electrode stacked vertically in a first region and a second region, and a channel structure including a first portion that penetrates the stacked structure in the vertical direction in the first region and a second portion that extends upward from the first portion. A second semiconductor structure, an input / output pad electrically connected to the circuit element, and a semiconductor storage device including: A controller electrically connected to the semiconductor storage device via the input / output pad and controlling the semiconductor storage device. The first semiconductor structure includes: A lower wiring structure electrically connected to the circuit element, And a lower bonding structure connected to the lower wiring structure. The second semiconductor structure includes: An upper wiring structure disposed under the stacked structure, An upper bonding structure connected to the upper wiring structure and joined to the lower bonding structure, A cell guide structure that separates the first region and the second region above the stacked structure, A contact plug that penetrates the stacked structure in the vertical direction in the second region and is connected to a contact region of the gate electrode, A first conductive layer that contacts the inner surface of the cell guide structure in the first region, is disposed above the stacked structure, and is connected to the second portion of the channel structure, And a protective layer that contacts the outer surface of the cell guide structure in the second region and is disposed above the stacked structure. A data storage system.

20. The data storage system according to claim 19, wherein in the first region, the first conductive layer has a thickness greater than the length of the second portion of the channel structure, and the area of the upper surface of the first conductive layer is smaller than the area of the lower surface.

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