Multilayer electronic device including capacitor having precisely controlled capacitive area

The multilayer electronic device design with controlled capacitive areas using offset edges and dielectric materials addresses the challenge of precise capacitance control, achieving high-frequency filter performance with low loss and temperature stability.

JP2025114788APending Publication Date: 2025-08-05KYOCERA AVX COMPONENTS CORP
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
JP2025080207
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2018-12-20
Filing Date
2025-05-13
Publication Date
2025-08-05

AI Technical Summary

Technical Problem

Precise control over the capacitive area of capacitors in multilayer electronic devices, particularly in high-frequency filters, is challenging due to the need for very small and controlled capacitance values, which is essential for high-frequency applications like 5G spectrum frequencies.

Method used

A multilayer electronic device design that includes a first conductive layer with parallel edges and an offset edge within the overlapping area, allowing precise control over the capacitive area by adjusting the overlap size through protrusions or recesses, with an offset distance less than 500 micrometers, and using dielectric materials with controlled dielectric constants.

Benefits of technology

Achieves precise control over capacitance, enabling high-frequency filters with low insertion loss, excellent frequency rejection, and consistent performance across temperature variations, suitable for frequencies up to 80 GHz and beyond.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 2025114788000001_ABST
    Figure 2025114788000001_ABST
Patent Text Reader

Abstract

To provide a multilayer electronic device including a capacitor having a precisely controlled capacitive area.SOLUTION: A multilayer electronic device includes a first conductive layer 502 overlying one of multiple dielectric layers, and a second conductive layer 504 overlying another of the multiple dielectric layers and spaced apart from the first conductive layer in the Z-direction. The second conductive layer overlaps the first conductive layer in the X-Y plane at an overlapping area to form a capacitor. The first conductive layer has a pair of parallel edges 506, 508 at a boundary 501 of the overlapping area, and an offset edge 512, 516 within the overlapping area that is parallel with the pair of parallel edges. An offset distance 514 between the offset edge and at least one of the pair of parallel edges is less than about 500 micrometers (500 microns).SELECTED DRAWING: Figure 5A
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • Thick film condenser

    JP1983028821A

  • Manufacturing of capacitor and substrate mounted with capacitor

    JP1998149946A