Imaging device

Abstract

To provide an imaging device with which high-quality image data can be obtained.SOLUTION: The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit is an imaging device with a seventh transistor, and can correct the variation in electric characteristics of an amplifier transistor included in the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] CMOS (Complementary Metal Oxide Semiconductor) is a semiconductor device in which pixels having photosensors are arranged in a matrix. omplementary Metal Oxide Semiconductor) CMOS image sensors are used as image sensors in digital cameras. It is widely used in portable devices such as cameras and mobile phones.

[0005] Generally, semiconductor materials applicable to transistors that make up CMOS image sensors, etc. Silicon is widely known as a material for semiconductors, but oxide semiconductors are also attracting attention. do.

[0006] For example, Patent Document 1 discloses a transistor including an oxide semiconductor and having an extremely low off-state current. The transistor has a silicon semiconductor that can be used as part of the pixel circuit and can be used to fabricate a CMOS circuit. It is disclosed that a high-speed and low-power image pickup device can be manufactured by using the capacitor in the peripheral circuit. It is being done. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 Summary of the Invention [Problem to be solved by the invention]

[0008] A CMOS image sensor has an amplifier transistor that outputs data for each pixel. To obtain high-quality image data, the electrical characteristics of the transistors in all pixels must be uniform. However, as miniaturization progresses, the manufacturing process of transistors becomes more difficult, and the electrical characteristics It becomes difficult to suppress the variation.

[0009] In addition, data that corrects variations in electrical characteristics is stored in a capacitance element, etc., Although it is possible to correct the data, writing data to the capacitance element for each image capture reduces the overall The imaging time becomes longer, and the increase in power consumption also becomes a problem.

[0010] Therefore, one aspect of the present invention provides an imaging device capable of obtaining high-quality imaging data. Alternatively, the electrical characteristics of the amplifier transistor in the pixel circuit can be improved. It is an object of the present invention to provide an imaging device capable of correcting the variations in the Another object of the present invention is to provide an imaging device that consumes low power. One of the objects is to provide an imaging device. Or, to provide a highly sensitive imaging device. Another object of the present invention is to provide an imaging device with a wide dynamic range. Another object is to provide an imaging device with high resolution. One of the objects of the present invention is to provide a low-cost imaging device. One of the purposes of the present invention is to provide a novel imaging device. Another object is to provide a novel semiconductor device or the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a pixel circuit including an amplifier transistor. The present invention relates to an imaging device that can

[0013] One embodiment of the present invention is an imaging device including a first circuit and a second circuit, The circuit includes a photoelectric conversion element, a first transistor, a second transistor, and a third transistor. a first transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first a first capacitance element, a second capacitance element, and a third capacitance element; One terminal of the photoelectric conversion element is connected to the source or drain of the first transistor. The other of the source or drain of the first transistor is electrically connected to The first transistor is electrically connected to either the source or the drain of the second transistor. The other of the source and drain of the capacitor is electrically connected to one terminal of the first capacitance element. One of the source and drain of the third transistor is connected to the other terminal of the first capacitor element. The other terminal of the first capacitance element is electrically connected to one terminal of the second capacitance element. The source or drain of the fourth transistor is connected to the second capacitor element. the other terminal of the fourth transistor is electrically connected to the other terminal of the source or drain of the fourth transistor. a third capacitance element electrically connected to one of the source and the drain of the fifth transistor; One terminal of the capacitor is electrically connected to the other terminal of the second capacitor, and the other terminal of the third capacitor is electrically connected to the other terminal of the third capacitor. The other terminal is electrically connected to the other of the source and drain of the fifth transistor. The gate of the fifth transistor is electrically connected to one terminal of the third capacitance element, and the sixth transistor One of the source or drain of the fifth transistor is connected to the source or drain of the fifth transistor. The other of the source and drain of the sixth transistor is electrically connected to the other of the source and drain of the sixth transistor. 7, and is electrically connected to one of the source and drain of the transistor It is an imaging device.

[0014] The imaging device has a third circuit, and the third circuit includes an eighth transistor, a resistive element, and and one of the source and drain of the eighth transistor is connected to the source of the sixth transistor. the other of the source or drain of the eighth transistor. The other terminal of the input may be electrically connected to one terminal of the resistor element.

[0015] The second circuit also has a ninth transistor, and the source or drain of the ninth transistor One of the drains is electrically connected to the other of the source or drain of the seventh transistor. The gate of the ninth transistor is electrically connected to the gate of the seventh transistor, The gate of the ninth transistor is electrically connected to the other of the source or drain of the ninth transistor. The power supply may be electrically connected.

[0016] The other of the source and drain of the third transistor is electrically connected to the other terminal of the photoelectric conversion element. The power supply may be electrically connected.

[0017] The first circuit also has a fourth capacitance element, and one terminal of the fourth capacitance element is connected to the third transistor. The fourth transistor may be electrically connected to either the source or the drain of the fourth transistor. The other terminal of the capacitor is electrically connected to the other of the source and drain of the fourth transistor. They may be connected.

[0018] The first to ninth transistors each include an oxide semiconductor in an active layer. n, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or H f) and [Effects of the Invention]

[0019] According to one aspect of the present invention, there is provided an imaging device capable of obtaining high-quality imaging data. Alternatively, the variation in the electrical characteristics of the amplification transistor in the pixel circuit can be corrected. Alternatively, it is possible to provide an imaging device that consumes low power. Alternatively, an imaging device suitable for high-speed operation can be provided. It is possible to provide a high-sensitivity imaging device or an imaging device with a wide dynamic range. Alternatively, an imaging device with high resolution can be provided. This makes it possible to provide a low-cost imaging device, or to provide a highly reliable imaging device. Alternatively, a new imaging device or the like can be provided. Therefore, it is possible to provide a semiconductor device and the like.

[0020] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 2 illustrates a circuit included in the imaging device. [Figure 2] FIG. 2 illustrates a circuit included in the imaging device. [Figure 3] 10 is a timing chart illustrating a correction operation. [Figure 4] FIG. [Figure 5] FIG. [Figure 6] FIG. [Figure 7] FIG. [Figure 8] FIG. [Figure 9] FIG. 2 illustrates a circuit included in the imaging device. [Figure 10] FIG. 1 is a cross-sectional view of an imaging device including a circuit portion. [Figure 11] FIG. 1 is a diagram illustrating a curved imaging device. [Figure 12] FIG. 1 is a diagram illustrating a configuration of an imaging apparatus. [Figure 13] 4 is a timing chart illustrating the operation of a global shutter system and the operation of a rolling shutter system. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 20] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 21] 1A and 1B are cross-sectional views of a transistor in a channel length direction; [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 23] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 25] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 28] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 30] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 31] 1A and 1B are cross-sectional views of a transistor in a channel length direction; [Figure 32] FIG. 1 is a top view illustrating a transistor. [Figure 33] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 34] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 35] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 36] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 37] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 38] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 39] 1A to 1C illustrate electronic devices. [Figure 40] 4 is a timing chart illustrating the operation of the imaging device. [Figure 41] 4 is a timing chart illustrating the operation of the imaging device. [Figure 42] FIG. 2 illustrates a circuit included in the imaging device. DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0023] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0024] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0025] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0026] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0027] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0028] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0029] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0030] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0031] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0032] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0033] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0034] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0035] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0036] The imaging device according to one aspect of the present invention is an imaging device that outputs signal charges (data) using a source follower. Compensating for variations in the electrical characteristics of the source follower amplifier transistor in the device's pixels The pixel circuit has a pixel circuit that can control the threshold voltage and transition voltage of a transistor. Not only the mobility variations, but also the size (L, W) of the transistor channel formation region and gate It is also possible to correct variations in current values caused by variations in the film thickness (capacitance value) of the gate insulating film. can.

[0037] FIG. 1 shows a circuit that can function as a pixel circuit included in an imaging device of one embodiment of the present invention. a circuit 11, a circuit 12 that can function as a reference current source circuit, and a 1 and the like, the transistor Although an example in which the capacitor is an n-ch type is shown, one embodiment of the present invention is not limited to this. By reversing the magnitude relationship, the transistor can be made into a p-ch type as shown in Figure 42. Alternatively, some of the transistors may be replaced with p-ch transistors. .

[0038] The circuit 11 is roughly divided into a photoelectric conversion section and a signal generation section. 0, a transistor 51, and a transistor 52. a capacitor 53, a transistor 54, a transistor 55, a transistor 56, a capacitance element C1, a capacitance The capacitors C2, C3 and C4 are included. Note that the capacitor C4 can be omitted. It is also possible.

[0039] The circuit 12 includes a transistor 57 and a transistor 59 .

[0040] The circuit 13 includes a transistor 58, a resistor R, and an output terminal (OUT).

[0041] The circuit 12 and the circuit 13 connected to the wiring 30 are in the form shown in FIGS. FIG. 2A shows a configuration in which the transistor 59 is omitted from the circuit 12. FIG. 2B shows a configuration in which the circuit 13 is omitted and an output terminal (OUT) is provided on the wiring 30. 2C, the transistor 59 of the circuit 12 and the circuit 13 are omitted, and the wiring 30 is connected to the output terminal. This configuration has a child (OUT).

[0042] In the circuit 11 of FIG. 1, one terminal of the photodiode 60 is connected to the The source or drain of the transistor 51 is electrically connected to the The other of the drain and the source is electrically connected to one of the source and drain of the transistor 52. The other of the source and drain of the transistor 51 is connected to one of the capacitors C1. The source or drain of the transistor 53 is electrically connected to the The other terminal of the capacitance element C1 is electrically connected to the other terminal of the capacitance element C1. The capacitor C2 is electrically connected to the source or the drain of the transistor 54. One of the drains is electrically connected to the other terminal of the capacitance element C2. The other of the source or drain of transistor 54 is connected to the source or drain of transistor 55. One terminal of the capacitance element C3 is electrically connected to the other terminal of the capacitance element C2. The other terminal of the capacitance element C3 is electrically connected to the The gate of the transistor 55 is electrically connected to the other of the source and drain. One terminal of the capacitance element C4 is electrically connected to one terminal of the capacitance element C3. The capacitor C4 is electrically connected to one terminal of the capacitor C2. It is electrically connected to one of the source and drain of the transistor 55. The other of the source or drain of transistor 55 is connected to the source or drain of transistor 56. One is electrically connected to the other.

[0043] The other terminal of the photodiode 60 is electrically connected to the wiring 21 (VPD). The other of the source and the drain of the transistor 52 is electrically connected to the wiring 22 (VPR). The source or drain of the transistor 55 is connected to the wiring 23 (VPI The gate of the transistor 51 is electrically connected to the wiring 25 (TX). The gate of the transistor 52 is electrically connected to the wiring 26 (PR). The gate of the transistor 53 is electrically connected to the wiring 27(W). The gate of the transistor 54 is electrically connected to the wiring 28 (AZ). The gate of the transistor 56 is electrically connected to the wiring 29 (SE). The other of the source or drain of 6 is electrically connected to wiring 30 .

[0044] In the circuit 12, one of the source and drain of the transistor 57 is electrically connected to the wiring 30. The other of the source and drain is electrically connected to the wiring 24 (VPO). In addition, one of the source and drain of the transistor 59 is electrically connected to the wiring 31 (BR). In addition, either the source or the drain of the transistor 59 is connected to the The gate of the transistor 59 and the gate of the transistor 57 are electrically connected to each other. The other of the source or drain of the stator 59 is electrically connected to the wiring 24 (VPO).

[0045] In the circuit 13, one of the source and drain of the transistor 58 is electrically connected to the wiring 30. The source or drain of the transistor 58 is connected to the output terminal The other of the source and drain of the transistor 58 is connected to a resistor (OUT). The gate of the transistor 58 is electrically connected to one terminal of the resistor R. 32 (OE). The other terminal of the resistor element R is electrically connected to the wiring 24 (VP O).

[0046] Here, the wiring 21 (VPD), the wiring 22 (VPR), the wiring 23 (VPI), and the wiring 24 (VPO) can function as a power supply line. 6 (PR), Wiring 27 (W), Wiring 28 (AZ), Wiring 29 (SE), Wiring 30, Wiring 3 1 (BR) and the wiring 32 (OE) can function as signal lines.

[0047] In FIG. 1, the other of the source and drain of the transistor 53 is connected to the wiring 21 (VPD). However, it may be connected to a wiring that can supply a fixed potential. It may be possible.

[0048] In addition, in FIG. 1, the other terminal of the capacitance element C4 is connected to the wiring 23 (VPI). However, they may be connected to wiring that can supply other fixed potentials.

[0049] In the above configuration, the other of the source and drain of the transistor 51, the transistor 52 The node to which one of the source or drain of and one terminal of the capacitance element C1 are connected is called F. Let's call it D1.

[0050] In addition, one of the source and drain of the transistor 53, the other terminal of the capacitance element C1, The node to which one terminal of the capacitance element C2 and one terminal of the capacitance element C4 are connected is designated as FD2. do.

[0051] In addition, one of the source and drain of the transistor 54, the other terminal of the capacitance element C2, Let AG be the node to which one terminal of the capacitance element C3 and the gate of the transistor 55 are connected. do.

[0052] The other of the source and drain of the transistor 55, the other terminal of the capacitance element C3, and A node to which either the source or the drain of the transistor 56 is connected is designated as AS.

[0053] The photodiode 60 has a pn-type or pin-type junction formed on a silicon substrate. A diode element can be used. Alternatively, an amorphous silicon film or a microcrystalline silicon film can be used. In the circuit 11, a pin type diode element using a photodiode may be used. Although the configuration having a photodiode is shown as an example, other photoelectric conversion elements may be used. A diode-connected transistor may also be used. Also, a variable resistor utilizing the photoelectric effect may be used. It may be formed using silicon, germanium, selenium, or the like.

[0054] Alternatively, a photoelectric conversion element using selenium, which utilizes the phenomenon of avalanche multiplication, may be used. The photoelectric conversion element is a highly sensitive sensor with a large amplification of electrons relative to the amount of incident light. It can be said that:

[0055] The selenium-based material can be amorphous selenium or crystalline selenium. For example, crystalline selenium can be obtained by forming a film of amorphous selenium and then heat treating it. By making the crystal grain size of the silicon smaller than the pixel pitch, the characteristic variation between pixels is reduced. It is possible.

[0056] In the circuit 11, the photodiode 60 is a light receiving element that responds to light incident on the circuit 11. The transistor 51 can have a function of generating a current corresponding to the photodiode. 60 to control charge accumulation at node FD1. The transistor 52 can have a function of resetting the potential of the node FD1. The transistor 53 has a function of resetting the potential of the node FD2. The transistor 54 can have the function of causing a current to flow through the transistor 55. The transistor 55 has a function of outputting a signal according to the potential of the node AG. The transistor 56 controls the selection of the circuit 11 (pixel circuit) during readout. It can have the function of performing the following operations.

[0057] In the circuit 12, the transistors 57 and 59 form a current mirror circuit. The current flowing through the transistor 57 is equal to the current flowing through the transistor 59. Possess the ability.

[0058] In the circuit 13, a voltage signal corresponding to the current flowing through the transistor 58 and the resistor element R is generated. It can have a function to output from the output terminal (OUT).

[0059] In the imaging device according to one embodiment of the present invention having the above structure, the transistor included in the circuit 11 The saturation region of the capacitor 55 (Vds>Vgs-Vth, Vds: drain-source voltage, Vgs Vgs determines the reference output at By storing the signal in the circuit 11, correction of the output signal can be performed.

[0060] The correction operation and the output operation after correction will be explained using the timing chart shown in Figure 3. A detailed explanation will be given. The timing chart shown in FIG. 3 is a timing chart of the wiring 25 (TX) and the wiring 26 (P R), Wiring 27 (W), Wiring 28 (AZ), Wiring 29 (SE), Wiring 31 (BR), Wiring 32(OE), node FD1, node FD2, node AG, node AS and output terminal ( OUT) is shown. Note that each transistor is connected to a wiring The on or off operation is performed according to the potential.

[0061] In addition, in the circuit diagrams used in this explanation, transistors 55 and below are shown as being in a conducting state in order to clarify the state. The other transistors are shown as switch symbols. Some symbols are omitted. The transistors 59 and 57 are switched in conjunction with each other. In this case, the wiring 21 (VPD) is at low potential (GND), and the wiring 22 (VPR) is at high potential (V PR”), wire 23 (VPI) is at high potential (“VPI”), and wire 24 (VPO) is at low potential ( "GND").

[0062] At time T1, transistors 52, 53, 54, 56, 57, and 59 are turned on. When a reference signal current is supplied to the wiring 31 (BR), the transistors 51 and 58 are turned off. The reference current (Iref) flows through the transistor 59, and the wiring 23 (VPI) and the wiring 24 (VPO A bias current (Ibias) flows between the input and output terminals through a transistor 57 (see FIG. 4). (The current path is shown by a broken line.) Note that even if a reference signal voltage is supplied to the wiring 31 (BR), good.

[0063] At this time, the node FD1 is set to the potential ("VPR") of the wiring 22 (VPR). In addition, the node FD2 is set to the potential ("GND", for example, 0V) of the wiring 21 (VPD). Also, the node AG is set to the potential ("VPI") of the wiring 23 (VPI). Here, if the potential difference between the gate and source of the transistor 55 is "Vgs", then the gate Since the potential (potential of node AG) is "VPI", the potential of node AS is "VPI -Vgs”. Then, the potential of node AG is set to “VPI”, and the potential of node AS is set to Since it is "VPI-Vgs", "Vgs" is applied to both ends of the capacitance element C3. Vgs=Vth (threshold voltage of the transistor 55)+Vov (overvoltage) The above gives the voltage Vgs for passing the bias current (Ibias). " is set.

[0064] Next, at time T2, when the transistor 54 is turned off, the node AG becomes floating. This causes the capacitance element C3 to hold "Vgs" (see FIG. 5).

[0065] Next, at time T3, when all the transistors are turned off, the bias current (Ibia s) is cut off, and the potential of the node AS rises from "VPI-Vgs" to "VPI". In addition, the potential of node AG rises from "VPI" to "VPI+Vgs". If "GND" is 0V, the potential of node FD2 rises from "GND" to "Vgs" (see Figure 6). This completes the maintenance of "Vgs" to allow the bias current (Ibias) to flow. That is, the "Vgs" that determines the reference output of the transistor 55 is stored in the circuit 11. Complete it.

[0066] Next, the output operation after the correction will be described. At time T4, the transistors 56 and 58 is turned on, and transistors 51, 52, 53, 54, 57, and 59 are turned off. The capacitor C3 holds "Vgs" to pass the bias current (Ibias). Therefore, the circuit 13 (transistor 58) is connected between the wiring 23 (VPI) and the wiring 24 (VPO). The bias current (Ibias) flows through the resistor R. The reference output voltage "R·Ibias" is output from the output terminal (OUT) of 3 (Figure 7). At this time, the potential of the other terminal of the capacitance element C3 becomes "R·Ibias". Therefore, the potential of node AG is "R·Ibias+Vgs".

[0067] Next, assuming an actual imaging operation, the operation when the potential of node FD2 changes by -Vα First, in order for the potential of the node FD2 to change by -Vα, The transistor 52 is turned off, and the potential "VPR" of the wiring 22 (VPR) is maintained at the node FD1. In this state, the transistor 51 is turned on, and a charge equivalent to -Vα is applied to the The light is emitted to the wiring 21 (VPD) through the photodiode 60. 51 is turned off to maintain the potential of the node FD1. can be changed from "VPR" to "VPR-Vα".

[0068] When the node FD1 changes from "VPR" to "VPR-Vα", the node FD2 changes to "Vgs ” to “Vgs-Vα”. Also, node AG changes from “R·Ibias+Vgs”. Therefore, the voltage between the wiring 23 (VPI) and the wiring 24 (VPI) changes to "R·Ibias+Vgs-Vα". Between line 24 (VPO) and node AG, the potential is determined by "R·Ibias+Vgs-Vα". At this time, the output terminal (OUT) of the circuit 13 is "R·Ibias-Vα", that is, "R·Ibias´" (Ibias´ <Ib ias) is output (see Figure 8).

[0069] As a result, an output signal that is lower than the reference output voltage by the voltage equivalent to -Vα can be obtained. That is, in the circuit configuration of FIG. The higher the intensity, the smaller the output signal output from the output terminal (OUT).

[0070] The above correction operation does not need to be performed for each image capture, and continuous image capture can be performed with only one correction operation. Of course, you can also set it before shooting, after shooting, when powering on, powering off, or on a timer. The correction operation may be performed at any timing using the above-mentioned signal.

[0071] The imaging device of one embodiment of the present invention may have the structure shown in FIGS. 9(A) shows that the connection direction of the photodiode 60 of the photoelectric conversion unit in the circuit 11 is different from that in FIG. In this case, the wiring 21 (VPD) is at a high potential, and the wiring 22 (VPR) is at a low potential. The compensation operation and output operation can be seen in the explanation of the circuit in Figure 1 above. However, in this case, the higher the intensity of the light irradiated on the photodiode 60, the higher the Therefore, in the circuit configuration of FIG. 9(A), the photodiode 60 The higher the intensity of the light irradiated onto the device, the larger the output signal from the output terminal (OUT) will be. do.

[0072] 9B shows a configuration in which the transistor 52 is omitted from the circuit 11 shown in FIG. In this case, the wiring 21 (VPD) is configured to be able to change between a low potential and a high potential. The power-on operation can be performed by setting the wiring 21 (VPD) to a high potential. In this case, when the wiring 21 (VPD) is set to a high potential, a forward bias is applied to the photodiode 60. Therefore, the node FD1 can be set to the potential of the wiring 21 (VPD). Cut.

[0073] When a light detecting operation (storage operation) is performed, the wiring 21 (VPD) is set to a low potential. By setting the wiring 21 (VPD) at a low potential, a reverse bias is applied to the photodiode 60. Therefore, charges are discharged from the node FD1 to the wiring 21 (VPD) according to the intensity of light. In this case, the higher the intensity of the light irradiated onto the photodiode 60, the higher the voltage at the node F Therefore, in the circuit configuration of FIG. 9(B), the potential of the photodiode The higher the intensity of the light irradiated onto the diode 60, the smaller the output signal output from the output terminal (OUT). It gets smaller.

[0074] In the imaging device of one embodiment of the present invention, a transistor including an oxide semiconductor is preferably used. When a transistor including an oxide semiconductor is used in the circuit 11, the dynamic range of imaging can be improved. In the circuit configuration shown in FIG. When the intensity of the light entering the transistor is high, the potential of the node AG decreases. Since the off-state current of the transistor 55 is extremely low, the potential of the node AG (the gate potential of the transistor 55) ) is extremely small, the current corresponding to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, i.e., the dynamic range, can be It can be expanded.

[0075] Furthermore, the low off-state current of the transistor including an oxide semiconductor To extremely extend the period during which charges can be held at node FD2, node AG, and node AS. Therefore, it is possible to transfer charges almost simultaneously to all pixels without complicating the circuit configuration or operation method. A global shutter system that performs accumulation operation can be applied. Even for moving objects, images with little distortion can be easily obtained. Since the period during which the sensor operates can be extended, it is also suitable for imaging in low-light environments. .

[0076] Also, connect to any of node FD1, node FD2, node AG, and node AS. The transistors are required to have low noise. The transistor with the semiconductor layer has a buried channel, which makes it highly resistant to noise. Therefore, by using this transistor, it is possible to obtain an image with less noise. Cut.

[0077] According to the above embodiment of the present invention, the amplification transistor (transistor 55 ) parameters (threshold voltage, mobility, size of the channel formation region (L, W), gate It is possible to obtain an output signal that is not dependent on variations in the film thickness (capacitance value, etc.) of the insulating film.

[0078] 10A is an example of a cross-sectional view of an imaging device including a circuit section. The circuit section 90 is made of silicon. A transistor 70 having an active region on a substrate 40 and a transistor having an oxide semiconductor as an active layer are It is a combination with the MOS transistor 71, and can be used to form, for example, an inverter circuit or a memory circuit. The circuit section 92 can be formed on the silicon substrate 40. and a transistor 51 having an oxide semiconductor as an active layer. This corresponds to a part of the photoelectric conversion section in the circuit 11. The lug indicates that its position in the depth direction is different from that of other wiring and contact plugs. .

[0079] In FIG. 10A, the photodiode 60 and the transistor 51 are formed so as to overlap each other. This allows for a higher pixel integration density. In addition, in the area occupied by the circuit section 92, the silicon substrate 40 Since no transistor is formed, the area of the photodiode can be made larger. Therefore, images with little noise can be obtained even in low-light environments.

[0080] In FIG. 10, the photodiode 60 and the transistor 70 are provided on the same silicon substrate 40. For example, the transistor 70 may be formed on a silicon substrate 4. 0 and a photodiode fabricated on a separate substrate may be attached to it. The transistor 70 is not provided on the silicon substrate 40, and an oxide semiconductor is used in the same manner as the transistors 71 and 51. Alternatively, as shown in FIG. 10(B), a transistor may be used as an active layer. The transistors 70 and 51 may be provided on the silicon substrate 40. For example, a capacitor element, a diode, or the like may be provided on the silicon substrate 40. A resistor, a resistor element, etc. may be provided.

[0081] In the configuration shown in FIG. 10A, a transistor 70 and a photodiode 60 are included. An insulating layer 80 is provided between the area where the transistor 71 and the area where the transistor 51 are provided. will be established.

[0082] The hydrogen in the insulating layer near the active region of the transistor 70 acts as a dangling silicon. Therefore, the hydrogen has the effect of improving the reliability of the transistor 70. On the other hand, the active layers of the transistors 71 and 51 are oxide semiconductors. Hydrogen in the insulating layer provided near the oxide semiconductor layer is one of the factors that generate carriers in the oxide semiconductor. Therefore, the hydrogen reduces the reliability of the transistor 71 and the transistor 51. Therefore, transistors using silicon-based semiconductor materials One layer having a transistor using an oxide semiconductor is stacked on the other layer having a transistor using an oxide semiconductor. In this case, it is preferable to provide an insulating layer 80 between them, which has the function of preventing hydrogen diffusion. The insulating layer 80 confines hydrogen to one layer, improving the reliability of the transistor 51. In addition, the diffusion of hydrogen from one layer to the other layer is suppressed. Therefore, the reliability of the transistor 71 and the transistor 51 can be improved at the same time. .

[0083] The insulating layer 80 may be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxynitride Hafnium oxide, yttria-stabilized zirconia (YSZ), etc. can be used.

[0084] Furthermore, the silicon substrate 40 is not limited to a bulk silicon substrate, but may be an SOI substrate. In addition, instead of the silicon substrate 40, germanium, silicon germanium, silicon carbide, , gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors A substrate made of a solid material or a substrate on which a thin film of such a material is formed can also be used.

[0085] The transistor 70 may be any type of transistor, not just a planar type. For example, FIN type, TRI-GATE type ) type transistors, etc.

[0086] The transistor 51 may include not only an oxide semiconductor but also various other semiconductors depending on the situation. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors It may also have a conductor or the like.

[0087] The imaging device may also be curved as shown in FIG. 11(A1) and FIG. 11(B1). FIG. 11(A1) shows a state in which the imaging device is bent in the direction of the two-dot chain line X1-X2 in the same figure. FIG. 11(A2) is a cross-section of the portion indicated by the two-dot chain line X1-X2 in FIG. 11(A1). FIG. 11(A3) is a cross-sectional view of the portion indicated by the two-dot chain line Y1-Y2 in FIG. 11(A1). Cross-sectional view.

[0088] FIG. 11(B1) shows the case where the imaging device is bent in the direction of the two-dot chain line X3-X4 in the same figure, and FIG. 11(B2) shows the state where the lens is bent in the direction of the two-dot chain line Y3-Y4 in the drawing. FIG. 11(B3) is a cross-sectional view of the portion indicated by the two-dot chain line X3-X4 in FIG. 11(B1) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG.

[0089] By curving the imaging device, it is possible to reduce field curvature and astigmatism. This makes it easier to design the optical system, such as lenses, that are used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, allowing for miniaturization of semiconductor devices that use imaging devices. It is possible to easily reduce the size and weight of the camera. In addition, it is possible to improve the quality of the captured image. Cut.

[0090] Note that one embodiment of the present invention has been described in this embodiment. However, the present invention is not limited to these. For example, although an example in which the present invention is applied to an imaging device has been shown as one embodiment of the present invention, One aspect of the present invention is not limited to this. The embodiment of the present invention does not necessarily have to be applied to an imaging device. For example, the embodiment of the present invention may be applied to a device having another function. Alternatively, one embodiment of the present invention may be applied to a semiconductor device having a transistor. Although examples have been given of devices that have the function of correcting variations and deterioration, or that perform correction operations, However, one aspect of the present invention is not limited to this. In one embodiment of the present invention, it is not necessary to correct variations or deterioration in the electrical characteristics of transistors.

[0091] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0092] (Embodiment 2) In this embodiment, an example of a method for driving a pixel circuit will be described.

[0093] The pixel circuit described in the first embodiment performs a first operation for performing normal imaging and a second operation for performing imaging of an initial frame. The difference data between the image data and the image data of the current frame is stored, and a signal corresponding to the difference data is generated. In the second operation, an external circuit can output a signal. Since differential data can be output without performing comparison processing, it is possible to achieve low power consumption. It can be applied to security cameras, etc.

[0094] The imaging device according to one embodiment of the present invention includes a circuit 11 arranged in a matrix as shown in FIG. a pixel section 400 having a row driver 410 connected to the circuit 11; a circuit 12 and a circuit 13 connected to the A / D converter circuit 420; The pixel array includes a column driver 430 connected to the switching circuit 420 .

[0095] The imaging data acquired by the circuit 11 selected by the row driver 410 is transmitted via the circuit 12. The A / D conversion circuit 420 converts the input image data The A / D converted digital data is The row driver 410 and the column driver 430 sequentially extract the signals to the outside. For example, various circuits such as a decoder and a shift register can be used.

[0096] Next, regarding the first operation of the circuit shown in FIG. 1, the timing chart shown in FIG. This will be used to explain.

[0097] Between time T1 and time T2, the wiring 25 (TX) is set to a potential higher than VPR+Vth, and the wiring 26 (PR) is set to a potential higher than VPR+Vth, and wiring 27 (W) is set to a potential higher than Vth. At this time, the potential of the node FD1 is the potential of the wiring 22 (VPR) (i.e., "VPR" ), and the potential of the node FD2 is set to the potential of the wiring 21 (VPD) (i.e., "GND"). (reset operation).

[0098] Between time T2 and time T3, the wiring 25 (TX) is set to a potential higher than VPR+Vth, and the wiring 26 (PR) is set to "GND" and the wiring 27 (W) is set to a potential lower than -VPR. In response to light irradiating the photodiode 60, the potentials of the nodes FD1 and FD2 drop. If the amount of potential drop at node FD1 at time T3 is V1, then the potential drop at node FD1 is The potential at node FD2 is VPR-V1. The potential at node FD2 is reduced by V2 due to capacitive coupling. In the circuit configuration shown in Figure 1, the photodiode 6 The stronger the light irradiating node FD0, the lower the potentials of node FD1 and node FD2.

[0099] Between time T3 and time T4, the wiring 25 (TX) is set to "GND" and the wiring 26 (PR) is set to " GND”, and the wiring 27(W) are set to a potential lower than −VPR, the node FD1 and the node The potential of FD2 is maintained.

[0100] Between time T4 and time T5, the wiring 30 (SE) is set to a potential higher than VPI+Vth. Then, a signal corresponding to the image data is output to the output terminal (OUT) according to the potential of node FD2. The first operation is then performed (selection operation).

[0101] Next, regarding the second operation of the circuit shown in FIG. 1, the timing chart shown in FIG. This will be used to explain.

[0102] Between time T1 and time T2, the wiring 25 (TX) is set to a potential higher than VPR+Vth, and the wiring 26 (PR) is set to a potential higher than VPR+Vth, and wiring 27 (W) is set to a potential higher than Vth. At this time, the potential of the node FD1 is the potential of the wiring 22 (VPR) (i.e., "VPR" ), and the potential of the node FD2 is set to the potential of the wiring 21 (VPD) (i.e., "GND"). can be.

[0103] Between time T2 and time T3, the wiring 25 (TX) is set to a potential higher than VPR+Vth, and the wiring 26 (PR) is set to "GND" and the wiring 27 (W) is set to a potential higher than Vth. The potential of the node FD1 decreases in response to the light irradiating the diode 60. If the amount of potential drop at node FD1 is V1, the potential at node FD1 becomes VPR-V1. In the circuit configuration of FIG. 1, the stronger the light irradiating the photodiode 60, the The potential of the node FD1 decreases.

[0104] Between time T3 and time T4, the wiring 25 (TX) is set to "GND" and the wiring 26 (PR) is set to " When the potential of the GND line and the wiring 27 (W) is set higher than Vth, the potential of the node FD1 is maintained. can be.

[0105] Between time T4 and time T5, the wiring 25 (TX) is set to "GND" and the wiring 26 (PR) is set to " GND” and the wiring 27(W) are set to a potential lower than −VPR, the potential of the node FD1 and The potential of the node FD2 is maintained.

[0106] Between time T5 and time T6, the wiring 25 (TX) is set to a potential higher than VPR+Vth, and the wiring 26 (PR) is set to a potential higher than VPR+Vth, and wiring 27 (W) is set to a potential lower than -VPR. Then, the potential of node FD1 rises by V1, and the potential of node FD2 rises by V 2, where V1 and V2 are potentials reflecting the illumination of the initial frame. .

[0107] Between time T6 and time T7, the wiring 25 (TX) is set to a potential higher than VPR+Vth, and the wiring If 26 (PR) is set to "GND" and wiring 27 (W) is set to a potential lower than -VPR, In response to light irradiating the diode 60, the potentials of the nodes FD1 and FD2 decrease. If the amount of potential drop at node FD1 at time T6 is V1', the potential at node FD1 is VPR-V1'. The potential at node FD2 decreases by V2' due to capacitive coupling, and G It becomes ND+V2-V2'.

[0108] Between time T7 and time T8, the wiring 25 (TX) is set to "GND" and the wiring 26 (PR) is set to " GND”, and the wiring 27(W) are set to a potential lower than −VPR, the node FD1 and the node The potential of FD2 is maintained.

[0109] Between time T8 and time T9, the wiring 30 (SE) is set to a potential higher than VPI+Vth. Then, a signal corresponding to the image data is output to the output terminal (OUT) according to the potential of node FD2. In the above configuration, the potential of node FD2 when a signal is output is GND+V2-V2'. Therefore, when GND is, for example, 0V, the potential is V2-V2'. 2 is the potential that reflects the illuminance of the initial frame, and V2' is the potential that reflects the illuminance of the subsequent frame (current frame). This is the potential that reflects the illuminance at the time of the initial frame. A second operation can be performed.

[0110] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0111] (Embodiment 3) In this embodiment, an example of a method for driving a pixel circuit will be described.

[0112] As described in the second embodiment, the operation of the pixel circuit is a reset operation, a storage operation, and a selection operation. The global imaging method is used to control the entire pixel matrix. The shutter system and the rolling shutter system are known.

[0113] FIG. 13(A) is a timing chart for the global shutter system. The timing chart has a plurality of pixel circuits arranged in a matrix, and the pixel circuits are For example, in an imaging device having a circuit, the pixels in the first to nth rows (n is a natural number of 3 or more) The operation of the circuit is explained. The operation is the same as the first operation explained in the second embodiment. This work will be explained as an example.

[0114] In FIG. 13A, signals 501, 502, and 503 are shown in the first row, second row, This is a signal input to the wiring 26 (PR) connected to each pixel circuit in the nth row. Signals 504, 506, and 508 are connected to the pixel circuits in the first, second, and nth rows. The signals 505, 507, and 508 are input to the wiring 25 (TX) connected to the signal line 504. No. 509 is a wiring 29 (SE) connected to each pixel circuit of the first row, the second row, and the nth row. This is the signal input to

[0115] Furthermore, period 510 is the period required for one image capture. 0 indicates that the pixel circuits in each row perform the reset operation and accumulation operation at the same time. The selection operation is performed sequentially in the pixel circuits of each row. This is the period when the pixel circuits in the first row are performing selection operations. In this method, reset and accumulation operations are performed almost simultaneously in all pixel circuits, and sequential reading is performed row by row. A read operation is performed.

[0116] In other words, in the global shutter system, accumulation operations are performed in all pixel circuits almost simultaneously. Therefore, the image pickup is performed simultaneously in the pixel circuits of each row. Even if the object is moving, it is possible to obtain images with little distortion.

[0117] On the other hand, FIG. 13(B) is a timing chart when the rolling shutter method is used. For signals 501 to 509, please refer to the explanation in FIG. 13(A). The period 10 is the period required for one image capture. The period 611 is the period during which the pixels in the first row perform the reset operation. A period 612 is a period during which the pixels in the second row perform a reset operation. A period 613 is a period in which the pixels in the nth row perform a reset operation. A period 621 is a period in which the pixels in the first row perform a reset operation. The period 622 is a period during which the pixels in the second row perform an accumulation operation. The period 623 is a period in which the pixels in the nth row perform the accumulation operation. This is the period during which the pixel circuits in the first row are performing a selection operation. In the pixel method, the accumulation operation is not performed simultaneously in all pixel circuits, but is performed sequentially for each row. Therefore, the first and last rows of the pixel circuits cannot be imaged simultaneously. Since the timing of capturing images is different, images with a moving subject will be distorted. Put away.

[0118] To realize the global shutter system, the signal readout from each pixel must be completed sequentially. The potential of the charge storage section (node FD2) must be maintained for a long time until the charge storage section (node Holding the potential of the gate FD2 for a long time causes the channel forming region of the transistor 55 to be oxide. This can be achieved by using a transistor formed from a semiconductor and having extremely low off-state current. Applying a transistor with a channel formation region made of silicon or other materials to transistor 55, etc. In this case, the potential of the charge storage section (node FD2) cannot be maintained for a long time due to the high off-current. Therefore, it becomes difficult to use the global shutter method.

[0119] As described above, a transistor in which a channel formation region is formed using an oxide semiconductor is used in a pixel circuit. This makes it easy to realize the global shutter method.

[0120] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0121] (Fourth embodiment) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be made with reference to the drawings. For clarity, some elements may be enlarged, reduced, or omitted.

[0122] 14A and 14B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. The cross section taken along the dashed line B1-B2 in FIG. 14(A) corresponds to FIG. 14(B). 20(A) corresponds to the cross section taken along the dashed line B3-B4 in FIG. , the dashed line B1-B2 direction is the channel length direction, and the dashed line B3-B4 direction is the channel width direction. It may be referred to as.

[0123] The transistor 101 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 11 in contact with the conductive layer 150. 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. Furthermore, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0124] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0125] 14(B) is a source region, a region 232 is a drain region, and a region 233 is a The region 33 can function as a channel forming region. The conductive layers 140 and 150 are in contact with each other, for example, the conductive layers 140 and 150. If a conductive material that easily bonds with oxygen is used as 150, the resistance of the region 231 and the region 232 can be reduced. It can be countered.

[0126] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0127] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" are used interchangeably in this specification. The term "electrode layer" can also be used interchangeably with "wiring." can.

[0128] In addition, the conductive layer 170 is shown as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0129] Although the conductive layer 140 and the conductive layer 150 are shown as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may also be applied to other transistors described in this embodiment. can.

[0130] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 15A is a top view of the transistor 102. The cross section in the direction of 1-C2 corresponds to FIG. 15(B). The cross section in the direction of -C4 corresponds to FIG. 20(B). The direction of the dashed dotted line C3-C4 may be referred to as the channel length direction, and the direction of the dashed dotted line C3-C4 may be referred to as the channel width direction.

[0131] The transistor 102 is formed by connecting the edge of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the edge of the conductive layer 170 acting as a The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layers 140, 150, and 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0132] The transistor 101 and the transistor 102 are formed by the conductive layer 170 and the conductive layer 140 and the conductive layer 140. The top gate structure has a region where the gate electrode 150 overlaps the gate electrode 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this structure, no offset region is formed in the oxide semiconductor layer 130, and therefore, the on-current is high. This makes it easier to form a small transistor.

[0133] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 16A is a top view of the transistor 103, and the dashed line D in FIG. The cross section in the 1-D2 direction corresponds to FIG. 16(B). The cross section in the -D4 direction corresponds to FIG. 20(A). The direction of the dashed dotted line D3-D4 may be referred to as the channel length direction, and the direction of the dashed dotted line D3-D4 may be referred to as the channel width direction.

[0134] The transistor 103 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. The edge layer 175, the insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and the insulating layer 180 a conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. If necessary, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0135] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0136] 16B, a region 231 is a source region, a region 232 is a drain region, and a region 2 The region 33 can function as a channel forming region. The region 231 and the region 232 are insulating layers. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0137] Specifically, the insulating layer 175 is formed in the regions 231 and 232 by the steps up to the formation of the insulating layer 175. The oxygen vacancies caused by the ion implantation and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232 interact with each other. As a result, the regions 231 and 232 become n-type with low resistance. For example, silicon nitride or aluminum nitride can be used.

[0138] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 17A is a top view of the transistor 104, and the dashed line E in FIG. The cross section in the 1-E2 direction corresponds to FIG. 17(B). The cross section in the -E4 direction corresponds to FIG. 20(A). The direction of the dashed dotted line E3-E4 may be referred to as the channel length direction, and the direction of the dashed dotted line E3-E4 may be referred to as the channel width direction.

[0139] The transistor 104 is configured such that the conductive layer 140 and the conductive layer 150 are disposed at the edge of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103 except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0140] 17B, the regions 331 and 334 are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. .

[0141] Regions 331 and 332 correspond to regions 231 and 232 in transistor 101. As with 2, the resistance can be reduced.

[0142] Regions 334 and 335 are the same as regions 231 and 232 in transistor 103. The resistance of the region 334 in the channel length direction can be reduced in the same manner as the region 232. and when the length of region 335 is 100 nm or less, preferably 50 nm or less, the gate The on-current does not decrease significantly due to the contribution of the electric field. In some cases, the resistance reduction step 5 is not performed.

[0143] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive layer 140. The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. Therefore, it is suitable for high-speed operation.

[0144] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 18A is a top view of the transistor 105, and the dashed line F in FIG. The cross section in the 1-F2 direction corresponds to FIG. 18(B). The cross section in the direction of -F4 corresponds to FIG. 20(A). The direction of the dashed dotted line F3-F4 may be referred to as the channel length direction, and the direction of the dashed dotted line F3-F4 may be referred to as the channel width direction.

[0145] The transistor 105 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; and a conductive layer the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151. the conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175; and an insulating layer 180 that is electrically conductive through openings in the insulating layers 175 and 180. Conductive layer 142 and conductive layer 151 are electrically connected to layer 141 and conductive layer 152, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0146] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are It is designed so that it does not come into contact with the

[0147] The transistor 105 has a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening formed in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0148] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 19A is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 19(B). The cross section in the -G4 direction corresponds to FIG. 20(A). The direction of the dashed dotted line G3-G4 may be referred to as the channel length direction, and the direction of the dashed dotted line G3-G4 may be referred to as the channel width direction.

[0149] The transistor 106 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; and a conductive layer the insulating layer 160 in contact with the oxide semiconductor layer 130; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. , the conductive layer 141 and the conductive layer 142 are electrically connected to each other through openings provided in the insulating layer 175 and the insulating layer 180 . The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, the insulating layer 180, the conductive layer 142, and the insulating layer (planarization film) in contact with the conductive layer 152 are ) and the like.

[0150] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are It is designed so that it does not come into contact with the

[0151] Transistor 106 has the same structure as transistor 106 except that it has conductive layer 141 and conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has the same structure as the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 152) can act as a base electrode layer. 2) can act as a drain electrode layer.

[0152] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 50 is not in contact with the insulating layer 120, the oxygen in the insulating layer 120 is and the conductive layer 150 is less likely to take away the oxide from the insulating layer 120 into the oxide semiconductor layer 130. This makes it easier to supply the raw material.

[0153] Regions 231 and 232 in transistor 103, transistor 104 and In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed to increase the conductivity. Impurities that form oxygen vacancies in the oxide semiconductor layer may be added. Examples include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, and helix. Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more impurities selected from zinc and carbon can be used. The methods of adding the metal oxide include plasma treatment, ion implantation, ion doping, plasma ion implantation, and the like. A method such as ion implantation can be used.

[0154] When the above-described elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes the oxide The conductivity of the semiconductor layer can be increased.

[0155] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by adding an impurity element, the oxygen vacancies are Hydrogen enters the loss site and a donor level is formed near the conduction band. Here, an oxide semiconductor that has been made into a conductor is referred to as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0156] Oxide conductors are degenerate semiconductors, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a The contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer functioning as the drain electrode layer can be reduced.

[0157] Further, the transistor of one embodiment of the present invention can be formed by the following methods. 20(C) and (D) are cross-sectional views of the channel length direction shown in FIG. 20(F) and FIG. 20(C) and (D). As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer 173 may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is The width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. The width may be shorter than that of the

[0158] To increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and the double In addition, to control the threshold voltage, A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 20(D), 73 can be electrically connected via a contact hole.

[0159] In addition, in the transistors 101 to 106 in FIGS. Although the oxide semiconductor layer 130 is illustrated as a single layer, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 is preferably Alternatively, it can be replaced with the oxide semiconductor layer 130 shown in FIG.

[0160] 22(A), (B), and (C) are top views of the oxide semiconductor layer 130 having a two-layer structure, and The cross section taken along the dashed line A1-A2 in FIG. 22(A) corresponds to FIG. 22(B). The cross section along the dashed line A3-A4 shown in FIG. 22(A) corresponds to FIG. 22(C). do.

[0161] 23A, 23B, and 23C are top views of the oxide semiconductor layer 130 having a three-layer structure. The cross section along the dashed line A1-A2 shown in FIG. 23(A) is shown in FIG. 23(B). Also, the cross section along the dashed line A3-A4 shown in FIG. 23(A) corresponds to FIG. 23(C). Equivalent.

[0162] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers or the like having different compositions can be used.

[0163] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 24A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 24(B). The cross section in the -H4 direction corresponds to Fig. 30(A). The longitudinal direction, the direction of the dashed dotted line H3-H4, may be referred to as the channel width direction.

[0164] The transistor 107 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and a The conductive layer 140 and the conductive layer 150 that are connected, and the stacked layer, the conductive layer 140 and the conductive layer 15 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and a and an insulating layer 180 that functions as a planarizing film, if necessary. A function may be added.

[0165] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The conductive layer 140 and the conductive layer 150 are the insulating layer 160. The oxide semiconductor layer 130c is formed between the first and second electrodes 130a and 130b. It has the same configuration as the transistor 101 .

[0166] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 25A is a top view of the transistor 108. The cross section in the direction of 1-I2 corresponds to FIG. 25(B). The cross section in the direction of -I4 corresponds to FIG. 30(B). The direction of the dashed dotted line I1-I2 corresponds to the channel The longitudinal direction, the direction of the dashed dotted line I3-I4, may be referred to as the channel width direction.

[0167] The transistor 108 is formed such that the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the edge of 0.

[0168] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 26A is a top view of the transistor 109, and the dashed line J in FIG. The cross section in the 1-J2 direction corresponds to FIG. 26(B). The cross section in the -J4 direction corresponds to Fig. 30(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, may be referred to as the channel width direction.

[0169] The transistor 109 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. the oxide semiconductor layer 130c, the insulating layer 160 in contact with the oxide semiconductor layer 130c, and the insulating layer 16 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covering the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and and a conductive layer 14 electrically connected to the stack through an opening provided in the insulating layer 180. 0 and conductive layer 150. In addition, an insulating layer 180, a conductive layer 140 and An insulating layer (planarizing film) or the like may be provided in contact with the conductive layer 150.

[0170] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The transistor 103 has the same configuration as the transistor 103 except that it is a compound semiconductor layer 130c.

[0171] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 27A is a top view of the transistor 110. The cross section in the direction of 1-K2 corresponds to FIG. 27(B). The cross section in the direction of -K4 corresponds to Fig. 30(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, may be referred to as the channel width direction.

[0172] The transistor 110 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The transistor 104 has the same configuration as the transistor 104 except that it is a compound semiconductor layer 130c.

[0173] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 28A is a top view of the transistor 111. The cross section in the 1-L2 direction corresponds to FIG. 28(B). The cross section in the -L4 direction corresponds to Fig. 30(A). The longitudinal direction, the direction of the dashed dotted line L3-L4, may be referred to as the channel width direction.

[0174] The transistor 111 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and a The conductive layer 141 and the conductive layer 151 that are connected, and the stacked layer, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the stacked conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the compound semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 is in contact with the insulating layer 175, and openings are formed in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 is also provided. If necessary, an insulating layer 180, a conductive layer 142, and a conductive layer 1 An insulating layer (flattening film) or the like may be provided in contact with 52.

[0175] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The conductive layer 141 and the conductive layer 151 are the insulating layer 160. The oxide semiconductor layer 130c is formed between the first and second electrodes 130a and 130b. It has the same configuration as the transistor 105 .

[0176] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 29A is a top view of the transistor 112. The cross section in the 1-M2 direction corresponds to FIG. 29(B). The cross section in the direction of -M4 corresponds to Fig. 30(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, may be referred to as the channel width direction.

[0177] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c, oxide semiconductor layer 130d, oxide semiconductor layer 130e, oxide semiconductor layer 130f ...). The transistor 106 and the transistor 107 are the same except that the first and second layers are the organic semiconductor layer 130b and the oxide semiconductor layer 130c. They have a similar configuration.

[0178] Further, the transistor of one embodiment of the present invention can be formed by the following methods. 30(C) and (D) are cross-sectional views in the channel length direction shown in FIG. 30(F) and FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows for an increase in on-current and control of the threshold voltage. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive layer 170. It may be shorter than the width.

[0179] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is formed by the conductive layer 140 and the conductive layer 150 as shown in FIG. Width of 150 (W SD ) is the width (W OS ) has been formed longer than Also, as shown in FIG. SD is W OS It is formed shorter than Good. W OS ≧W SD (W SD is W OS (below) so that the gate electric field is This makes it easier for the metal to be applied to the entire dielectric layer 130, thereby improving the electrical characteristics of the transistor. .

[0180] In the transistors of one embodiment of the present invention (transistors 101 to 112), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction through the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel This is called the (s-channel) structure.

[0181] In addition, a transistor having the oxide semiconductor layer 130a and the oxide semiconductor layer 130b, etc. and oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c. In a transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By flowing current through the conductor layer 130b, the device is less susceptible to the influence of interface scattering and a high on-current can be obtained. It should be noted that increasing the thickness of the oxide semiconductor layer 130b can improve the on-state current. For example, when the thickness of the oxide semiconductor layer 130b is set to 100 nm to 200 nm, Good too.

[0182] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0183] Note that in this specification, the channel length refers to, for example, the length of a semiconductor device in a top view of a transistor. The conductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate The source (source region or This refers to the distance between the source electrode and the drain electrode. In one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions where the channel is formed. The value may be a maximum, minimum or average value.

[0184] The channel width is, for example, the width of the semiconductor (or the semiconductor when the transistor is in the on state). The region where the gate electrode overlaps with the current-carrying part of the gate, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0185] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, When the gate electrode covers the side of the semiconductor, the effective channel width becomes larger than the apparent channel width. For example, when the gate electrode is In a transistor where the side of the semiconductor is covered, the percentage of the channel region formed on the side of the semiconductor is In this case, the effective channel width may be larger than the apparent channel width. The width will be larger.

[0186] In such a case, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known exactly, it is difficult to estimate the effective chip size. Channel width is difficult to measure accurately.

[0187] Therefore, in this specification, the apparent channel width is referred to as the "surrounding channel width (SCW)". In this specification, When simply described as channel width, it is the enclosed channel width or apparent channel width. In this specification, when simply referred to as a channel width, it refers to an effective The channel length, channel width, and effective channel width are also used. The apparent channel width, enclosed channel width, etc. can be determined by analyzing cross-sectional TEM images. The value can be determined by

[0188] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0189] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0190] (Embodiment 5) In this embodiment, components of the transistor shown in Embodiment 4 will be described in detail. do.

[0191] The substrate 115 is a silicon substrate on which transistors and / or photodiodes are formed. and a conductive layer having functions as an insulating layer, wiring, or contact plug on the silicon substrate. In addition, a p-channel transistor is formed on a silicon substrate. If n - It is preferable to use a silicon substrate having a conductivity type of n. - Type Alternatively, it may be an SOI substrate having an i-type silicon layer. The plane on which the transistor is formed is preferably a (110) plane. 10) By forming a p-ch transistor on the surface, mobility can be increased.

[0192] The insulating layer 120 serves to prevent the diffusion of impurities from elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The insulating layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. The insulating layer 120 is preferably an insulating film containing a fluorine atom in an amount equivalent to an oxygen atom measured by the TDS method. The calculated oxygen release rate is 1.0 x 10 19 atoms / cm 3 It is preferable that the value is equal to or greater than The surface temperature of the film during the TDS analysis was 100°C or higher and 700°C or lower, or 1 The insulating layer 120 also functions as an interlayer insulating film. CMP (Chemical Mechanical Polishing) is used to make the surface flat. A flattening process may be performed using a method such as a hing method.

[0193] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The insulating film may be a laminate of the above materials. It is also possible.

[0194] In this embodiment, the oxide semiconductor layer 130 included in the transistor is a) The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side. The details will be mainly explained for the three-layer structure.

[0195] Note that when the oxide semiconductor layer 130 is a single layer, the oxide semiconductor layer 13 Just use the layer corresponding to 0b.

[0196] In addition, when the oxide semiconductor layer 130 is a two-layer structure, the oxide semiconductor layer 13 A layer corresponding to oxide semiconductor layer 130a and a layer corresponding to oxide semiconductor layer 130b are formed in this order from the insulating layer 120 side. In this structure, the oxide semiconductor layer 130a and the oxide semiconductor layer It can also be swapped with 130b.

[0197] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having a three-layer structure. can be done.

[0198] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band) than the oxide layer 130c. The electron affinity is determined by the energy difference between the vacuum level and the top of the valence band (ion The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the

[0199] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum is 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be formed of a thin oxide semiconductor.

[0200] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. do.

[0201] The oxide semiconductor layer 130a contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface states may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a As a result, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0202] The oxide semiconductor layer 130c contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0203] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may contain, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf as an element having a higher conductivity than the oxide semiconductor layer 130b. Specifically, the atomic ratio is preferably 1.5 times or more. The amount is preferably two times or more, and more preferably three times or more. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from occurring in the oxide semiconductor layer. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0204] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also used. It is preferred that it contains

[0205] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and Gd. , Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0206] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0207] Here, for example, In-Ga-Zn oxide is a material having In, Ga, and Zn as main components. It means oxide. Metal elements other than In, Ga, and Zn may also be included. In this specification, a film made of In-Ga-Zn oxide is also called an IGZO film. .

[0208] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It refers to a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and A material expressed by the formula (n is an integer) may be used.

[0209] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are at least Both indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the oxide semiconductor layer 130a In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is In:M Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Zn=x If the atomic ratio is 3:y3:z3, then y1 / x1 and y3 / x3 are greater than y2 / x2. It is preferable that y1 / x1 and y3 / x3 are at least 1.5 times larger than y2 / x2. The thickness of the oxide semiconductor layer is preferably two times or more, and more preferably three times or more. In 130b, when y2 is equal to or greater than x2, the electrical characteristics of the transistor can be stabilized. However, if y2 is three times or more of x2, the field effect mobility of the transistor decreases. Therefore, it is preferable that y2 is less than three times x2.

[0210] When Zn and O are removed from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more for In and 75 atomic % or more for M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0211] The oxide semiconductor layer 130b is formed by multiplying the oxide semiconductor layer 130a and the oxide semiconductor layer 130b by the same amount. It is preferable to have a higher indium content than the c content. In oxide semiconductors, the s orbital of heavy metals is mainly The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are Because of the overlap of the paths, oxides with more In than M are compared with oxides with the same or less In than M. Therefore, when the oxide semiconductor layer 130b contains a large amount of indium, the mobility increases. By using an oxide, a transistor with high field-effect mobility can be realized.

[0212] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less. More preferably, the thickness of the oxide semiconductor layer 130c is 15 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. It is preferable that the thickness of the oxide semiconductor layer 30a is larger than that of the oxide semiconductor layer 130c.

[0213] In order to provide a transistor having an oxide semiconductor layer as a channel with stable electrical characteristics, The impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is 1 x10 17 / cm 3 Less than 1 x 10 15 / cm 3 Less than or equal to 1 x10 13 / cm 3 It shall be less than.

[0214] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels become traps and may degrade the electrical characteristics of the transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in the layer 130c and at the respective interfaces.

[0215] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, SIMS (Secondary Induction Measuring Machine) is used. The silicon concentration estimated by ion mass spectrometry (Ion Mass Spectrometry) analysis is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 Controlled to have an area that is less than In addition, the hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5 x 10 1 9 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, further Preferably 5 x 10 18 atoms / cm 3 The control is performed so as to have the following region. The nitrogen concentration may be, for example, at a certain depth in the oxide semiconductor layer or at a certain depth in the oxide semiconductor layer. In a region of the layer, 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Further details are as follows: Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0216] When silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced. In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, the silicon concentration is set to, for example, 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, even more preferred Or 1 x 10 18 atoms / cm 3 The control is performed so that the area is less than Carbon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 have an area that is less than Control it as follows.

[0217] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several It is possible to reduce the resistance to yA / μm to several zA / μm.

[0218] Since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is Therefore, it is preferable that the gate insulating film does not come into contact with the insulating film. When a channel is formed at the interface between the oxide semiconductor layer and the silicon dioxide layer, scattering of carriers occurs at the interface. From this viewpoint, the oxide semiconductor layer It is preferable to separate the region that will become the channel from the gate insulating film.

[0219] Therefore, the oxide semiconductor layer 130 is divided into the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b. This allows the formation of a transistor with high field-effect mobility and stable electrical characteristics. It is possible to form a

[0220] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers with different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0221] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, specifically, a U-shaped junction in which the energy of the bottom of the conduction band changes continuously between layers) The layers are fabricated so that a U-shaped well is formed. There are no impurities that form defect levels such as trap centers or recombination centers at the interface. If impurities are mixed between the stacked oxide semiconductor layers, When the energy band is not uniform, the continuity of the energy band is lost and carriers are trapped or recombined at the interface. It will disappear when combined.

[0222] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are made of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxide with an atomic ratio of 9:6 can be used. The compound semiconductor layer 130b has a composition of In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or Alternatively, an In-Ga-Zn oxide having an atomic ratio of 3:1:2 or the like can be used. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The atomic ratios of c each include a variation of ±20% of the above atomic ratios as an error. nothing.

[0223] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and The oxide semiconductor layer 130b has a conduction band minimum. Because the energy changes continuously, it can also be called a U-shaped well. A channel formed in this manner can also be called a buried channel.

[0224] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a film such as a silicon oxide film. Trap levels due to impurities and defects can be formed near the interface with the insulating layer. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c allows the oxide semiconductor layer 13 This can keep 0b away from the trap level.

[0225] However, the energy of the conduction band minimum of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the bottom of the conduction band of the oxide semiconductor layer 130b and the energy of the bottom of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap level, a negative charge is generated at the interface of the insulating layer, and the transistor The threshold voltage of the transistor shifts in the positive direction.

[0226] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include: It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, it is possible to form a transistor. In addition, the c-axis oriented crystal is resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0227] Conductive layer 140 acts as a source electrode layer and conductive layer 1 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Typical examples include Ti, which is particularly susceptible to bonding with oxygen, and materials that can be processed at relatively high temperatures afterward. For these reasons, it is more preferable to use W, which has a high melting point. Also, low-resistance Cu and Cu-M A stack of an alloy such as n and the above material may be used. 06, transistor 111, transistor 112, for example, conductive layer 141 and The conductive layer 142 and the conductive layer 152 are made of a laminated film of Ti and Al. You can be there.

[0228] The above-mentioned material has a property of extracting oxygen from the oxide semiconductor layer. In a part of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies combine with the small amount of hydrogen contained in the layer, turning the region into an n-type region. Therefore, the n-type region is used as the source or drain of a transistor. It can be used.

[0229] When W is used for the conductive layer 140 and the conductive layer 150, nitrogen doping is also effective. By doping with nitrogen, the oxygen-pulling property can be weakened appropriately, and n-type In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding into the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By contacting the n-type region with the As the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0230] The insulating layer 160, which acts as a gate insulating film, may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. It may contain r and the like as impurities.

[0231] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is made of, for example, oxygen. , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0232] Hafnium oxide and aluminum oxide are relatively It has a high dielectric constant. Therefore, the film thickness can be made larger than when silicon oxide is used. It is possible to reduce the leakage current due to the tunnel current. Furthermore, hafnium oxide, which has a crystalline structure, can be used in amorphous It has a higher dielectric constant than hafnium oxide, which has a structure. Therefore, it has a small off-state current. To make a small transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic systems. An embodiment is not limited to these.

[0233] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. For example, a silicon oxynitride film or an aluminum oxynitride film that emits a small amount of nitrogen oxides may be used. It can be used.

[0234] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it releases, typically 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The amount of ammonia released is as follows: Heat treatment at a surface temperature of the film of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower The amount released is the amount released by the

[0235] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0236] The conductive layer 170 acting as a gate electrode layer may be made of, for example, Al, Ti, Cr, Co, or Ni. Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W Furthermore, alloys of the above materials and conductive nitrides of the above materials may also be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are used. Typically, tungsten or a stack of tungsten and titanium nitride is used. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys, etc. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a silicon dioxide film.

[0237] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor transistor 106, transistor 109, transistor 110, and transistor 112 By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer becomes n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0238] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In transistors 107, 108, and 111, the insulating layer 175 is made of oxide. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Therefore, aluminum oxide has a high blocking effect, preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. to prevent oxygen from being mixed into the oxide semiconductor layer 130, to prevent oxygen from being released from the oxide semiconductor layer, and to prevent the insulating layer 1 Suitable for use as a protective film that has the effect of preventing unnecessary release of oxygen from 20 In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0239] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0240] Here, the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. It is preferable that oxygen released from the insulating layer 180 travels through the insulating layer 160 to the oxide semiconductor. Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, which leads to the formation of a stable transistor. Electrical properties can be obtained.

[0241] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate with the miniaturization of the channel width. When the size of the gate electrode decreases, the on-state current decreases.

[0242] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and reduces the on-state voltage of the transistor. The flow can be increased.

[0243] In addition, in the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from the direction perpendicular to the channel forming layer. Since the gate electric field is applied to the It can be improved.

[0244] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. In the first embodiment, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. This has the effect of making it difficult for an interface state to be formed. In a transistor having a three-layer oxide semiconductor layer 130, the oxide semiconductor layer 130b is located in the middle of the three-layer structure. By placing it in the layer above the ground, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor as described above, the threshold voltage is stabilized. Therefore, it is possible to reduce the S value (subthreshold value). The current when the voltage VG is 0V can be reduced, and power consumption can be reduced. Since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device is improved. Furthermore, the transistor of one embodiment of the present invention can improve electrical characteristics with miniaturization. Since deterioration of the semiconductor device can be suppressed, it can be said that this method is suitable for forming a highly integrated semiconductor device.

[0245] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0246] (Sixth embodiment) In this embodiment, the transistor 101, the transistor 107, and the transistor 108 described in Embodiment 4 are A method for manufacturing the transistor 111 will be described.

[0247] First, a method for fabricating a silicon transistor included in the substrate 115 will be described. As an example, we will explain how to fabricate a p-channel transistor. - A single-crystal silicon substrate is used, and an insulating layer (also called a field oxide film) is used to separate the The element formation region is formed by the LOCOS method (Local Oxide ation of Silicon), STI method (Shallow Trench Is olation) etc. can be used.

[0248] The substrate is not limited to a single crystal silicon substrate, but can also be SOI (Silicon on Insulator) A substrate or the like can also be used.

[0249] Next, a gate insulating film is formed to cover the element formation region. The surface of the silicon oxide film is oxidized to form a silicon oxide film. After forming the silicon oxide film, the surface of the silicon oxide film may be nitrided by performing nitriding treatment.

[0250] Next, a conductive film is formed to cover the gate insulating film. Elements selected from Mo, Al, Cu, Cr, Nb, etc. or containing these elements as the main component It can be made of alloy or compound materials. It can also be made of a metal nitride film. It can also be formed from a semiconductor material such as silicon.

[0251] Next, the conductive film is selectively etched to form a gate electrode layer on the gate insulating film. Form.

[0252] Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed to cover the gate electrode layer. Then, sidewalls are formed on the side surfaces of the gate electrode layer by etching back.

[0253] Next, a resist mask is selectively formed so as to cover areas other than the element formation area. By introducing impurity elements using the mask and gate electrode layer, p + Type Impurity Here, to form a p-channel transistor, impurity elements and As the impurity element, B, Ga, etc., which imparts p-type conductivity can be used.

[0254] This completes the fabrication of a p-channel transistor with an active region on the silicon substrate. A passivation film such as a silicon nitride film or an aluminum oxide film is formed on the transistor. It is preferable to form

[0255] Next, an interlayer insulating film is formed on the silicon substrate on which the transistors are formed, and various contact plates are Forming lugs and various wiring.

[0256] Next, a manufacturing method of the transistor 101 will be described with reference to FIGS. The left side of the drawing shows a cross section of the transistor in the channel length direction, and the right side shows a cross section in the channel width direction. The cross section is shown. The drawing in the channel width direction is an enlarged view, so the apparent film thickness of each element is shown on the left. It is different in the drawing on the right.

[0257] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The oxide semiconductor layer 130 has a three-layer structure, and the oxide semiconductor layer 130c has a two-layer structure. In this case, the oxide semiconductor layer 130 may be a two-layer structure including the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. In addition, when the oxide semiconductor layer 130 has a single layer structure, the oxide semiconductor layer 130b is a single layer. That's fine.

[0258] First, an insulating layer 120 is formed on a substrate 115. The type of substrate 115 and the insulating layer 120 For the material, the explanation of the fifth embodiment can be referred to. The insulating layer 120 is formed by a sputtering method, a CV method, and the like. It is formed using the D method, MBE (Molecular Beam Epitaxy) method, etc. It is possible.

[0259] The insulating layer 120 may be formed by ion implantation, ion doping, plasma immersion ion implantation, or the like. Oxygen may be added by implantation, plasma treatment, or the like. By adding oxygen, the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130 is further facilitated. It can be made easier.

[0260] The surface of the substrate 115 is an insulator, and the influence of impurity diffusion into the oxide semiconductor layer 130 to be formed later is small. If there is no noise, the insulating layer 120 may not be provided.

[0261] Next, an oxide semiconductor film 130A, which will become the oxide semiconductor layer 130a, is formed on the insulating layer 120. The oxide semiconductor film 130B that will become the semiconductor layer 130b and the oxide semiconductor film 130c that will become the oxide semiconductor layer 130c The oxide semiconductor film 130C is formed by sputtering, CVD, MBE, or the like (FIG. 3 3(A)).

[0262] When the oxide semiconductor layer 130 has a stacked structure, the oxide semiconductor film is Each layer is exposed to the atmosphere using a multi-chamber deposition device (e.g., a sputtering device). It is preferable to laminate the layers continuously without causing any damage to the film. In order to remove as much water as possible, which is an impurity for semiconductors, a cryopump is used. High vacuum evacuation (5×10) was performed using an adsorption type vacuum pump. -7 Pa~1×10 -4 Pa level and the substrate can be heated to 100°C or higher, preferably 500°C or higher. It is preferable to use a turbomolecular pump and a cold trap to separate the gas from the exhaust system. It is preferable to prevent gas containing carbon components, moisture, etc. from flowing back into the bar. An exhaust system combining a polymer pump and a cryopump may also be used.

[0263] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is preferable to highly purify the sputtering gas. The gas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By purifying the oxide semiconductor film to a high level, it is possible to prevent moisture and other substances from being absorbed into the oxide semiconductor film as much as possible. It is possible.

[0264] The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C are The materials described in the fifth embodiment can be used. The film can be formed using the material described in the fifth embodiment as a target.

[0265] However, as described in detail in the fifth embodiment, the oxide semiconductor film 130B contains an oxide semiconductor A material having a higher electron affinity than the oxide semiconductor film 130A and the oxide semiconductor film 130C is used.

[0266] The oxide semiconductor film is preferably formed by a sputtering method. RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0267] After the oxide semiconductor film 130C is formed, first heat treatment may be performed. , at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, The reaction may be carried out in a gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. The atmosphere of the first heat treatment is an inert gas atmosphere, and then the desorbed oxygen is replenished. In order to achieve this, the first heat treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C and the insulating layer 120, the oxide semiconductor film 130A, and the oxide semiconductor film 130 Impurities such as hydrogen and water can be removed from B and the oxide semiconductor film 130C. Note that the first heat treatment is performed on the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, The etching may be performed after the etching for forming the oxide semiconductor layer 130c.

[0268] Next, a conductive layer is formed on the oxide semiconductor film 130C. The conductive layer is formed, for example, by the following method. It can be formed by

[0269] First, a first conductive film is formed on the oxide semiconductor film 130C. l, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and related metallic materials A single layer or a laminate of materials selected from the alloys of the above can be used.

[0270] Next, a resist film is formed on the first conductive film, and the resist film is exposed to an electron beam. The first resist is exposed using a method such as immersion exposure or EUV exposure, and then developed. A mask is formed. An organic coating film is placed between the first conductive film and the resist film as an adhesive. It is also preferable to form the first resist by using nanoimprint lithography. A mask may be formed.

[0271] Next, the first conductive film is selectively etched using the first resist mask. The resist mask is then ashed to form a conductive layer.

[0272] Next, the conductive layer is used as a hard mask to form an oxide semiconductor film 130A. 130B and the oxide semiconductor film 130C are selectively etched to remove the conductive layer. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c The oxide semiconductor layer 130 is formed by stacking the above-mentioned conductive films (see FIG. 33B). The oxide semiconductor layer 130 may be formed using a first resist mask without forming a layer. Here, oxygen ions may be implanted into the oxide semiconductor layer 130.

[0273] Next, a second conductive film is formed to cover the oxide semiconductor layer 130. is a material that can be used for the conductive layer 140 and the conductive layer 150 described in the fifth embodiment. The second conductive film can be formed by a method such as sputtering, CVD, or MBE. You can be there.

[0274] Next, a second resist mask is formed on the portions that will become the source and drain regions. Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150. (See Figure 33(C)).

[0275] Next, an insulating film 160A is formed on the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150. The insulating film 160A can be used for the insulating layer 160 described in the fifth embodiment. The insulating film 160A can be formed by a method such as sputtering, CVD, or MBE. etc. can be used.

[0276] Next, a second heat treatment may be performed under the same conditions as the first heat treatment. By the second heat treatment, oxygen is removed from the insulating layer 120 and transferred to the oxide semiconductor layer 1. It is possible to diffuse the fluorine-containing compound into the entire surface of the substrate 30. The third heat treatment can be performed without performing the second heat treatment. The above effect may be obtained by the above theory.

[0277] Next, a third conductive film 171A and a fourth conductive film 171B, which will become the conductive layer 170, are formed on the insulating film 160A. The third conductive film 171A and the fourth conductive film 172A are formed as in the embodiment. The conductive layer 171 and the conductive layer 172 may be formed of a material that can be used for the conductive layer 171 and the conductive layer 172 described in Section 5. The third conductive film 171A and the fourth conductive film 172A can be formed by a sputtering method, a CVD method, or the like. The method, MBE, etc. can be used.

[0278] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 34(A) Then, using the third resist mask 156, the third conductive film 171A and the fourth conductive film 171B are formed. The conductive film 172A and the insulating film 160A are selectively etched to remove the conductive layer 171 and the conductive A conductive layer 170 made of a layer 172 and an insulating layer 160 are formed (see FIG. 34(B)). If the insulating film 160A is not etched, the transistor 102 can be fabricated. It is possible.

[0279] Next, the oxide semiconductor layer 130, the conductive layer 140, the conductive layer 150, the insulating layer 160 and the conductive layer An insulating layer 175 is formed on the insulating layer 170. For the material of the insulating layer 175, see the description of the fifth embodiment. In the case of the transistor 101, an aluminum oxide film is preferably used. The insulating layer 175 can be formed by a sputtering method, a CVD method, an MBE method, or the like. .

[0280] Next, the insulating layer 180 is formed on the insulating layer 175 (see FIG. 34(C)). For the material, the explanation of the fifth embodiment can be referred to. In addition, the insulating layer 180 is formed by sputtering. The method can be used for forming the thin film, such as a CVD method or an MBE method.

[0281] In addition, the insulating layer 175 and / or the insulating layer 180 may be subjected to ion implantation, ion doping, Oxygen is introduced using plasma immersion ion implantation, plasma treatment, etc. By adding oxygen, the insulating layer 175 and / or the insulating layer 1 This makes it easier to supply oxygen from 80 to the oxide semiconductor layer 130.

[0282] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be carried out by the insulating layer 120, the insulating layer 175, and the insulating layer 18. 0, excess oxygen is easily released, and oxygen vacancies in the oxide semiconductor layer 130 are reduced. can be done.

[0283] Next, a method for manufacturing the transistor 107 will be described. Detailed explanation of the steps that overlap with the manufacturing method of 02 will be omitted.

[0284] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a is formed on the insulating layer. The oxide semiconductor film 130A and the oxide semiconductor film 130B which will become the oxide semiconductor layer 130b are formed. The film is formed by using a sputtering method, a CVD method, an MBE method, or the like (see FIG. 35(A)).

[0285] Next, a first conductive film is formed on the oxide semiconductor film 130B, and the first conductive film is formed in the same manner as described above. A conductive layer is formed using a resist mask. Then, the conductive layer is subjected to an acid treatment using the resist mask as a hard mask. The conductive layer 130A and the oxide semiconductor layer 130B are selectively etched to form the conductive layer 130B. The layers are removed to form a stack of oxide semiconductor layers 130a and 130b. (See FIG. 35(B)). Note that a hard mask is not formed, and the first resist mask is used. Here, the stack may be formed using the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. Oxygen ions may be implanted into the layer 130b.

[0286] Next, a second conductive film is formed to cover the stacked layer. A second resist mask is formed on the portion that will become the gate region, and the second resist mask is used to Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150 ( See Figure 35(C)).

[0287] Next, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are stacked, and the conductive layer 140 and the conductive layer 150, an oxide semiconductor film 130C which becomes the oxide semiconductor layer 130c is formed. Furthermore, an insulating film 160A and a third conductive film 171A are formed on the oxide semiconductor film 130C. And the fourth conductive film 172A is formed.

[0288] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 36(A) Then, using the resist mask, the third conductive film 171A and the fourth conductive film 171B are formed. 72A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched to form conductive a conductive layer 170 consisting of a layer 171 and a conductive layer 172, an insulating layer 160, and an oxide semiconductor The insulating film 160A and the oxide semiconductor layer 130c are formed (see FIG. 36(B)). The film 130C is etched using a fourth resist mask to form the transistor 108. can be produced.

[0289] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 140, conductive layer 150, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed over the conductive layer 170 (see FIG. 36(C)).

[0290] Through the above steps, the transistor 107 can be manufactured.

[0291] Next, a method for manufacturing the transistor 111 will be described. Detailed explanation of the steps that overlap with the manufacturing method of 02 will be omitted.

[0292] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a is formed on the insulating layer 120. The oxide semiconductor film 130A and the oxide semiconductor film 130B that will become the oxide semiconductor layer 130b The first conductive film is formed by sputtering, CVD, MBE, or the like. A conductive layer 141a is formed on the compound semiconductor film 130B using a first resist mask. (See Figure 37(A)).

[0293] Then, the oxide semiconductor film 130A and the oxide semiconductor film 130B are removed using the conductive layer 141a as a hard mask. The oxide semiconductor layer 130B is selectively etched to remove the oxide semiconductor layer 130a and the oxide semiconductor layer 130 A stack of the oxide layer 141b and the conductive layer 141a is formed (see FIG. 37B). Oxygen ions may be implanted into the semiconductor layer 130a and the oxide semiconductor layer 130b.

[0294] Next, a second resist mask is formed on the portions that will become the source region and the drain region, Part of the conductive layer 141a is etched using the second resist mask, and the conductive layer 141 Then, a conductive layer 151 is formed (see FIG. 37(C)).

[0295] Next, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are stacked, and the conductive layer The oxide semiconductor film 130C that becomes the oxide semiconductor layer 130c is formed on the conductive layer 141 and the conductive layer 151. Furthermore, an insulating film 160A and a third conductive film 171A are formed on the oxide semiconductor film 130C. And the fourth conductive film 172A is formed.

[0296] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 38(A) Then, using the third resist mask 156, the third conductive film 171A and the fourth conductive film 171B are formed. The conductive film 172A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched. The conductive layer 170, which is made up of the conductive layer 171 and the conductive layer 172, the insulating layer 160, and the oxide layer Then, a compound semiconductor layer 130c is formed (see FIG. 38(B)).

[0297] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 140, conductive layer 150, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed on the conductive layer 170 .

[0298] Next, openings are formed in the insulating layer 175 and the insulating layer 180, reaching the conductive layer 141 and the conductive layer 151. A fifth conductive film is formed so as to cover the opening. A fourth resist mask is provided, and the fifth conductive film is selectively etched using the resist mask. The conductive layer 142 and the conductive layer 152 are formed by etching (see FIG. 38(C)).

[0299] Through the above steps, the transistor 111 can be manufactured.

[0300] The various films described in this embodiment, such as the metal film, semiconductor film, and inorganic insulating film, are typically It can be formed by a deposition method or a plasma CVD method, but other methods, such as thermal CVD, are also possible. The thermal CVD method may be, for example, MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atomic ic Layer Deposition) method.

[0301] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0302] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber. By reacting the material near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0303] In the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is introduced into the chamber. The film is formed by repeating this process. For example, two or more kinds of carrier gases (e.g., argon, nitrogen, etc.) may be introduced. The source gases may be supplied to the chamber in order. In this case, multiple source gases are not mixed. In this way, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be introduced into the surface of the substrate to form a first layer by adsorbing and reacting with the surface of the substrate. The second source gas introduced later is adsorbed and reacted with the first layer, and the second layer is formed on the first layer. The order of gas introduction is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is introduced. This is suitable for fabricating miniaturized FETs.

[0304] The thermal CVD method such as the MOCVD method or the ALD method can be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a Zn-O film, trimethylindium (In(CH3)3), Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and trimethylgallium may be replaced with triethylene. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0305] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and Liquid containing hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium) Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide ) hafnium amide) as a raw material gas and ozone ( Two types of gases are used:

[0306] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas, which is vaporized from other materials, and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0307] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorodisilane is adsorbed onto the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are supplied. is fed to react with the adsorbate.

[0308] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The two gases are introduced sequentially to form a tungsten film. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0309] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced sequentially to form a GaO layer. Then, Zn(CH3)2 gas and O3 gas are introduced sequentially to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. H2O gas obtained by bubbling with an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0310] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0311] (Embodiment 7) A structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described below. .

[0312] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°.

[0313] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0314] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0315] First, the CAAC-OS film will be described.

[0316] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0317] Transmission Electron Microscope (TEM) A bright-field image and a combined analysis image of the diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be identified. On the other hand, high-resolution TEM images also reveal clear boundaries between crystalline parts, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0318] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. The CAAC-OS film is formed on a surface (also called a surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is arranged parallel to the surface on which the CAAC-OS film is formed or the upper surface thereof.

[0319] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0320] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0321] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0322] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. These are elements other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that constitute the oxide semiconductor film, such as fluorine, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius (or molecular radius) is large, and when it is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement and cause a decrease in crystallinity. Objects can act as carrier traps or carrier sources.

[0323] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a source of carrier generation.

[0324] Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "substantially highly purified intrinsic" refers to a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics ( It is also called normally-on.) It is rare for it to become a high-purity intrinsic or substantially high-purity The intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The impurity concentration is high and the charge is stable for a long time, so the charge may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may occur.

[0325] In addition, transistors using CAAC-OS films show improved electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0326] Next, a microcrystalline oxide semiconductor film will be described.

[0327] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a crystal region and a crystal region where no clear crystal part can be identified. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fine particles are often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In addition, the nc-OS film has clearly defined grain boundaries in high-resolution TEM images. It may not be possible to recognize it.

[0328] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) using X-rays with a diameter larger than that of the crystals is used for nc-OS films. When structural analysis is performed using the D device, the crystal plane is In addition, the peaks indicating the probes larger than the crystalline part were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nanobeam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. When this is done, spots distributed circumferentially may be observed. When nanobeam electron diffraction is performed, multiple spots may be observed within a ring-shaped region. do.

[0329] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher defect state density than the CAAC-OS film.

[0330] Next, the amorphous oxide semiconductor film will be described.

[0331] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0332] In the amorphous oxide semiconductor film, no crystalline portion can be confirmed in a high-resolution TEM image.

[0333] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the analysis by the Lane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0334] The oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be used, particularly, for amorphous-like oxidation. Amorphous-like Oxide Semiconductor (a-like OS) The membrane is called a conductor membrane.

[0335] In the a-like OS film, voids are observed in high-resolution TEM images. In addition, crystals can be clearly seen in high-resolution TEM images. The a-like OS film has a region where the crystal part is not observed and a region where the crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed with a TEM, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be detected. Almost no crystallization due to electron irradiation is observed.

[0336] The size of the crystalline parts of the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO4 crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. The structure has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. Therefore, the spacing between these adjacent layers is The lattice spacing (also called the d value) is approximately the same as the value of 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in high-resolution TEM images and calculated the spacing between the lattice fringes. In the region where the distance is between 0.28 nm and 0.30 nm, each lattice fringe is InG aIt corresponds to the ab plane of the ZnO4 crystal.

[0337] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a finely crystalline oxide semiconductor film. The film may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0338] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0339] (Embodiment 8) An imaging device according to one embodiment of the present invention and a semiconductor device including the imaging device are used in a display device, a personal computer ... personal computers, image playback devices equipped with recording media (typically DVDs: Digital l Versatile Disc and other recording media can be played and images can be displayed on the disc. In addition, the imaging device according to one embodiment of the present invention can be used in a device having a display. Examples of electronic devices that can use the semiconductor device including the imaging device include a mobile phone, Game consoles including portable ones, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras, goggle-type displays (head-mounted displays), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (ATMs) Examples of such electronic devices include electronic devices such as smartphones, tablets, and vending machines. Specific examples of such electronic devices are shown in Figure 39.

[0340] FIG. 39(A) shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 39(A) has two display units 903 and the like. and a display unit 904, the number of display units that the portable game machine has is not limited to this. The imaging device of one embodiment of the present invention can be used as the camera 909.

[0341] FIG. 39(B) shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. The imaging device of one embodiment of the present invention can be used as the camera 919.

[0342] FIG. 39(C) shows a digital camera, which includes a housing 921, a shutter button 922, a microphone 9 23, a light emitting unit 927, a lens 925, etc. The imaging device may include an imaging device according to one embodiment of the present invention.

[0343] FIG. 39(D) shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, a wristband 9 The display unit 932 may be a touch panel. The imaging device of one embodiment of the present invention can be used for the laser 939.

[0344] FIG. 39(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2. The focal point of the lens 945 is can be equipped with the imaging device according to one aspect of the present invention.

[0345] FIG. 39(F) shows a mobile phone, which includes a housing 951, a display unit 952, a microphone 957, a speaker, and the like. The camera 954, the camera 959, the input / output terminal 956, the operation button 955, etc. The imaging device of one embodiment of the present invention can be used for 959.

[0346] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. . [Explanation of symbols]

[0347] 11 Circuits 12 circuits 13 Circuit 21 Wiring 22 Wiring 23 Wiring 24 Wiring 25 Wiring 26 Wiring 27 Wiring 28 Wiring 29 Wiring 30 Wiring 31 Wiring 32 Wiring 40 Silicon substrate 51 Transistor 52 transistors 53 Transistor 54 transistors 55 transistors 56 transistors 57 Transistor 58 transistors 59 Transistor 60 photodiodes 70 transistors 71 Transistor 80 insulating layer 90 Circuit section 92 Circuit section 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 107 Transistor 108 transistors 109 Transistor 110 Transistor 111 Transistor 112 transistors 115 PCB 120 insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130A oxide semiconductor film 130b Oxide semiconductor layer 130B Oxide semiconductor film 130c Oxide semiconductor layer 130C oxide semiconductor film 140 Conductive layer 141 Conductive layer 141a Conductive layer 142 Conductive layer 150 conductive layer 151 Conductive layer 152 Conductive layer 156 Resist mask 160 Insulating Layer 160A insulating film 170 Conductive Layer 171 Conductive layer 171A Conductive film 172 Conductive layer 172A Conductive film 173 Conductive Layer 175 Insulating Layer 180 insulating layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 400 pixel unit 410 line driver 420 A / D conversion circuit 430 column driver 501 signal 502 signal 503 signal 504 signal 505 signal 506 signal 507 signal 508 signal 509 signal 510 period 511 period 520 period 531 period 610 period 611 period 612 period 613 period 621 period 622 period 623 period 631 period 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 chassis 912 Display section 919 Camera 921 Case 922 shutter button 923 Mike 925 lens 927 Light-emitting part 931 Case 932 Display section 933 Wristband 939 Camera 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 Case 952 Display section 954 Speaker 955 Button 956 Input / output terminal 957 Mike 959 Camera

Claims

[Claim 1] An imaging device having a first circuit and a second circuit, the first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a third capacitor; the second circuit includes a seventh transistor; one terminal of the photoelectric conversion element is electrically connected to one of the source and the drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to the one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to one terminal of the first capacitance element; one of the source and the drain of the third transistor is electrically connected to the other terminal of the first capacitance element; the other terminal of the first capacitance element is electrically connected to one terminal of the second capacitance element; one of the source and the drain of the fourth transistor is electrically connected to the other terminal of the second capacitance element; the other of the source and the drain of the fourth transistor is electrically connected to the one of the source and the drain of the fifth transistor; one terminal of the third capacitance element is electrically connected to the other terminal of the second capacitance element; the other terminal of the third capacitance element is electrically connected to the other of the source and the drain of the fifth transistor; a gate of the fifth transistor is electrically connected to one terminal of the third capacitance element; one of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor; The other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor.

Images