Semiconductor device

Abstract

To provide a semiconductor device that can reduce leakage current.SOLUTION: A semiconductor device according to an embodiment comprises a first electrode, a first semiconductor area of a first conductivity type, a second semiconductor area of a second conductivity type, a third semiconductor area of the first conductivity type, an electric conductor, a gate electrode, and a second electrode. The electric conductor is provided in the first semiconductor area with an insulating part therebetween. The electric conductor includes a first conductive part and a second conductive part. The first conductive part has a first surface intersecting a first direction and a second surface stretching from the first surface and inclined with respect to the first surface. The second conductive part is provided on the first conductive part. In a second direction, the length of the first conductive part is longer than the length of the second conductive part. The first conductive part includes a first portion and a second portion. The first portion has the first surface and the second surface, and its length in the second direction increases toward the upper part. The second portion is provided on the first portion, and its length in the second direction decreases toward the upper part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, for example, and there is a demand for reducing leakage current in semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-108322 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of reducing leakage current. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductor, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode and electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on a portion of the second semiconductor region. The conductor is provided in the first semiconductor region via an insulating portion. The conductor includes a first conductive portion and a second conductive portion. The first conductive portion has a first surface that intersects with a first direction from the first electrode toward the first semiconductor region, and a second surface that is continuous with the first surface and inclined with respect to the first surface. The second conductive portion is provided on the first conductive portion. In a second direction perpendicular to the first direction, the length of the first conductive portion is longer than the length of the second conductive portion. The first conductive portion includes a first portion and a second portion. The first portion has the first surface and the second surface, and its length in the second direction increases upward. The second portion is provided on the first portion, and its length in the second direction decreases upward. The gate electrode is provided in the insulating portion and faces the second semiconductor region in the second direction via a gate insulating layer. The second electrode is provided on the second semiconductor region and the third semiconductor region, and is electrically connected to the second semiconductor region and the third semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view of a part of FIG. [Figure 3] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6]1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to a reference example. [Figure 8] 1 is a graph schematically showing characteristics of a semiconductor device. [Figure 9] FIG. 10 is a perspective cross-sectional view showing a part of a semiconductor device according to a modified example of the embodiment. [Figure 10] FIG. 10 is a perspective cross-sectional view showing a part of a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate. In the following description and drawings, n + , n - , p + The notations "+" and "p" indicate the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] FIG. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes n- p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + source region 3 (third semiconductor region), p + Shape contact area 4, n + The semiconductor device 100 includes a drain region 5, a conductor 10, an insulating portion 21, a gate electrode 30, a drain electrode 41 (first electrode), and a source electrode 42 (second electrode). The semiconductor device 100 is, for example, a MOSFET.

[0009] The embodiment will be described using an XYZ Cartesian coordinate system. - The direction toward the drift region 1 is the Z direction (first direction). The direction perpendicular to the Z direction is the X direction (second direction). The direction perpendicular to the X and Z directions is the Y direction. - The direction toward the drift region 1 is called "up" and the opposite direction is called "down." These directions are the direction between the drain electrode 41 and the n - This is a direction based on the relative positional relationship with the shape drift region 1 and is unrelated to the direction of gravity.

[0010] The drain electrode 41 is provided on the bottom surface of the semiconductor device 100. + The drain region 5 is provided on the drain electrode 41 and is electrically connected to the drain electrode 41. - The drift region 1 is n + The n-type drain region 5 is provided on the n-type drain region 5. - The n-type impurity concentration in the n-type drift region 1 is + The n-type impurity concentration in the n-type drain region 5 is lower than that in the n-type - The drift region 1 is n + The gate electrode 41 is electrically connected to the drain electrode 41 via the drain region 5 .

[0011] The p-type base region 2 is - The n-type drift region 1 is provided on the n-type drift region 1. + The p-type source region 3 is provided on a part of the p-type base region 2. +The p-type contact region 4 is provided on another part of the p-type base region 2. + The p-type impurity concentration in the p-type contact region 4 is higher than the p-type impurity concentration in the p-type base region 2.

[0012] The conductor 10 is connected to the n - The gate electrode 30 is provided in the insulating portion 21 and is located on the conductor 10. The gate electrode 30 is provided in the insulating portion 21 and faces the p-type base region 2 in the X direction via the gate insulating layer 31. The gate insulating layer 31 is a part of the insulating portion 21. In the illustrated example, the gate electrode 30 is - A part of the drift region 1 and n + It also faces a part of the source region 3.

[0013] The source electrode 42 is + Shape source region 3 and p + provided on the contact region 4, + Shape source region 3 and p + In the illustrated example, a part of the source electrode 42 extends downward and is electrically connected to a pair of n-type contact regions 4 arranged in the X direction. + The p-type base region 2 is provided between the p-type source regions 3. + The gate electrode 30 is electrically connected to the source electrode 42 via the contact region 4. The gate electrode 30 is electrically isolated from the source electrode 42 by the gate insulating layer 31.

[0014] p-type base region 2, n + Shape source region 3, p + The contact region 4, the conductor 10, and the gate electrode 30 each extend in the Y direction, and a plurality of them are provided in the X direction. The end of the conductor 10 in the Y direction is pulled upward and electrically connected to the source electrode 42. Alternatively, the insulating portion 21 may not be provided between the conductor 10 and the gate electrode 30, and the conductor 10 may be electrically connected to the gate electrode 30.

[0015] FIG. 2 is an enlarged cross-sectional view of a part of FIG. 2, the bottom surface of the conductor 10 includes a first surface S1, a second surface S2, and a third surface S3. The first surface S1 is parallel to the XY plane. The second surface S2 and the third surface S3 are continuous with the first surface S1 and are inclined with respect to the X and Z directions. The position of the first surface S1 in the X direction is between the position of the second surface S2 in the X direction and the position of the third surface S3 in the X direction.

[0016] More specifically, the conductor 10 includes a first conductive portion 11, a second conductive portion 12, and a third conductive portion 13. The first conductive portion 11 is located at the lower end of the conductor 10. The second conductive portion 12 is provided on the first conductive portion 11. The third conductive portion 13 is provided on the second conductive portion 12.

[0017] The first conductive portion 11 has a first surface S1 to a third surface S3. The width (length in the X direction) W1 of the first conductive portion 11 is longer than the width W2 of the second conductive portion 12. The width W2 of the second conductive portion 12 is shorter than the width W3 of the third conductive portion 13. The width W2 of the second conductive portion 12 may be the same as the width W3 of the third conductive portion 13.

[0018] The first conductive part 11 includes a first portion 11a and a second portion 11b. The first portion 11a has a first surface S1 to a third surface S3. The second portion 11b is provided on the first portion 11a. The width of the first portion 11a increases upward. The width of the second portion 11b decreases upward. For example, the length of the first portion 11a in the Z direction is shorter than the length of the second portion 11b in the Z direction.

[0019] As shown in the figure, a void V may be provided in the first conductive part 11. The void V provided in the first conductive part 11 extends in the Y direction. Alternatively, a plurality of voids V may be scattered in the Y direction.

[0020] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 41 relative to the source electrode 42, a voltage equal to or greater than the threshold is applied to the gate electrode 30. This forms a channel (inversion layer) in the p-type base region 2, turning the semiconductor device 100 on. Electrons flow through the channel from the source electrode 42 to the drain electrode 41. When the voltage applied to the gate electrode 30 becomes lower than the threshold, the channel in the p-type base region 2 disappears, turning the semiconductor device 100 off.

[0021] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 41 increases relative to the source electrode 42. At this time, the potential difference between the drain electrode 41 and the source electrode 42 or the potential difference between the drain electrode 41 and the gate electrode 30 causes the insulating portion 21 and the n - From the interface with the drift region 1, - The depletion layer spreads toward the n-type drift region 1. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the breakdown voltage of the semiconductor device 100 can be increased while maintaining the breakdown voltage. - The n-type impurity concentration in the n-type drift region 1 can be increased, and the on-resistance of the semiconductor device 100 can be reduced.

[0022] An example of the material of each component of the semiconductor device 100 will be described. n - p-type drift region 1, p-type base region 2, n + Shape source region 3, p + contact region 4, and n + The n-type drain region 5 includes a semiconductor material. The semiconductor material may be silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, the n-type impurity may be arsenic, phosphorus, or antimony. The p-type impurity may be boron.

[0023] The insulating portion 21 includes an insulating material. For example, the insulating portion 21 includes silicon oxide, silicon nitride, or silicon oxynitride. The conductor 10 and the gate electrode 30 include a conductive material such as polysilicon. The conductor 10 and the gate electrode 30 may be doped with n-type or p-type impurities. The drain electrode 41 and the source electrode 42 include a metal such as titanium, tungsten, or aluminum.

[0024] 3 to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. An example of a method for manufacturing the semiconductor device 100 according to the embodiment will be described with reference to FIGS. + A semiconductor substrate Sub including a semiconductor layer 5a is prepared. As shown in FIG. + Silicon is epitaxially grown on the semiconductor layer 5a to form an n-type - A thin semiconductor layer 1a is formed.

[0025] As shown in Figure 3(b), photolithography and reactive ion etching (RIE) were used to create n - A plurality of trenches T1 are formed on the upper surface of the semiconductor layer 1a. A mildly anisotropic etching gas is used during RIE. This allows the bottom surfaces of the trenches T1 to be curved. The {100} and {110} silicon planes are exposed on this curved surface. Sulfur hexafluoride (SF6) can be used as the etching gas.

[0026] As shown in Figure 4(a), n -An insulating layer 21a is formed on the upper surface of the semiconductor layer 1a and along the inner surface of the trench T1. The insulating layer 21a is formed by thermal oxidation. During this process, oxidation progresses along the silicon

[0100] and

[0110] directions. As a result, a flat surface S1a, an inclined surface S2a, and an inclined surface S3a are formed on the lower surface of the trench T2 surrounded by the insulating layer 21a. The {100} plane of silicon oxide is exposed on the flat surface S1a. The {110} plane of silicon oxide is exposed on the inclined surfaces S2a and S3a. Furthermore, during the formation of the insulating layer 21a, the width of the bottom of the trench T2 becomes wider than its upper portion. This is thought to be due to the influence of stress during thermal oxidation, as described below.

[0027] For silicon and silicon oxide, the {100} plane refers to any of the (100), (010), and (001) planes, which are equivalent to each other, and the {110} plane refers to any of the (110), (011), and (101) planes, which are equivalent to each other.

[0028] A conductive layer 10a is formed on the insulating layer 21a to fill the trench T2. The conductive layer 10a is formed by chemical vapor deposition (CVD) of a conductive material such as polysilicon. During the formation of the conductive layer 10a, a void V is formed at the bottom of the trench T2. A portion of the conductive layer 10a is removed by chemical dry etching (CDE) or the like to recess the upper surface of the conductive layer 10a. This results in the formation of multiple conductive layers 10a, each separated and provided within the multiple trenches T2. As shown in FIG. 4(b), an insulating layer 21b is formed on the insulating layer 21a and the multiple conductive layers 10a by CVD. The conductive layer 10a has a first surface S1 in contact with the flat surface S1a. The conductive layer 10a also has a second surface S2 and a third surface S3 in contact with the inclined surfaces S2a and S3a, respectively.

[0029] The upper surfaces of the insulating layers 21a and 21b are recessed by wet etching. - The upper surface of the n-type semiconductor layer 1a and a part of the side surface of the trench T1 are exposed. -An insulating layer 31a is formed on the upper surface of the semiconductor layer 1a and on the side surfaces of the trenches T1. The thickness of the insulating layer 31a is smaller than the thickness of the insulating layer 21a. A conductive layer 30a is formed on the insulating layer 31a. As shown in FIG. 5(a), the upper surface of the conductive layer 30a is recessed by CDE or wet etching, and the conductive layer 30a is formed inside each trench T1.

[0030] Between trenches T1 - P-type impurities and n-type impurities are ion-implanted successively into the upper portion of the p-type semiconductor layer 1a to form p-type semiconductor regions 2a and n-type semiconductor regions 2b. + 5(b), an insulating layer 31b is formed to cover the plurality of conductive layers 30a.

[0031] Insulating layer 31b, insulating layer 31a, and n + An opening OP is formed through the p-type semiconductor region 3a to reach the p-type semiconductor region 2a. P-type impurities are ion-implanted into the p-type semiconductor region 2a through the opening OP, and as shown in FIG. + A semiconductor region 4a is formed.

[0032] A metal layer 42a is formed on the insulating layer 31b to fill the opening OP. + The lower surface of the semiconductor substrate Sub is ground until the shaped semiconductor layer 5a reaches a predetermined thickness. As shown in Figure 6(b), a metal layer 41a is formed on the ground lower surface. Through the above steps, the semiconductor device 100 shown in Figure 1 is manufactured.

[0033] n shown in Figure 6(b) - The semiconductor layer 1a is a n-type semiconductor layer shown in FIG. - The p-type semiconductor region 2a corresponds to the p-type drift region 1. The p-type semiconductor region 2a corresponds to the p-type base region 2. + The semiconductor region 3a is n + Corresponding to the shape source region 3. p + The semiconductor region 4a is p + corresponding to the contact area 4. + The semiconductor layer 5a is an n-type +The metal layer 41a corresponds to the drain region 5. The conductive layer 10a corresponds to the conductor 10. The insulating layers 21a and 21a correspond to the insulating portion 21. The conductive layer 30a corresponds to the gate electrode 30. The insulating layers 31a and 31b correspond to the gate insulating layer 31. The metal layer 41a corresponds to the drain electrode 41. The metal layer 42a corresponds to the source electrode 42.

[0034] The advantages of the semiconductor device according to the embodiment will be described. FIG. 7 is a cross-sectional view showing a part of a semiconductor device according to a reference example. In the semiconductor device 100r shown in Figure 7, the conductor 10r has a bottom surface BS, a side surface SS1, and a side surface SS2. The bottom surface BS is parallel to the XY plane. The side surfaces SS1 and SS2 are parallel to the YZ plane. Therefore, the angle between the bottom surface BS and the side surface SS1 and the angle between the bottom surface BS and the side surface SS2 are right angles.

[0035] When the semiconductor device 100r is in an off state, the potential difference between the drain electrode 41 and the source electrode 42 causes n - An electric field is generated between the drift region 1 and the conductor 10r. At this time, the electric field is concentrated at the corner of the lower end of the conductor 10r. A leakage current flows in the insulating portion 21 due to the large electric field.

[0036] FIG. 8 is a graph schematically showing the characteristics of the semiconductor device. 8, the horizontal axis represents the voltage Vds of the drain electrode 41 relative to the source electrode 42. The vertical axis represents the current Id flowing between the drain electrode 41 and the source electrode 42. The solid line represents the characteristics of the semiconductor device according to the reference example. The dashed line represents the characteristics of a desirable semiconductor device.

[0037] In a desirable semiconductor device, the current Id is small until the voltage reaches the breakdown voltage Vbd. Once the voltage reaches the breakdown voltage Vbd, the current Id increases sharply. In contrast, in the semiconductor device 100r according to the reference example, the current Id begins to increase at a voltage V1. The voltage V1 is smaller than the breakdown voltage Vbd. This is due to leakage current flowing through the insulating portion 21. Furthermore, as the voltage Vds further increases and reaches a voltage V2, the current Id increases sharply. This is due to avalanche breakdown occurring at a portion of the insulating portion 21 with high electric field strength. As shown in FIG. 8, the leakage current flowing through the insulating portion 21 causes the effective breakdown voltage of the semiconductor device 100 to decrease from the original breakdown voltage Vbd to voltage V2.

[0038] To address this issue, in the semiconductor device 100 according to the embodiment, the lower surface of the conductor 10 includes a first surface S1 and a second surface S2. The first surface S1 is parallel to the X direction. The second surface S2, which is continuous with the first surface S1, is inclined with respect to the X direction and the Z direction. Therefore, the angle between the first surface S1 and the second surface S2 is less than 90 degrees. This reduces the electric field strength near the lower end of the conductor 10 compared to the semiconductor device 100r. As a result, leakage current can be suppressed from flowing through the insulating portion 21, improving the breakdown voltage of the semiconductor device 100.

[0039] If the angle between the first surface S1 and the second surface S2 is large, the effect of reducing the electric field strength is weakened. On the other hand, if the angle is small, the width of the lower end of the conductor 10 becomes long. As a result, it becomes difficult to miniaturize the conductor 10, the insulating portion 21, etc., and the on-resistance of the semiconductor device 100 may increase. For this reason, the angle is preferably greater than 30 degrees and less than 60 degrees.

[0040] The bottom surface of the conductor 10 also includes a third surface S3 that is continuous with the first surface S1. The third surface S3 is inclined with respect to the X and Z directions. Therefore, the angle between the first surface S1 and the third surface S3 is less than 90 degrees. This further reduces the electric field strength near the bottom end of the conductor 10. The angle between the first surface S1 and the third surface S3 is preferably greater than 30 degrees and less than 60 degrees.

[0041] 2, the conductor 10 includes a first conductive portion 11 and a second conductive portion 12. In the X direction, the length of the first conductive portion 11 is longer than the length of the second conductive portion 12. In other words, the lower end of the conductor 10 bulges. This structure, like the structures of the first surface S1 to the third surface S3, can reduce the electric field strength near the first conductive portion 11.

[0042] As shown in Figures 1 and 2, the first conductive portion 11 preferably includes voids V. When voids V are provided, the conductor 10 is more likely to deform in response to the stress of the insulating portion 21 than when voids V are not provided. This reduces the stress of the insulating portion 21. - The stress applied to the drift region 1 is reduced. - The occurrence of crystal defects in the drift region 1 can be suppressed.

[0043] The voids V preferably extend in the Y direction. In this case, the volume of the voids V is larger than when multiple voids V are scattered in the Y direction. This further reduces the stress in the insulating portion 21.

[0044] In the semiconductor device 100, the bottom of the insulating portion 21 is in contact with the conductor 10 in the Z direction. - The side of the insulating portion 21 is located between the conductor 10 and the n-type drift region 1 in the X direction. - The insulating portion 21 is located between the first and second drift regions 1 and 1. According to the embodiment, the thickness T2a of the bottom of the insulating portion 21 can be increased, and the difference between the thickness T1a and the thickness T2a of the side of the insulating portion 21 can be reduced. As a result, the electric field strength in the insulating portion 21 can be reduced, and the leakage current flowing through the insulating portion 21 can be reduced.

[0045] The reason for the increase in thickness T2a is believed to be as follows. When forming the insulating portion 21, a large compressive stress is generated at the bottom of the insulating portion 21. In the semiconductor device 100r shown in FIG. 7, the angle between the bottom surface BS and the side surface SS1 is approximately a right angle, making it difficult to disperse the compressive stress at the bottom of the insulating portion 21. As a result, in the semiconductor device 100r, the thickness T2b of the bottom of the insulating portion 21 is small, and the difference between the thicknesses T1b and T2b of the side surfaces of the insulating portion 21 is large. On the other hand, in the semiconductor device 100, the second surface S2 connected to the first surface S1 is inclined with respect to the X direction and the Z direction. The dispersion of the compressive stress is unlikely to be hindered by the right-angle corner. As a result, the compressive stress at the bottom of the insulating portion 21 is reduced, and the thickness T2a is increased.

[0046] In particular, for silicon oxide, the compressive stress in the

[0110] direction is smaller than the compressive stress in the

[0100] direction. When the insulating portion 21 contains silicon oxide, the {110} plane of the silicon oxide is present at the contact surface with the second surface S2 of the insulating portion 21. This reduces the compressive stress at the portion of the insulating portion 21 that contacts the second surface S2. As a result, the compressive stress at the bottom of the insulating portion 21 is more easily dispersed, and the thickness T2a increases.

[0047] (Variation) 9 and 10 are perspective cross-sectional views showing a part of the semiconductor device according to the embodiment. The structure of the conductor 10 other than the lower end, the structure of the gate electrode 30, and the like are not limited to the example shown in FIG. 1 and can be modified as appropriate. For example, as in the semiconductor device 110 shown in FIG. 9, multiple gate electrodes 30 may be provided in one insulating part 21. In the example shown, a pair of gate electrodes 30 are provided above the conductor 10. When viewed from the Z direction, the conductor 10 is located between the pair of gate electrodes 30 in the X direction.

[0048] Alternatively, as in a semiconductor device 120 shown in FIG. 10, the upper portion of the conductor 10 may be located between a pair of gate electrodes 30 in the X direction.

[0049] In either embodiment, the lower surface of the conductor 10 includes the first surface S1 to the third surface S3, thereby making it possible to prevent leakage current from flowing through the insulating portion 21 and improving the breakdown voltage of the semiconductor device.

[0050] The specific shape of the lower surface of the conductor 10 is not limited to the above example. For example, the lower surface of the conductor 10 may have a curved shape instead of the first surface S1, the second surface S2, and the third surface S3. In this case, the electric field strength near the lower end of the conductor 10 can also be reduced.

[0051] In the embodiments described above, the relative levels of impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative levels of carrier concentration between each semiconductor region can also be confirmed using SCM. The impurity concentration in each semiconductor region can be measured using secondary ion mass spectrometry (SIMS).

[0052] Electron backscatter diffraction (EBSD) can be used to analyze the crystal orientation of the insulating part 21 in contact with the lower surface of the conductor 10. For example, the vicinity of the interface between the conductor 10 and the insulating part 21 is analyzed using EBSD. When the lower surface of the conductor 10 includes the first surface S1 to the third surface S3, the analysis results show that the intensity of the peak corresponding to the {100} plane of silicon oxide is greater than the intensity of the peaks corresponding to the other planes. When the lower surface of the conductor 10 has a curved shape, the analysis results show multiple peaks corresponding to the multiple planes of silicon oxide.

[0053] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0054] 1:n - Shape drift region, 1a:n - 2: p-type base region; 2a: p-type semiconductor region; 3: n + Shape source area, 3a:n + Shape semiconductor area, 4:p + Shape contact area, 4a:p + Shape semiconductor area, 5:n + Shaped drain region, 5a:n + semiconductor layer, 10, 10r: conductor, 10a: conductive layer, 11: first conductive portion, 11a: first portion, 11b: second portion, 12: second conductive portion, 13: third conductive portion, 21: insulating portion, 21a, 21b: insulating layer, 30: gate electrode, 30a: conductive layer, 31: gate insulating layer, 31a, 31b: insulating layer, 41: drain electrode, 41a: metal layer, 42: source electrode, , 42a: metal layer, 100, 100r: semiconductor device, BS: bottom surface, OP: opening, S1: first surface, S1a: flat surface, S2: second surface, S2a: inclined surface, S3: third surface, S3a: inclined surface, SS1, SS2: side surface, Sub: semiconductor substrate, T1, T2: trench, T1a, T1b, T2a, T2b: Thickness, V: Void

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on a portion of the second semiconductor region; a conductor provided in the first semiconductor region via an insulating portion, the conductor comprising: a first conductive portion having a first surface that intersects with a first direction from the first electrode toward the first semiconductor region, and a second surface that is continuous with the first surface and is inclined with respect to the first surface; a second conductive portion provided on the first conductive portion, In a second direction perpendicular to the first direction, the length of the first conductive portion is longer than the length of the second conductive portion; The first conductive portion is a first portion having the first surface and the second surface, the first portion having a length in the second direction increasing upward; a second portion provided on the first portion, the second portion having a length in the second direction that decreases upward; the conductor comprising: a gate electrode provided in the insulating portion and facing the second semiconductor region in the second direction via a gate insulating layer; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; A semiconductor device comprising:

2. the conductor further includes a third conductive portion provided on the second conductive portion; The semiconductor device according to claim 1 , wherein a length of the second conductive portion in the second direction is shorter than a length of the third conductive portion.

3. a {100} plane of silicon oxide is present on a surface of the insulating portion in contact with the first surface, 3. The semiconductor device according to claim 1, wherein a {110} plane of silicon oxide exists on a surface of said insulating portion that contacts said second surface.

4. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on a portion of the second semiconductor region; a conductor provided in the first semiconductor region via an insulating portion, the lower surface of the conductor having a first surface intersecting a first direction from the first electrode toward the first semiconductor region; a second surface connected to the first surface and inclined relative to the first surface; the conductor including: a {100} plane of silicon oxide present on a surface of the insulating portion in contact with the first surface; and a {110} plane of silicon oxide present on a surface of the insulating portion in contact with the second surface; a gate electrode provided in the insulating portion and facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; A semiconductor device comprising:

5. the conductor includes a first conductive portion having the first surface and the second surface, and a second conductive portion provided on the first conductive portion; The semiconductor device according to claim 4 , wherein the length of the first conductive portion is longer than the length of the second conductive portion in the second direction.

6. the conductor further includes a third conductive portion provided on the second conductive portion; The semiconductor device according to claim 5 , wherein the length of the second conductive portion in the second direction is shorter than the length of the third conductive portion.

7. 7. The semiconductor device according to claim 1, wherein a void is provided at the lower end of said conductor.

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