Semiconductor device and storage device

Abstract

To provide a semiconductor device capable of miniaturization or high integration.SOLUTION: A semiconductor device includes an oxide semiconductor layer, first to third insulating layers, and first to third conductive layers. The first and second conductive layers are provided apart from each other on the first insulating layer. The first insulating layer includes a groove part between the first conductive layer and the second conductive layer. The oxide semiconductor layer includes a region in contact with an upper surface and a side surface of the first conductive layer, a region in contact with an upper surface and a side surface of the second conductive layer, and a region in contact with a side surface of the groove part. The second insulating layer is provided on the oxide semiconductor layer. The third conductive layer is provided on the second insulating layer. The side surfaces of the third conductive layer, the second insulating layer, and the oxide semiconductor layer coincide or substantially coincide with each other. The third insulating layer includes a region in contact with each of the side surface of the oxide semiconductor layer, the side surface of the second insulating layer, and the side surface of the third conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device or the memory device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] BACKGROUND ART Integrated circuits (IC chips) such as LSIs, CPUs, or memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in an off state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 also discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-211537 [Non-patent literature]

[0010] [Non-Patent Document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 Summary of the Invention [Problem to be solved by the invention]

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, or memory device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims. [Means for solving the problem]

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, first to third insulating layers, and first to third conductive layers. The first conductive layer and the second conductive layer are provided over the first insulating layer and are spaced apart from each other. The first insulating layer has a groove between the first conductive layer and the second conductive layer. The oxide semiconductor layer has a region in contact with an upper surface and a side surface of the first conductive layer on the groove side, a region in contact with an upper surface and a side surface of the second conductive layer on the groove side, and a region in contact with a side surface of the groove. The second insulating layer is provided over the oxide semiconductor layer. The third conductive layer is provided over the second insulating layer. The side surfaces of the third conductive layer, the second insulating layer, and the oxide semiconductor layer are aligned or substantially aligned. The third insulating layer has, outside the groove, a region in contact with the top surface of the first conductive layer, the top surface of the second conductive layer, a side surface of the oxide semiconductor layer, a side surface of the second insulating layer, and a side surface of the third conductive layer, and, inside the groove, a region in contact with the side surface of the oxide semiconductor layer, a side surface of the second insulating layer, and a side surface of the third conductive layer, respectively.

[0014] It is preferable that the semiconductor device has a fourth conductive layer, the fourth conductive layer being in contact with the upper surface of the third conductive layer, and the direction in which the fourth conductive layer extends intersects with the direction in which the groove portion extends.

[0015] Preferably, the semiconductor device includes a fifth conductive layer, the fifth conductive layer having regions overlapping with the first conductive layer and the second conductive layer with a first insulating layer sandwiched therebetween, the fifth conductive layer having a recess in the region overlapping with the groove, and the oxide semiconductor layer having regions in contact with side surfaces and a bottom of the recess.

[0016] In the semiconductor device, the recess preferably has a curved portion.

[0017] One embodiment of the present invention is a memory device including a capacitor, a transistor over the capacitor, a first insulating layer, and a second insulating layer. The transistor includes an oxide semiconductor layer, a third insulating layer, and first to fourth conductive layers. The first insulating layer is provided to cover the first conductive layer. The second conductive layer and the third conductive layer are provided over the first insulating layer and are spaced apart from each other. The first insulating layer has a groove between the second conductive layer and the third conductive layer. The first conductive layer has a recess in a region overlapping with the groove. The oxide semiconductor layer includes a region in contact with a top surface and a side surface of the second conductive layer on the groove side, a region in contact with a top surface and a side surface of the third conductive layer on the groove side, a region in contact with a side surface of the groove, and a region in contact with a side surface and a bottom of the recess. The third insulating layer is provided over the oxide semiconductor layer. The fourth conductive layer is provided over the third insulating layer. The side surfaces of the fourth conductive layer, the third insulating layer, and the oxide semiconductor layer are aligned or substantially aligned. The second insulating layer has a region outside the groove that contacts the top surface of the second conductive layer, the top surface of the third conductive layer, the side surface of the oxide semiconductor layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer, and a region inside the groove that contacts the side surface of the oxide semiconductor layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer,

[0018] Preferably, the memory device has a fifth conductive layer, the fifth conductive layer contacting the upper surface of the fourth conductive layer, and the direction in which the fifth conductive layer extends intersects with the direction in which the groove portion extends.

[0019] In the above storage device, the recess preferably has a curved portion.

[0020] In the above memory device, the capacitor preferably has a sixth conductive layer, a fourth insulating layer on the sixth conductive layer, and a first conductive layer on the fourth insulating layer.

[0021] In the above memory device, it is preferable that the third insulating layer has a first layer, and the first layer has an oxide containing hafnium.

[0022] In the above storage device, the first layer preferably includes hafnium zirconium oxide.

[0023] In the above memory device, it is preferable that the third insulating layer has a second layer on the first layer, and the second layer has silicon nitride.

[0024] One embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a first transistor, and a second transistor. The first insulating layer has a groove. The first transistor has a first oxide semiconductor layer including a channel formation region. The second transistor has a second oxide semiconductor layer including a channel formation region. At least a part of each of the first oxide semiconductor layer and the second oxide semiconductor layer is located in the groove. In a plan view, the first oxide semiconductor layer and the second oxide semiconductor layer face each other with the second insulating layer sandwiched therebetween in a direction perpendicular to the direction in which the groove extends.

[0025] In the above semiconductor device, it is preferable that the first transistor has first to third conductive layers, the second conductive layer is provided over the first insulating layer, the first conductive layer has a region overlapping with the second conductive layer with the first insulating layer sandwiched therebetween, the first conductive layer has a recessed portion in a region overlapping with the groove, the first oxide semiconductor layer has a region in contact with side surfaces and a bottom of the recessed portion of the first conductive layer and a region in contact with a top surface and a side surface of the second conductive layer, and the third conductive layer is provided above the first oxide semiconductor layer.

[0026] In the above semiconductor device, the second insulating layer preferably has, inside the groove, a region in contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.

[0027] Preferably, the semiconductor device has a fourth conductive layer, the fourth conductive layer being connected to the gate of the first transistor and the gate of the second transistor, and the direction in which the fourth conductive layer extends intersects with the direction in which the trench extends.

[0028] One embodiment of the present invention is a memory device including the above semiconductor device and a capacitor, in which the capacitor is located under the first transistor, and the first conductive layer has a region functioning as one of a pair of electrodes of the capacitor. [Effects of the Invention]

[0029] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, or memory device can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief explanation of the drawings]

[0031] [Figure 1] 1A1 and 1A2 are plan views showing an example of a semiconductor device, and FIGS. 1B to 1E are cross-sectional views showing an example of a semiconductor device. [Figure 2] FIG. 2 is a schematic perspective view showing an example of a semiconductor device. [Figure 3] 3A to 3C are cross-sectional views showing an example of a semiconductor device. [Figure 4] 4A and 4B are cross-sectional views showing an example of a semiconductor device. [Figure 5] 5(A) and 5(B) are cross-sectional views showing an example of a semiconductor device. [Figure 6] 6A and 6B are cross-sectional views showing an example of a semiconductor device. [Figure 7] 7A to 7F are cross-sectional views showing an example of a semiconductor device. [Figure 8] 8A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 8B to 8E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 9] 9A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 9B to 9E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 10] 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 10B to 10E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 11] 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 11B to 11E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 12] Fig. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 12B to Fig. 12E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 13] 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 13B to 13E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 14] 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 14B to 14E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 15] Fig. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 15B to Fig. 15E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 16] 16(A) and 16(B) are cross-sectional views showing an example of a semiconductor device. [Figure 17]Fig. 17(A) is a plan view showing an example of a semiconductor device, and Fig. 17(B) to Fig. 17(D) are cross-sectional views showing an example of the semiconductor device. [Figure 18] Fig. 18(A) is a plan view showing an example of a semiconductor device, and Fig. 18(B) to Fig. 18(E) are cross-sectional views showing an example of the semiconductor device. [Figure 19] FIG. 19 is a cross-sectional view showing an example of a semiconductor device. [Figure 20] Fig. 20(A) is a plan view showing an example of a semiconductor device, and Fig. 20(B) and Fig. 20(C) are cross-sectional views showing an example of a semiconductor device. [Figure 21] 21(A1) and 21(A2) are plan views showing an example of a semiconductor device, and Fig. 21(B) to Fig. 21(E) are cross-sectional views showing an example of a semiconductor device. [Figure 22] 22(A) and 22(B) are cross-sectional views showing an example of a semiconductor device. [Figure 23] Fig. 23(A) is a plan view showing an example of a semiconductor device, and Fig. 23(B) and Fig. 23(C) are cross-sectional views showing an example of a semiconductor device. [Figure 24] FIG. 24 is a schematic perspective view showing an example of a semiconductor device. [Figure 25] 25A to 25C are cross-sectional views showing an example of a semiconductor device. [Figure 26] 26A to 26C are cross-sectional views showing an example of a semiconductor device. [Figure 27] FIG. 27 is a band diagram of an oxide semiconductor layer. [Figure 28] Fig. 28(A) is a plan view showing an example of a memory device, and Fig. 28(B) and Fig. 28(C) are cross-sectional views showing an example of a memory device. [Figure 29] 29A to 29C are plan views showing an example of a memory device, and FIG. 29D is a diagram illustrating an example of a circuit configuration of a memory cell. [Figure 30] FIG. 30 is a schematic perspective view showing an example of a semiconductor device. [Figure 31]31(A) and 31(B) are cross-sectional views showing an example of a memory device. [Figure 32] Fig. 32(A) is a plan view showing an example of a memory device, Fig. 32(B) is a cross-sectional view showing an example of a memory device, and Fig. 32(C) is a diagram explaining an example of the circuit configuration of a memory cell. [Figure 33] FIG. 33 is a schematic perspective view showing an example of a semiconductor device. [Figure 34] Fig. 34(A) is a plan view showing an example of a memory device, and Fig. 34(B) is a diagram illustrating an example of the circuit configuration of a memory cell. [Figure 35] FIG. 35 is a cross-sectional view showing an example of a memory device. [Figure 36] FIG. 36 is a cross-sectional view showing an example of a memory device. [Figure 37] FIG. 37 is a cross-sectional view showing an example of a storage device. [Figure 38] FIG. 38 is a cross-sectional view showing an example of a memory device. [Figure 39] FIG. 39 is a graph showing an example of a hysteresis characteristic. [Figure 40] 40A to 40C are equivalent circuit diagrams of semiconductor devices, and Fig. 40D is a diagram illustrating the Id-Vg characteristics of a transistor. [Figure 41] Fig. 41(A) is a timing chart for explaining the operation of the semiconductor device, and Fig. 41(B) is a circuit diagram for explaining the operation of the semiconductor device. [Figure 42] Fig. 42(A) is a timing chart for explaining the operation of the semiconductor device, and Fig. 42(B) is a circuit diagram for explaining the operation of the semiconductor device. [Figure 43] Fig. 43(A) is a timing chart for explaining the operation of the semiconductor device, and Fig. 43(B) is a circuit diagram for explaining the operation of the semiconductor device. [Figure 44] FIG. 44 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 45] 45A to 45G are diagrams illustrating examples of circuit configurations of memory cells. [Figure 46] 46(A) and 46(B) are perspective views illustrating a configuration example of a semiconductor device. [Figure 47] FIG. 47 is a block diagram illustrating the CPU. [Figure 48] 48(A) and 48(B) are perspective views of the semiconductor device. [Figure 49] 49(A) and 49(B) are perspective views of the semiconductor device. [Figure 50] FIG. 50 is a conceptual diagram illustrating the hierarchy of a storage device. [Figure 51] 51(A) and 51(B) are circuit diagrams of a semiconductor device according to one embodiment of the present invention, and FIG. 51(C) is a diagram showing an example of an electronic component using a semiconductor device according to one embodiment of the present invention. [Figure 52] FIG. 52 is a diagram illustrating an example of an electronic component. [Figure 53] Figures 53(A) to 53(C) are diagrams showing an example of a mainframe computer. Figure 53(D) is a diagram showing an example of space equipment. Figure 53(E) is a diagram showing an example of a storage system applicable to a data center. [Figure 54] 54(A) to 54(F) are diagrams showing examples of electronic devices. [Figure 55] 55(A) to 55(G) are diagrams showing examples of electronic devices. [Figure 56] 56(A) to 56(F) are diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0033] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0034] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0035] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking). Furthermore, the ordinal numbers attached to components in one part of this specification may not match the ordinal numbers attached to the same components in other parts of this specification or in the claims.

[0036] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an IGFET (Insulated Gate Field Effect Transistor) and a TFT (Thin Film Transistor).

[0037] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0038] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) is provided, and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0039] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0040] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V O (also referred to as "interstitial space") may be formed.

[0041] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0042] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic % or more, or 1 atomic % or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic % or less, or 1 atomic % or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0043] In this specification and the like, the term "content" refers to the proportion of a component contained in a film. For example, if an oxide semiconductor layer contains metal elements X, Y, and Z, and the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is A, then the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is A. X , A Y , A Z When the content of metal element X is X / (A X +A Y +A Z ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: X :B Y :B Z When the content of the metal element X is expressed as B X / (B X +B Y +B Z ) can be shown as

[0044] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0045] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0046] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0047] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an electrical potential interaction occurs between A and B, it can still be defined as "A and B are indirectly connected" if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B.

[0048] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film or the like is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0049] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another from a power supply, GND, etc.

[0050] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or the cut-off state). Unless otherwise specified, the off-state refers to the leakage current between the source and the gate when the voltage V gs is the threshold voltage V th (For p-channel transistors, V th This refers to a state of being (higher than)

[0051] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0052] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0053] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0054] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0055] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0056] The groove includes, for example, an opening, a trench, a slit, etc. Furthermore, the region where the groove is formed may be referred to as a groove portion.

[0057] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0058] <Configuration Example 1 of Semiconductor Device> The structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0059] FIG. 1(A1) is a plan view of a semiconductor device having a transistor. FIG. 1(A2) is a plan view showing an example of arranging a plurality of transistors. FIG. 1(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 1(A1). FIG. 1(C) is a cross-sectional view taken along dashed line A3-A4 in FIG. 1(A1). FIG. 1(D) is a cross-sectional view taken along dashed line B1-B2 in FIG. 1(A1). FIG. 1(E) is a cross-sectional view taken along dashed line B3-B4 in FIG. 1(A1). Note that some elements are omitted in the plan views of FIG. 1(A1) and FIG. 1(A2) for clarity. Some elements may also be omitted in the subsequent plan views.

[0060] Fig. 2 is a schematic perspective view of the semiconductor device shown in Fig. 1(A1) to Fig. 1(E). Specifically, Fig. 2 is a schematic perspective view of a semiconductor device including four transistors. In Fig. 2, only the outlines of some components (such as interlayer insulating layers) are shown by dotted lines.

[0061] 1(A1) to 2, the X direction, Y direction, and Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in FIGS. 1(A1) to 1(E) and 2, the directions do not necessarily have to match.

[0062] Moreover, Fig. 3(A) is a cross-sectional view taken along the dashed dotted line A1-A2 shown in Fig. 1(B) Fig. 3(A) corresponds to an example of an enlarged view of Fig. 1(B).

[0063] 1(A1) to 1(E) includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 284 over the insulating layer 280, an insulating layer 285 over the insulating layer 284, and a conductive layer 265 over the transistor 200, the insulating layer 284, and the insulating layer 285. The insulating layer 210, the insulating layer 280, the insulating layer 284, and the insulating layer 285 function as interlayer films.

[0064] [Transistor 200] The transistor 200 includes a conductive layer 220 over an insulating layer 210, conductive layers 240a and 240b over an insulating layer 280, an oxide semiconductor layer 230 over the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0065] Note that Figure 3(A) shows an example in which the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1, the conductive layer 240a has a two-layer structure of a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1, and the conductive layer 240b has a two-layer structure of a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1.

[0066] A cross-sectional view taken along the dashed dotted line C1-C2 in Fig. 1B is shown in Fig. 3B. A cross-sectional view in the XY plane including the conductive layer 240a2 is shown in Fig. 3C.

[0067] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and at least one of the conductive layers 240a and 240b functions as the other of the source electrode and the drain electrode. For example, when the conductive layer 240a and the conductive layer 240b are connected to each other, the conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode. When the conductive layer 240a and the conductive layer 240b are not connected to each other, the conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode.

[0068] The conductive layer 265 has a region in contact with the top surface of the conductive layer 260. Note that the conductive layer 265 may be considered a component of the transistor 200. The conductive layer 265 is provided to extend in the X direction. The conductive layer 265 functions as a gate wiring.

[0069] 1A1 to 1E, the conductive layer 220 is provided to extend in the Y direction. Note that the conductive layer 220 may be provided in an island shape.

[0070] An insulating layer 280 is located on the conductive layer 220 .

[0071] 1(A1) to 1(C), a groove 290 is provided in the insulating layer 280, reaching the conductive layer 220. The groove 290 extends in the Y direction. At this time, the direction in which the conductive layer 265 extends intersects with the direction in which the groove 290 extends.

[0072] 1(B), the conductive layer 220 has a recess in a region overlapping with the groove portion 290. Note that, when the conductive layer 220 has a two-layer structure of conductive layers 220_1 and 220_2 as shown in FIG. 3(A), the bottom surface of the recess corresponds to the bottom surface of the recess of the conductive layer 220_2, and the side surface of the recess corresponds to the side surface of the recess of the conductive layer 220_2. Here, it can be considered that the bottom of the groove portion 290 includes the bottom surface of the recess of the conductive layer 220_2, and the side surface of the groove portion 290 includes the side surface of the recess of the conductive layer 220_2 and the side surface of the insulating layer 280.

[0073] The conductive layer 240a and the conductive layer 240b are provided spaced apart from each other on the insulating layer 280. The conductive layer 240a and the conductive layer 240b are provided extending in the Y direction. The conductive layer 240a and the conductive layer 240b may be provided in an island shape.

[0074] 1B and the like, a side surface of the conductive layer 240a on the groove 290 side coincides or substantially coincides with a side surface of the groove 290. Furthermore, a side surface of the conductive layer 240b on the groove 290 side coincides or substantially coincides with a side surface of the groove 290. With this structure, the conductive layer 240a, the conductive layer 240b, and the groove 290 can be formed at the same time. Furthermore, when the side surfaces of the conductive layer 240a and the insulating layer 280, and the side surfaces of the conductive layer 240b and the insulating layer 280 coincide or substantially coincide with each other in the groove 290, the film thickness distribution of the oxide semiconductor layer 230 and the like provided inside the groove 290 can be made uniform. Furthermore, it is possible to prevent the oxide semiconductor layer 230 and the like from being divided by a step between the conductive layer 240a and the insulating layer 280 and a step between the conductive layer 240b and the insulating layer 280. Here, the side surface of the groove 290 can be considered to include the side surface of the conductive layer 240a on the groove 290 side and the side surface of the conductive layer 240b on the groove 290 side.

[0075] At least some of the components of the transistor 200 are disposed in the groove 290. Specifically, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each disposed such that at least a portion of each of them is located in the groove 290.

[0076] The oxide semiconductor layer 230 is provided so as to cover at least a part of the side surface and at least a part of the bottom surface of the groove 290. Within the groove 290, the oxide semiconductor layer 230 has a region in contact with the side surface of the insulating layer 280, a region in contact with the side surface of the conductive layer 240a facing the groove 290, a region in contact with the side surface of the conductive layer 240b facing the groove 290, and a region in contact with the side surface and bottom surface of the recess of the conductive layer 220. Furthermore, outside the groove 290, the oxide semiconductor layer 230 has a region in contact with the top surface of the conductive layer 240a and a region in contact with the top surface of the conductive layer 240b.

[0077] Furthermore, outside the groove 290, the end of the oxide semiconductor layer 230 is located more inward than the end of the conductive layer 240a and more inward than the end of the conductive layer 240b.

[0078] The insulating layer 250 is provided so as to cover the oxide semiconductor layer 230. The insulating layer 250 is in contact with the upper surface of the oxide semiconductor layer 230. The insulating layer 250 has a recess at a position overlapping the groove 290.

[0079] The conductive layer 260 has a portion located in a recessed portion of the insulating layer 250. The conductive layer 260 has a region in the groove 290 that faces the oxide semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0080] 3(A), the side surfaces of the conductive layer 260, the insulating layer 250, and the oxide semiconductor layer 230 are aligned or substantially aligned outside the groove 290. Furthermore, as shown in FIGS. 3(B) and 3(C), the side surfaces of the conductive layer 260, the insulating layer 250, and the oxide semiconductor layer 230 that are in contact with the insulating layer 284 are aligned or substantially aligned inside the groove 290.

[0081] As described above, the oxide semiconductor layer 230 has a portion located inside the groove 290. In addition, the transistor 200 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located below and the other of the source electrode and the drain electrode (here, at least one of the conductive layer 240a and the conductive layer 240b) is located above, so that current flows vertically. In other words, a channel is formed along the side surface of the groove 290.

[0082] 1A1 to 1E, the source electrode and the drain electrode are located at different heights, and a current flows in the semiconductor layer in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or a vertical channel transistor.

[0083] In the transistor 200 illustrated in FIGS. 1A1 to 1E, a source electrode, a semiconductor layer, and a drain electrode can be provided in a stacked manner, and therefore the occupied area can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0084] A region of the oxide semiconductor layer 230 facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween in the groove 290 and its vicinity function as a channel formation region of the transistor 200. A region of the oxide semiconductor layer 230 near the conductive layer 220 functions as one of a source region and a drain region, and at least one of a region of the oxide semiconductor layer 230 near the conductive layer 240a and a region of the oxide semiconductor layer 230 near the conductive layer 240b functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0085] With the above structure, a channel formation region, a source region, and a drain region can be formed in the groove 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0086] As shown in FIG. 3B, the side surface of the conductive layer 260 provided at the center of the groove 290, which faces the side surface of the groove 290, faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, in a plan view, the two side surfaces of the oxide semiconductor layer 230 on the insulating layer 250 side become channel formation regions. In this case, for example, the channel width of the transistor 200 is determined by the length of the oxide semiconductor layer 230 in the Y direction. It can also be said that the channel width of the transistor 200 is determined by the width of the conductive layer 260 in the Y direction or the width of the insulating layer 250 in the Y direction. In FIG. 3B, the length H230 of the oxide semiconductor layer 230 in the Y direction is shown. The channel width of the transistor 200 can be calculated as "2 × H230".

[0087] Increasing the length H230 of the oxide semiconductor layer 230 in the Y direction increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200, for example, the area of the transistor 200 in a plan view, is roughly determined by the length H230. Reducing the length H230 reduces the area occupied by the transistor 200, allowing for higher integration of the semiconductor device.

[0088] When the groove 290 is formed using photolithography, the width of the groove 290 in the X direction is set by the exposure limit of photolithography. The width of the groove 290 in the X direction is set by the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the groove 290. The width of the groove 290 in the X direction is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.

[0089] 1A1 to 1E, the channel length of the transistor 200 is the distance between the source region and the drain region. For example, the channel length of the transistor 200 can be considered as the distance between the edge of a region where the oxide semiconductor layer 230 and the conductive layer 220 are in contact with each other and the edge of a region where the oxide semiconductor layer 230 and the conductive layer 240a or the conductive layer 240b are in contact with each other in a cross-sectional view. In other words, the channel length of the transistor 200 can be determined by the thickness of the insulating layer 280 over the conductive layer 220. In FIG. 3A, the channel length L of the transistor 200 is indicated by a dashed double-headed arrow.

[0090] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0091] Note that the channel length of the transistor 200 is determined by the film thickness of the insulating layer 280, and therefore the channel length does not affect the area occupied by the transistor 200, for example, the area of the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in forming the groove 290, for example.

[0092] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0093] 1A1 to 1E can be controlled by the thickness of the insulating layer 280. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and a large on-state current can be realized.

[0094] The channel length L of the transistor 200 is preferably smaller than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With this structure, a transistor with good electrical characteristics and high reliability can be realized. Note that the channel width W of the transistor 200 may be equal to or smaller than the channel length L of the transistor 200. With this structure, miniaturization or high integration of a semiconductor device can be achieved.

[0095] As described above, the insulating layer 250 and the conductive layer 260 are provided along the shape of the oxide semiconductor layer 230. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, allowing the gate electric field to be applied to the oxide semiconductor layer 230 approximately uniformly.

[0096] The conductive layer 220_2 shown in FIG. 3A has a recess. By having the recess at a position where the conductive layer 220_2 overlaps with the groove 290, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 in the groove 290 can be lower than the height of the upper surface of the conductive layer 220_2 in contact with the insulating layer 280, relative to the upper surface of the insulating layer 210 in the region overlapping with the conductive layer 220, as compared to a case where the recess is not provided. Here, the height of each surface can be determined based on the surface where the transistor is to be formed. Here, the upper surface of the insulating layer 210 in the region overlapping with the conductive layer 220 is used as the reference. The surface used as the reference is not limited to the surface where the transistor is to be formed. For example, the upper surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0097] The conductive layer 220_2 has a recess, so that the side surface of the conductive layer 220_2 comes into contact with the oxide semiconductor layer 230. This increases the contact area between the conductive layer 220_2 and the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230. Therefore, a decrease in the on-current of the transistor 200 caused by the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed.

[0098] Furthermore, a gate electric field is easily applied to the channel formation region of the oxide semiconductor layer 230, which can improve the electrical characteristics of the transistor 200. Furthermore, a gate electric field is easily applied to a region of the oxide semiconductor layer 230 in contact with the conductive layer 220_2, which can increase the on-state current of the transistor 200. Furthermore, the electrical characteristics of the transistor 200 can be improved regardless of whether the conductive layer 220, the conductive layer 240a, or the conductive layer 240b is used as the drain electrode.

[0099] 3A, the recess of the conductive layer 220_2 preferably has a curved portion. The curved portion of the recess reduces electric field concentration, improves the withstand voltage of the transistor, and suppresses electrostatic breakdown of the transistor. Therefore, the reliability of the semiconductor device can be improved.

[0100] When a recess is provided in the conductive layer 220_2, a recess may be provided in the insulating layer 210 at a position overlapping the groove 290.

[0101] 1B shows an example in which the conductive layer 220 has a recessed portion. Note that the present invention is not limited to this. For example, the upper surface of the conductive layer 220 can be flat.

[0102] 3A, the insulating layer 284 is provided over the insulating layer 280, the conductive layer 240a, and the conductive layer 240b. Outside the groove 290, the insulating layer 284 has regions in contact with the top surfaces and side surfaces of the conductive layer 240a and the conductive layer 240b, a region in contact with the side surface of the oxide semiconductor layer 230, a region in contact with the side surface of the insulating layer 250, and a region in contact with the side surface of the conductive layer 260. As shown in FIGS. 3B and 3C, within the groove 290, the insulating layer 284 has a region in contact with the side surface of the oxide semiconductor layer 230, a region in contact with the side surface of the insulating layer 250, a region in contact with the side surface of the conductive layer 260, and a region in contact with the side surface of the insulating layer 280. The insulating layer 284 has a region that contacts the side surface of the conductive layer 240a on the groove 290 side, and a region that contacts the side surface of the conductive layer 240b on the groove 290 side.

[0103] The insulating layer 284 is preferably an insulating layer having a function of capturing or fixing hydrogen. When the insulating layer 284 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 284, and the hydrogen can be captured or fixed. Furthermore, diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230 can be suppressed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. The insulating layer 284 can be formed using an aluminum oxide film, a hafnium oxide film, a hafnium silicate film, or the like.

[0104] Furthermore, a barrier insulating layer against hydrogen can be used as the insulating layer 284. This can suppress diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 284.

[0105] When a silicon nitride film is used as the insulating layer 284, the silicon nitride film is preferably deposited by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by depositing the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0106] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may be a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0107] An opening 270 is provided in the insulating layer 284 at a position overlapping the groove 290, and the opening 270 reaches the insulating layer 250. The conductive layer 260 is disposed so that at least a portion of the conductive layer 260 is located within the opening 270. The conductive layer 260 contacts the insulating layer 250 within the opening 270.

[0108] The insulating layer 284 also has an opening in the groove 290 in a region that does not overlap with the insulating layer 250. An insulating layer 285 is provided so as to be embedded in the opening.

[0109] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0110] The conductive layer 260 is provided so as to fill the groove 290 and the opening 270. The conductive layer 260 has a portion that faces the oxide semiconductor layer 230 in the groove 290 with the insulating layer 250 interposed therebetween, and a portion that is located within the opening 270.

[0111] The portion of the conductive layer 265 that does not overlap with the groove portion 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240a via the insulating layer 284 and the insulating layer 285. This increases the physical distance between the conductive layer 265 and the conductive layer 240a, thereby reducing the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240a. Note that the conductive layer 240a and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween. Note that the same applies to the positions of the conductive layer 240b and the conductive layer 265.

[0112] That is, the transistor 200 has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0113] 3A shows an example in which the width of the opening 270 is larger than the width of the groove 290. Note that, in a plan view, it is preferable that the overlapping area between the opening 270 and the groove 290 is small. The smaller the overlapping area between the opening 270 and the groove 290, the greater the physical distance between the conductive layer 240a and the conductive layer 260, and the smaller the parasitic capacitance generated between the conductive layer 240a and the conductive layer 260. Similarly, the physical distance between the conductive layer 240b and the conductive layer 260 can be increased, and the smaller the parasitic capacitance generated between the conductive layer 240b and the conductive layer 260.

[0114] In this embodiment, the opening 270 is rectangular in plan view, but the present invention is not limited to this. In plan view, the opening 270 can be, for example, a circle, an approximately circle such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0115] Furthermore, the width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0116] It is preferable that the height of the top surface of the conductive layer 260 is the same as or approximately the same as the height of the top surface of the insulating layer 285 or the insulating layer 284. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 284, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0117] <Materials for semiconductor devices> Materials that can be used in the semiconductor device of this embodiment will be described below. Each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure. In the following, the conductive layer 240a and the conductive layer 240b may be collectively referred to as the conductive layer 240.

[0118] [Oxide semiconductor layer] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0119] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0120] The transistor 200 preferably includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. When a metal oxide functioning as a semiconductor is used for the oxide semiconductor layer 230, the transistor 200 can be referred to as an OS transistor.

[0121] An OS transistor is a transistor in which oxygen vacancies (V O ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. O H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the oxide semiconductor contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities in the channel formation region in the oxide semiconductor be reduced as much as possible. In other words, it is preferable that the carrier concentration in the channel formation region in the oxide semiconductor be reduced and the channel formation region in the oxide semiconductor be made i-type (intrinsic) or substantially i-type.

[0122] On the other hand, the source and drain regions of the OS transistor have more oxygen vacancies than the channel formation region. O The source and drain regions of an OS transistor are preferably n-type regions with a high carrier concentration and low resistance, which are obtained by increasing the carrier concentration or by increasing the concentration of impurities such as hydrogen, nitrogen, or metal elements, compared to the channel formation region.

[0123] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the oxide semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0124] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0125] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0126] Examples of semiconductors made of simple elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0127] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0128] Furthermore, a transistor in which a layer material functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode. Note that the layer material will be described in detail in Embodiment Mode 7.

[0129] [Insulating layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 280, insulating layer 284, insulating layer 285, insulating layer 250, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0130] For example, as transistors become more miniaturized and highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using a high-k material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0131] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0132] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0133] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to 1:1. In the above, lanthanum may be replaced by a lanthanoid. Furthermore, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0134] Examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without element M2. Examples of materials that may exhibit ferroelectricity include materials obtained by adding element M3 to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0135] Furthermore, materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0136] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0137] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0138] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0139] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0140] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, the manifestation of ferroelectricity is presumed to depend on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystalline structure, as this will result in the manifestation of ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having both an amorphous structure and a crystalline structure.

[0141] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in an oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0142] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0143] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Other examples include nitride oxides such as silicon nitride oxide.

[0144] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0145] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0146] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), and oxides containing hafnium and silicon (hafnium silicate). These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0147] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the above metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0148] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0149] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0150] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0151] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH.- Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Furthermore, oxygen when described as corresponding substances refers to at least one of, for example, oxygen atoms and oxygen molecules, etc.

[0152] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0153] Examples of materials for the oxygen barrier insulating layer include oxides containing either or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0154] Since the insulating layer 210 functions as an interlayer film, it is preferable to use the above-mentioned material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0155] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used for the insulating layer 210.

[0156] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 and can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0157] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0158] 3A shows an example in which the insulating layer 210 has a single-layer structure. Note that the insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer over the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0159] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the aforementioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0160] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0161] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least a portion of the layers constituting the insulating layer 280 using a sputtering method, oxygen is supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, and oxygen vacancies and V O H can be reduced.

[0162] Note that the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately according to the design value of the channel length of the transistor 200 .

[0163] FIG. 3A shows an example in which the insulating layer 280 has a single-layer structure. The insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIG. 4B, the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use the above-mentioned material with a low relative dielectric constant for the insulating layer 280_2, and to use barrier insulating layers against oxygen for the insulating layers 280_1 and 280_3. This can suppress oxidation of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, thereby preventing high resistance.

[0164] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 280_1 and the insulating layer 280_3, and a silicon oxide film for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0165] A barrier insulating layer against hydrogen is preferably used for the insulating layer 250. When the insulating layer 250 provided over the oxide semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0166] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer that has a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. As a result, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V O By reducing H, the channel forming region can be made i-type or substantially i-type.

[0167] An insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the oxide semiconductor layer 230, thereby reducing oxygen vacancies in the oxide semiconductor layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0168] 3A shows an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. When the insulating layer 250 is formed using two or more types of films, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0169] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized. For example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer and a silicon nitride film can be used as the second insulating layer.

[0170] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be provided.

[0171] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0172] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, it is possible to suppress a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230.

[0173] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0174] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is in contact with the oxide semiconductor layer 230 and the conductive layer 240. The fourth insulating layer has a barrier property against oxygen, which can prevent oxygen from being released from the oxide semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0175] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0176] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, it is possible to reduce the subthreshold swing value (also referred to as the S value), which is one of the transistor characteristics. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0177] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each layer constituting the insulating layer 250 may have a region with the above-described thickness in at least a portion thereof.

[0178] Typically, the film thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. For example, as shown in FIG. 7A, the insulating layer 250a may be made of aluminum oxide having a film thickness of 1 nm, the insulating layer 250b may be made of silicon oxide having a film thickness of 2 nm, the insulating layer 250d may be made of hafnium oxide, hafnium zirconium oxide, or hafnium zirconium oxide containing yttrium having a film thickness of 2 nm, and the insulating layer 250c may be made of silicon nitride having a film thickness of 1 nm. Here, the insulating layer 250a corresponds to the fourth insulating layer, the insulating layer 250b corresponds to the third insulating layer, the insulating layer 250d corresponds to the first insulating layer, and the insulating layer 250c corresponds to the second insulating layer. In this case, the insulating layer 250 includes an insulating layer 250a on the oxide semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250d on the insulating layer 250b, and an insulating layer 250c on the insulating layer 250d. However, as shown in FIG. 7(A) and other figures, when viewed locally within the groove 290, it can also be considered that the insulating layer 250a is provided inside the oxide semiconductor layer 230, the insulating layer 250b is provided inside the insulating layer 250a, the insulating layer 250d is provided inside the insulating layer 250b, and the insulating layer 250c is provided inside the insulating layer 250d. Note that FIG. 7(A) is an enlarged view corresponding to region A shown in FIG. 3(A).

[0179] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using an ALD process. By forming at least two or more types of insulating films using an ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using an ALD process.

[0180] 7A, the insulating layer 250d may be provided with an insulator capable of capturing or fixing hydrogen. For example, it is preferable to use an oxide containing hafnium as the insulating layer 250d. Examples of oxides containing hafnium that can be used include hafnium oxide, hafnium aluminate, hafnium silicate, hafnium zirconium oxide, and hafnium zirconium oxide containing yttrium. Alternatively, the insulating layer 250d may be made of hafnium zirconium oxide containing a lanthanoid such as lanthanum.

[0181] By providing the insulating layer 250d between the insulating layer 250c and the insulating layer 250b, hydrogen contained in the insulating layer 250b and the like can be more effectively captured or fixed. The channel formation region of the oxide semiconductor layer 230 and the insulating layers 250a and 250d, which have the function of capturing or fixing hydrogen, are provided below the insulating layer 250c, which has the function of suppressing hydrogen diffusion. In the region where hydrogen diffusion from above is blocked by the insulating layer 250c, hydrogen contained in the channel formation region of the oxide semiconductor layer 230 and the like can be captured or fixed by the insulating layers 250a and 250d. This reduces the hydrogen concentration in the oxide semiconductor layer 230, thereby suppressing a negative shift in the initial characteristics of the transistor 200 and achieving normally-off characteristics. Furthermore, negative drift degradation in a +GBT (Gate Bias-Temperature) stress test can be suppressed.

[0182] Note that a structure in which the insulating layers 250a, 250b, and 250d are provided without providing the insulating layer 250c may also be used. In this case, it is preferable to provide the insulating layer 284 on the insulating layer 250 with an insulator (e.g., silicon nitride) having a function of suppressing hydrogen diffusion. With such a structure, the oxide semiconductor layer 230 and the insulating layers 250a and 250d having a function of capturing or fixing hydrogen are formed in a region covered with silicon nitride, which has a high hydrogen barrier property. Therefore, hydrogen contained in a channel formation region of the oxide semiconductor layer 230 can be captured or fixed by the insulating layer 250a and the insulating layer 250d.

[0183] The above-described structure allows the channel formation region to be i-type or substantially i-type, and the source and drain regions to be n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, the above-described structure allows the semiconductor device to have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0184] Furthermore, the hafnium-containing metal oxide used for the insulating layer 250d preferably functions as a high-k material. This configuration allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

[0185] Furthermore, it is preferable that the insulating layer 250d has ferroelectricity. For example, the insulating layer 250d can be made of ferroelectric materials such as hafnium zirconium oxide and hafnium zirconium oxide containing yttrium. The insulating layer 250d may also have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. Note that when a ferroelectric material is used for the insulating layer 250d, the insulating layer 250d does not necessarily need to have the function of capturing or fixing hydrogen. For example, the insulating layer 250d can be made of the above-mentioned materials that can have ferroelectricity.

[0186] In this way, by using a ferroelectric material for the insulating layer 250d, the transistor 200 can function as a Ferroelectric Field Effect Transistor (FeFET). The FeFET functions as a memory element by itself. Therefore, the structure of the memory element can be made smaller than that of a Dynamic Random Access Memory (DRAM) type memory element having a transistor and a capacitor. Therefore, miniaturization and high integration of a memory device including the transistor 200 can be achieved. Furthermore, productivity of a memory device including the transistor 200 can be improved.

[0187] Although the above description has been given of a structure in which the insulating layer 250 has a three-layer structure of insulating layers 250a to 250c or a four-layer structure of insulating layers 250a to 250d, the present invention is not limited to this. The insulating layer 250 can also have a single-layer structure, a two-layer structure, or a stacked structure of five or more layers. The insulating layer 250 can also have a structure including at least one of the insulating layers 250a to 250d. For example, the insulating layer 250 can also have a single-layer structure of the insulating layer 250c. In this case, the insulating layer 250 can also be formed of a single layer of hafnium zirconium oxide. By forming the insulating layer 250 using one, two, or three of the insulating layers 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0188] When the insulating layer 250 has a four-layer structure or a five-layer structure, it can have a stacked structure as shown in Figures 7(B) to 7(F), for example. Figures 7(B) to 7(F) are enlarged views corresponding to region A shown in Figure 3(A).

[0189] 7B shows an example in which the insulating layer 250 has a stacked structure including an insulating layer 250a on the oxide semiconductor layer 230, an insulating layer 250d on the insulating layer 250a, an insulating layer 250b on the insulating layer 250d, and an insulating layer 250c on the insulating layer 250b. That is, the insulating layer 250 shown in FIG. 7B is obtained by swapping the positions of the insulating layer 250b and the insulating layer 250d in the insulating layer 250 shown in FIG. 7A. For example, the insulating layer 250a may be made of aluminum oxide with a thickness of 1 nm, the insulating layer 250d may be made of hafnium zirconium oxide or hafnium zirconium oxide containing yttrium with a thickness of 2 nm, the insulating layer 250b may be made of silicon oxide with a thickness of 2 nm, and the insulating layer 250c may be made of silicon nitride with a thickness of 1 nm. Alternatively, the insulating layer 250d may have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. However, the insulating layers 250a to 250d are not limited to the above structure. The insulating materials described above can be selected as appropriate for the insulating layers 250a to 250d, and the film thicknesses of the insulating layers 250a to 250d can also be selected as appropriate. By stacking the insulating layers 250a to 250d as shown in FIG. 7B, the insulating layer 250a and the insulating layer 250d, which have the function of capturing or fixing hydrogen, are provided adjacent to each other, thereby enabling more effective capture or fixation of hydrogen.

[0190] 7(C), the positions of the insulating layer 250c and the insulating layer 250b can be interchanged. In this case, the insulating layer 250 has a stacked structure including an insulating layer 250a on the oxide semiconductor layer 230, an insulating layer 250d on the insulating layer 250a, an insulating layer 250c on the insulating layer 250d, and an insulating layer 250b on the insulating layer 250c.

[0191] 7B, the insulating layer 250c may be provided in contact with both the upper and lower surfaces of the insulating layer 250b. In this case, as shown in FIG. 7D, the insulating layer 250 has a stacked structure including an insulating layer 250a on the oxide semiconductor layer 230, an insulating layer 250d on the insulating layer 250a, an insulating layer 250c1 on the insulating layer 250d, an insulating layer 250b on the insulating layer 250c1, and an insulating layer 250c2 on the insulating layer 250b. The insulating layers 250c1 and 250c2 may be made of any of the insulators that can be used for the insulating layer 250c. For example, the insulating layers 250c1 and 250c2 may each be made of silicon nitride with a thickness of 1 nm.

[0192] 7(E) shows an example in which the insulating layer 250 has a stacked structure including an insulating layer 250a on the oxide semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250d1 on the insulating layer 250b, an insulating layer 250c on the insulating layer 250d1, and an insulating layer 250d2 on the insulating layer 250c. That is, the insulating layer 250 shown in FIG. 7(E) has a configuration in which insulators that can be used for the insulating layer 250d are provided in contact with the upper and lower surfaces of the insulating layer 250c in the insulating layer 250 shown in FIG. Here, an insulator that can capture or fix hydrogen (e.g., hafnium oxide) can be used for the insulating layer 250d1, and a ferroelectric insulator (e.g., hafnium zirconium oxide or hafnium zirconium oxide containing yttrium) can be used for the insulating layer 250d2. Alternatively, the insulating layer 250d2 may have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. By using a ferroelectric material for the insulating layer 250d2 with such a structure, the transistor 200 can function as an FeFET. Furthermore, since the insulating layer 250d1 can capture or fix hydrogen, the electrical characteristics and reliability of the transistor 200 can be improved.

[0193] Furthermore, when an insulating layer 250d2 is formed and a ferroelectric material such as hafnium zirconium oxide is used for the insulating layer 250d2, a conductive layer 252 can be provided in contact with the lower surface of the insulating layer 250d2, as shown in FIG. 7(F). The conductive layer 252 is preferably made of a material that easily generates polarization in the insulating layer 250d2, such as titanium nitride. In this case, it is also preferable that the lower portion of the conductive layer 260 that is in contact with the insulating layer 250d2 is made of titanium nitride. With this configuration, the insulating layer 250d2 is made ferroelectric, allowing the transistor 200 to function as an FeFET.

[0194] [Conductive layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element or an alloy combining the above-mentioned metal elements. The alloy containing the above-mentioned metal element may be a nitride of the alloy or an oxide of the alloy. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0195] Nitrogen-containing conductive materials such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, and titanium and aluminum nitride are preferred, as are oxygen-containing conductive materials such as ruthenium oxide, strontium and ruthenium oxide, and lanthanum and nickel oxide. Materials containing metal elements such as titanium, tantalum, and ruthenium are preferred because they are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In-Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (ITSO), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0196] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0197] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0198] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0199] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0200] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferably able to maintain its conductivity. For example, ITO, ITSO, In-Zn oxide, or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0201] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0202] The conductive layer 220 shown in FIG. 3A has a two-layer structure including a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 220_2 and a material having higher conductivity than the conductive layer 220_1 for the conductive layer 220_2. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) for the conductive layer 220_2 and tungsten for the conductive layer 220_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 220_1. By using an oxide conductor for the conductive layer 220_2 that is mainly in contact with the oxide semiconductor layer 230, the contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 220, the conductivity of the conductive layer 220 can be increased.

[0203] Note that the conductive layer 220_1 may be formed using a conductive material containing oxygen, and the conductive layer 220_2 may be formed using a material having higher conductivity than the conductive layer 220_1. In this case, a highly conductive material is used for a layer of the conductive layer 220 that is closest to a channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0204] FIG. 3A shows an example in which the conductive layer 220_1 and the conductive layer 220_2 each have a single-layer structure. Note that one or both of the conductive layer 220_1 and the conductive layer 220_2 may have a stacked structure of two or more layers. For example, as shown in FIG. 4A, the conductive layer 220_1 may have a two-layer structure of a conductive layer 220_11 and a conductive layer 220_12 on the conductive layer 220_11. In this case, the conductive layer 220 has a three-layer structure of the conductive layer 220_11, the conductive layer 220_12 on the conductive layer 220_11, and the conductive layer 220_2 on the conductive layer 220_12. For example, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 220_11, a material with high conductivity as the conductive layer 220_12, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220_2. Specifically, it is preferable to use titanium nitride for the conductive layer 220_11, tungsten for the conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) for the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the oxide semiconductor layer 230. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared with tungsten, the oxide conductor has lower contact resistance with the oxide semiconductor layer 230, thereby shortening the current path between the source and drain and increasing the on-current of the transistor 200. With this structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed. Furthermore, when a metal material (tungsten in this example) having higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220_12, the conductivity of the conductive layer 220 can be increased.

[0205] The conductive layer 240a shown in FIG. 3A has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240a2 and a material having higher conductivity than the conductive layer 240a2 for the conductive layer 240a1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) for the conductive layer 240a2 and tungsten for the conductive layer 240a1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240a1. By using an oxide conductor for the conductive layer 240a2, which is mainly in contact with the oxide semiconductor layer 230, the contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layer constituting the conductive layer 240a, the conductivity of the conductive layer 240a can be increased.

[0206] Note that the conductive layer 240a1 may be formed using a conductive material containing oxygen, and the conductive layer 240a2 may be formed using a material having higher conductivity than the conductive layer 240a1. In this case, an oxide conductor is used for the conductive layer 240a that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0207] The conductive layer 260 has a region that functions as a gate electrode. The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0208] Furthermore, the conductive layer 260 is preferably made of a conductive material containing oxygen and the metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer may be captured.

[0209] FIG. 3A shows an example in which the conductive layer 260 has a single-layer structure. Note that the conductive layer 260 can have a stacked structure of two or more layers. For example, as shown in FIG. 4A, the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use a titanium nitride film as the conductive layer 260_1 and a tungsten film as the conductive layer 260_2. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260_1 and a copper film as the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0210] The conductive layer 260 may also have a stacked structure of three or more layers, such as a three-layer structure of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0211] The conductive layer 265 functions as a gate wiring. The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0212] 3A shows an example in which the conductive layer 265 has a single-layer structure. Note that the conductive layer 265 can also have a stacked structure of two or more layers.

[0213] [substrate] Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate, are also available. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having metal nitrides and substrates having metal oxides. Other examples include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0214] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0215] The semiconductor device of one embodiment of the present invention may include an insulating layer over the transistor 200. Specifically, an insulating layer may be provided over the conductive layer 265 and the insulating layer 285.

[0216] The insulating layer is preferably a barrier insulating layer against hydrogen, which can prevent hydrogen from diffusing from above the transistor 200 to the oxide semiconductor layer 230.

[0217] 3(A) shows a configuration in which the side surface of the conductive layer 240 in the groove 290 and the side surface of the insulating layer 280 in the groove 290 are flush (which can also be said to be aligned, approximately aligned, coincident, or substantially coincident), but the present invention is not limited to this. For example, the side surface of the conductive layer 240a in the groove 290 and the side surface of the insulating layer 280 in the groove 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240a in the groove 290 and the inclination of the side surface of the insulating layer 280 in the groove 290 may differ from each other. In this case, part of the side surface of the groove 290 has a tapered shape.

[0218] 5(A) and 5(B) show examples in which at least a portion of the side surface of the groove portion 290 is tapered. Fig. 5(A) shows an example in which the side surface of the conductive layer 240a in the groove portion 290 is tapered, and Fig. 5(B) shows an example in which the side surface of the conductive layer 240a and the side surface of the insulating layer 280 in the groove portion 290 are both tapered.

[0219] By tapering the side surface of the groove 290, the coverage of the oxide semiconductor layer 230, the insulating layer 250, and the like can be improved, and defects such as voids can be reduced. When the side surface of the groove 290 is tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240a facing the groove 290 and the taper angle (angle θ280) of the side surface of the insulating layer 280 in the groove 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, an angle of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of the semiconductor device. Furthermore, an angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because this improves the coverage of the film formed in the groove 290.

[0220] Also, for example, it is preferable that the angle θ240 is smaller than the angle θ280. With this configuration, the coverage of the oxide semiconductor layer 230 and the like on the side surface of the conductive layer 240a on the groove 290 side is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a stacked structure, the inclination of the side surface of each layer in the groove 290 may be different. Similarly, when the conductive layer 240a has a stacked structure, the inclination of the side surface of each layer on the groove 290 side may be different.

[0221] As described above, the oxide semiconductor layer 230 can have a stacked structure of two or more layers.

[0222] 6A shows an example in which the oxide semiconductor layer 230 included in the semiconductor device shown in FIG. 3A has a two-layer structure. The oxide semiconductor layer 230 shown in FIG. 6A can have a two-layer structure including an oxide semiconductor layer 230_1 and an oxide semiconductor layer 230_2 over the oxide semiconductor layer 230_1.

[0223] 6B shows an example in which the oxide semiconductor layer 230 included in the semiconductor device shown in FIG. 3A has a three-layer structure. The oxide semiconductor layer 230 shown in FIG. 6B can have a three-layer structure including an oxide semiconductor layer 230_1, an oxide semiconductor layer 230_2 over the oxide semiconductor layer 230_1, and an oxide semiconductor layer 230_3 over the oxide semiconductor layer 230_2.

[0224] For an oxide semiconductor layer applicable to the oxide semiconductor layers 230_1 to 230_3, the description in Embodiment 2 can be referred to.

[0225] <Example of a method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts that are the same as those described above may be omitted.

[0226] The thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD.

[0227] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0228] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD: Thermal CVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD: Metal CVD) and metal-organic CVD (MOCVD: Metal Organic CVD) depending on the source gas used.

[0229] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0230] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0231] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs a high substrate temperature during film formation and / or performs an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these treatments.

[0232] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings or grooves with high aspect ratios.

[0233] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings or grooves with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0234] Furthermore, the CVD method allows for the deposition of a film with any desired composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows for the deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to when depositing a film using multiple deposition chambers, since no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0235] Furthermore, the ALD method allows for the deposition of films of any desired composition by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, the number of cycles for each precursor can be controlled to deposit films of any desired composition.

[0236] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0237] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0238] There are two typical photolithography methods: One is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask. The other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0239] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. Instead of light used for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0240] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0241] An example of a method for manufacturing the semiconductor device shown in FIGS. 1A1 to 1E will be described with reference to FIGS.

[0242] 8(A) to 8(E), an insulating layer 210 is formed on a substrate (not shown), and a conductive layer 220 is formed on the insulating layer 210. For example, a first conductive film that becomes the conductive layer 220_1 is formed, a second conductive film that becomes the conductive layer 220_2 is formed on the first conductive film, and the first conductive film and the second conductive film are processed, thereby forming the conductive layer 220 having the conductive layer 220_1 and the conductive layer 220_2.

[0243] Next, as shown in FIGS. 8A to 8E, an insulating layer 280 is formed over the conductive layer 220 and the insulating layer 210. Note that after the insulating layer 280 is formed, planarization treatment is preferably performed to planarize the top surface of the insulating layer 280. As the planarization treatment, planarization treatment (also referred to as CMP treatment) using a chemical mechanical polishing (CMP) method is preferable. By performing the planarization treatment on the insulating layer 280, the formation surfaces of the conductive layers 240a and 240b, which have regions that function as wirings, can be flattened, and discontinuities in the conductive layers 240a and 240b can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0244] It is preferable to perform treatment to supply oxygen after the formation of the insulating layer 280. As a result, oxygen is supplied to the insulating layer 280, and oxygen can be supplied from the insulating layer 280 to the oxide semiconductor layer 230 by heat or the like applied after the formation of the oxide semiconductor layer 230.

[0245] Examples of treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 280 by forming an oxide film (preferably a metal oxide film) by sputtering in an oxygen-containing atmosphere. The formed oxide film may be removed immediately or may be left as is. In the case where the formed oxide film is left as is, the oxide film can be used as part of the insulating layer 280. Note that the oxygen-containing atmosphere includes not only oxygen gas (O2) but also atmospheres containing a gas of a compound containing oxygen, such as ozone (O3) or nitrous oxide (NO). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25°C) and equal to or lower than 450°C.

[0246] 8(A) to 8(E), a conductive layer 240f is formed on the insulating layer 280. For example, a first conductive film that will become the conductive layer 240a1 and the conductive layer 240b1 is formed, a second conductive film that will become the conductive layer 240a2 and the conductive layer 240b2 is formed on the first conductive film, and the first conductive film and the second conductive film are processed, thereby forming the conductive layer 240f having the first conductive layer and the second conductive layer.

[0247] Next, as shown in FIGS. 9(A) to 9(E), a groove 290 is formed in the conductive layer 240f and the insulating layer 280. The groove 290 is formed so that at least a portion of the upper surface of the conductive layer 220 is exposed. By forming the groove 290, the conductive layers 240a and 240b can be formed on the conductive layer 240f, spaced apart from each other. At this time, it is preferable that a recess be provided in the conductive layer 220 at a position overlapping the groove 290. It is preferable that by forming the groove 290, the bottom and side surfaces of the recess in the conductive layer 220 are exposed.

[0248] To facilitate microfabrication and reduce the size of the transistor, it is preferable to use anisotropic etching to process a portion of the conductive layer 220, a portion of the insulating layer 280, and a portion of the conductive layer 240f when forming the groove 290. Dry etching is particularly preferable because it is suitable for microfabrication. The groove 290 may be formed under different processing conditions depending on the layer. Note that the slope of the side surface of the conductive layer 220, the insulating layer 280, and the conductive layer 240f within the groove 290 may differ depending on the materials and processing conditions of the conductive layer 220, the insulating layer 280, and the conductive layer 240f.

[0249] Furthermore, by a process of forming the groove 290 or the like, a region containing a halogen element may be provided on at least one of the bottom and side surfaces of the recess of the conductive layer 220, the side surface of the insulating layer 280, and the top and side surface of the conductive layer 240f. Examples of such a region include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine. For example, a halogen element derived from the etching gas used in the dry etching may remain in such a region.

[0250] Subsequently, heat treatment is preferably carried out at a temperature of, for example, 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.

[0251] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing such heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 and the like can be reduced before the formation of the oxide semiconductor layer 230.

[0252] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulating layer 280 as much as possible.

[0253] 10A to 10E, the oxide semiconductor layer 230 is formed so as to cover the groove 290, the conductive layer 240a, the conductive layer 240b, and the insulating layer 280. The oxide semiconductor layer 230 is provided in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220, the side surface of the insulating layer 280, and the top surfaces and side surfaces of the conductive layer 240a and the conductive layer 240b.

[0254] For a method for manufacturing the oxide semiconductor layer 230, refer to the description in Embodiment 2.

[0255] In this embodiment, a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film are formed in this order as the oxide semiconductor layer 230. The first oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230_1 shown in FIG. 6B, the second oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230_2 shown in FIG. 6B, and the third oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230_3 shown in FIG.

[0256] For example, an In-Ga-Zn oxide film is formed as the first oxide semiconductor film by a thermal ALD method, an indium oxide film is formed as the second oxide semiconductor film by a thermal ALD method, and an In-Ga-Zn oxide film is formed as the third oxide semiconductor film by a sputtering method.

[0257] Note that the first oxide semiconductor film and the second oxide semiconductor film are preferably formed successively without exposure to the air. By forming the first oxide semiconductor film and the second oxide semiconductor film successively without exposure to the air, productivity can be improved. Furthermore, impurities (typically moisture) introduced into the interface between the first oxide semiconductor film and the second oxide semiconductor film and the vicinity thereof can be reduced.

[0258] After the second oxide semiconductor film is formed, a process of supplying oxygen to the second oxide semiconductor film may be performed. By this process, oxygen can be supplied to the oxide semiconductor layer 230 by heat or the like applied after the process. Note that the above description can be referred to for details of the process of supplying oxygen.

[0259] Next, it is preferable to carry out a heat treatment. The temperature of the heat treatment is preferably from 100° C. to 650° C., more preferably from 250° C. to 600° C., and even more preferably from 350° C. to 550° C. For details of the heat treatment, see the above description.

[0260] The gas used in the heat treatment is preferably highly purified. When the heat treatment is performed using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 230 as much as possible.

[0261] The heat treatment can reduce impurities such as carbon, hydrogen, or water in the oxide semiconductor layer 230. Reducing the impurities in the film in this manner improves the crystallinity of the oxide semiconductor layer 230, enabling the oxide semiconductor layer 230 to have a denser and more compact structure. This increases the number of crystalline regions in the oxide semiconductor layer 230, reducing in-plane variations in the crystalline regions in the oxide semiconductor layer 230. This reduces in-plane variations in the electrical characteristics of the transistor.

[0262] In addition, when the insulating layer 280 contains oxygen, the heat treatment preferably supplies oxygen from the insulating film containing oxygen to the channel formation region of the oxide semiconductor layer 230. This reduces oxygen vacancies and VO H can be reduced.

[0263] In this manner, excess oxygen may be supplied to the oxide semiconductor layer 230 from the insulating layer 280 in contact with the oxide semiconductor layer 230. The excess oxygen has a function of trapping electrons, which makes it easier for negative charges to be generated. Therefore, the threshold voltage of the transistor is shifted in the positive direction, and a normally-off transistor can be realized.

[0264] Note that microwave plasma treatment may be performed after the second oxide semiconductor film or the third oxide semiconductor film is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 230 may grow. Note that details of the microwave plasma treatment will be described in Embodiment 2.

[0265] 10(A) to 10(E), an insulating layer 250 is formed over the oxide semiconductor layer 230. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230. The insulating layer 250 is formed in a groove 290 with a large aspect ratio. Therefore, the insulating layer 250 is preferably formed using a film formation method with good coverage, and more preferably formed using a CVD method, an ALD method, or the like.

[0266] Microwave plasma treatment is preferably performed after the insulating layer 250 is formed. The microwave plasma treatment can reduce the concentration of impurities such as hydrogen or water in the oxide semiconductor layer 230. Furthermore, a crystalline region of the oxide semiconductor layer 230 might grow.

[0267] When insulating layer 250 has a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer, microwave plasma treatment may be performed after the third insulating layer is formed. Furthermore, microwave plasma treatment may be performed again after the first insulating layer is formed. Thus, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more).

[0268] After the third insulating layer is formed, treatment for supplying oxygen to the third insulating layer may be performed, which allows oxygen to be supplied to the oxide semiconductor layer 230. For details of the treatment for supplying oxygen, see the above description.

[0269] In this embodiment, an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are deposited in this order by ALD to form the insulating layer 250. Also, instead of the hafnium oxide film, a hafnium zirconium oxide film or the like can be deposited.

[0270] 11(A) to 11(E), a sacrificial layer 262 is formed on the insulating layer 250. The sacrificial layer 262 is provided so as to overlap at least a portion of the groove portion 290. A SOC (Spin On Carbon) film and a SOG (Spin On Glass) film are suitable for the sacrificial layer 262. The sacrificial layer 262 preferably has a two-layer structure, for example, an SOC film and an SOG film on the SOC film.

[0271] Providing the sacrificial layer 262 on and in contact with the insulating layer 250 is preferable because damage to the oxide semiconductor layer 230 can be reduced in a manufacturing process of the semiconductor device compared to providing the sacrificial layer 262 on and in contact with the oxide semiconductor layer 230. Note that when the insulating layer 250 has a stacked structure, some layers constituting the insulating layer 250 may be formed before the sacrificial layer 262 is formed, and the remaining layers may be formed after the sacrificial layer 262 is removed.

[0272] 12(A) to 12(E), an etching process is performed using the sacrificial layer 262 as a mask to remove part of the insulating layer 250 and part of the oxide semiconductor layer 230. As a result, island-shaped insulating layers 250 and island-shaped oxide semiconductor layers 230 can be formed.

[0273] The sacrificial layer 262 preferably has a structure in which a large portion thereof overlaps with the top surfaces of the conductive layer 240a and the conductive layer 240b. The etching treatment is performed to leave the oxide semiconductor layer 230 in the region overlapping with the sacrificial layer 262. With this structure, the contact area between the oxide semiconductor layer 230 and the conductive layer 240a can be increased, and the contact resistance between the conductive layer 240a and the oxide semiconductor layer 230 can be reduced. Therefore, a decrease in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 240a and the oxide semiconductor layer 230 can be suppressed. The same applies to the conductive layer 240b and the oxide semiconductor layer 230.

[0274] The sacrificial layer 262 may have a small portion overlapping with the top surfaces of the conductive layer 240a and the conductive layer 240b. A gate electrode (conductive layer 260) is provided in a later step in the region where the sacrificial layer 262 is provided. With this structure, the distance between the conductive layer 240a and the conductive layer 260 provided in a later step can be increased, and parasitic capacitance generated between the conductive layer 240a and the gate electrode can be reduced. The same applies to the conductive layer 240b and the oxide semiconductor layer 230.

[0275] Note that the etching process may result in a decrease in the thickness (thinning) of the conductive layer 240a at a portion that does not overlap with the sacrificial layer 262. Alternatively, the conductive layer 240a may be removed at a portion that does not overlap with the sacrificial layer 262. The same applies to the conductive layer 240b.

[0276] Furthermore, by performing the etching treatment, the thickness of the insulating layer 280 in the portions that do not overlap with the conductive layer 240a and the conductive layer 240b may be reduced (thickness may be reduced).

[0277] Next, as shown in Figures 13(A) to 13(E), an insulating layer 284 is formed to cover the conductive layer 220, the conductive layer 240a, the conductive layer 240b, the insulating layer 280, and the sacrificial layer 262, and an insulating layer 285 is formed on the insulating layer 284.

[0278] By increasing the thickness of the insulating layer 285, the distance between the conductive layer 240a or the conductive layer 240b and the conductive layer 265 to be provided in a later step can be increased, and the parasitic capacitance generated between the conductive layer 240a or the conductive layer 240b and the gate wiring can be reduced.

[0279] For example, the insulating layer 285 is preferably a silicon oxide film formed by sputtering.

[0280] Here, if the insulating layer 284 is not provided, when a silicon oxide film is formed as the insulating layer 285 by a sputtering method, the sacrificial layer 262 is exposed to plasma containing oxygen, and thus part or all of the sacrificial layer 262 may be etched. As described above, depending on the method for forming the insulating layer 285, the shape of the sacrificial layer 262 may be reduced or the sacrificial layer 262 may be lost. For this reason, it is preferable that the insulating layer formed on the sacrificial layer 262 has a stacked structure of the insulating layer 284 and the insulating layer 285, rather than a single layer of the insulating layer 285. This provides the effects of broadening the range of choices for materials for the sacrificial layer 262 and the insulating layer 285, reducing the difficulty of manufacturing a semiconductor device, and so on.

[0281] When an oxide film is used for the insulating layer 284, it is preferable to form it by a method other than sputtering, for example, by ALD. For example, it is preferable to form an aluminum oxide film or a hafnium oxide film as the insulating layer 284 by ALD. Alternatively, it is preferable to use a nitride film (such as a silicon nitride film) for the insulating layer 284. This can prevent the sacrificial layer 262 from being unintentionally processed when the insulating layer 284 and the insulating layer 285 are formed.

[0282] Furthermore, the insulating layer 284 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, so that the insulating layer 284 can be provided with good coverage even on the side surfaces of the sacrificial layer 262, etc.

[0283] 14(A) to 14(E), planarization treatment is performed to expose the upper surface of the sacrificial layer 262 and to planarize the upper surfaces of the sacrificial layer 262, the insulating layer 284, and the insulating layer 285. CMP treatment is suitable as the planarization treatment. In the planarization treatment, at least a portion of the insulating layer 284 and the insulating layer 285 is removed. Furthermore, a portion of the sacrificial layer 262 may be removed.

[0284] 14(A) to 14(E), the sacrificial layer 262 is removed. There is no particular limit to the method for removing the sacrificial layer 262. For example, the sacrificial layer 262 can be removed by dry etching. By removing the sacrificial layer 262, it can be said that the insulating layer 284 has openings 270 at positions overlapping with the groove portions 290 and the insulating layer 250.

[0285] 15(A) to 15(E), a conductive layer 260 is formed on the insulating layer 250. The conductive layer 260 is preferably provided so as to fill the grooves 290 and the openings 270.

[0286] The conductive layer 260 is formed in the groove 290, which has a large aspect ratio. Therefore, the conductive layer 260 is preferably formed using a film formation method with good coverage, and more preferably, the conductive layer 260 is formed using a CVD method, an ALD method, or the like.

[0287] Subsequently, a conductive layer 265 is formed on the conductive layer 260, the insulating layer 284, and the insulating layer 285.

[0288] Through the above steps, the semiconductor devices shown in FIGS. 1A1 to 1E can be manufactured.

[0289] As described above, when etching is performed using the sacrificial layer 262 as a mask, the thickness of the conductive layer 240a in a portion that does not overlap with the sacrificial layer 262 may be thin (the film may be reduced). A semiconductor device manufactured in this manner is shown in FIG. 16A. Even in the structure shown in FIG. 16A, the contact area between the conductive layer 240a and the oxide semiconductor layer 230 and the contact area between the conductive layer 240b and the oxide semiconductor layer 230 are not reduced.

[0290] 16B shows a semiconductor device manufactured in the case where a portion of the conductive layer 240a that does not overlap with the sacrificial layer 262 is removed by performing etching treatment using the sacrificial layer 262 as a mask. In the structure shown in FIG. 16B, the contact area between the conductive layer 240a and the oxide semiconductor layer 230 and the contact area between the conductive layer 240b and the oxide semiconductor layer 230 are not reduced.

[0291] In the above-described example of the method for manufacturing a semiconductor device, the sacrificial layer 262 is formed over the insulating layer 250; however, the present invention is not limited to this. For example, a semiconductor device can be manufactured by forming the sacrificial layer 262 before forming the insulating layer 250 and then forming the insulating layer 250 after removing the sacrificial layer 262 (see FIGS. 14A to 14E). In other words, a semiconductor device can be manufactured by forming the sacrificial layer 262 over the oxide semiconductor layer 230.

[0292] Another structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 17A to 17D. FIG. 17A is a plan view of a semiconductor device including a transistor. FIG. 17B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 17A. FIG. 17C is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 17A. FIG. 17D shows a cross-sectional view taken along dashed-dotted line C1-C2 in FIG. 17B. Note that FIG. 1C can be referred to for a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 17A, and FIG. 1E can be referred to for a cross-sectional view taken along dashed-dotted line B3-B4 in FIG. 17A.

[0293] The semiconductor device shown in Figures 17(A) to 17(C) includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 284 on the insulating layer 280, an insulating layer 285 on the insulating layer 284, and a conductive layer 265 on the insulating layer 284.

[0294] The transistor 200 shown in Figures 17(A) to 17(C) includes a conductive layer 220 over an insulating layer 210, a conductive layer 240a and a conductive layer 240b over an insulating layer 280, an oxide semiconductor layer 230 over the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0295] The semiconductor device shown in FIGS. 17A to 17C is different from the semiconductor device shown in FIGS. 1A to 1E in that the insulating layer 250 has a portion in contact with the conductive layer 265.

[0296] In the transistor 200 illustrated in FIGS. 17A to 17C, the stacked structure from the conductive layer 220 to the oxide semiconductor layer 230 is similar to that of the above-described transistor 200, and therefore detailed description thereof will be omitted.

[0297] The insulating layer 250 contacts the oxide semiconductor layer 230 and the insulating layer 284 within the opening 270. The insulating layer 250 has a region that contacts at least a part of the lower surface of the conductive layer 265. Furthermore, the portion of the insulating layer 250 that is disposed within the opening 270 is provided to reflect the shape of the opening 270. Specifically, the insulating layer 250 is provided so as to contact the side surface of the opening 270 (the side surface of the insulating layer 284). Then, the conductive layer 260 is provided so as to fill at least a part of the recess in the insulating layer 250 that reflects the shape of the opening 270.

[0298] 17A to 17C, the insulating layer 250 is located between the insulating layer 284 and the conductive layer 260 in the opening 270, and therefore the overlapping area between the conductive layer 240a and the conductive layer 260 is small in a plan view. Therefore, the physical distance between the conductive layer 240a and the conductive layer 260 can be increased compared to the transistor 200 shown in FIGS. 1A1 to 1E. Therefore, the parasitic capacitance generated between the conductive layer 240a and the conductive layer 260 can be reduced. The same applies to the conductive layer 240b and the conductive layer 260.

[0299] 17A to 17C has a structure in which the parasitic capacitance between the gate electrode and the other of the source electrode and the drain electrode and the parasitic capacitance between the gate wiring and the other of the source electrode and the drain electrode are reduced, thereby improving the frequency characteristics of a circuit using the transistor.

[0300] 17(D), in the groove portion 290, the conductive layer 260 is surrounded by the insulating layer 250. That is, the conductive layer 260 is not in contact with the insulating layer 284. Therefore, when an oxide insulating layer is used for the insulating layer 284, the insulating layer 284 can prevent the conductive layer 260 from being oxidized, and can prevent the resistance from increasing.

[0301] Furthermore, when the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2, a semiconductor device can also be manufactured by forming a sacrificial layer 262 over the conductive layer 260_1, removing the sacrificial layer 262, and then forming the conductive layer 260_2 (see Figures 14(A) to 14(E)).

[0302] In the above-described example of the method for manufacturing a semiconductor device, the oxide semiconductor layer 230 is formed after the formation of the groove 290. However, the present invention is not limited to this. For example, a semiconductor device can be manufactured by forming the insulating layer 225 before forming the oxide semiconductor layer 230.

[0303] Another structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 18A to 18E. FIG. 18A is a plan view of a semiconductor device including a transistor. FIG. 18B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 18A. FIG. 18C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 18A. Note that FIG. 1D can be referred to for a cross-sectional view taken along dashed dotted line B1-B2 in FIG. 18A, and FIG. 1E can be referred to for a cross-sectional view taken along dashed dotted line B3-B4 in FIG. 18A.

[0304] Also, a cross-sectional view taken along the dashed dotted line C1-C2 in FIG. 18(B) is shown in FIG. 18(D), and a cross-sectional view in the XY plane including the conductive layer 240a2 is shown in FIG. 18(E).

[0305] The semiconductor device shown in Figures 18(A) to 18(C) includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 284 on the insulating layer 280, an insulating layer 285 on the insulating layer 284, and a conductive layer 265 on the insulating layer 284.

[0306] The transistor 200 shown in Figures 18(A) to 18(C) includes a conductive layer 220 over the insulating layer 210, a conductive layer 240a and a conductive layer 240b over the insulating layer 280, an insulating layer 225, an oxide semiconductor layer 230 over the conductive layer 220, the insulating layer 225, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0307] The semiconductor device shown in FIGS. 18A to 18C differs from the semiconductor device shown in FIGS. 1A to 1E in that an insulating layer 225 is provided in a groove 290.

[0308] In the transistor 200 shown in Figures 18(A) to 18(C), the stacked structure from the conductive layer 220 to the conductive layer 240 and the stacked structure from the oxide semiconductor layer 230 to the conductive layer 260 are similar to those of the above-described transistor 200, and therefore detailed description thereof will be omitted.

[0309] The insulating layer 225 is provided along at least a portion of the side surface of the groove 290. In FIGS. 18(B) to 18(E), the insulating layer 225 is provided so as to cover the side surface of the groove 290. Specifically, the insulating layer 225 has a region in contact with the side surface of the insulating layer 280 within the groove 290. The insulating layer 225 also has a region in contact with the side surface of the conductive layer 240a on the groove 290 side, a region in contact with the side surface of the conductive layer 240b on the groove 290 side, and a region in contact with the conductive layer 220. The insulating layer 225 can also be called a sidewall, a sidewall insulating layer, a side surface protection layer, or the like.

[0310] The insulating layer 225 can be made of an insulating material that can be used for the insulating layer 250 .

[0311] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor layer. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor layer.

[0312] Therefore, a barrier insulating layer against hydrogen is preferably used for the insulating layer 225 provided outside the oxide semiconductor layer 230. This can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, the insulating layer 225 is preferably a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film, and more preferably a silicon nitride film.

[0313] Note that a silicon nitride film also has a barrier property against oxygen. Therefore, using a silicon nitride film for the insulating layer 225 can prevent oxygen from being extracted from the oxide semiconductor layer 230 and oxygen vacancies from being formed in the oxide semiconductor layer 230. Furthermore, using a silicon nitride film for the insulating layer 225 can prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Therefore, the channel formation region of the oxide semiconductor layer 230 can be prevented from becoming oxygen-excessive, thereby improving the reliability of the transistor 200. Furthermore, the insulating layer 225 may be in contact with the side surface of the conductive layer 240a in the groove 290. In this case, using a silicon nitride film for the insulating layer 225 can prevent the side surface of the conductive layer 240a in the groove 290 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0314] The silicon nitride film of the insulating layer 225 is preferably formed using the PEALD method, which can improve the coverage of the insulating layer 225 on the side surfaces of the grooves 290 and form an insulating layer 225 with a uniform thickness.

[0315] 18B shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers.

[0316] 19, the conductive layer 220_2 preferably has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the groove 290, the second recess is provided in the conductive layer 220_2, and then when processing the insulating layer 225, the first recess is provided in the conductive layer 220_2. Therefore, in FIG. 19, the side surface of the second recess is aligned with the side surface of the insulating layer 280 in the groove 290, and the side surface of the first recess is aligned with the side surface of the insulating layer 225 on the oxide semiconductor layer 230 side. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0317] 19 , the insulating layer 225 contacts the bottom and side surfaces of the recesses (specifically, second recesses) of the conductive layer 220, and also contacts the side surfaces of the insulating layer 280, the side surfaces of the conductive layers 240a, and the side surfaces of the conductive layers 240b within the grooves 290. The oxide semiconductor layer 230 contacts the bottom and side surfaces of the recesses (specifically, first recesses) of the conductive layer 220 and the side surfaces of the insulating layer 225 within the grooves 290. The insulating layer 250 is located inside the oxide semiconductor layer 230 within the grooves 290, and the conductive layer 260 is located inside the insulating layer 250 within the grooves 290.

[0318] The conductive layer 220_2 has the first recess and the second recess, so that the side surface of the conductive layer 220_2 contacts with the oxide semiconductor layer 230. This increases the contact area between the conductive layer 220_2 and the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230. Therefore, a decrease in the on-current of the transistor 200 caused by the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed.

[0319] In the above-described example of the method for manufacturing a semiconductor device, the groove 290 is formed after the conductive layer 240f is formed, but the present invention is not limited to this. For example, a semiconductor device can be manufactured by forming the groove 290 after forming the first conductive film and the second conductive film that will become the conductive layer 240f.

[0320] Another structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 20A to 20C. FIG. 20A is a plan view of a semiconductor device including a transistor. Note that FIG. 20A shows a plan view of a region including two transistors adjacent in the X direction. FIG. 20B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 20A. FIG. 20C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 20A. Note that FIG. 1D can be referred to for the cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 20A, and FIG. 1E can be referred to for the cross-sectional view taken along dashed-dotted line B3-B4 in FIG. 20A.

[0321] 20(A) to 20(C) includes an insulating layer 210 over a substrate (not shown), a transistor 200[1] and a transistor 200[2] over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 284 over the insulating layer 280, an insulating layer 285 over the insulating layer 284, and a conductive layer 265 over the insulating layer 284. The transistor 200[1] and the transistor 200[2] are adjacent to each other in the X direction.

[0322] The transistor 200[1] includes a conductive layer 220[1] on an insulating layer 210, a conductive layer 240[1] and a conductive layer 240[2] on an insulating layer 280, an oxide semiconductor layer 230 on the conductive layer 220[1], the conductive layer 240[1], and the conductive layer 240[2], an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0323] The transistor 200[2] includes a conductive layer 220[2] on an insulating layer 210, a conductive layer 240[2] and a conductive layer 240[3] on an insulating layer 280, an oxide semiconductor layer 230 on the conductive layer 220[2], the conductive layer 240[2], and the conductive layer 240[3], an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0324] 20A to 20C differ from the semiconductor device illustrated in FIGS. 1A1 to 1E in that the transistors 200 adjacent in the X direction share the conductive layer 240. Specifically, the transistors 200[1] and 200[2] share the conductive layer 240[2]. The transistors 200 adjacent in the X direction share the conductive layer 240, which enables the area occupied by the semiconductor device to be reduced.

[0325] For materials, structures, and the like applicable to the conductive layers 220[1] and 220[2], the description of the conductive layer 220 can be referred to. For materials, structures, and the like applicable to the conductive layers 240[1] to 240[3], the description of the conductive layer 240 can be referred to.

[0326] <Configuration Example 2 of Semiconductor Device> 21(A1) to 22(B), a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device exemplified in <Configuration Example 1 of Semiconductor Device> will be described. Note that a description of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their description may be omitted.

[0327] FIG. 21(A1) is a plan view of a semiconductor device having a transistor. FIG. 21(A2) is a plan view showing an example of arranging a plurality of transistors. FIG. 21(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 21(A1). FIG. 21(C) is a cross-sectional view taken along dashed line A3-A4 in FIG. 21(A1). FIG. 21(D) is a cross-sectional view taken along dashed line B1-B2 in FIG. 21(A1). FIG. 21(E) is a cross-sectional view taken along dashed line B3-B4 in FIG. 21(A1). Note that some elements are omitted from the plan views of FIG. 21(A1) and FIG. 21(A2) for clarity.

[0328] The semiconductor device shown in Figures 21(A1) to 21(E) includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 284 on the insulating layer 280, an insulating layer 285 on the insulating layer 284, and a conductive layer 265 on the transistor 200A, the insulating layer 284, and the insulating layer 285.

[0329] [Transistor 200A] The transistor 200A includes conductive layers 240a and 240b on an insulating layer 280, an oxide semiconductor layer 230 on the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0330] A transistor 200A illustrated in FIGS. 21A1 to 21E differs from the transistor 200 illustrated in FIGS. 1A1 to 1E in that the conductive layer 220 is not included.

[0331] In the transistor 200A, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 240a functions as one of a source electrode and a drain electrode, and the conductive layer 240b functions as the other of the source electrode and the drain electrode.

[0332] A region of the oxide semiconductor layer 230 facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween in the groove 290 and its vicinity functions as a channel formation region of the transistor 200A. A region of the oxide semiconductor layer 230 near the conductive layer 240a functions as one of the source region and the drain region, and a region of the oxide semiconductor layer 230 near the conductive layer 240b functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0333] Here, a cross-sectional view taken along the dashed dotted line A1-A2 shown in Fig. 21(B) is shown in Fig. 22(A), which corresponds to an example of an enlarged view of Fig. 21(B).

[0334] As shown in FIG. 22A, the channel length of the transistor 200A is the distance between the source region and the drain region. For example, the channel length of the transistor 200A can be considered as the sum of the height of the side of the trench 290 on the conductive layer 240a side, the width of the bottom, and the height of the side of the trench 290 on the conductive layer 240b side. In other words, the channel length of the transistor 200A is determined by the depth of the trench in the insulating layer 280. In FIG. 22A, the channel length L of the transistor 200A is indicated by a dashed double-headed arrow.

[0335] Compared to a planar transistor, the deeper the groove 290 of the transistor 200A, the longer the channel length of the transistor 200A. In other words, the channel length can be increased without changing the area occupied by the transistor 200A. Increasing the channel length of the transistor can reduce variations in the threshold voltage of the transistor.

[0336] Furthermore, when manufacturing a transistor 200A having the same channel length as a vertical transistor, the depth of the groove in the insulating layer 280 can be made shallower than in the vertical transistor. That is, the depth of the groove 290 can be made shallower. Therefore, compared to the transistor 200, a finer groove 290 can be formed with a higher yield.

[0337] The channel width of the transistor 200A is equal to or substantially equal to the length in the Y direction of the oxide semiconductor layer 230 (length H230 shown in FIG. 3B). It can also be said that the channel width of the transistor 200A is equal to or substantially equal to the width in the Y direction of the conductive layer 260 or the width in the Y direction of the insulating layer 250.

[0338] Note that a structure similar to that of the transistor 200 can also be applied to the transistor 200A. For example, as shown in FIG. 22B, the transistors 200A adjacent in the X direction can share a conductive layer 240. Specifically, the transistors 200A[1] and 200A[2] adjacent in the X direction share the conductive layer 240[2]. This can reduce the area occupied by the semiconductor device.

[0339] The above is a description of an example of the configuration of a semiconductor device including the transistor 200A.

[0340] In the semiconductor device exemplified in the above-mentioned <Configuration Example 1 of Semiconductor Device>, one transistor is provided in the region where the groove 290 and the gate wiring overlap. However, the present invention is not limited to this. For example, the semiconductor device can have two transistors in the region where the groove 290 and the gate wiring overlap.

[0341] <Configuration Example 3 of Semiconductor Device> 23(A) to 26(C), a description will be given of a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device exemplified in <Configuration Example 1 of Semiconductor Device>. Note that a description of the same parts as those described above will be omitted, and only the differences will be described in detail. Furthermore, even if the position or shape of components differs, if the functions are the same, the same reference numerals will be used and the description may be omitted.

[0342] Fig. 23(A) is a plan view of a semiconductor device having two transistors. Fig. 23(B) is a cross-sectional view taken along dashed line A1-A2 in Fig. 23(A). Fig. 23(C) is a cross-sectional view taken along dashed line A3-A4 in Fig. 23(A).

[0343] Fig. 24 is a schematic perspective view of the semiconductor device shown in Fig. 23(A) to Fig. 23(C). Specifically, Fig. 24 is a schematic perspective view of a semiconductor device including four transistors. In Fig. 24, only the outlines of some components (such as interlayer insulating layers) are shown by dotted lines.

[0344] 23A to 23C includes an insulating layer 210 over a substrate (not shown), a transistor 200Ba and a transistor 200Bb over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 284 over the insulating layer 280, an insulating layer 285 over the insulating layer 284, and conductive layers 265 over the transistor 200Ba, the transistor 200Bb, the insulating layer 284, and the insulating layer 285. Note that hereinafter, the transistor 200Ba and the transistor 200Bb may be collectively referred to as the transistor 200B.

[0345] The semiconductor device shown in Figures 23(A) to 23(C) differs from the semiconductor device shown in Figures 1(A1) to 1(E) in that the transistor 200Ba and the transistor 200Bb are included in the region where the conductive layer 265 and the groove 290 overlap.

[0346] [Transistor 200B] The transistor 200Ba includes a conductive layer 220a on an insulating layer 210, a conductive layer 240a on an insulating layer 280, an oxide semiconductor layer 230a on the conductive layer 220a and the conductive layer 240a, an insulating layer 250a on the oxide semiconductor layer 230a, and a conductive layer 260a on the insulating layer 250a. The insulating layer 284 has an opening 270a that reaches the insulating layer 250a at a position overlapping with the groove 290. The conductive layer 260a is disposed so that at least a portion thereof is located within the opening 270a.

[0347] Similarly, the transistor 200Bb has a conductive layer 220b on the insulating layer 210, a conductive layer 240b on the insulating layer 280, an oxide semiconductor layer 230b on the conductive layer 220b and the conductive layer 240b, an insulating layer 250b on the oxide semiconductor layer 230b, and a conductive layer 260b on the insulating layer 250b. The insulating layer 284 has an opening 270b that reaches the insulating layer 250b at a position overlapping the groove 290. The conductive layer 260b is arranged so that at least a portion of it is located within the opening 270b.

[0348] The transistors 200Ba and 200Bb are configured to be symmetrical with respect to the perpendicular bisector of the dashed-dotted line A1-A2 in a plan view. Therefore, the configuration of the transistor 200Bb can be understood by referring to the description of the configuration of the transistor 200Ba, replacing the transistor 200Ba, conductive layer 220a, conductive layer 240a, oxide semiconductor layer 230a, insulating layer 250a, and conductive layer 260a with the transistor 200Bb, conductive layer 220b, conductive layer 240b, oxide semiconductor layer 230b, insulating layer 250b, and conductive layer 260b, respectively, and making appropriate modifications. The following description will mainly focus on the transistor 200Ba.

[0349] In the transistor 200Ba, the oxide semiconductor layer 230a functions as a semiconductor layer, the conductive layer 260a functions as a gate electrode, the insulating layer 250a functions as a gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source electrode and the drain electrode. The conductive layer 265 has a region that functions as a gate wiring.

[0350] Here, a cross-sectional view taken along the dashed dotted line C1-C2 shown in Figure 23(B) is shown in Figure 25(A), and a cross-sectional view in the XY plane including the conductive layer 240a2 is shown in Figure 25(B).

[0351] 25A and 25B, the insulating layer 284 is provided inside the groove 290 so as to be in contact with the side surface of the oxide semiconductor layer 230a. By using an insulating layer having a function of capturing or fixing hydrogen as the insulating layer 284, it is possible to suppress diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230a and further to capture or fix hydrogen contained in the oxide semiconductor layer 230a. Therefore, the hydrogen concentration in the oxide semiconductor layer 230a can be reduced.

[0352] By providing two transistors in a region where the groove 290 and the conductive layer 265 overlap, the area occupied by the semiconductor device can be reduced, and miniaturization or high integration of the semiconductor device can be achieved.

[0353] The transistor 200Ba and the transistor 200Bb can be formed, for example, by providing two sacrificial layers 262 at a distance from each other in the region of the groove 290 where the conductive layer 265 is to be disposed.

[0354] Note that a structure similar to at least one of the transistors 200 and 200A can also be applied to the transistor 200B. For example, as shown in FIG. 25C, the transistors 200Ba and 200Bb adjacent to each other in the X direction can share a conductive layer 240. Specifically, the transistors 200Bb[1] and 200Ba[2] share the conductive layer 240[2]. This can reduce the area occupied by the semiconductor device. Note that at least some of the components of the transistors 200Ba[1] and 200Bb[1] are disposed in the groove 290[1], and at least some of the components of the transistors 200Ba[2] and 200Bb[2] are disposed in the groove 290[2].

[0355] 25C illustrates a configuration in which the transistor 200Bb[1] and the transistor 200Ba[2] are connected to the same conductive layer 265, but the present invention is not limited to this. For example, the transistor 200Bb[1] and the transistor 200Ba[2] can be connected to different conductive layers 265.

[0356] In addition, FIG. 25(A) shows a configuration in which the oxide semiconductor layer 230a and the oxide semiconductor layer 230b adjacent in the X direction within one groove portion 290 are provided so as to face each other with the insulating layer 285 interposed therebetween, but the present invention is not limited to this.

[0357] For example, as shown in FIG. 26(A), the oxide semiconductor layer 230a and the oxide semiconductor layer 230b located in one groove 290 may be arranged to be shifted in the Y direction or may be arranged alternately. Specifically, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b can be arranged so that they do not face each other in a plan view. With this configuration, the width of the groove 290 in the X direction can be reduced, thereby enabling miniaturization and high integration of the semiconductor device. FIG. 26(B) shows a configuration in which the width of the groove 290 in the X direction is smaller than the configuration shown in FIG. 26(A).

[0358] 26(C), the conductive layer 260a, the insulating layer 250a, and the oxide semiconductor layer 230a may be formed so that their side surfaces are inclined with respect to the X direction in a plan view. With such a configuration, the width of the groove 290 in the X direction can be reduced, which may lead to miniaturization and high integration of the semiconductor device. Alternatively, with the configuration shown in FIG. 26(C), foreign matter such as dust and particles that may be generated during the manufacturing process can be easily removed from the groove 290 by a cleaning process. Therefore, a semiconductor device with a high yield can be provided.

[0359] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0360] (Embodiment 2) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. As the oxide semiconductor layer of one embodiment of the present invention, a layer containing a metal oxide can be used as a single layer or a stacked layer. Note that in an oxide semiconductor layer with a stacked structure, it may be difficult to identify boundaries between stacked films, as will be described later.

[0361] [Metal oxides] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0362] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), indium aluminum zinc oxide (In-Al-Zn oxide, IAZO), and Examples of usable metal oxides include indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable metal oxides include gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as the metal oxide according to one embodiment of the present invention.

[0363] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0364] The metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0365] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0366] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0367] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0368] A structural example of an oxide semiconductor layer capable of increasing the field-effect mobility of a transistor will be described. For example, it is preferable to use indium oxide or a stacked structure of indium oxide and IGZO. Specifically, it is preferable that the oxide semiconductor layer has indium oxide and IGZO on the indium oxide. It is also preferable to use IGZO containing nitrogen as the oxide semiconductor layer. For example, IGZO containing nitrogen can be formed by performing NO plasma treatment during or after film formation. It is also preferable to use at least one of indium oxide, In-Ga oxide, In-Zn oxide, and IGZTO as the oxide semiconductor layer.

[0369] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0370] The oxide semiconductor layer of one embodiment of the present invention preferably contains a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0371] Note that the crystallinity of the metal oxide contained in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0372] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of these techniques may be used for the analysis.

[0373] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being aligned in the ab-plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0374] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface or surface of the oxide semiconductor layer on which the oxide semiconductor layer is formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° to 110°), more preferably within 90°±15° (75° to 105°), more preferably within 90°±10° (80° to 100°), and even more preferably within 90°±5° (85° to 95°) relative to the surface on which the oxide semiconductor layer is formed.

[0375] When the oxide semiconductor layer has a CAAC structure, bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms are observed in a cross section of the oxide semiconductor layer observed using a TEM image. Specifically, bright spots are observed to be arranged in layers parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed.

[0376] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0377] Furthermore, an FFT pattern obtained by performing a fast Fourier transform (FFT) on a TEM image reflects reciprocal lattice spatial information similar to that of an electron diffraction pattern.

[0378] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT pattern is created by performing FFT processing on each region in the cross-sectional TEM image. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots with high brightness and located at approximately equal distances from the center is defined as the crystal axis direction. Regions whose crystal axis direction calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0379] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the ab plane, and the oxide semiconductor layer has crystallinity.

[0380] [Metal oxide composition] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content for the oxide semiconductor layer, the on-state current of a transistor can be increased and frequency characteristics can be improved. For example, indium oxide is preferably used for the oxide semiconductor layer.

[0381] Furthermore, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, it becomes a metal oxide with high crystallinity, for example, a metal oxide having a CAAC structure. For example, an In-Zn oxide can be used for the oxide semiconductor layer. Specifically, a metal oxide having a composition of In:Zn=1:1 (atomic ratio) or a composition close to that, an In:Zn=2:1 (atomic ratio) or a composition close to that, or an In:Zn=4:1 (atomic ratio) or a composition close to that can be used. Note that a composition close to that includes a range of ±30% of the desired atomic ratio.

[0382] Furthermore, the metal oxide according to one embodiment of the present invention can contain an element M. When the metal oxide contains the element M, oxygen vacancies can be prevented from being formed in the metal oxide. Therefore, the reliability of a transistor including an oxide semiconductor layer can be improved.

[0383] For example, the oxide semiconductor layer can be made of an In-Zn oxide containing a trace amount of element M. Specifically, metal oxides having an atomic ratio of In:Ga:Zn=4:0.1:1 or a similar ratio, an atomic ratio of In:Ga:Zn=2:0.1:1 or a similar ratio, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a similar ratio can be used. Furthermore, metal oxides having an atomic ratio of In:Sn:Zn=4:0.1:1 or a similar ratio, an atomic ratio of In:Sn:Zn=2:0.1:1 or a similar ratio, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a similar ratio can be used.

[0384] The oxide semiconductor layer can be made of an In-Zn oxide containing an element M. Specifically, metal oxides having a composition of In:M:Zn=1:1:1 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:1.2 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:0.5 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:2 (atomic ratio) or a composition close thereto, In:M:Zn=4:2:3 (atomic ratio) or a composition close thereto, In:M:Zn=1:3:2 (atomic ratio) or a composition close thereto, or In:M:Zn=1:3:4 (atomic ratio) or a composition close thereto can be used.

[0385] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0386] Furthermore, when depositing a metal oxide film containing multiple metal elements, such as In-Ga-Zn oxide, using the ALD method, the ratio of the number of cycles of precursors containing each metal element can be adjusted to match the target composition. For example, to deposit an In-Ga-Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of depositing an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of depositing a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of depositing a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element may not match the atomic ratio of each metal element in the deposited metal oxide film.

[0387] The composition of the metal oxide used in the oxide semiconductor layer can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0388] The oxide semiconductor layer of one embodiment of the present invention may have a stacked structure of two or more layers. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the second layer preferably has a different composition from the first layer. When the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer preferably has a different composition from the first layer and the third layer. Note that the first layer can have the same composition as the third layer. Alternatively, the first layer and the third layer can have different compositions.

[0389] The first to third layers may each be made of the metal oxides described above.

[0390] The second layer can be made of, for example, indium oxide, In-Zn oxide, or In-Zn oxide containing a trace amount of element M. Specifically, metal oxides having an In:Zn=1:1 atomic ratio or a similar composition, an In:Zn=2:1 atomic ratio or a similar composition, or an In:Zn=4:1 atomic ratio or a similar composition can be used. For example, metal oxides having an In:Ga:Zn=4:0.1:1 atomic ratio or a similar composition, an In:Ga:Zn=2:0.1:1 atomic ratio or a similar composition, or an In:Ga:Zn=1:0.1:1 atomic ratio or a similar composition can be used. Alternatively, for example, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a similar composition, an atomic ratio of In:Sn:Zn=2:0.1:1 or a similar composition, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a similar composition can be used. Increasing the In content in the second layer can increase the on-current and improve the frequency characteristics.

[0391] The conduction band minimums of the first and third layers are preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of the first and third layers is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first and third layers, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0392] By sandwiching the second layer between the first and third layers, carriers trapped at and near the interface of the second layer can be reduced. Furthermore, the channel can be moved away from the surface of the gate insulating layer, reducing the effects of surface scattering. This allows for a buried channel transistor in which the channel is moved away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the effects of interface states that may form on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving transistor reliability.

[0393] For example, a band diagram of the oxide semiconductor layer 230 including the oxide semiconductor layers 230_1 to 230_3 and their vicinity shown in FIG. 21B is as shown in FIG. 27. In FIG. 27, the vertical axis represents energy, and the horizontal axis represents the film thickness direction at the center of the channel formation region. FIG. 27 shows the valence band maximum (VBM) and the conduction band minimum (CBM) of each of the oxide semiconductor layer 230_1, the oxide semiconductor layer 230_2, the oxide semiconductor layer 230_3, the insulating layer 280, and the insulating layer 250 in a state where no voltage is applied between the gate and the source. In FIG. 27, the vacuum level Vac is indicated by a dashed line.

[0394] Note that the energy of the upper end of the valence band and the energy of the lower end of the conduction band vary depending on the constituent elements and compositions of the oxide semiconductor layer 230_1, the oxide semiconductor layer 230_2, the oxide semiconductor layer 230_3, the insulating layer 280, and the insulating layer 250. Therefore, the relationship between the energies of the upper ends of the valence bands and the energy of the lower ends of the conduction bands will be mainly described using the band diagram in FIG.

[0395] Depending on the constituent elements and compositions of the oxide semiconductor layers 230_1 to 230_3, the oxide semiconductor layer 230_2 may be sandwiched between the oxide semiconductor layers 230_1 and 230_3, whose conduction band minimums are closer to the vacuum level than the oxide semiconductor layer 230_2, as shown in FIG. 27 . This structure can realize a buried channel. That is, this structure forms a path through which more current (electrons are illustrated as carriers in FIG. 27 ) flows in the oxide semiconductor layer 230_2. Therefore, an increase in on-state current or improvement in reliability can be achieved.

[0396] When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide with a higher Ga content than the second layer. Specifically, the first and third layers can be made of a metal oxide with an In:Ga:Zn=1:1:1 atomic ratio or a composition similar thereto, a metal oxide with an In:Ga:Zn=1:3:2 atomic ratio or a composition similar thereto, or a metal oxide with an In:Ga:Zn=1:3:4 atomic ratio or a composition similar thereto. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can sometimes position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

[0397] Furthermore, increasing the Ga content in the first layer and the third layer can improve the barrier properties of the first layer and the third layer against hydrogen. Therefore, hydrogen diffusion from below the first layer or above the third layer to the second layer can be suppressed. Furthermore, increasing the Ga content in the first layer and the third layer can reduce impurities such as hydrogen and water contained in the oxide semiconductor layer due to heat or the like applied after the formation of the oxide semiconductor layer. Note that the same effect may be achieved by using a metal oxide with a lower In content than the second layer for the first layer and the third layer.

[0398] For example, the third layer preferably uses a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, or an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition, and the third layer contains indium and gallium.

[0399] Furthermore, increasing the Ga content in the first and third layers can improve the oxygen barrier properties of the first and third layers. This can suppress oxygen release from the second layer where the channel is formed, and can suppress the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This can improve the electrical characteristics of the transistor.

[0400] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can be made higher than that of the second layer in some cases. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, and the transistor can be made normally off. As a result, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0401] The band gap of metal oxides can be evaluated using optical analysis with a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Analysis can also be performed by combining multiple of these techniques. The electron affinity or conduction band minimum can be determined from the ionization potential, which is the energy difference between the vacuum level and the valence band maximum, and the band gap. The ionization potential can be evaluated using, for example, ultraviolet photoelectron spectroscopy (UPS).

[0402] The first layer and the third layer may be made of a metal oxide having a higher In content than the second layer. Alternatively, one of the first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

[0403] The first, second, and third layers may each be formed by stacking multiple layers having the compositions described above. For example, the first layer may be formed by stacking a metal oxide having a high In content on a metal oxide having a high Ga content. For example, the third layer may be formed by stacking a metal oxide having a high Ga content on a metal oxide having a high In content.

[0404] [Method for producing oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by a sputtering method, a CVD method, a vacuum evaporation method, an MBE method, a PLD method, an ALD method, or the like.

[0405] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method.

[0406] The oxide semiconductor layer of one embodiment of the present invention can have a two-layer structure including a first layer and a second layer over the first layer. In the case where the oxide semiconductor layer has a two-layer structure, the oxide semiconductor layer can be manufactured by forming the first layer over a surface to be formed by a first film formation method and then forming the second layer thereover by a second film formation method.

[0407] The first deposition method is preferably a deposition method that causes less damage to the surface on which the oxide semiconductor layer is formed than the second deposition method. This can prevent a mixed layer from being formed at the interface between the oxide semiconductor layer and the layer on which the oxide semiconductor layer is formed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, which may improve the crystallinity of the oxide semiconductor layer.

[0408] Examples of the first film formation method include the ALD method, the CVD method, and the MBE method. Examples of the CVD method include the PECVD method, the thermal CVD method, the photo-CVD method, and the MOCVD method. The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed. Also, a wet method can be used as the first film formation method. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed. Examples of the wet method include the spray coating method.

[0409] The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, a sputtering method is suitable as the second film formation method.

[0410] When a metal oxide is formed on a surface to be formed using the second film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0411] For example, when a sputtering method is used as the second film formation method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or by energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed by the second film formation method using a silicon-containing insulating layer, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the inclusion of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide. Furthermore, there is a concern that using an oxide semiconductor layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when heat treatment, which will be described later, is performed, it is difficult to improve the crystallinity of the alloyed region.

[0412] Therefore, as described above, by forming a metal oxide by the first film formation method before forming a metal oxide by the second film formation method, it is possible to prevent impurities from being mixed into the oxide semiconductor layer. Furthermore, it is possible to prevent alloying with the layer on which the metal oxide is to be formed. Therefore, it is possible to improve the initial characteristics and reliability of the transistor. Furthermore, it is possible to further increase the crystallinity of the oxide semiconductor layer.

[0413] A mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the components contained in the first layer and the components contained in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, when the indium content of the second layer is higher than that of the first layer, the indium content of the mixed layer is equal to or greater than that of the first layer and equal to or less than that of the second layer.

[0414] The ALD method is suitable as the first film formation method because it can suppress damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with better coverage than the sputtering method, and using the ALD method as the film formation method for the first layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well coated on steps, openings, grooves, etc. with high aspect ratios.

[0415] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure. The crystallinity of the first layer may be increased by forming a second layer having high crystallinity on the first layer having low crystallinity, or by performing heat treatment after forming the second layer, with the second layer acting as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0416] The layer serving as the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that, depending on the transistor structure, the layer may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the surface to be formed does not need to be crystalline. Note that, when the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor layer.

[0417] The first layer is preferably formed by ALD. Here, a method for forming an In-M-Zn oxide as the first layer by ALD will be described.

[0418] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, desorbing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0419] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0420] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer of combined element M and oxygen. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer of combined zinc and oxygen.

[0421] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on a layer that is a surface to be formed by the ALD method.

[0422] When an oxide semiconductor layer is formed by the ALD method, ozone (O), oxygen (O), water (H2O), etc. can be used as an oxidizing agent. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as an oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0423] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge excess reactant, reaction products, etc. from the reaction chamber.

[0424] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0425] The second layer is preferably formed by sputtering.

[0426] In-M-Zn oxide can be used as a target for sputtering. When forming metal oxides by sputtering, oxygen or a mixture of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film can be increased.

[0427] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed may be.

[0428] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and less than 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, for film formation. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0429] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, it may be possible to form a metal oxide with high crystallinity. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0430] By using the above-described manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the alloyed region formed at the interface between the layer to be formed and the metal oxide can be made thin enough to be unobservable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0431] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0432] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is to be formed as the depth direction. Next, in the profile of the quantitative values of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer but is not the main component of the layer that will become the surface on which the layer is to be formed (In if the first layer contains In) becomes half-maximum is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is to be formed but is not the main component of the first layer (e.g., Si) becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is to be formed. From the above, the thickness of the alloyed region can be calculated.

[0433] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm.

[0434] For example, when SIMS analysis is performed on an oxide semiconductor layer formed on a silicon oxide film, which is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0 × 10 20 atoms / cm 3 The distance between the depth at which the thickness decreases and the interface is defined as thickness t. The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0435] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0436] By reducing the alloyed region, the CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region from more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer.

[0437] The CAAC structure near the surface to be formed can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of an oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed are confirmed near the surface to be formed.

[0438] Furthermore, the oxide semiconductor layer of one embodiment of the present invention can have a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer.

[0439] When the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can be manufactured by forming a first layer on a surface to be formed by a first film formation method, forming a second layer by a second film formation method, and then forming a third layer by the first film formation method.

[0440] Even when the first and third layers of the oxide semiconductor layer have compositions that make it difficult to form a CAAC structure when they are formed as single layers, crystal growth occurs using the second layer as a nucleus, so that the entire oxide semiconductor layer including the first and third layers can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of each of the first and third layers and the second layer.

[0441] In particular, even when the first layer and the third layer have a high In content, the oxide semiconductor layer can have suitable crystallinity for a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by having a CAAC structure with high crystallinity.

[0442] The first and third layers may be made of metal oxides having the same composition as the second layer, which may increase the likelihood of CAAC formation after heat treatment.

[0443] Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0444] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0445] When an oxide semiconductor layer is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor layer, may be in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is on.

[0446] The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during or after the deposition of the second layer. The crystallinity of the third layer may be increased by heat treatment during or after the deposition of the third layer. The heat treatment has the function of assisting in increasing the crystallinity.

[0447] As described above, in the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (the first and third layers in this case) can be increased by using the second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower metal oxides can be grown in a solid phase using the second layer as a nucleus or seed to form an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a deposition method, i.e., a CAAC film in this case, can be referred to as an axial growth CAAC (AG CAAC).

[0448] In the oxide semiconductor layer, it is preferable that a region having a CAAC structure is widely present throughout the layer. The region having a CAAC structure in the first layer is crystallinely connected to a region having a CAAC structure in the second layer. The region having a CAAC structure in the third layer is crystallinely connected to a region having a CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Also, the boundary between the second layer and the third layer may not be observed. The oxide semiconductor layer may be expressed as a single layer with no clearly observable interface. The oxide semiconductor layer may be expressed as a single layer.

[0449] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or approximately parallel to the surface on which the CAAC structure is formed are observed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or approximately parallel to the normal direction of the surface on which the CAAC structure is formed or the surface of the oxide semiconductor layer.

[0450] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0451] When the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can also be manufactured by forming a first layer on a surface to be formed by a first film formation method, then forming a second layer by the first film formation method, and then forming a third layer by the second film formation method.

[0452] As mentioned above, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. However, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, by using a metal oxide with a high In content in the second layer adjacent to the third layer, it is possible to form crystals that reflect the crystal orientation of the third layer.

[0453] Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to form crystals that reflect the orientation of the crystals of the third layer. In this case, for example, when a cross-section of the oxide semiconductor layer is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface on which the oxide semiconductor layer is formed are observed in the second layer.

[0454] The crystal structure of the second layer is not particularly limited as long as the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0455] In the above structure, typically, the first layer is a layer containing gallium oxide or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition similar thereto; the second layer is a layer containing indium oxide or a metal oxide containing a trace amount of the aforementioned element M; and the third layer is a layer containing a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition similar thereto. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition similar thereto, the indium content in the first layer is lower than the gallium content. Furthermore, the indium content in the second layer is higher than the indium content in the third layer.

[0456] When the first layer and the second layer are formed using the first film formation method, it is preferable to form the first layer and the second layer successively without exposing them to the atmosphere. By forming the first layer and the second layer successively without exposing them to the atmosphere, productivity can be improved. Furthermore, impurities (typically moisture, etc.) that are introduced into the interface between the first layer and the second layer and its vicinity can be reduced.

[0457] One or more of the first to third layers may have a stack of layers with different compositions. For example, the first layer may be formed by forming a layer containing a metal oxide with a high Ga content by the first film formation method, and then forming a layer containing a metal oxide with a higher In content than the first layer by the first film formation method.

[0458] After forming the layer by the first film formation method, it is preferable to perform microwave plasma treatment.

[0459] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device with a power source that generates high-density plasma using microwaves. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0460] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor layer 230 can be reduced. Examples of impurities include hydrogen and carbon. Although the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0461] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa to 1000 Pa, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and can be 400°C to 450°C.

[0462] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0463] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( 3 P j )), singlet oxygen (O( 1 D2)), and oxygen ions (O2 +) can take three states. Note that oxygen ions effectively act to reduce the hydrogen concentration in oxide films by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions of a low oxygen flow rate ratio and low pressure, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge and etching the oxide film. Therefore, for example, the oxygen flow rate ratio (O2 / (O2+Ar)) in microwave plasma processing is preferably greater than 0% and less than 10%, preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0464] The shorter the processing time of the microwave plasma treatment, the more the oxidation of the conductive layer 220 or the conductive layer 240, etc. can be suppressed. Also, the productivity increases. Therefore, for example, the processing time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0465] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. O By splitting H into oxygen vacancies and hydrogen, the impurity hydrogen can be removed from the oxide semiconductor layer. O H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0466] Furthermore, microwave plasma treatment can improve the crystallinity of a layer formed using the first film formation method. Here, the principle of how microwave plasma treatment improves the crystallinity of an oxide semiconductor will be described. First, active species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the active species and oxygen in the oxide semiconductor layer. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable that the active species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, thereby improving the crystallinity of the oxide semiconductor.

[0467] On the other hand, a part of oxygen present in the oxide semiconductor layer before the microwave plasma treatment reacts with hydrogen in the oxide semiconductor layer, in other words, the reaction "2H + O → H2O↑" occurs, and the hydrogen can be removed as H2O (also referred to as dehydration or dehydrogenation). H2O is one of the factors that hinder improvement of crystallinity, so it is preferable to remove it from the oxide semiconductor layer. Removing hydrogen in the oxide semiconductor layer as H2O and reducing the hydrogen concentration in the oxide semiconductor layer can also promote improvement of crystallinity. Note that the hydrogen concentration in the oxide semiconductor layer can be further reduced by increasing the temperature during the microwave plasma treatment.

[0468] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0469] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0470] The improved crystallinity of the layer formed by the first film formation method can further improve the crystallinity of a layer formed thereover, thereby increasing the crystallinity of the entire oxide semiconductor layer.

[0471] Oxygen supplied to the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0472] After the oxide semiconductor layer is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer. The heat treatment here is not limited to heat treatment. For example, heat applied during a manufacturing process may be used.

[0473] The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. It can typically be 400°C±25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer formed using the second film formation method with the third layer formed using the first film formation method.

[0474] The heating device used for heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device performs heat treatment using high-temperature gas.

[0475] The heat treatment step may enhance the crystallinity of the region having the CAAC structure in the third layer formed by the first deposition method. Furthermore, if the region is formed only below the third layer after ALD deposition, the heat treatment step may cause the region to expand upward. That is, the heat treatment may result in the region having the CAAC structure being formed throughout the entire third layer.

[0476] Furthermore, it is preferable that the heat treatment step converts at least a portion of the first or second layer formed using the first film formation method into a CAAC. It is expected that the CAAC conversion is facilitated by the mixed layer formed in the first or second layer during the formation of the layer formed using the second film formation method, which acts as a nucleus or seed. It is preferable that the region in the first or second layer that is converted into a CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface on which it is formed.

[0477] Furthermore, because the CAAC process is performed from the top to the bottom of the first or second layer, the CAAC process can be performed up to the vicinity of the layer, regardless of the material or crystallinity of the layer on which the CAAC process is performed. For example, even if the layer has an amorphous structure, the crystallinity of the first or second layer can be increased. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer on which the CAAC process is performed has an amorphous structure.

[0478] As described above, by performing microwave plasma treatment and / or heat treatment, the crystallinity of the entire oxide semiconductor layer can be improved. Furthermore, impurities in the oxide semiconductor layer can be reduced. Crystal growth can be performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, thereby further improving the crystallinity.

[0479] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0480] Note that one or both of the microwave plasma treatment and the heat treatment may be performed directly on the oxide semiconductor layer, or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0481] Before forming the first layer or after forming the first layer or the second layer by the first film formation method, a treatment for supplying oxygen to the first layer or the second layer may be performed, whereby oxygen can be supplied to the oxide semiconductor layer by heat or the like applied after the treatment.

[0482] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the first or second layer formed by the first film formation method by forming an oxide film (preferably a metal oxide film) by sputtering in an oxygen-containing atmosphere. The formed oxide film may be removed immediately or left as is. When the formed oxide film is left as is, the oxide film can be used as a layer (second or third layer) provided on the first or second layer. Note that the oxygen-containing atmosphere includes not only oxygen gas (O2) but also an atmosphere containing a gas of an oxygen-containing compound such as ozone (O3) or nitrous oxide (NO). The substrate temperature during the plasma treatment is set to be from room temperature (25°C) to 450°C.

[0483] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor layer, the boundaries between the stacked films of the first to third layers may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0484] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness, as compared with an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0485] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods in a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0486] The oxide semiconductor layer of one embodiment of the present invention can be formed by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, the oxide semiconductor layer of one embodiment of the present invention can be formed without using the second film formation method. For example, by performing one or both of microwave plasma treatment and heat treatment after forming a first layer by the first film formation method, the crystallinity of the first layer can be increased. Therefore, the crystallinity of a second layer formed on the first layer by the first film formation method can be increased using the first layer as a nucleus or seed. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the second layer, the crystallinity of the oxide semiconductor layer can be increased. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0487] As described above, even in a manufacturing method that does not use the second film formation method, the first layer formed by the first film formation method can be used as a nucleus or seed to perform solid-phase growth of the oxide semiconductor thereover, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method can also be called an AG CAAC.

[0488] When the oxide semiconductor layer has a stacked structure of two or more layers, it can also be formed by forming a metal oxide using one film formation method. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the oxide semiconductor layer can be formed by, for example, forming the first layer and the second layer in this order by a sputtering method. Sputtering has a higher film formation rate than ALD, and therefore can improve productivity. Furthermore, when the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the first layer to the third layer can also be formed by a sputtering method. Furthermore, some of the first layer to the third layer can also be formed by an ALD method. For example, one or both of the second layer and the third layer may be formed by an ALD method.

[0489] [Oxide semiconductor layer of transistor] The oxide semiconductor layer of this embodiment can be used as a semiconductor layer of a transistor.

[0490] The oxide semiconductor layer in this embodiment can be used as the oxide semiconductor layer 230 or the like included in each transistor described in Embodiment 1. The layer on which the oxide semiconductor layer is formed corresponds to the insulating layer 280 or the like described in Embodiment 1. For example, the first layer can be used as the oxide semiconductor layer 230_1, the second layer can be used as the oxide semiconductor layer 230_2, and the third layer can be used as the oxide semiconductor layer 230_3.

[0491] The oxide semiconductor layer of this embodiment preferably has a CAAC structure, in which metal atoms are arranged in layers in a direction parallel or substantially parallel to a surface on which the oxide semiconductor layer is formed.

[0492] It is believed that an oxide semiconductor layer with a CAAC structure exhibits current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. In other words, it is believed that in an oxide semiconductor layer with a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

[0493] In the semiconductor device described in the above embodiment, the oxide semiconductor layer 230 has metal atoms arranged in a layered manner parallel or substantially parallel to the surface on which the oxide semiconductor layer 230 is formed. It can also be expressed as the ab plane of the CAAC structure being parallel or substantially parallel to the surface on which the oxide semiconductor layer 230 is formed. With this structure, the ab plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0494] When the oxide semiconductor layer of this embodiment is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor layer is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, further preferably 5 nm to 12 nm, and further preferably 5 nm to 10 nm. Furthermore, the average thickness of the oxide semiconductor layer in a channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0495] The thickness of the first layer is, for example, preferably 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm. The thickness of the first layer is further preferably 0.5 nm to 3 nm.

[0496] The first layer preferably has a region with a thickness of 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, or more preferably 0.5 nm to 3 nm, and even more preferably 0.5 nm to 2 nm.

[0497] The thickness of the second layer is preferably, for example, 200 nm or less. When the second layer is lamellar, the thickness is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

[0498] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer exist discretely.

[0499] For the preferred range of the thickness of the third layer, see the description of the thickness of the first layer.

[0500] [Impurities in the oxide semiconductor layer] Here, the influence of each impurity in the oxide semiconductor layer will be described.

[0501] As described in the above embodiment, in a transistor including an oxide semiconductor in a semiconductor layer, oxygen vacancies (V O The presence of impurities such as hydrogen, carbon, and nitrogen can cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor layer is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor layer, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen.

[0502] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3Less than 1×10, more preferably 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 or less, more preferably 1 × 10 18 atoms / cm 3 The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 or less, more preferably 1 × 10 18 atoms / cm 3 The following applies.

[0503] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Less than or equal to 5 × 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm3 The following applies.

[0504] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than 1×10 17 atoms / cm 3 Less than.

[0505] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0506] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0507] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0508] (Embodiment 3) In this embodiment, a memory device of one embodiment of the present invention will be described with reference to Figures 28A to 38. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0509] <Storage device configuration example 1> The structure of a memory device having a transistor and a capacitor will be described with reference to Figures 28A to 30. Figure 28A is a plan view of a memory device having memory cells. Figure 28B is a cross-sectional view taken along dashed line A1-A2 in Figure 28A, and Figure 28C is a cross-sectional view taken along dashed line A3-A4 in Figure 28A.

[0510] 28A to 28C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, an insulating layer 280 over the insulating layer 180, an insulating layer 284 over the insulating layer 280, an insulating layer 285 over the insulating layer 284, and a conductive layer 265 over the insulating layer 284, the insulating layer 285, and the memory cell 150. The insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 284, and the insulating layer 285 function as interlayer films. The conductive layer 110 functions as a wiring.

[0511] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0512] The capacitor 100 includes a conductive layer 115 on a conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 220 on the insulating layer 130.

[0513] In the capacitor 100, the conductive layer 220 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0514] As shown in Figures 28(B) and 28(C), an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. The conductive layer 115 is disposed in the opening 190. The conductive layer 115 has a region in contact with the top surface of the conductive layer 110 within the opening 190 and a region in contact with the side surface of the insulating layer 180 within the opening 190. The insulating layer 130 is disposed so as to be located within the opening 190. The conductive layer 220 is disposed so that at least a portion thereof is located within the opening 190. As shown in Figure 28(B), the conductive layer 220 is preferably disposed so as to fill the opening 190. The films disposed inside the opening 190 are preferably formed using an ALD method, which improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220 are preferably formed using an ALD method.

[0515] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0516] As shown in Fig. 28(A), opening 190 is preferably circular in plan view. By making opening 190 circular, the processing precision when forming opening 190 can be improved, and opening 190 of a fine size can be formed. Note that in this specification and the like, "circular" is not limited to a perfect circle. Also, in the present embodiment, an example has been shown in which opening 190 is circular in plan view, but the present invention is not limited to this. Shapes that can be applied to opening 190 are the same as the shapes that can be applied to opening 270 described above.

[0517] 28B shows an example in which the side surface of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0518] A conductive layer 115 is provided along the side surface of the opening 190 and the upper surface of the conductive layer 110. An insulating layer 130 is provided on the conductive layer 115. A conductive layer 220 is provided on the insulating layer 130 so as to fill the opening 190. A capacitor 100 having such a configuration may be called a trench capacitor. However, the configuration of the capacitor 100 is not limited to this, and for example, a pillar-type capacitor, a parallel-plate capacitor, or the like may also be used.

[0519] The insulating layer 140 can be made of an insulating material that can be used for the insulating layer 210 .

[0520] Since the insulating layer 180 functions as an interlayer film, it is preferable that it has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 180, an insulating layer containing a material with a low dielectric constant can be used in a single layer or a stacked layer. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. Note that the insulating layer 180 can use an insulating material that can be used for the insulating layer 280, or the like.

[0521] An insulating layer 280 is disposed on the capacitive element 100 .

[0522] 28B illustrates components of the transistor 200. The detailed description of the transistor 200 is omitted here because the description in Embodiment 1 (FIG. 1B, etc.) can be referred to. The transistor included in the memory cell 150 is not limited to the transistor 200, and any of the transistors exemplified in Embodiment 1 can be applied.

[0523] As shown in FIG. 28B, the transistor 200 is provided so as to overlap with the capacitor 100. A groove 290 in which part of the structure of the transistor 200 is provided has a region that overlaps with an opening 190 in which part of the structure of the capacitor 100 is provided. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of the memory cells 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the storage device. In other words, the storage device can be highly integrated.

[0524] FIG. 28B illustrates an example in which the width of the opening 190 in the X direction is equal to or approximately equal to the width of the groove 290. The relationship in size between the width of the opening 190 and the width of the groove 290 is not particularly limited. The width of the opening 190 can be smaller than the width of the groove 290. By making the width of the opening 190 in the X direction smaller than the width of the groove 290, the required alignment accuracy between the end of the conductive layer 220 and the opening 190 can be reduced, making it relatively easy to process the conductive layer 220. This also enables miniaturization or high integration of the memory device. Furthermore, the width of the opening 190 can be larger than the width of the groove 290 in the X direction. By making the width of the opening 190 larger than the width of the groove 290 in the X direction, the capacitance of the capacitor 100 can be increased. For example, as shown in FIG. 28B, the relationship in size between the two widths in a semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.

[0525] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0526] 29(A) is a plan view showing an example of a memory device in which a plurality of memory cells 150 shown in FIG. 28(A) to FIG. 28(C) are arranged. FIG. 29(A) shows an example in which 2×2 memory cells 150 are arranged in the X and Y directions. Note that the X direction shown in FIG. 29(A) is parallel to the A1-A2 direction shown in FIG. 1(A1), and the Y direction shown in FIG. 29(A) is parallel to the B1-B2 direction shown in FIG. 1(A1).

[0527] 29(A) is shown in Fig. 30. Fig. 30 is a perspective schematic diagram of a memory device including four memory cells. In Fig. 30, only the outlines of some components (such as interlayer insulating layers) are shown by dotted lines.

[0528] As described in Embodiment 1, when the conductive layer 240a and the conductive layer 240b are connected to each other, the conductive layer 240a and the conductive layer 240b can function as the other of the source electrode and the drain electrode of the transistor 200 included in the memory cell 150.

[0529] Methods for connecting the conductive layer 240a and the conductive layer 240b include using one conductive layer as the conductive layer 240a and the conductive layer 240b, connecting the conductive layer 240a and the conductive layer 240b via a conductive layer, and applying the same potential to the conductive layer 240a and the conductive layer 240b.

[0530] FIG. 29B shows a structure example in which one conductive layer is used as the conductive layer 240a and the conductive layer 240b. As shown in FIG. 29B, a groove can be provided in the one conductive layer in a region where the memory cell 150 is disposed. With such a structure, the conductive layer in the region where the memory cell 150 is disposed can function as the conductive layer 240a or the conductive layer 240b. The groove can be formed so as to overlap with the groove 290 described in Embodiment 1, for example. This allows the groove to be formed without adding any additional steps.

[0531] 29C shows a structure example in which the conductive layer 240a and the conductive layer 240b are connected through a conductive layer. As shown in FIG. 29C, the conductive layer 240a and the conductive layer 240b can be connected through a conductive layer 241a, a conductive layer 241b, and a conductive layer 242. The conductive layer 241a and the conductive layer 241b function as plugs, and the conductive layer 242 functions as a wiring.

[0532] FIG. 29D shows a circuit diagram in the case where the conductive layer 240a and the conductive layer 240b are connected in the memory device shown in FIG.

[0533] One of the source and drain of the transistor 200 is connected to one of a pair of electrodes of the capacitor 100, the other of the source and drain of the transistor 200 is connected to a wiring BIL, and a gate of the transistor 200 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor 100 is connected to a wiring CAL.

[0534] Here, the wiring BIL corresponds to the conductive layer 240a and the conductive layer 240b, the wiring WOL corresponds to the conductive layer 265, and the wiring CAL corresponds to the conductive layer 110.

[0535] As shown in FIG. 29(A), it is preferable that the conductive layer 265 is provided to extend in the X direction, and the conductive layers 240a and 240b are provided to extend in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided to intersect with each other. Also, in FIG. 29(A), the wiring CAL is provided parallel to the wiring WOL. However, the present invention is not limited to this. For example, the wiring CAL may be provided parallel to the wiring BIL.

[0536] The memory cells will be described in detail in a later embodiment.

[0537] [Capacitor element 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 220. The conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0538] The conductive layer 110 functions as wiring CAL and can be provided in, for example, a strip shape. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, Y direction, or Z direction).

[0539] The conductive layer 110 has a recess in the area that overlaps the opening 190 .

[0540] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. For example, a conductive material with high conductivity, such as tungsten, can be used for the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0541] The conductive layer 115 has a region 101 with rounded corners in the recess of the conductive layer 110. This makes it possible to suppress electric field concentration in the insulating layer 130 near the region 101, compared to when the region 101 is a right angle or an acute angle (having a corner). Furthermore, the end 103 of the conductive layer 115 is located at a position lower in height from the reference plane than the top surface of the insulating layer 180. This makes it possible to suppress electric field concentration in the insulating layer 130 near the end 103, compared to when the end 103 is located on the insulating layer 180. As described above, suppressing electric field concentration in the insulating layer 130 suppresses dielectric breakdown of the insulating layer 130, thereby providing a highly reliable memory device. The reference plane can be the top surface of the substrate, the top surface of the insulating layer 140, or the like.

[0542] The conductive layer 115 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. The conductive layer 115 is preferably formed as a single layer or a stacked layer using a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can prevent the conductive layer 115 from being oxidized. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can prevent the conductive layer 115 from being oxidized.

[0543] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to be in contact with the upper surface of the conductive layer 115. In other words, the insulating layer 130 is preferably structured to cover the side edges of the conductive layer 115. This can prevent the conductive layer 115 and the conductive layer 220 from shorting out.

[0544] It is preferable to use a material with a high relative dielectric constant for the insulating layer 130. By using a material with a high relative dielectric constant for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently ensured.

[0545] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of materials with a high dielectric constant, and preferably by stacking a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. Using a stack of insulating layers with a relatively high dielectric strength, such as aluminum oxide, improves the dielectric strength and suppresses electrostatic breakdown of the capacitor element 100.

[0546] Furthermore, a material that can have ferroelectricity can be used for the insulating layer 130. For details about the material that can have ferroelectricity, refer to the description in Embodiment 1.

[0547] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when they are as thin as a few nm, and are therefore preferred as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0548] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm 2 Below, 10μm 2 Below, 1μm 2 Less than or equal to 0.1 μm 2 Even if the thickness is less than 10,000 nm, the material can still have ferroelectricity. 2 or less than 1000nm 2 Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor 100 can be reduced.

[0549] Yttrium can also be added to metal oxides containing either or both of hafnium and zirconium. For example, adding yttrium to hafnium zirconium oxide can enhance ferroelectricity.

[0550] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 100, the storage device described in this embodiment functions as a ferroelectric memory.

[0551] The conductive layer 220 is provided so as to cover the insulating layer 130. The side edges of the conductive layer 220 are preferably positioned outward relative to the side edges of the conductive layer 115. This configuration allows the conductive layer 220 to be embedded in the opening 190. Furthermore, by increasing the area of the conductive layer 220 in a plan view, the required alignment accuracy with the groove 290 can be reduced, making it relatively easy to process the groove 290.

[0552] For materials, structures, and the like applicable to the conductive layer 220, the description of Embodiment 1 can be referred to.

[0553] FIG. 31(A) is a diagram showing an example in which the end 103 shown in FIG. 28(B) is located on the insulating layer 180. In the example shown in FIG. 31(A), the insulating layer 180 has a region 102 extending from the top surface to the side surface of the opening 190, which has a curved portion. Also, in the example shown in FIG. 31(A), the end 103 has a tapered shape. By having the region 102 have a curved portion and the end 103 have a tapered shape, even when the end 103 is located on the insulating layer 180, electric field concentration in the insulating layer 130 near the region 102 and the end 103 can be suppressed. This suppresses dielectric breakdown of the insulating layer 130, making it possible to provide a highly reliable memory device.

[0554] 31(B) is a diagram showing an example in which an insulating layer 187 is provided on the insulating layer 130 shown in Fig. 31(A), for example, in a region of the insulating layer 130 that overlaps with the insulating layer 180. By providing the insulating layer 187, electric field concentration on the insulating layer 130 can be preferably suppressed in some cases.

[0555] <Storage device configuration example 2> In the above-described <Configuration Example 1 of Memory Device>, the transistor 200 described in Embodiment 1 is used as the transistor included in the memory cell 150. However, a transistor that can be used as the transistor is not limited to this. For example, the transistor 200B described in Embodiment 1 can be used.

[0556] Another configuration of a memory device having a transistor and a capacitor will be described with reference to Figures 32(A) and 32(B). Figure 32(A) is a plan view of a memory device having two memory cells. Figure 32(B) is a cross-sectional view taken along the dashed line A1-A2 in Figure 32(A).

[0557] 32(A) and 32(B) is shown in Fig. 33. Fig. 33 is a perspective schematic diagram of a memory device including four memory cells. In Fig. 33, only the outlines of some components (such as interlayer insulating layers) are shown by dotted lines.

[0558] The memory device shown in Figures 32(A) and 32(B) includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150a and a memory cell 150b over the conductive layer 110, an insulating layer 180 over the conductive layer 110, an insulating layer 280 over the insulating layer 180, an insulating layer 284 over the insulating layer 280, an insulating layer 285 over the insulating layer 284, and conductive layers 265 over the insulating layer 284, the insulating layer 285, the memory cell 150a, and the memory cell 150b. The insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 284, and the insulating layer 285 function as interlayer films. The conductive layer 110 functions as a wiring. Note that hereinafter, the memory cell 150a and the memory cell 150b may be collectively referred to as memory cells 150.

[0559] The memory cell 150a includes a capacitor 100a on the conductive layer 110 and a transistor 200Ba on the capacitor 100a. Similarly, the memory cell 150b includes a capacitor 100b on the conductive layer 110 and a transistor 200Bb on the capacitor 100b. Note that hereinafter, the transistors 200Ba and 200Bb may be collectively referred to as the transistor 200B.

[0560] The capacitor 100a and the capacitor 100b have the same configuration as the capacitor 100 in the above-described <Configuration Example 1 of Memory Device>, and therefore the description of the capacitor 100 can be referred to.

[0561] 32A and 32B, the transistor 200B illustrated in Embodiment 1 is used as a transistor included in the memory cell 150 of the memory device. Therefore, the description in Embodiment 1 (FIG. 23B) can be referred to for the transistor 200Ba and the transistor 200Bb, and detailed description thereof will be omitted.

[0562] 32A and 32B, two memory cells can be provided in a region where the groove 290 and the gate wiring (conductive layer 265) overlap with each other. This reduces the area occupied by the memory device, enabling miniaturization or high integration of the memory device.

[0563] Here, a circuit diagram of the memory device shown in FIGS. 32(A) and 32(B) is shown in FIG. 32(C).

[0564] One of the source and drain of the transistor 200Ba is connected to one of the pair of electrodes of the capacitor 100a, the other of the source and drain of the transistor 200Ba is connected to the wiring BILa, and the gate of the transistor 200Ba is connected to the wiring WOL. The other of the pair of electrodes of the capacitor 100a is connected to the wiring CAL.

[0565] One of the source and drain of the transistor 200Bb is connected to one of a pair of electrodes of the capacitor 100b, the other of the source and drain of the transistor 200Bb is connected to a wiring BILb, and the gate of the transistor 200Bb is connected to a wiring WOL. The other of the pair of electrodes of the capacitor 100b is connected to a wiring CAL.

[0566] Here, the wiring BILa corresponds to the conductive layer 240a, the wiring BILb corresponds to the conductive layer 240b, the wiring WOL corresponds to the conductive layer 265, and the wiring CAL corresponds to the conductive layer 110.

[0567] 25C can be used as the transistor 200Ba and the transistor 200Bb included in the memory device shown in FIG. 32A and FIG. 32B. A plan view of the memory device in this case is shown in FIG. 34A. Note that the cross-sectional view of the memory device shown in FIG. 34A can refer to a configuration in which the semiconductor device shown in FIG. 25C and the memory device shown in FIG. 32B are combined.

[0568] 34(A), the conductive layer 265 is arranged so that its extension direction is inclined with respect to the Y direction. Each of the memory cells 150a and the memory cells 150b is provided at an intersection between the conductive layer 240 extending in the Y direction and the conductive layer 265. This configuration allows for miniaturization and high integration of the memory device.

[0569] FIG. 34B shows a circuit diagram of the memory device shown in FIG.

[0570] One of the source and drain of the transistor 200Ba is connected to one of a pair of electrodes of the capacitor 100a, the other of the source and drain of the transistor 200Ba is connected to a wiring BIL, and the gate of the transistor 200Ba is connected to a wiring WOL1. The other of the pair of electrodes of the capacitor 100a is connected to a wiring CAL.

[0571] One of the source and drain of the transistor 200Bb is connected to one of a pair of electrodes of the capacitor 100b, the other of the source and drain of the transistor 200Bb is connected to a wiring BIL, and the gate of the transistor 200Bb is connected to a wiring WOL2. The other of the pair of electrodes of the capacitor 100b is connected to a wiring CAL.

[0572] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL1 corresponds to the conductive layer 265, the wiring WOL2 corresponds to the conductive layer 265 adjacent to the wiring WOL1, and the wiring CAL corresponds to the conductive layer 110.

[0573] <Storage device configuration example 3> The memory cell 150 described in this embodiment can be used as a memory cell of a memory device. The transistor 200 is preferably an OS transistor. Because an OS transistor has a low off-state current, its use in a memory device allows stored data to be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so the power consumption of the memory device can be sufficiently reduced. By using the transistor 200 in a memory device, the memory device can be highly integrated and have low power consumption. Furthermore, the high frequency characteristics of an OS transistor enable high-speed reading and writing to and from the memory device.

[0574] A memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix.

[0575] 35 shows an example in which one memory cell shown in FIG. 28(B) is stacked in n layers (n is an integer of 3 or more) in the Z direction. The C1-C2 direction shown in FIG. 35 is parallel to the X direction, and the region shown between C1 and C2 includes two memory cells. The C1-C3 direction shown in FIG. 35 is parallel to the Y direction, and the region shown between C1 and C3 includes the region where conductive layer 240a extends.

[0576] The memory device shown in FIG. 35 has n memory layers 160. Specifically, a memory layer 160[2] is provided on the memory layer 160[1], and (n-3) memory layers are further provided on the memory layer 160[2], with the memory layer 160[n] provided at the top. The number of memory cells ...

Claims

1. an oxide semiconductor layer, first to third insulating layers, and first to third conductive layers; the first conductive layer and the second conductive layer are provided on the first insulating layer and spaced apart from each other; the first insulating layer has a groove between the first conductive layer and the second conductive layer; the oxide semiconductor layer has a region in contact with an upper surface of the first conductive layer and a side surface thereof on the groove portion side, a region in contact with an upper surface of the second conductive layer and a side surface thereof on the groove portion side, and a region in contact with a side surface of the groove, the second insulating layer is provided on the oxide semiconductor layer; the third conductive layer is provided on the second insulating layer; side surfaces of the third conductive layer, the second insulating layer, and the oxide semiconductor layer are aligned or substantially aligned; the third insulating layer has, outside the groove, a region in contact with a top surface of the first conductive layer, a top surface of the second conductive layer, a side surface of the oxide semiconductor layer, a side surface of the second insulating layer, and a side surface of the third conductive layer, and, inside the groove, a region in contact with a side surface of the oxide semiconductor layer, a side surface of the second insulating layer, and a side surface of the third conductive layer.

2. In claim 1, a fourth conductive layer; the fourth conductive layer is in contact with an upper surface of the third conductive layer; a direction in which the fourth conductive layer extends intersects with a direction in which the trench extends;

3. In claim 1, a fifth conductive layer; the fifth conductive layer has regions overlapping with the first conductive layer and the second conductive layer, with the first insulating layer sandwiched therebetween; the fifth conductive layer has a recess in a region overlapping with the groove, The oxide semiconductor layer has a region in contact with a side surface and a bottom surface of the recess.

4. In claim 3, The recess has a curved portion.

5. a capacitance element, a transistor on the capacitance element, a first insulating layer, and a second insulating layer; the transistor includes an oxide semiconductor layer, a third insulating layer, and first to fourth conductive layers; the first insulating layer is provided to cover the first conductive layer, the second conductive layer and the third conductive layer are provided on the first insulating layer and spaced apart from each other; the first insulating layer has a groove between the second conductive layer and the third conductive layer; the first conductive layer has a recess in a region overlapping with the groove; the oxide semiconductor layer has a region in contact with an upper surface of the second conductive layer and a side surface on the groove side, a region in contact with an upper surface of the third conductive layer and a side surface on the groove side, a region in contact with a side surface of the groove, and a region in contact with a side surface and a bottom of the recess, the third insulating layer is provided on the oxide semiconductor layer; the fourth conductive layer is provided on the third insulating layer; side surfaces of the fourth conductive layer, the third insulating layer, and the oxide semiconductor layer are aligned or substantially aligned; the second insulating layer has, outside the groove, a region in contact with a top surface of the second conductive layer, a top surface of the third conductive layer, a side surface of the oxide semiconductor layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer, and, inside the groove, a region in contact with a side surface of the oxide semiconductor layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer.

6. In claim 5, a fifth conductive layer; the fifth conductive layer is in contact with an upper surface of the fourth conductive layer; a direction in which the fifth conductive layer extends intersects with a direction in which the trench extends;

7. In claim 5, The storage device, wherein the recess has a curved portion.

8. In claim 5, The memory device, wherein the capacitive element has a sixth conductive layer, a fourth insulating layer on the sixth conductive layer, and the first conductive layer on the fourth insulating layer.

9. In any one of claims 5 to 8, the third insulating layer comprises a first layer; The first layer comprises an oxide containing hafnium.

10. In claim 9, The first layer comprises hafnium zirconium oxide.

11. In claim 10, the third insulating layer has a second layer on the first layer; The second layer comprises silicon nitride.

12. a first insulating layer, a second insulating layer, a first transistor, and a second transistor; the first insulating layer has a groove; the first transistor includes a first oxide semiconductor layer including a channel formation region; the second transistor includes a second oxide semiconductor layer including a channel formation region; at least a portion of each of the first oxide semiconductor layer and the second oxide semiconductor layer is located in the groove; In a plan view, the first oxide semiconductor layer and the second oxide semiconductor layer face each other with the second insulating layer sandwiched therebetween in a direction perpendicular to a direction in which the trench extends.

13. In claim 12, the first transistor has first to third conductive layers; the second conductive layer is provided on the first insulating layer; the first conductive layer has a region overlapping the second conductive layer with the first insulating layer sandwiched therebetween; the first conductive layer has a recess in a region overlapping with the groove; the first oxide semiconductor layer has a region in contact with a side surface and a bottom surface of the recessed portion of the first conductive layer and a region in contact with a top surface and a side surface of the second conductive layer; The semiconductor device, wherein the third conductive layer is provided above the first oxide semiconductor layer.

14. In claim 13, the second insulating layer has regions inside the trench that are in contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.

15. In claim 13, a fourth conductive layer; the fourth conductive layer is connected to a gate of the first transistor and a gate of the second transistor, a direction in which the fourth conductive layer extends intersects with a direction in which the trench extends;

16. A semiconductor device comprising: a semiconductor device according to any one of claims 13 to 15; and a capacitive element; the capacitive element is located below the first transistor, The memory device, wherein the first conductive layer has a region that functions as one of a pair of electrodes of the capacitor.

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