LED array

Abstract

To provide a method of producing a light emitting diode (LED) array.SOLUTION: There is provided a method of producing a light emitting diode (LED) array. The method includes steps of: forming a plurality of layers 100, 101, 103 of a semiconductor material; forming a dielectric mask layer 104 covering the plurality of layers, the dielectric mask layer having an array of holes 106 which each expose an area of one of the layers of the semiconductor material and penetrating the dielectric mask layer; and growing LED structures 110, 112, 114 arranged to emit light over a range of wavelengths, in each of the holes. At least some of the plurality layers 101 form a distributed Bragg reflector (DBR) arranged to reflect light of at least some of the range of wavelengths.SELECTED DRAWING: Figure 1c

Description

[Technical Field]

[0001] The present invention relates to light emitting diode (LED) arrays and methods for manufacturing LED arrays. In particular, but not exclusively, the present invention relates to arrays of LEDs on the micrometer scale. [Background technology]

[0002] There is a significantly growing demand for developing III-nitride light-emitting diodes (LEDs) at the micrometer scale, i.e., micro-sized LEDs (μLEDs), the key building blocks for new generation displays and visible light communication (VLC) applications. III-nitride μLEDs offer several unique features for display applications compared to organic light-emitting diodes (OLEDs) and liquid crystal displays (LCDs). Unlike LCDs, III-nitride microdisplays, in which μLEDs are the key building blocks, are self-emissive. Monochrome displays using μLEDs offer high resolution, high efficiency, and high contrast ratios. OLEDs are typically operated at current densities several orders of magnitude lower than semiconductor LEDs to maintain reasonable lifetimes. As a result, the luminance of OLEDs is very low, typically 3000 cd / m for full-color displays. 2 while III-nitride μLEDs are 10 5 cd / m 2III-nitride μLEDs exhibit higher luminance than conventional LEDs. Naturally, III-nitride μLEDs inherently exhibit longer operational lifetimes and chemical robustness compared to OLEDs. Therefore, III-nitride μLEDs are expected to potentially replace LCDs and OLEDs for high-resolution, high-brightness displays in a wide range of near-term applications, such as smartphones. In addition to display applications, μLEDs exhibit significantly reduced junction capacitance as a result of their reduced dimensions compared to broad-area LEDs, potentially leading to high-speed transmission with GHz modulation bandwidths in VLC applications. Currently, III-nitride μLEDs are fabricated exclusively by combining standard photolithography and subsequent dry etching processes on standard III-nitride LED wafers, which is similar to the fabrication of conventional broad-area LEDs with typical device areas of 300 μm × 300 μm or even larger. The only major difference in device fabrication between broad-area LEDs and μLEDs is due to the device dimensions. Typically, the diameter of μLEDs ranges from 50 μm to several micrometers. Current technology is described, for example, in ZY Fan, JY Lin, and HX Jiang, J. Phys. D: Appl. Phys. 41, 094001 (2008); HX Jiang and JY Lin, Optical Express 21, A476 (2013); and J. Day, J. Li, DY C Lie, C. Bradford, JY Lin, and HX Jiang, Appl. Phys. Lett. 99, 031116 (2011).

[0003] Currently, there is a major challenge in using current μLEDs for VLC applications due to so-called crosstalk. When a single μLED lights up, neighboring μLEDs and regions appear to light up simultaneously, generating crosstalk. As an illustration, in the case of a multi-channel VLC system using a micro-pixelated μLED array as a transmitter, when a signal is sent along an optical channel from a single μLED, neighboring channels may be carrying the same signal due to optical crosstalk. The mechanism of crosstalk generation is complex and still not very clear. Generally speaking, two main mechanisms are discussed by H.Y. Lin, C.W. Sher, D.H. Hsieh, X.Y. Chen, H.M. Philip Chen, T.M. Chen, K.M. Lau, C.H. Chen, C.C. Lin, and H.C. Kuo, Photonics Research 5, 411 (2017); and KH Li, YFCheung, WSCheung, and HW Choi, Appl. Phys. Lett. 107, 171103 (2015), are accepted as the cause of this crosstalk issue. First, the light emission mechanism of μLEDs is due to a spontaneous emission process, which means that light emitted from a μLED is dispersed in all directions. The pitch of μLEDs (i.e., pixels) is typically on a scale ranging from a few micrometers to tens of micrometers. As a result, it is expected that light emitted from the sidewall of one μLED will interact with light from neighboring μLEDs, which will lead to interference and then crosstalk. Second, even if the sidewalls of all μLEDs in an array configuration are sufficiently covered with an opaque coating, which means that light emitted from the sidewalls of the μLEDs should be completely suppressed, the crosstalk problem still exists. This means that there is another channel through which light emanating from one μLED can reach a neighboring μLED. Summary of the Invention [Problem to be solved by the invention]

[0004] III-nitride LEDs are typically grown on sapphire. The refractive index of GaN is greater than 1 (the refractive index of air is 1) but less than that of sapphire, which naturally forms a waveguide within the GaN layer sandwiched between the air and sapphire. Due to the total internal reflection (TIR) effect, only a small fraction (approximately 6%) of the emitted light can be extracted from the GaN surface toward the top surface into the air, while the majority of the remaining emitted light (approximately 66%) is trapped within the GaN layer due to TIR. This is determined by Snell's law. For μLED arrays, only a small fraction of the emitted light will be extracted from the top surface and diverge within an emission cone with a limited solid angle determined by Snell's law, while below the active region, a large fraction of the emitted light emanating downward from the active region will be trapped within the GaN layer below the active region due to TIR. These trapped emissions from all μLEDs are thus channeled in the GaN (and potentially in the sapphire) which acts as a waveguide. Therefore, the emissions from all μLEDs interact or interfere with each other through the GaN waveguide. This corresponds to the majority fraction of the emission from the μLEDs and thus dominates the crosstalk problem. [Means for solving the problem]

[0005] The present invention provides a method of manufacturing a light emitting diode (LED) array, comprising the steps of forming a plurality of layers of semiconductor material; forming a dielectric mask layer overlying the plurality of layers, the dielectric mask layer having an array of holes therethrough, each exposing an area of one of the layers of semiconductor material; and growing in each of the holes an LED structure configured to emit light over a range of wavelengths, at least some of the plurality of layers forming a distributed Bragg reflector (DBR) configured to reflect light over at least a portion of the range of wavelengths.

[0006] At least one of the layers can form an electrical contact connecting at least a portion of the LED structure together. The electrical contact can be formed between the DBR and the dielectric layer. The contact layer can be an upper layer of the semiconductor layer. The electrical contact can be formed from a doped semiconductor material, such as an n-doped III-nitride material, e.g., n-GaN.

[0007] The step of forming the DBR includes forming at least five pairs of layers, or preferably at least ten pairs of layers, each pair including a first layer of a first material and and a second layer of a second material, the two layers in each pair exhibiting different refractive indices. For example, the first and second materials may both comprise III-nitride materials, but of different compositions, such as different aluminum contents, leading to a difference in refractive index.

[0008] One layer of each pair may be formed from a doped semiconductor material, such as n-GaN, which may be electrochemically etched to its native state to become porous, thus exhibiting a refractive index much lower than that of GaN, and the other layer of each pair may be formed from an undoped semiconductor material that remains unaffected during the electrochemical etching process.

[0009] An LED structure can be grown on the exposed area of the upper layer of semiconductor layers. Growth is generally upward because growth does not occur from the dielectric sidewalls of the hole. Upward growth of the LED structure within the hole can therefore result in a layered LED structure, with each layer being generally flat or planar and of substantially constant thickness.

[0010] The semiconductor layer may be formed on a substrate of, for example, a III-nitride such as GaN, or of sapphire, silicon (Si), silicon carbide (SiC), or glass.

[0011] Growing an LED structure in each of the holes may include growing an n-type layer. Growing an LED structure in each of the holes may include growing a prelayer in each of the holes. Growing an LED structure in each of the holes may include growing at least one active layer in each of the holes. Growing an LED structure in each of the holes may include growing a p-type layer in each of the holes. The at least one active layer may include at least one quantum well layer, and may include multiple quantum well layers. These may be formed, for example, from InGaN or another suitable III-nitride material. The prelayer may be, for example, either an InGaN layer with a low indium content and a typical thickness of <100 nm, or an InGaN / GaN superlattice with a low indium content (the total thickness of the superlattice is typically less than 300 nm). The n-type and p-type layers may also be composed of III-nitride materials such as GaN, InGaN, or AlGaN.

[0012] Each LED structure is grown in a respective one of the holes, so that each LED structure is formed from multiple layers that all have the same cross-sectional area equal to the cross-sectional area of the hole in which the LED structure is grown.

[0013] At least one active layer may have an upper surface that is below the upper surface of the dielectric layer. If only one quantum well layer is present, the upper surface is the upper surface of that quantum well layer. If multiple quantum well layers are present, the upper surface is the upper surface of the uppermost quantum well layer. The upward direction may be defined as the direction of growth of the semiconductor layers and / or the LED structure.

[0014] Forming the dielectric mask layer may include growing a layer of dielectric material and etching an array of holes into the layer of dielectric material. Alternatively, the dielectric layer may be grown around areas where holes will later be formed, for example using a mask during growth of the dielectric layer.

[0015] The method may further include the step of etching each of the exposed areas of the semiconductor layer prior to the step of growing an LED structure in each of the holes.

[0016] The contact layer may be doped. For example, the contact layer may include a single layer of an n-type or p-type III-nitride material. Alternatively, the contact layer may include a first sublayer and a second sublayer, with the heterointerface between the first and second sublayers configured to form a two-dimensional charge carrier gas at the heterointerface. The sublayers may form a buffer layer and a barrier layer. The two-dimensional charge carrier gas may be, for example, a two-dimensional electron gas (2DEG). A two-dimensional hole gas (2DHG) may also be used, but typically has a lower charge carrier density and / or mobility. For example, it is well known that a heterostructure comprising a layer of GaN and a layer of AlGaN or InGaN, or more generally, two layers of AlGaN with different Al contents or two layers of InGaN with different In contents, can form a 2DEG at the interface between the two layers, and that the electron density within the 2DEG varies with several factors, including the Al content of the AlGaN layer or the In content of the InGaN layer. Other III-nitride heterointerfaces can be used with the same effect.

[0017] The present invention further provides an LED array including a plurality of semiconductor layers and a dielectric layer extending beyond the semiconductor layers and having an array of LED structures extending through the dielectric layer and configured to emit light over a range of wavelengths, at least a portion of the plurality of layers forming a distributed Bragg reflector (DBR) configured to reflect light over at least a portion of the range of wavelengths.

[0018] An electrical contact layer can be between the DBR and the dielectric layer, which has the advantage that the current powering the LED does not flow through the DBR structure, which therefore does not need to be electrically conductive.

[0019] The LED array may further include an electrode formed on the contact layer. The method or LED array may further include, in any operable combination, any one or more features of the preferred embodiments of the invention hereinafter described with reference to the accompanying drawings. [Brief explanation of the drawings]

[0020] [Figure 1a] FIG. 1a shows an as-grown template formed in a process according to a first embodiment of the present invention. [Figure 1b] FIG. 1b illustrates the template of FIG. 1a with a masking pattern formed in a mask layer of the template. [Figure 1c] FIG. 1c illustrates the template of FIG. 1a with micro LEDs grown in holes in the mask layer to form an LED array. [Figure 1d] FIG. 1d shows the LED array of FIG. 1c with electrical contacts formed on the LED array. [Figure 2] FIG. 1d is a cross-sectional view through the LED structure of the LED array template. [Figure 3] FIG. 1c is a schematic cross-sectional view through the DBR-forming portion of the LED array of FIG. 1d. [Figure 4] FIG. 4 is a diagram of the reflectance curve of the DBR of FIG. 3. DETAILED DESCRIPTION OF THE INVENTION

[0021] 1a, a bottom semiconductor layer 100 of III-nitride or other suitable semiconductor, for example, a standard undoped GaN (u-GaN) layer, is initially grown on a substrate 102. The substrate 102 may be a GaN substrate, or may be any foreign substrate, such as sapphire, silicon (Si), silicon carbide (SiC), or even glass. The bottom semiconductor layer 100 may be grown on any suitable substrate, using either metalorganic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE), or any other suitable growth method. The lower semiconductor layer 100 may be grown by means of any standard GaN growth method. A number of additional layers 101 are grown above the lower semiconductor layer 100. These layers are configured to form a distributed Bragg reflector (DBR), with alternating layers of two different materials, as will be described in more detail below. An upper semiconductor layer 103 is grown above the DBR layer 101. This layer 103 is configured to form an electrical contact layer for the LED device and may be composed of, for example, n-type GaN (n-GaN). The contact layer may have a thickness of 50 nm to 10 μm. A dielectric layer 104, such as silicon dioxide (SiO2) or silicon nitride (SiN), or any other suitable dielectric material, is deposited on the upper semiconductor layer 103 by PECVD or any other suitable deposition method. The thickness of the dielectric layer may be in the range of 20 nm to 500 μm.

[0022] Referring to FIG. 1b, an array of holes 106 is then formed in the dielectric layer 104. The holes 106 are typically on the micrometer scale and are therefore referred to as microholes. This can be done by photolithography followed by an etching process (which can be dry or wet etching). To form the microholes 106, the dielectric layer 104 is etched through its entire thickness, down to the upper surface of the upper semiconductor layer 103. If the holes 106 are rounded, they can have a diameter of 1 μm to 500 μm, and the pitch distance, i.e., the distance between the centers of adjacent microholes, can be, for example, 5 μm to 500 μm. Further etching of the upper semiconductor layer 103 only in the microhole areas can be performed using the remaining dielectric layer 104 as a mask. The n-GaN etching depth can be from zero (meaning no GaN etching) to 10 μm, depending on the n-GaN layer thickness. Typically, the optimal etching method or conditions will be different for the upper semiconductor layer 103 than for the dielectric layer 104. For example, an SF etchant can be used to etch the dielectric layer 104 but will not etch the n-GaN layer 100. Therefore, etching all the way through the dielectric layer 104 and stopping at the top surface of the upper semiconductor layer 103 is simple to achieve. This, in turn, has benefits for the quality of the LED structure grown in the hole 106.

[0023] The holes 106 are rounded in cross section in the embodiment shown, although other cross sections, such as oval or square, may be used.

[0024] Next, referring to FIG. 1c, a standard III-nitride LED structure is grown on the exposed areas of the top semiconductor layer 103. However, because only discrete areas of the top semiconductor layer 103 are exposed by the micro-holes 106 in the dielectric layer or mask, the LED structure is formed as an array of discrete LEDs 108 separated by the remaining portions of the dielectric layer 104 between the micro-holes 106. The LED structures 108 are grown by either MOVPE or MBE, or any other suitable growth method. Growth occurs upward from the exposed areas of the GaN (or other semiconductor) of the top layer 103, and not from the sidewalls of the holes 106. Therefore, a layered LED structure can be built up inside each of the holes 106, with each of the layers being substantially flat or planar. The LED structure may include an n-GaN layer 110, an InGaN pre-layer, an active region 112, a thin p-type AlGaN layer (not shown) as a blocking layer, and then a final p-doped GaN layer 114. The active region 112 may include an InGaN-based multiple quantum well (MQW). The pre-layer may be, for example, either an InGaN layer with low indium content and a typical thickness of <100 nm, or an InGaN / GaN superlattice with low indium content (the total thickness of the superlattice is typically below 300 nm). An example of an LED structure is described in more detail below with reference to FIG. 2. As mentioned above, due to the dielectric mask 104, the LED structure forms a μLED array, as shown in FIG. 1c. As shown, the nanoparticles can be grown only in the micropores 106 .

[0025] It is important that the topmost layer of InGaN MQWs 112 should not extend above the upper surface of the dielectric layer 104, as this could cause shorting effects after the template is fabricated into the final μLED array. It is also important that the overgrown n-GaN 110 in each of the micro-hole areas directly contacts the upper semiconductor layer 103 in the unetched portion of the template below the dielectric mask 104, so that all of the individual μLEDs are electrically connected to each other by the upper semiconductor layer 103 in the unetched portion below the dielectric mask 104.

[0026] Referring to FIG. 1d, once the LED array structure is completed, further device fabrication is performed, including forming electrical contacts to the array. For example, a top contact layer 116 may be formed over the dielectric mask layer 104 and over the top p-GaN layer of the individual micro LED devices 108. The top contact layer 116 thus forms a p-contact for all of the LED devices 108. This p-contact may be a common p-contact for all of the LED devices 108, or may be formed as multiple separate areas, each in contact with one or more respective groups of the LED devices and having a separate contact formed thereon. This allows the LED devices 108 to be switched in groups, thus forming an addressable array. The top contact layer 116 may be formed from ITO or a Ni / Au alloy. An anode 118 may then be formed on the p-contact layer 116. For example, a portion of the dielectric layer 104 can be etched away, and then a portion of the LED structure on the etched dielectric layer section can be etched further down to the top semiconductor layer 103, which exposes an area 122 of the n-GaN top semiconductor layer 103, and a cathode 120 can be formed on the exposed area 122 of the n-GaN.

[0027] In the finished structure shown in FIG. 1d, light is emitted from each of the LEDs 108 in all directions, but the DBR reflects the downward-emitted light, thereby significantly increasing the proportion of upward-emitted light. Generally, DBR structures exhibit very high reflectivity, typically greater than 90%. Therefore, the DBR structure significantly enhances extraction efficiency, meaning that the majority of the light emitted from the individual micro-LEDs is extracted from the surface, while both the portion of the light emitted from the sidewalls of the micro-LED and the portion of the light trapped within the GaN waveguide below the active region are reduced or, in ideal cases, even eliminated. With proper design (such as by properly designing the microLED layer thickness and the microLED pitch), extraction efficiencies approaching 100% can be obtained due to photonic crystal effects (see Photonic Crystals: Molding the Flow of Light, JD Joannopoulos, RD Meade, JN Winn, SG Johnson, Princeton University Press, 1995) and microcavity effects. Crosstalk can therefore be significantly reduced or virtually eliminated.

[0028] It will be appreciated that various modifications to the above-described embodiments are possible. For example, in one variation, the structure is reversed, with a p-GaN layer grown on a substrate and covered with a dielectric layer, and then the p-GaN layer of LED device 108 formed first, followed by a multiple quantum well layer and then an n-GaN layer. An n-contact layer is then formed above the top surface of the dielectric layer in place of the p-contact layer, and the positions of the anode and cathode are reversed.

[0029] 1a to 1d, the overgrown n-GaN 110 in the micro-holes 106 must match the n-GaN in the unetched portion of the n-GaN upper semiconductor layer 103 below the dielectric mask 104 so that all individual μLEDs 108 are electrically connected to each other by the n-GaN layer 103. Instead of using the n-GaN in the unetched portion below the dielectric mask 104 as the electrically connected channel, in a further embodiment, a III-nitride heterostructure with a two-dimensional electron gas (2DEG) at the heterojunction is used as the semiconductor layer instead of the n-GaN layer. In this embodiment, a standard AlGaN / GaN HEMT structure is used. The high-sheet-carry-density and high-electron-mobility electron gas (2DEG) formed at the interface between the AlGaN barrier and the GaN buffer of the high-electron-mobility transistor (HEMT) structure is used as the electrically connected channel.

[0030] To fabricate such a device, a standard AlGaN / GaN HEMT structure is grown above the DBR layer. For example, a GaN layer forming a buffer layer can be grown above the DBR layer, and then an AlGaN layer forming a barrier layer is grown on the GaN layer. This structure is referred to herein as the "as-grown HEMT template." Subsequently, a dielectric layer, such as SiO or SiN, or any other dielectric material, with a thickness in the range of 2 nm to 500 μm, is deposited on the as-grown HEMT template using PECVD or any other suitable deposition method. The resulting structure will be the same as that shown in FIG. 1a, but with the HEMT structure in place of the upper semiconductor layer 103. Thereafter, by means of photolithography and then an etching process (which may be dry or wet etching), the dielectric layer is etched down to the surface of the HEMT structure to form a microhole array in the dielectric layer, where the microhole diameter may be 1 μm to 500 μm and the pitch distance between adjacent hole centers may be in the range of 5 μm to 500 μm. Further etching of the as-grown HEMT within the microhole area may be performed using the remaining area of the dielectric layer as a mask. The as-grown HEMT etch depth may be zero (meaning no etching at all) to 10 μm, depending on the AlGaN barrier position of the as-grown HEMT template. However, typically, the etching will extend downward at least as far as the heterointerface between the two layers of the as-grown HEMT structure to provide good electrical contact between each of the LED structures and the 2DEG.

[0031] Next, a standard III-nitride LED structure is grown on the dielectric mask-patterned HEMT template characterized by microholes, e.g., by either MOVPE or MBE, as described above with reference to Figure 1c, or any other epitaxial method, and contacts are provided, e.g., as described above with reference to Figure 1d. As with the embodiment of Figures 1a-1d, the important point is that the upper surface of the InGaN MQW 212 should be below the upper surface of the dielectric layer 204 to avoid shorting effects after fabrication into the final μLED array.

[0032] 2, the LED structures in the LED arrays of FIGS. 1a-1d can have any suitable structure, but in one example, they can include an n-GaN layer 210, an InGaN pre-layer 216 formed above the n-GaN layer 210, several InGaN quantum well layers 212 formed above the pre-layer 216, a p-doped blocking layer 218, for example of p-AlGaN, and then a p-GaN layer 214. It will be appreciated that this structure can be varied in several ways. As noted above, As noted above, the top surface of the uppermost one of the quantum well layers 212 is preferably below the top surface of the dielectric layer. Even more preferably, the top surface of the blocking layer 218 is also below the top surface of the dielectric layer.

[0033] 3, as explained above, DBR layer 101 includes alternating layers 101a, 101b of two different materials with different refractive indices so that light from the LED is reflected at the interface between layers 101. The principles of DBRs are well known and therefore will not be described in detail, but layers 101a, 101b are of approximately equal thickness, which is about one-quarter the wavelength of the light (within the material of the DBR layer) that is reflected to produce constructive interference of the reflected light and destructive interference of the transmitted light.

[0034] The DBR structure 101 may be based on the Al(Ga)N / GaN system, which refers to pairs of alternating Al(Ga)N and GaN layers grown by MOVPE, MBE, or any other growth method. Alternatively, the DBR structure may include pairs of alternating GaN and nanoporous GaN layers. To produce this structure, pairs of alternating n-doped GaN and undoped GaN layers may be prepared by MOVPE, MBE, or any other growth method, followed by standard electrochemical (EC) etching. The EC etching mechanism is based on a combination of an oxidation process and a subsequent dissolution process in an acidic solution under an anodic bias, as described in Y. Hou, Z. Ahmed Syed, L. Jiu, J. Bai, and T. Wang, Appl. Phys. Lett. 111, 203901 (2017). Under a positive anode bias, the injection current will flow through the conductive n-doped GaN portion, leading to its oxidation. The oxidized layer is then chemically dissolved in an acidic electrolyte, which transforms the n-doped GaN into nanoporous GaN. Therefore, EC etching can be performed only on the n-type GaN due to its good conductivity, while the non-conductive undoped GaN remains unetched.

[0035] Referring to Figure 4, the reflectivity of a DBR is a function of wavelength, but typically a DBR can be configured to have a relatively broad range of wavelengths, the stopband 400, over which nearly total internal reflection is achieved. For either Al(Ga)N / GaN DBRs or GaN and nanoporous GaN DBRs, the stopband can be tuned to cover a wide spectral range, from the infrared through the full visible to the ultraviolet. Reflectivity is also a function of the angle of incidence of light onto the DBR, but in the LED arrays described above, the primary function of the DBR is to reflect light emitted downward 180° back in the upward direction, and so the DBR can be designed to accomplish that.

[0036] The reflectivity of the DBR increases with the number of pairs of layers 101a, 101b. Therefore, the DBR structure may have at least five pairs of layers, and more preferably at least ten pairs of layers.

[0037] The LEDs 108 will each emit light over a range of wavelengths. The range of wavelengths can be selected, among other things, by selecting the cross-sectional area of the LEDs 108. For example, LEDs grown as described above have been shown to have peak wavelengths in the red portion of the spectrum when the LEDs are about 30 μm in diameter, in the green portion of the spectrum when the LEDs are about 20 μm in diameter, and in the blue portion of the spectrum when the LEDs are about 10 μm in diameter. If the LEDs all have the same electroluminescence spectrum, the DBR can be configured to have a stop band centered on or at least including the peak wavelength of the LEDs. If the LEDs are designed to have different electroluminescence spectra with different peak wavelengths, the DBR can be optimized to give the best overall reflectivity for the different LEDs.

Claims

1. 1. A method of manufacturing a light emitting diode (LED) array, the method comprising: forming a plurality of layers of semiconductor material; forming a dielectric mask layer overlying the plurality of layers, the dielectric mask layer having an array of holes therethrough, each hole exposing an area of one of the layers of semiconductor material; and growing an LED structure in each of the holes, the LED structure being configured to emit light over a range of wavelengths, at least some of the plurality of layers forming a distributed Bragg reflector (DBR) configured to reflect light over at least a portion of the range of wavelengths.

2. The method of claim 1 , wherein at least one of the plurality of layers forms an electrical contact that connects at least some of the LED structures together.

3. The method of claim 2 , wherein the electrical contact is formed between the DBR and the dielectric layer.

4. 4. The method according to claim 1, wherein the electrical contact is formed by a doped semiconductor material.

5. 5. The method of claim 1, wherein forming the DBR comprises forming at least two pairs of layers, each pair including a first layer of a first material and a second layer of a second material.

6. 6. The method of claim 5, wherein one of the layers of each pair is formed from a doped semiconductor material and is electrochemically etched to increase the porosity of the doped semiconductor material.

7. 7. The method of claim 6, wherein the other of each pair of layers is formed of an undoped semiconductor material.

8. 1. An LED array comprising: a plurality of semiconductor layers; and a dielectric layer extending above the semiconductor layers and having an array of LED structures thereon, the LED structures extending through the dielectric layer and configured to emit light over a range of wavelengths, at least some of the plurality of layers forming a distributed Bragg reflector (DBR) configured to reflect at least a portion of light in the range of wavelengths.

9. 10. The LED array of claim 8, wherein at least one of the plurality of layers forms an electrical contact layer connecting at least some of the LED structures together.

10. 10. The LED array of claim 9, wherein the electrical contact layer is between the DBR and the dielectric layer.

11. 11. The LED array according to claim 9, further comprising an electrode formed on the contact layer.

12. 12. The LED array of claim 8, wherein the electrical contacts comprise a doped semiconductor material.

13. The DBR includes at least two pairs of layers, each pair including a first layer of a first material and a second layer of a second material.

13. The LED array of claim 8, comprising a first layer of a second material.

14. 14. The LED array of claim 13, wherein one of the layers of each pair is formed from a doped semiconductor material that has been electrochemically etched to increase the porosity of the doped semiconductor material.

15. 15. The LED array of claim 14, wherein the other of each pair of layers is formed of an undoped semiconductor material.

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