Imaging device

Abstract

To provide an imaging device capable of performing image processing.SOLUTION: Analog data (image data) acquired by an imaging operation is held in pixels, and in the pixels, the analog data is subjected to a product-sum operation with an arbitrary weighting coefficient and converted into 2-value data. The 2-value data is taken in a neural network or the like to allow processing such as image recognition. Since a huge amount of image data can be held in the pixels in a form of analog data, processing can be performed with efficiency.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] The technology of constructing transistors using oxide semiconductor thin films formed on substrates has been attracting attention. For example, a transistor having an oxide semiconductor and extremely low off-state current is used in a pixel circuit. An imaging device having such a configuration is disclosed in Patent Document 1.

[0005] Furthermore, Patent Document 2 discloses a technique for adding a calculation function to an imaging device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-123087 Summary of the Invention [Problem to be solved by the invention]

[0007] With the advancement of technology, imaging devices equipped with solid-state imaging elements such as CMOS image sensors are becoming increasingly popular. In the next generation, imaging devices will be more sophisticated and capable of capturing high-quality images. It is required to be equipped with such functions.

[0008] Currently, image data compression and image recognition are performed by converting image data (analog data) into digital data. The data is converted and then extracted to the outside, after which processing is performed. If this becomes possible, cooperation with external devices will become faster, and user convenience will improve. It also reduces the load and power consumption of peripheral devices. If complex data processing can be performed, the time required for data conversion can also be reduced.

[0009] Therefore, one aspect of the present invention is to provide an imaging device capable of image processing. One of the purposes is to provide an imaging device that can recognize acquired image data. One of the purposes is to provide the image data. One of the objects of the present invention is to provide an imaging device that can

[0010] Another object is to provide an imaging device with low power consumption. It is an object of the present invention to provide an imaging device that can perform high-quality imaging. One of the objects is to provide a novel imaging device. Another object of the present invention is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a method for storing data in a pixel and processing the data. The present invention relates to an imaging device.

[0013] One embodiment of the present invention is an imaging device including a pixel block, a first circuit, and a second circuit. The image block includes a plurality of pixels and a third circuit, and the pixels and the third circuit are The pixels are electrically connected via a first wiring, and have a function of obtaining a first signal by photoelectric conversion. The pixel has a function of multiplying the first signal by an arbitrary magnification to generate a second signal, and the second signal to the first wiring, and the third circuit has a function of outputting the second The third signal is generated by calculating the sum of the signals, and the third signal is output to the first circuit. The first circuit binarizes the third signal to generate a fourth signal, and transmits the fourth signal to the second circuit. It is an imaging device that outputs to.

[0014] The second circuit may have a function of converting the fourth signal from parallel to serial. The second circuit has a neural network that uses the fourth signal as input data. Good too.

[0015] The plurality of pixels are arranged in a matrix, and it is preferable that one of the rows is light-shielded. .

[0016] The pixel includes a photoelectric conversion element, a first transistor, a second transistor, and a third transistor. a fourth transistor, a first capacitor, and a second capacitor. The electrode is electrically connected to one of the source and drain of the first transistor. The other of the source or drain of the first transistor is connected to the source or drain of the second transistor. and one of the source and drain of the second transistor is electrically connected to the third transistor. The gate of the third transistor is electrically connected to the gate of the first capacitor. One of the electrodes of the element is electrically connected to one of the source and drain of the third transistor. The first electrode of the first capacitor is electrically connected to the first wiring, and the other electrode of the first capacitor is electrically connected to the fourth transistor. the first and second transistors, electrically connected to either the source or the drain of the first transistor, The transistor may have a structure in which a metal oxide is included in a channel formation region.

[0017] The pixel further includes a fifth transistor and a sixth transistor. The gate of the third transistor is electrically connected to the gate of the fifth transistor. One of the source and drain of the sixth transistor is electrically connected to one of the source and drain of the sixth transistor. Alternatively, the power supply 10 may be electrically connected.

[0018] The third and fourth transistors preferably have silicon in their channel formation regions. .

[0019] The third circuit includes a current source circuit, a seventh transistor, an eighth transistor, and a ninth transistor. The current source circuit has a transistor, a second capacitance element, and a resistance element, and the current source circuit is connected to the first wiring and The first wiring is electrically connected to one electrode of the second capacitor element, and the second wiring is electrically connected to one electrode of the second capacitor element. One electrode of the capacitance element is electrically connected to one electrode of the resistance element, and the second capacitance element The other electrode of the seventh transistor is electrically connected to one of the source and drain of the seventh transistor. , the source or drain of the seventh transistor is connected to the gate of the eighth transistor. The source or drain of the eighth transistor is electrically connected to the ninth transistor. The transistor may be configured to be electrically connected to either the source or the drain of the transistor.

[0020] The seventh to ninth transistors preferably have silicon in a channel formation region.

[0021] Metal oxides include In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, C It is preferred that the alloy comprises at least one of:

[0022] The photoelectric conversion element preferably contains selenium or a compound containing selenium. [Effects of the Invention]

[0023] By using one embodiment of the present invention, an imaging device capable of image processing can be provided. Alternatively, an imaging device capable of recognizing acquired image data can be provided. Alternatively, it is possible to provide an imaging device that can compress acquired image data. This can be done.

[0024] Alternatively, it is possible to provide an imaging device with low power consumption. Alternatively, it is possible to perform imaging with high sensitivity. It is possible to provide an imaging device. Alternatively, it is possible to provide an imaging device with high reliability. Alternatively, a novel imaging device or the like can be provided. Alternatively, a novel semiconductor device or the like can be provided. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a block diagram illustrating an imaging apparatus. [Figure 2] FIG. 2 is a diagram illustrating a pixel block 200. [Figure 3] FIG. 2 is a diagram illustrating a pixel 100 and a reference pixel 150. [Figure 4] FIG. 2 is a diagram for explaining a reference pixel 150. [Figure 5] FIG. 2 is a diagram illustrating a current source circuit 210. [Figure 6] 4 is a timing chart illustrating the operation of the pixel block 200. [Figure 7] FIG. 2 is a diagram illustrating a pixel 100 and a pixel block 200. [Figure 8] 3A and 3B are diagrams for explaining signals output from a pixel block 200 and a circuit 302. [Figure 9] FIG. 3 is a diagram illustrating a circuit 302 (neural network). [Figure 10] FIG. 3 illustrates a pixel included in a circuit 302. [Figure 11] FIG. 1 is a diagram showing an example of the configuration of a neural network. [Figure 12] 3A and 3B are diagrams illustrating a circuit 301 and a pixel 100. [Figure 13] FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 14] FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 15]FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 16] FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 17] FIG. 2 is a diagram illustrating the configuration of a pixel of an imaging device. [Figure 18] FIG. 1 is a perspective view of a package and module that houses an imaging device. [Figure 19] 1A to 1C illustrate electronic devices. [Figure 20] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 21] FIG. 1 is a block diagram of a pixel array. [Figure 22] FIG. [Figure 23] FIG. 4 is a diagram for explaining weighting coefficients input to pixels. [Figure 24] FIG. 2 is a diagram for explaining pixel output. [Figure 25] 10A and 10B are diagrams illustrating images used in pattern extraction and weighting coefficients input to pixels. [Figure 26] FIG. 10 is a diagram illustrating a pattern extraction result. DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0027] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0028] One aspect of the present invention is an imaging device having additional functions such as image recognition. The analog data (image data) acquired during the imaging operation is stored in the pixels, and the analog data Binary data can be extracted from the data multiplied by an arbitrary weighting coefficient.

[0029] By incorporating this binary data into a neural network, image recognition and other processing can be performed. It is possible to store a huge amount of image data in the pixels as analog data. Therefore, processing can be performed efficiently.

[0030] FIG. 1 is a block diagram illustrating an imaging device according to one embodiment of the present invention. Circuit 300, circuit 301, circuit 302, circuit 303, circuit 304, and circuit 305 Note that the circuits 301 to 305 are not limited to a single circuit configuration, but may be configured with multiple circuits. This may be achieved.

[0031] The pixel array 300 includes a plurality of pixel blocks 200. The pixel blocks 200 are shown in FIG. As shown in FIG. 2, the pixel circuit 201 includes a plurality of pixels arranged in a matrix.

[0032] Of the plurality of pixels, one column is designated as the reference pixel 150, and the others are designated as the pixel 100. Image data can be acquired at pixel 100, and at reference pixel 150, In FIG. 2, the number of pixels is set to 2×3 as an example. However, it is preferable to provide the same number of reference pixels as the number of rows.

[0033] The pixel block 200 operates as a multiply-and-accumulate circuit, and the circuit 201 is connected to the pixel 100 and the reference pixel 101. It has the function of extracting the product of image data and weighting coefficients from the signal output from the pixel 150. .

[0034] As shown in FIG. 3, the pixel 100 includes a photoelectric conversion element 101, a transistor 102, and a The transistor 103, the capacitor element 104, the transistor 105, and the transistor 106 are included. The reference pixel 150 can also have a similar configuration. The explanation of pixel 100 will be mainly focused on the pixel 100, and the explanation of the reference pixel 150 will be focused on only the differences between the pixel 100 and the reference pixel 150. Give an explanation.

[0035] One electrode of the photoelectric conversion element 101 is connected to one of the source and drain of the transistor 102. The other of the source and the drain of the transistor 102 is electrically connected to the The source or drain of the transistor 103 is electrically connected to the One of the source and the drain is electrically connected to one electrode of the capacitor 104. One electrode of the capacitor 104 is electrically connected to the gate of the transistor 105. The other electrode of the element 104 is electrically connected to one of the source and drain of the transistor 106. is connected to.

[0036] The other electrode of the photoelectric conversion element 101 is electrically connected to a wiring 114. The gate of the transistor 102 is electrically connected to the wiring 116. The other drain is electrically connected to a wiring 115. The gate of the transistor 103 is The transistor 105 is electrically connected to the wiring 117. , and is electrically connected to the wiring 113. The other of the source and drain of the transistor 105 The source or drain of the transistor 106 is electrically connected to a GND wiring or the like. The other end of the transistor 106 is electrically connected to the wiring 111a. 12 is electrically connected to

[0037] In the reference pixel 150, the other of the source and drain of the transistor 106 is The point electrically connected to the wiring 111b and the source or drain of the transistor 105 The pixel 100 differs from the pixel 100 in that one of the electrodes is electrically connected to a wiring 153 .

[0038] Here, the other of the source or drain of the transistor 102 and the source of the transistor 103 One of the source and drain electrodes of the capacitor 104 and the gate electrode of the transistor 105 are connected to each other. The electrical connection point with the port is called node N.

[0039] The wirings 114 and 115 can function as power supply lines. The wiring 112 can function as a high-potential power supply line, and the wiring 115 can function as a low-potential power supply line. , 116, and 117 can function as signal lines for controlling the conduction of each transistor. The wirings 111a and 111b are used to supply a potential corresponding to the weighting coefficient to the pixel 100. The wiring 113 can function as a signal line for connecting the pixel 100 and the circuit 201. The wiring 153 can function as a wiring for electrically connecting the reference pixel 150 and the circuit. The wiring 201 can function as an electrical connection.

[0040] The wiring 113 may be electrically connected to an amplifier circuit or a gain adjustment circuit.

[0041] A photodiode can be used as the photoelectric conversion element 101. If it is desired to increase the output sensitivity, it is preferable to use an avalanche photodiode.

[0042] In the reference pixel 150, a signal is generated without the contribution of the photoelectric conversion element 101. Therefore, it is preferable to provide a light-shielding layer 151 on the reference pixel 150 as shown in FIG. 4(A). Alternatively, as shown in FIG. 4B, a structure without the photoelectric conversion element 101 may be used. Alternatively, in the configuration shown in FIG. 3, the transistor 103 is always in a conducting state (reset state). It may be in a locked state.

[0043] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. 5 can have a function of controlling the current flowing from the circuit 201 in accordance with the potential of the node N. The transistor 106 has a function of supplying a potential corresponding to a weighting coefficient to the node N. It is possible.

[0044] When an avalanche photodiode is used as the photoelectric conversion element 101, a high voltage is applied. Therefore, a high-voltage transistor is used as the transistor connected to the photoelectric conversion element 101. For example, a metal oxide film is preferably used in the channel formation region of a high-voltage transistor. A transistor using an organic carbide (hereinafter referred to as an OS transistor) can be used. Specifically, OS transistors are used as the transistors 102 and 103. It is preferable that:

[0045] In addition, the OS transistor has an extremely low off-state current. By using an OS transistor in 03, the period during which a charge can be held at node N can be maximized. Therefore, it is possible to make the length longer by using a single pixel. It is possible to apply a global shutter system in which charge accumulation is performed simultaneously. While storing image data in node N, perform multiple calculations using the image data. It is also possible.

[0046] On the other hand, it is desirable that the transistor 105 has excellent amplification characteristics. Since the photodiode 106 is frequently turned on and off, it has high mobility and is capable of high-speed operation. Therefore, the transistors 105 and 106 are preferably A transistor using silicon in the channel formation region (hereinafter referred to as a Si transistor) is applied. It is preferable that

[0047] The present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. Alternatively, all the transistors may be OS transistors or Si transistors. You may do so.

[0048] The potential of the node N in the pixel 100 is a voltage between the reset potential and the photoelectric conversion potential of the photoelectric conversion element 101. The potential (image data) generated by the conversion is added to the potential supplied from the wiring 111a. The capacitance of the transistor 105 is determined by the potential corresponding to the weighting coefficient. The input signal includes the product of the image data and an arbitrary weighting factor.

[0049] The potential of the node N in the reference pixel 150 is a reset potential supplied from the wiring 115 and This is determined by capacitive coupling with a potential corresponding to the weighting coefficient supplied from the wiring 111b.

[0050] As shown in FIG. 2, the pixels 100 are electrically connected to each other by wiring 113, and the reference pixels 1 50 are electrically connected to each other by a wiring 153. Therefore, the circuit 201 The sum of the signals output by the transistors 105 of the reference pixels 100 and the transistors of the reference pixels 150 The calculation is performed using the sum of the signals output by the filter 105.

[0051] The circuit 201 includes a current source circuit 210, a capacitance element 202, a transistor 203, and a transistor The resistor 204, the transistor 205, the transistor 206, and the resistor element 207 are included. do.

[0052] The current source circuit 210 is electrically connected to one electrode of the capacitor 202. The other electrode of the transistor 202 is electrically connected to one of the source and drain of the transistor 203. The other of the source and drain of the transistor 203 is connected to the gate of the transistor 204. One of the source and drain of the transistor 204 is electrically connected to the transistor The transistor 205 is electrically connected to either the source or the drain of the transistor 205. The source or drain of the transistor 206 is connected to the source or drain of the transistor 206. One electrode of the resistor element 207 is electrically connected to one electrode of the capacitor element 202. electrically connected.

[0053] The current source circuit 210 is electrically connected to the wiring 113 and the wiring 153. The other of the source and drain of 203 is electrically connected to a wiring 218. The other of the source and drain of the transistor 204 is electrically connected to the wiring 219. The other of the source or drain of the transistor 205 is electrically connected to a reference power supply line such as a GND line. The other of the source and the drain of the transistor 206 is electrically connected to a wiring 212. The other electrode of the resistor element 207 is electrically connected to a reference power supply line such as a GND line. To be continued.

[0054] The wiring 219 can function as a power supply line. For example, the wiring 219 can be a high-voltage The wiring 218 can function as a potential power supply line. The wirings 213, 214, 215, and 216 can function as wirings. It can function as a signal line that controls the conduction of a transistor.

[0055] The transistor 203 has a function of resetting the potential of the wiring 211 to the potential of the wiring 218. The transistors 204 and 205 function as a source follower circuit. The transistor 206 has the function of selecting the pixel block 200. It is possible.

[0056] The current source circuit 210 can be configured as shown in FIG. The output side of the transistor 253 is a transistor The gate of transistor 254, the drain of transistor 254, and the gate of transistor 224 This configuration electrically connects the transistor 254 and the The transistor 224 acts as a current mirror circuit. When a desired signal potential is supplied and the wiring 214 is set to "H", the wiring 113 and the wiring 153 In this configuration, a constant current can be supplied to each transistor. and / or Si transistors can be used.

[0057] The circuit 220 included in the current source circuit 210 is a p-channel transistor as shown in FIG. The output side of the transistor 262 may be connected to the transistor 26 2 and the gate of transistor 261. In this configuration, it is preferable to use Si transistors for the transistors 261 and 262. stomach.

[0058] In the circuit 201, the offset components other than the product of the image data (potential X) and the weighting coefficient (potential W) are The current source circuit 210 shown in FIG. The flow of WX extraction when using the circuit shown is as follows.

[0059] First, in the circuit 201, the transistor 203 is turned on, and the line 218 is connected to the line 2 A potential Vr is written to the memory cell 11. Here, the potential Vr is a reference potential used in a read operation.

[0060] At this time, it is assumed that a potential X is written to the node N of the pixel 100 by photoelectric conversion. Also, the weighting coefficients written from the wirings 111a and 111b are set to 0.

[0061] Therefore, the total current (IREF) flowing through the reference pixel 150 is kΣ(0-V th ) 2 where k is a constant, V th is the threshold voltage of transistor 105.

[0062] The current ICM0 (ICM when the weight is 0) flowing through the current source circuit 210 is ICM0=ICR EF0(ICREF when weight is 0)-kΣ(0-V th ) 2 This becomes:

[0063] The total current (Ip) flowing through pixel 100 is kΣ(XV th ) 2 This becomes:

[0064] The current IR0 (IR when the weight is 0) flowing through the resistance element 207 is IR0=IC-ICM0 -kΣ(XV th ) 2 That is, IR0=IC-ICREF0+kΣ(0-V th ) 2 -kΣ(XV th ) 2 This becomes:

[0065] Then, the transistor 203 is turned off, and the potential Vr is held in the wiring 211. A weighting factor W is applied to the pixel 100 and the reference pixel 150 from the wirings 111a and 111b. Write.

[0066] At this time, the total current (IREF) flowing through the reference pixel 150 is kΣ(WV th ) 2 and become.

[0067] The total current (Ip) flowing through pixel 100 is kΣ(W+XV th ) 2 This becomes:

[0068] The current IR flowing through the resistance element 207 is IR=IC-ICM-kΣ(W+XV th ) 2 and That is, IR=IC-ICREF+kΣ(WV th ) 2 -kΣ(W+XV t h ) 2 This becomes:

[0069] Here, the difference between IR0 and IR is IR0-IR=kΣ(Vth 2 -(X-Vth) 2 -(W-Vth) 2 +(W+X-Vth) 2 )=kΣ(2WX). The offset component is removed and the term consisting of WX can be extracted.

[0070] When the current flowing through the resistor element 207 is IR0, the potential Vr is maintained in the wiring 211. Then, when the current flowing through the resistance element 207 is changed to IR, the capacitance of the capacitance element 202 The difference between the known reference potentials Vr and WX is applied to the wiring 211. The sum of the potential with the element becomes the gate potential of the transistor 204, and the transistor 206 By making the wiring 212 conductive, a signal from which the offset component has been removed can be output to the wiring 212.

[0071] FIG. 6 is a timing chart illustrating the operation of the pixel block 200. The timing of each signal conversion is also shown in the figure, but in reality, the timing may differ depending on the delay within the circuit. It is preferable to shift the time accordingly.

[0072] First, in a period T1, the potential of the wiring 117 is set to "H" and the potential of the wiring 116 is set to "H". 0 and the node N of the reference pixel 150 are set to a reset potential. and the wirings 112_1 to 112_4 (corresponding to the wirings 112 in the first to fourth rows) are set to “H”. , write weight coefficient 0.

[0073] The potential of the wiring 116 is maintained at "H" until the period T2. A potential X (image data) is written to the node N.

[0074] During the period T3, the wiring 214_1 (the wiring 214 in the first row) and the wiring 215_1 (the wiring 21 in the first row) 5), wiring 214_2 (wiring 214 in the second row), wiring 215_2 (wiring 215 in the second row) The wiring 216 is set to “H” and a potential Vr is written to the wiring 211 .

[0075] During the period T4, the potential of the wiring 111 is set to a potential corresponding to the weighting coefficient W111. 2_1 is set to "H", a weighting coefficient W111 is applied to the node N of the pixel 100 in the first row. Write.

[0076] In the period T5, the potential of the wiring 111 is set to a potential corresponding to the weighting coefficient W112. 2_2 is set to “H”, a weighting factor W112 is applied to the node N of the pixel 100 in the second row. Write.

[0077] During the period T6, the wiring 213_1 (the wiring 213 in the first row), the wiring 214_1, the wiring 21 By setting 5_1 to “H”, the offset The signal from which the component has been removed is output.

[0078] Thereafter, the same operation as above is repeated, and in periods T7, T8, and T9, the pixel block in the second row A signal obtained by multiplying the pixel 100 of 200 by an arbitrary weighting coefficient is output. In T12, pixel 100 in pixel block 200 in the first row is assigned a weight different from that in T4 and T5. The signal multiplied by the coefficient is output.

[0079] In the pixel blocks 200, adjacent pixel blocks 200 share the pixel 100. For example, in the pixel 100, as shown in FIG. A transistor 107 capable of outputting the same as that of the transistor 5 is provided. The transistor 105 is electrically connected to the source or drain, and the source or drain is electrically connected to the wiring 118. are connected to the network.

[0080] The wiring 118 is used for electrical connection with the circuits 201 of adjacent pixel blocks. (B) shows the image in adjacent pixel blocks 200 (pixel blocks 200a and 200b). Pixel 100 (pixels 100a, 100b, 100c, 100d, 100e, 100f, 100 100g, 100h) and circuit 201 (circuits 201a, 201b). It should be noted that the reference pixel 150 is omitted in FIG.

[0081] In the pixel block 200a, the pixels 100a, 100b, 100c, and 100d are connected to the wiring The pixels 100e and 100g are electrically connected to the circuit 201a via the pixel electrodes 113. is electrically connected to the circuit 201a through a wiring 118.

[0082] In the pixel block 200b, the pixels 100e, 100f, 100g, and 100h are connected to the wiring 113. The pixels 100b and 100d are electrically connected to the circuit 201b via the is electrically connected to the circuit 201b through a wiring 118.

[0083] That is, in the pixel block 200a and the pixel block 200b, the pixel 100b, It can be said that 100d, 100e, and 100g are shared. By adopting this format, The network between pixel blocks 200 can be made denser, improving the accuracy of image analysis, etc. It can be done.

[0084] The weighting coefficient can be output from the circuit 305 shown in FIG. 1 to the wiring 111. It is preferable to rewrite the weight coefficients at least once within the time period. The circuit 305 may also include a D / A converter and an SRAM. In addition, the pixel to which the weighting coefficient is input is selected by outputting a signal from the circuit 304 to the wiring 112. The circuit 304 may be a decoder or a shift register.

[0085] In addition, the wirings 213, 215, 216, etc. connected to the transistors of the circuit 201 are A signal can be output from the circuit 303. The circuit 303 includes a decoder or a shift register. A star can be used.

[0086] 8A is a diagram illustrating a signal output from the pixel block 200. For simplicity of explanation, in (A), the pixel array 300 is divided into four pixel blocks 200 (pixel Block 200c, pixel block 200d, pixel block 200e, pixel block 200 f), where each pixel block 200 has four pixels 100.

[0087] The generation of the signal will be described using the pixel block 200c as an example. 0d, 200e, and 200f can also output signals with similar operations.

[0088] In the pixel block 200c, each pixel 100 has p11, p12, p21, The image data of p22 is stored in node N. Each pixel 100 has a weighting coefficient ( W111, W112, W121, W122) are input, and wiring 212_1 (the wiring in the first column) 212), the result of the sum-of-products operation, h111, is output. Here, h111 = p11 × W 111+p12×W112+p21×W121+p22×W122. The numbers are not necessarily all different, and the same value may be input to multiple pixels 100.

[0089] In parallel, through the same process as above, a line 212_2 (the second column line) is connected from the pixel block 200d. The result of the sum-of-products operation, h121, is output to line 212, and the first row of pixel block 200 The output is complete.

[0090] Next, the second row of the pixel block 200 undergoes the same process as above, and the pixel block 20 0e outputs h112, which is the result of the sum-of-products operation, to the wiring 212_1. , the result of the multiplication and accumulation operation, h122, is output from the pixel block 200f to the wiring 212_2. , the output of the second row of pixel block 200 is completed.

[0091] Furthermore, the weighting coefficients in the first row of the pixel block 200 are changed, and the same process as above is carried out. By doing so, h211 and h221 can be output. By changing the weight coefficient in the th row and going through the same process as above, h212 and h222 are The above operation is repeated as necessary.

[0092] The data of the product-sum operation results output to the wirings 212_1 and 212_2 are as shown in FIG. 8(B). The signals are sequentially input to the circuit 301 as shown in the figure. The circuit 301 is a circuit that performs the calculation of the activation function. For example, For example, a comparator circuit can be used. The result of comparing the pixel value with the set threshold is output as binary data. Block 200 and circuit 301 act as elements of a neural network. It is possible.

[0093] The data output by the pixel block 200 corresponds to multi-bit image data. Since the image data is binarized in the path 301, it can be said that the image data is compressed.

[0094] The data binarized by the circuit 301 (h111', h121', h112', h122', h211', h221', h212', h222') are input to the circuit 302 in sequence.

[0095] The circuit 302 may have a configuration including, for example, a latch circuit and a shift register. This configuration allows parallel-to-serial conversion, as shown in FIG. In this way, data input in parallel can be output as serial data to the wiring 311. The connection destination of the wiring 311 is not limited. For example, it can be a neural network, a storage device, It can be connected to communication devices, etc.

[0096] 9, the circuit 302 may also include a neural network. The neural network has memory cells arranged in a matrix, and each memory cell The data output from the circuit 301 is stored in the cells in the row direction. The memory cells shown in FIG. The numbers are just examples and are not limiting.

[0097] The neural network shown in FIG. 9 is composed of memory cells 320 arranged in a matrix and and reference memory cell 325, circuit 340, circuit 350, circuit 360, and circuit 360. , circuit 370.

[0098] FIG. 10 shows an example of a memory cell 320 and a reference memory cell 325. 25 are arranged in any one row. The memory cells 320 and the reference memory cells 325 are similarly arranged. The transistor 161, the transistor 162, and the capacitor 163 are included. do.

[0099] The source or drain of the transistor 161 is connected to the gate of the transistor 162. The gate of the transistor 162 is electrically connected to one electrode of the capacitor 163. Here, either the source or the drain of the transistor 161 is connected to the The point where the gate of the capacitor 162 and one electrode of the capacitor 163 are connected is defined as a node NM.

[0100] The gate of the transistor 161 is electrically connected to the wiring WL. The electrode of the transistor 162 is electrically connected to the wiring RW. One of the terminals is electrically connected to a reference potential wiring such as a GND wiring.

[0101] In the memory cell 320, the other of the source and drain of the transistor 161 is connected to a wiring The other of the source and drain of the transistor 162 is electrically connected to the wiring WD. It is electrically connected to BL.

[0102] In the reference memory cell 325, the other of the source or drain of the transistor 161 is The source or drain of the transistor 162 is electrically connected to the wiring WDref. The other end is electrically connected to the wiring BLref.

[0103] The wiring WL is electrically connected to the circuit 330. The circuit 330 includes a decoder or a shift register. A resistor or the like can be used.

[0104] The wiring RW is electrically connected to the circuit 301. The wiring RW is electrically connected to each memory cell from the circuit 301. The binary data output to 311_1 and wiring 311_2 is written.

[0105] The wiring WD and the wiring WDref are electrically connected to the circuit 340. The circuit 340 includes: A decoder or a shift register can be used. The circuit 340 may include a converter and an SRAM. The coefficients can be output.

[0106] The wiring BL and the wiring BLref are electrically connected to the circuit 350 and the circuit 360. The circuit 350 is a current source circuit and can have the same configuration as the current source circuit 210. The circuit 360 can have the same configuration as the circuit 201, excluding the current source circuit 210. The circuit 350 and the circuit 360 obtain a signal obtained by removing the offset component from the product-sum operation result. It is possible.

[0107] The circuit 360 is electrically connected to the circuit 370. The circuit 370 has the same configuration as the circuit 301. The activation function circuit can be expressed as follows: Performs a calculation to transform the input signal according to a predefined activation function The activation function is, for example, a sigmoid function, a tanh function, a soft You can use max function, ReLU function, threshold function, etc. The converted signal is then output to the outside as output data.

[0108] As shown in FIG. 11(A), the neural network NN has an input layer IL, an output layer OL, It can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. Each HL has one or more neurons (units). It may be one layer or two or more layers. Neural networks can also be called DNNs (deep neural networks). Learning using deep neural networks can also be called deep learning.

[0109] Input data is input to each neuron in the input layer IL. The output signal of the neurons in the previous or next layer is input to each neuron in the output layer OL. The output signal of the neuron in the previous layer is input to each neuron. It can be connected to all neurons (fully connected), or it can be connected to only some neurons ( Good too.

[0110] Figure 11(B) shows an example of a neuron operation. Here, we consider a neuron N and a neuron B. The figure shows two neurons in the front layer that output signals to neuron N. Neuron N has a The output x1 of the neuron in the previous layer and the output x2 of the neuron in the previous layer are input. In Ron N, the multiplication result of output x1 and weight w1 (x1w1) and the multiplication result of output x2 and weight w2 After the sum of the calculation results (x2w2) x1w1+x2w2 is calculated, the bias b is applied as needed. are added to obtain the value a=x1w1+x2w2+b. The value a is then applied to the activation function h Thus, the neuron N outputs an output signal y=h(a+b).

[0111] In this way, the operation of a neuron involves adding the product of the output of the previous layer neuron and the weight. This multiplication and addition operation is called multiplication and addition (x1w1+x2w2 above). This may be done on software using a program, or on hardware. Good too.

[0112] In one embodiment of the present invention, a product-sum operation is performed using an analog circuit as hardware. When using analog circuits for the calculation circuit, it is necessary to reduce the circuit scale of the product-sum calculation circuit or to transfer the circuit to memory. This reduces the number of accesses, thereby improving processing speed and reducing power consumption.

[0113] The multiply-accumulate circuit preferably includes an OS transistor. Since the off-state current of the transistor is extremely small, it can be used as a transistor that constitutes the analog memory of the product-sum operation circuit. It is also possible to use both Si transistors and OS transistors for multiply-and-add operations. A calculation circuit may be configured.

[0114] In the above, in the imaging device according to one aspect of the present invention, the captured image data is processed. However, it is also possible to extract image data without processing it.

[0115] For example, in the pixel block 200c of FIG. 8A, in the above description, data p11, The sum of p12, p21, and p22 is output, but it is multiplied by any one pixel 100. By setting the weighting coefficient for the pixel to be multiplied to 1 and the weighting coefficient for the other pixels to be multiplied to 0, Image data of pixel 100 can be extracted. Also, pixel 100 with a weighting coefficient of 1 can be extracted. By sequentially selecting these, image data can be extracted from all the pixels 100.

[0116] As explained in the explanation of the flow of extracting WX from circuit 201, the difference between IR0 and IR is calculated. Here, if the weighting coefficient is set to 0, then the term consisting of WX can be extracted. Since the signals output from pixel 100 are canceled out, the weighting coefficient of pixel 100 is set to 1. If the resolution is acceptable, the overlap of all the pixels 100 can be obtained. The image data may be extracted with a coefficient of 1.

[0117] At this time, the circuit 301 has a comparator and a switch connected in parallel as shown in FIG. 12(A). It is preferable to have a configuration in which the output can be selected. The signal output from the clock 200 is input to a comparator, and the binarized signal is sent to the circuit 302. When acquiring image data, the signal output from the pixel block 200 is switched. The signal is output to the circuit 302 via a path that passes through the switch. A data may be provided.

[0118] Alternatively, as shown in FIG. 12B, the circuit 301 may be configured as a comparator and a selection circuit. The output may be connected to the circuit 302 or the circuit 306. A comparator and counter circuit can be used to configure an A / D converter. Note that the circuit 306 may be provided in the circuit 302.

[0119] Alternatively, as shown in FIG. 12C, the pixel 100 may include a transistor 108 and a transistor The transistor 108 outputs a signal corresponding to the potential of the node N. The transistor 109 can have a function of outputting a signal (image data). 00.

[0120] A gate of the transistor 108 is electrically connected to one electrode of the capacitor 104. One of the source and drain of transistor 108 is connected to the source or drain of transistor 109. The other of the source or drain of the transistor 108 is electrically connected to the other of the drain. The gate of the transistor 109 is electrically connected to a wiring 119. The other of the source and the drain of the transistor 109 is electrically connected to a wiring 120. and electrically connected to each other.

[0121] The wiring 119 can function as a signal line that controls the conduction of the transistor 109. The wiring 120 can function as an output line. The wiring 121 can function as a power supply line. For example, it can function as a high-potential power supply line.

[0122] The wiring 120 is electrically connected to the correlated double sampling circuit (CDS circuit) and the A / D converter. Alternatively, the wiring 113 can be electrically connected to the wiring 113 via a switch. In this case, the output of the transistor 105 and the output of the transistor 108 The output of the transistor 108 can be selectively input to the circuit 201. In this case, the circuit 301 can be configured as shown in FIGS. 12(A) and 12(B) to acquire image data. You can gain.

[0123] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0124] (Embodiment 2) In this embodiment, a configuration example of an imaging device according to one embodiment of the present invention will be described.

[0125] 13A illustrates an example of a pixel configuration of an imaging device. This is an example of a laminated structure of a layer 561 and a layer 562.

[0126] The layer 561 includes the photoelectric conversion element 101. The photoelectric conversion element 101 is In this way, the layer 565a, the layer 565b, and the layer 565c can be stacked.

[0127] The photoelectric conversion element 101 shown in FIG. 13(C) is a pn junction photodiode, for example, Layer 565a to p + layer 565b is an n-type semiconductor, layer 565c is an n-type semiconductor + Using type semiconductors Alternatively, layer 565a may include + p-type semiconductor layer 565b and p-type semiconductor layer 56 5c to p + Alternatively, a pin junction may be formed by using an i-type semiconductor as the layer 565b. It may be a photodiode.

[0128] The pn junction photodiode or pin junction photodiode is made of single crystal silicon. The pin junction photodiode can be formed using an amorphous silicon. It can also be formed using a thin film of crystalline silicon, microcrystalline silicon, polycrystalline silicon, etc. .

[0129] As shown in FIG. 13(D), the photoelectric conversion element 101 included in the layer 561 is A stack of a layer 566b, a layer 566c, and a layer 566d may be used. The photoelectric conversion element 101 is an example of an avalanche photodiode, and includes a layer 566a and a layer 56 6d corresponds to an electrode, and layers 566b and 566c correspond to a photoelectric conversion portion.

[0130] The layer 566a is preferably a low resistance metal layer, such as aluminum or titanium. It is possible to use tungsten, tantalum, silver or a laminate thereof.

[0131] The layer 566d is preferably formed using a conductive layer that has high transparency to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide oxide, indium-gallium-zinc oxide, or graphene can be used. The layer 566d may be omitted.

[0132] The layers 566b and 566c of the photoelectric conversion section are pn junctions in which a selenium-based material is used as the photoelectric conversion layer. The layer 566b is made of selenium, which is a p-type semiconductor. For the layer 566c, an n-type semiconductor such as gallium oxide can be used. preferable.

[0133] Photoelectric conversion elements using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In this photoelectric conversion element, avalanche multiplication is used to generate a large amount of light. In addition, selenium-based materials have a high optical absorption coefficient, This has the advantage in terms of production that the photoelectric conversion layer can be made as a thin film. The film can be formed by vacuum deposition or sputtering.

[0134] Selenium-based materials include crystalline selenium such as single crystal selenium and polycrystalline selenium, and amorphous selenium. , copper, indium, selenium compounds (CIS), or copper, indium, gallium, selenium Compounds of CIGS and the like can be used.

[0135] The n-type semiconductor is formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or These materials can be used for hole injection. It also functions as a blocking layer and can reduce dark current.

[0136] The layer 562 shown in FIG. 13(A) can be, for example, a silicon substrate. The silicon substrate has Si transistors and the like. The Si transistors are used to form pixel circuits. In addition to the circuit, a circuit for driving the pixel circuit, a circuit for reading out the image signal, an image processing circuit, etc. are provided. Specifically, the peripheral circuits (pixel 100 and reference Some or all of the circuits (such as pixel 150, circuit 201, and circuits 301 to 305) A transistor may be provided in layer 562 .

[0137] As shown in FIG. 13(B), the pixel has a laminated structure of a layer 561, a layer 563, and a layer 562. may have

[0138] Layer 563 is a layer for forming OS transistors (e.g., transistors 102, 103 of pixel 100, etc.). ) in which the layer 562 can have a Si transistor (e.g., pixel 10 It is preferable to have transistors 105, 106, etc. Some of the transistors included in the peripheral circuits described above may be provided in the layer 563 .

[0139] By adopting this configuration, the elements constituting the pixel circuit and the peripheral circuits are distributed across multiple layers, The elements can be overlapped with each other or with the peripheral circuit, so that the imaging device In the configuration of FIG. 13(B), the area of the supporting layer 562 can be reduced. The substrate may be used, and the pixel 100 and peripheral circuits may be provided on layers 561 and 563 .

[0140] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAC- An OS or the like can be used.

[0141] The semiconductor layer may be, for example, indium, zinc, and M (aluminum, titanium, gallium, Al, yttrium, zirconium, lanthanum, cerium, tin, neodymium or halide The film can be a film represented by an In-M-Zn oxide containing a metal such as fluorine.

[0142] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios were In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0143] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or This is called a highly pure intrinsic oxide semiconductor. This results in a low impurity concentration and a low defect state density. Since the SiO2 has a low SiO2 content, it can be said that the oxide semiconductor has stable characteristics.

[0144] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be carefully considered. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0145] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase, causing the semiconductor layer to become n-type. The concentrations of phosphate and carbon (obtained by secondary ion mass spectrometry) were measured at 2 × 10 18 atom s / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0146] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0147] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0148] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor, or C-Axis Aligne d and AB-plane Anchored Crystalline Oxi Semiconductor), including polycrystalline, microcrystalline, or amorphous structures. Among non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density. The defect level density is also low.

[0149] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0150] The semiconductor layer may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a CAAC structure. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0151] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This article explains the structure of the .NET composite OS.

[0152] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0153] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0154] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0155] In other words, CAC-OS is X3The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0156] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0157] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0158] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0159] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0160] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0161] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The nanoparticle-like regions are observed in the region where the metal element is the main component, and the region where In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0162] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0163] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction, the measurement region It can be seen that no orientation in the ab plane direction or the c axis direction is observed.

[0164] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped region with high brightness and the corresponding Several bright spots are observed in the ring region. Therefore, the electron diffraction pattern indicates that the CAC- The crystal structure of OS is nc(nan It can be seen that the crystalline structure is o-crystal.

[0165] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0166] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 OZ2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0167] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0168] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0169] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zn Y2 O Z2 , or InO X1The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) This can be done.

[0170] Furthermore, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0171] 14(A) is a diagram illustrating an example of a cross section of the pixel shown in FIG. 13(A). The photoelectric conversion element 101 is a pn junction photodiode with a silicon photoelectric conversion layer. The layer 562 has a Si transistor, and in FIG. 14(A) the transistors that constitute the pixel circuit are 1 shows an example of the transistors 102 and 105.

[0172] In the photoelectric conversion element 101, the layer 565a is p + layer 565b is an n-type region, layer 56 5c is n + The layer 565b can be used as a mold region. The layer 565b can also be used as a power supply line and a layer 565c. An area 536 is provided for connecting. For example, the area 536 is p + It can be considered as a type domain. can.

[0173] In FIG. 14(A), the Si transistor has a channel forming region in a silicon substrate 540. As shown in Figures 16(A) and 16(B), the silicon A fin-shaped semiconductor layer may be provided on the substrate 540. The cross section in the longitudinal direction, FIG. 16(B) corresponds to the cross section in the channel width direction.

[0174] Alternatively, as shown in FIG. 16(C), a transistor having a semiconductor layer 545 of a silicon thin film may be used. The semiconductor layer 545 may be, for example, a silicon substrate 540 on an insulating layer 546. Single crystal silicon (SOI (Silicon on Insulator)) It can be said that:

[0175] In FIG. 14A, the elements of the layer 561 and the elements of the layer 562 are electrically connected. This shows an example of a configuration in which connections are achieved by bonding technology.

[0176] The layer 561 is provided with an insulating layer 542, a conductive layer 533, and a conductive layer 534. 33 and conductive layer 534 have regions buried in insulating layer 542. Conductive layer 533 has The conductive layer 534 is electrically connected to the region 536. The surfaces of the insulating layer 542, the conductive layer 533, and the conductive layer 534 are at the same height. It has been flattened to resemble a square.

[0177] The layer 562 is provided with an insulating layer 541, a conductive layer 531, and a conductive layer 532. 31 and conductive layer 532 have regions buried in insulating layer 541. Conductive layer 531 has The conductive layer 532 is electrically connected to the source or drain of the transistor 102. In addition, the surfaces of the insulating layer 541, the conductive layer 531, and the conductive layer 532 are electrically connected to each other. The surfaces are flattened to have the same height.

[0178] Here, the conductive layer 531 and the conductive layer 533 preferably contain the same metal element as a main component. It is preferable that the conductive layer 532 and the conductive layer 534 have the same metal element as a main component. In addition, it is preferable that the insulating layer 541 and the insulating layer 542 are made of the same component. It's nice.

[0179] For example, the conductive layers 531, 532, 533, and 534 may be made of Cu, Al, Sn, Zn, W, or A. For ease of bonding, Cu, Pt, Au, etc. can be used. The insulating layers 541 and 542 are made of Al, W, or Au. Silicon nitride, silicon oxynitride, silicon nitride, titanium nitride, etc. can be used .

[0180] That is, the combination of the conductive layer 531 and the conductive layer 533 and the combination of the conductive layer 532 and the conductive layer 533 are It is preferable to use the same metal material as shown above for each of the 34 combinations. In addition, the insulating layer 541 and the insulating layer 542 are made of the same insulating material as described above. By adopting this configuration, it is possible to bond the layer 561 and the layer 562 at the boundary between them. Combinations can be made.

[0181] By this bonding, a combination of the conductive layer 531 and the conductive layer 533 and the conductive layer 53 2 and the conductive layer 534. As a result, a connection having mechanical strength between the insulating layers 541 and 542 can be obtained.

[0182] To bond metal layers together, the oxide film on the surface and the adsorption layer of impurities are removed by sputtering or other methods. The surface activated bonding method is used to bond the cleaned and activated surfaces together. Alternatively, a diffusion bonding method can be used, which uses a combination of temperature and pressure to bond surfaces together. Both of these bond at the atomic level, so they can be used not only electrically but also mechanically. Mechanically excellent bonding can also be obtained.

[0183] In addition, to bond the insulating layers together, after obtaining high flatness by polishing, etc., oxygen plasma etc. The hydrophilic treated surfaces are brought into contact with each other to temporarily bond them together, and then the final bonding is performed by dehydrating them through heat treatment. Aqueous bonding methods can be used. Hydrophilic bonding also occurs at the atomic level, so , and mechanically excellent bonding can be obtained.

[0184] When the layer 561 and the layer 562 are bonded together, the bonding surfaces are made up of a mixture of insulating and metal layers. To achieve this, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0185] For example, after polishing, the surface is cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment and then to a hydrophilic treatment. Alternatively, the surface of the metal layer may be treated with a hard metal such as Au. It is also possible to use an oxidized metal and then subject it to hydrophilic treatment. That's fine.

[0186] FIG. 14B shows a pixel layer 561 shown in FIG. 13A in which a selenium-based material is used as a photoelectric conversion layer. A cross-sectional view of a pn junction photodiode is shown. The second electrode includes layers 566b and 566c as photoelectric conversion layers, and a layer 566d as the other electrode.

[0187] In this case, layer 561 can be formed directly on layer 562. Layer 566a is a Layer 566d is electrically connected to the source or drain of transistor 102. The power supply line is electrically connected to the power supply line via the

[0188] 15(A) is a diagram illustrating an example of a cross section of the pixel shown in FIG. 13(B). The photoelectric conversion element 101 is a pn junction photodiode with a silicon photoelectric conversion layer. The layer 562 has a Si transistor, and in FIG. 15(A) the transistor that constitutes the pixel circuit is The layer 562 includes an OS transistor, and in FIG. The transistors 102 and 103 that constitute the circuit are shown as examples. The layer 561 and the layer 563 are bonded together. 1 shows an example of a configuration in which electrical connection is achieved by combining the two.

[0189] In FIG. 15A, the OS transistor has a self-aligned structure. As shown in 16(D), a non-self-aligned top-gate transistor Good too.

[0190] The transistors 102 and 103 are shown with a back gate 535. The back gate 535 may be formed as shown in FIG. In some cases, the gate electrode is electrically connected to the front gate of the transistor provided opposite to the gate electrode. Alternatively, the back gate 535 can be supplied with a fixed potential different from that of the front gate. The configuration may be as follows.

[0191] Between the region where the OS transistor is formed and the region where the Si transistor is formed, An insulating layer 543 having a function of preventing diffusion of elements is provided. Hydrogen in the insulating layer provided near the channel formation region terminates the dangling bonds of silicon. On the other hand, an insulating layer provided near the channel formation regions of the transistors 102 and 103 The hydrogen in the oxide semiconductor layer is one of factors that generate carriers in the oxide semiconductor layer.

[0192] The insulating layer 543 confines hydrogen to one layer, thereby improving the reliability of the transistor 105. In addition, the diffusion of hydrogen from one layer to another can be suppressed. This also improves the reliability of the transistors 102 and 103.

[0193] The insulating layer 543 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0194] FIG. 15(B) shows a case where a selenium-based material is used as a photoelectric conversion layer in the layer 561 of the pixel shown in FIG. 13(B). 5 is a cross-sectional view of a case where a pn junction photodiode is used. For details of the layers 561, 562, and 563, please refer to the above description. .

[0195] FIG. 17A illustrates an example in which a color filter or the like is added to a pixel of an imaging device according to one embodiment of the present invention. In this perspective view, cross sections of a plurality of pixels are also shown. An insulating layer 580 is formed on the layer 561 on which the element 101 is formed. A silicon oxide film or the like having high transparency to visible light can be used. A silicon nitride film may be laminated as the reflection film. A dielectric film such as silicon may be laminated on the insulating film.

[0196] A light-shielding layer 581 may be formed on the insulating layer 580. The light-shielding layer 581 may be formed on the upper color The light-shielding layer 581 has a function of preventing the color mixing of light passing through the filter. A metal layer such as tungsten can be used. A dielectric film having a function may be laminated.

[0197] An organic resin layer 582 is provided as a planarization film on the insulating layer 580 and the light-shielding layer 581. In addition, a color filter 583 (color filters 583a, 583b, For example, R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By applying the light, a color image can be obtained.

[0198] An insulating layer 586 or the like having a light-transmitting property to visible light is provided on the color filter 583. It is possible.

[0199] As shown in FIG. 17(B), an optical conversion layer 585 is provided instead of the color filter 583. By using such a configuration, it is possible to obtain images in various wavelength regions. The imaging device may be an imaging device.

[0200] For example, if a filter that blocks light having wavelengths shorter than visible light is used for the optical conversion layer 585, infrared In addition, the optical conversion layer 585 can be used to block light having a wavelength shorter than that of near-infrared rays. If a filter is used, it can be used as a far-infrared imaging device. By using a filter that blocks light with wavelengths greater than that of visible light, it can be used as an ultraviolet imaging device. .

[0201] In addition, if a scintillator is used for the optical conversion layer 585, the radiation used in X-ray imaging devices, etc. It can be used as an imaging device to obtain an image that visualizes the intensity of radiation such as X-rays that has passed through the subject. When radiation is incident on the scintillator, visible light and ultraviolet light are emitted by the photoluminescence phenomenon. The light is converted into light (fluorescence) such as rays. The light is then detected by the photoelectric conversion element 101. Image data can also be obtained by using an imaging device with this configuration as a radiation detector. good.

[0202] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. These include materials that emit visible and ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C Use materials such as eF3, LiF, LiI, and ZnO dispersed in resin or ceramics. can be done.

[0203] In addition, in the photoelectric conversion element 101 using a selenium-based material, radiation such as X-rays is directly converted into electric charges. Since the direct conversion can be performed, a configuration can be made in which a scintillator is not required.

[0204] Also, as shown in FIG. 17(C), a microlens array 58 is formed on the color filter 583. 4 may be provided. The light passing through each lens of the microlens array 584 is incident on the The light passes through the color filter 583 and is irradiated onto the photoelectric conversion element 101. A microlens array 584 may be provided on the optical conversion layer 585 shown in FIG. 7(B).

[0205] Below we will introduce an example of a package containing an image sensor chip and a camera module. The image sensor chip can use the configuration of the imaging device described above. do.

[0206] FIG. 18(A1) is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 410 to which an image sensor chip 450 is fixed, It has a cover glass 420 and an adhesive 430 that bonds the two together.

[0207] FIG. 18(A2) is a perspective view of the bottom surface of the package. , and has a BGA (Ball grid array) with solder balls as bumps 440. In addition to BGA, LGA (Land grid array) and PGA (Pin Grid Array) may also be included.

[0208] FIG. 18(A3) shows a package in which the cover glass 420 and the adhesive 430 are partially omitted. Electrode pads 460 are formed on the package substrate 410. The pad 460 and the bump 440 are electrically connected via a through hole. The pads 460 are electrically connected to the image sensor chip 450 by wires 470. are.

[0209] Also, Figure 18(B1) shows a camera in which an image sensor chip is housed in a lens-integrated package. 1 is a perspective view of the top surface of a camera module. A package substrate 411 for fixing a chip 451, a lens cover 421, and a lens 43 5, etc. In addition, between the package substrate 411 and the image sensor chip 451, An IC chip 490 having functions such as a driving circuit for the imaging device and a signal conversion circuit is also provided. It has a SiP (System in package) configuration.

[0210] 18(B2) is a perspective view of the appearance of the lower surface side of the camera module. The bottom and side surfaces of the package 411 are provided with lands 441 for mounting. It has a structure of a lattice no-lead package. Note that this structure is just an example. QFP (Quad flat package) and the BGA mentioned above are provided. Good too.

[0211] FIG. 18(B3) shows a diagram in which the lens cover 421 and the lens 435 are partially omitted. The land 441 is electrically connected to the electrode pad 461. The wire 461 is connected to the image sensor chip 451 or IC chip 490 by wire 471. are electrically connected.

[0212] By housing the image sensor chip in the package of the above type, it is possible to This makes it easier to mount image sensor chips on various semiconductor devices and electronic equipment. It is possible.

[0213] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0214] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of these electronic devices are shown in Figure 19.

[0215] FIG. 19(A) shows a surveillance camera, which includes a support base 951, a camera unit 952, and a protective cover 9 The camera unit 952 is provided with a rotation mechanism and can be installed on the ceiling. This allows for the capture of all surrounding images. The imaging device according to one embodiment of the present invention can be used as one of the cameras. It is a general name and does not limit the use. For example, it may have the function of a surveillance camera. The device is also called a camera or video camera.

[0216] FIG. 19B shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, The operation key 974, the lens 975, the connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring images in the video camera, one aspect of the present invention is The imaging device may include:

[0217] FIG. 19(C) shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, and a microphone 964. 63, a light emitting unit 967, a lens 965, etc. Acquiring an image with the digital camera The imaging device according to one embodiment of the present invention can be provided as one of the components for performing the imaging.

[0218] FIG. 19(D) shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, The display unit 932 has a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and can be easily attached to the body. As one of the components for acquiring images in the information terminal, The imaging device may be provided in the above embodiment.

[0219] FIG. 19(E) shows an example of a mobile phone, which includes a housing 981, a display unit 982, an operation button 983, It has an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone has a touch sensor on the display unit 982. All operations such as touching the display 982 with a finger or a stylus are performed. As one of the components for acquiring images in the mobile phone, an embodiment of the present invention is The camera may be equipped with an imaging device such as

[0220] FIG. 19(F) shows a portable data terminal, which includes a housing 911, a display portion 912, a camera 919, and the like. The display portion 912 has a touch panel function that allows input and output of information. As one of the components for acquiring images in the portable data terminal, the photographing device according to one aspect of the present invention is An imaging device may be provided.

[0221] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. [Example]

[0222] In this example, an imaging device having a configuration according to one embodiment of the present invention described in Embodiment 1 was fabricated. The results of image processing performed within the imaging device will now be described.

[0223] FIG. 20 shows a pixel circuit (corresponding to pixel 100) of the prototype imaging device. In the imaging device described above, image data (potential The structure is such that the product (WX) of the potential (X) and the weighting coefficient (potential W) is extracted. In the device, the reference pixel 150 is omitted, and double sampling is performed based on whether or not the weighting coefficient (potential W) is input. The difference is then calculated externally to extract WX.

[0224] The pixel circuit of the prototype image sensor consists of a photodiode PD, transistors Tr1 and Tr2, The configuration is as shown in Figure 20, which includes Tr3, Tr4, and Tr5. The transistor Tr3 has a configuration in which the source and drain are short-circuited, and a capacitance element (MOS The photoelectric conversion layer of the photodiode PD contains selenium. Transistors Tr1, Tr2, Tr3, Tr4, and Tr5 are OS transistors. Other specifications are shown in Table 1.

[0225] [Table 1]

[0226] TX, RS, and SE are signal potentials for driving each transistor. VPI is the power supply potential, VPD and VPI are high potentials, and VRS is low potential. This is the back gate potential for adjusting the threshold voltage of the transistors Tr1 and Tr2. W corresponds to a weighting coefficient (potential W) and is added to node N by capacitive coupling.

[0227] The operation of double sampling is as follows: First, transistors Tr1 and Tr2 are turned on. After the transistor Tr2 is turned off, the photodiode The potential of node N is changed by the operation of node PD. Next, transistor Tr1 is made non-conductive. The potential of node N is determined by supplying BW as the desired weighting factor. Tr5 is turned on to output the first image signal to the outside.

[0228] Next, BW is returned to the initial value, and the second image signal is output to the outside. The difference between the first image signal and the second image signal is calculated to extract WX. The order of signal acquisition may be reversed.

[0229] FIG. 21 shows a pixel array including the pixel PIX having the pixel circuit and the paths of various signals. It is a block diagram. WMux is a selection circuit that outputs BW, which corresponds to a weighting coefficient. , includes a transistor corresponding to the transistor 106 shown in FIG.

[0230] FIG. 22 shows the weighting coefficient (potential W) for image data (potential X: -0.2 to 1.4 V). The calculation results are shown below when the voltage is changed from 0.4 to 1.0 V. At this time, VRES is 1.2 V. From Figure 22, it was confirmed that the desired calculation was possible.

[0231] In addition, when capturing an image of a subject with a vertical stripe pattern, the weighting coefficients supplied to each pixel are as shown in FIG. The results when the directionality is given to the vertical stripes are shown in Figure 24. The rotation angle of the pattern (no rotation is 0°), the vertical axis is the digital value after A / D conversion of the output WX From Figure 24, when the direction of the vertical stripes and the directionality given to the weighting coefficients match, the output value is It was confirmed that it would grow.

[0232] Based on these results, it was assumed that patterns could be extracted from images, and this was verified. FIG. 25(A) is an image of a zebra captured with a fixed weight. 5(A), the weighting coefficient is given so as to have a vertical direction, and the weighting coefficient is given so as to have a vertical direction as shown in FIG. As shown in B), when the weighting coefficient is given so that it has a directional property in the horizontal direction, the pattern detection In Figure 25(A) and (B), the positive weighting coefficient is +0.8V, The negative weighting factor was set to -0.4V.

[0233] Figures 26(A) and (B) show the results of visualizing the extracted patterns. The result corresponds to 24(A), and it can be seen that the vertical stripes of the zebra have been extracted. Figure 26(A) corresponds to Figure 25(B), and shows that the zebra's horizontal stripes have been successfully extracted. We can see that.

[0234] From the above, it has been confirmed that image processing (image pattern recognition) can be performed using one embodiment of the present invention. I was able to confirm this. [Explanation of symbols]

[0235] 100: pixel, 100a: pixel, 100b: pixel, 100c: pixel, 100d: pixel, 1 00e: pixel, 100f: pixel, 100g: pixel, 100h: pixel, 101: photoelectric conversion element 102: transistor, 103: transistor, 104: capacitance element, 105: Transistor, 106: Transistor, 107: Transistor, 108: Transistor, 109 : transistor, 111: wiring, 111a: wiring, 111b: wiring, 112: wiring, 11 2_1: Wiring, 112_2: Wiring, 112_4: Wiring, 113: Wiring, 114: Wiring, 1 15: Wiring, 116: Wiring, 117: Wiring, 118: Wiring, 119: Wiring, 120: Wiring 121: wiring, 150: reference pixel, 151: light-shielding layer, 153: wiring, 161: transistor 162: transistor; 163: capacitance element; 200: pixel block; 200a: pixel 200b: pixel block, 200c: pixel block, 200d: pixel block 200e: pixel block, 200f: pixel block, 201: circuit, 201a: circuit , 201b: circuit, 202: capacitance element, 203: transistor, 204: transistor, 205: transistor, 206: transistor, 207: resistor element, 210: current source circuit ,211: Wiring, 212: Wiring, 212_1: Wiring, 212_2: Wiring, 213: Wiring, 213_1: Wiring, 214: Wiring, 214_1: Wiring, 214_2: Wiring, 215: Wiring ,215_1: Wiring, 215_2: Wiring, 216: Wiring, 218: Wiring, 219: Wiring, 220: circuit, 224: transistor, 253: transistor, 254: transistor, 261: transistor, 262: transistor, 300: pixel array, 301: circuit, 3 02:Circuit, 303:Circuit, 304:Circuit, 305:Circuit, 306:Circuit, 311:Wiring , 311_1: wiring, 311_2: wiring, 320: memory cell, 325: reference memory cell , 330:Circuit, 340:Circuit, 350:Circuit, 360:Circuit, 370:Circuit, 410: Package substrate, 411: package substrate, 420: cover glass, 421: lens cover 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode Pad, 470: Wire, 471: Wire, 490: IC chip, 531: Conductive layer, 53 2: conductive layer, 533: conductive layer, 534: conductive layer, 535: back gate, 536: region, 540: silicon substrate, 541: insulating layer, 542: insulating layer, 543: insulating layer, 545: semi-conductor Conductor layer, 546: insulating layer, 561: layer, 562: layer, 563: layer, 565a: layer, 565 b: layer, 565c: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 5 80: insulating layer, 581: light-shielding layer, 582: organic resin layer, 583: color filter, 583 a: Color filter, 583b: Color filter, 583c: Color filter, 584: Microlens array, 585: optical conversion layer, 586: insulating layer, 911: housing, 912: Display unit, 919: Camera, 932: Display unit, 933: Housing and wristband, 939: Camera 951: Support stand, 952: Camera unit, 953: Protective cover, 961: Housing, 9 62: Shutter button, 963: Microphone, 965: Lens, 967: Light emitter, 971: Housing, 972: Housing, 973: Display unit, 974: Operation keys, 975: Lens, 976: Connection connection part, 981: housing, 982: display part, 983: operation button, 984: external connection port, 985: Speaker, 986: Microphone, 987: Camera

Claims

[Claim 1] An imaging device having a pixel block, a first circuit, and a second circuit, the image block includes a plurality of pixels and a third circuit; the pixel and the third circuit are electrically connected via a first wiring, the pixel has a function of acquiring a first signal by photoelectric conversion, the pixel has a function of multiplying the first signal by an arbitrary magnification to generate a second signal and outputting the second signal to the first wiring; the third circuit has a function of calculating the sum of the second signals output to the first wiring to generate a third signal and outputting the third signal to the first circuit; the first circuit binarizes the third signal to generate a fourth signal, and outputs the fourth signal to the second circuit; the second circuit has a function of performing parallel-to-serial conversion of the fourth signal; the second circuit has a neural network that receives the fourth signal as input data; The imaging device has the plurality of pixels arranged in a matrix, and one of the rows is shielded from light.

Images