Solar cell and method for manufacturing the same, stacked cell, and photovoltaic module

Abstract

To provide, in the field of photovoltaic power, a solar cell and a method for manufacturing the same, a stacked cell, and a photovoltaic module.SOLUTION: The solar cell includes a substrate, a doped semiconductor layer located on the substrate, a passivation layer covering a surface of the doped semiconductor layer, and a plurality of electrodes arranged along a first direction. A second surface of the substrate is provided with a texture structure. The doped semiconductor layer is provided with a first hole penetrating the doped semiconductor layer, the first hole corresponding in a one-to-one manner with the texture structure. The texture structure is exposed from a bottom of the first hole. The passivation layer fills the first hole and covers the texture structure. The electrodes penetrate a thickness of the passivation layer so as to be in electrical contact with the doped semiconductor layer. The solar cell and the method for manufacturing the same, the stacked cell, and the photovoltaic module provided by the present embodiment can improve the photoelectric conversion efficiency of the solar cell.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present application relates to the field of photovoltaics, and more particularly to solar cells and methods of manufacturing the same, stacked cells, and photovoltaic modules. [Background technology]

[0002] Currently, with the depletion of fossil energy, solar cells are being used more and more widely as a new alternative energy source. A solar cell is a device that converts solar light energy into electrical energy. Solar cells use the principle of photovoltaic power to generate carriers, which are then extracted by electrodes, contributing to the effective use of electrical energy.

[0003] TOPCon (Tunnel Oxide Passivated Contact) cells or TBC (TOPCon-BC) cells consisting of an IBC using TOPCon technology require the creation of a passivation contact structure on the silicon surface, including an ultra-thin tunnel oxide layer and a heavily doped polycrystalline silicon layer. The chemical passivation of the tunnel oxide layer and the field passivation of the polycrystalline silicon layer significantly reduce the recombination rate of minority carriers on the silicon surface, while the heavily doped polycrystalline layer significantly improves the conductivity of majority carriers, contributing to an increase in the open-circuit voltage and backing factor of the battery.

[0004] Chemical vapor deposition (LPCVD) is the main technology for fabricating tunnel oxide layers and polycrystalline silicon layers. For example, low-pressure chemical vapor deposition (LPCVD) is currently widely used due to its advantages of low cost, high yield, and high performance of the fabricated films. However, there are some issues that may affect cell efficiency during the fabrication of the backside passivation contact structure. Summary of the Invention [Problem to be solved by the invention]

[0005] In the embodiments of the present application, a solar cell and a manufacturing method thereof, a stacked cell, and a photovoltaic module are provided, which are advantageous in improving at least the photoelectric conversion efficiency of the solar cell. [Means for solving the problem]

[0006] According to some embodiments of the present application, in one aspect of the embodiments of the present application, a solar cell is provided, the solar cell including: a substrate; a doped semiconductor layer located on the substrate; a passivation layer covering a surface of the doped semiconductor layer; and a plurality of electrodes arranged along a first direction, wherein a surface of a portion of the substrate has a textured structure; the doped semiconductor layer has a first hole penetrating the doped semiconductor layer, the first hole having a one-to-one correspondence with the textured structure, the textured structure being exposed from a bottom of the first hole; the passivation layer filling the first hole and covering the textured structure; and the electrode penetrating a thickness of the passivation layer to be in electrical contact with the doped semiconductor layer.

[0007] In some embodiments, the textured structure includes at least one protruding structure, and the number of the protruding structures corresponding to one first hole is 1 to 5.

[0008] In some embodiments, the substrate comprises first and second surfaces disposed opposite to each other, the first surface comprising a pyramidal structure, the pyramidal structure including a plurality of pyramids, and the second surface comprising a textured structure, wherein one dimension of a protrusion structure of the textured structure is equal to or smaller than one dimension of the pyramids.

[0009] In some embodiments, the range of one dimension of the protrusion structure is 1 μm to 20 μm, and the height of the protrusion structure is 1 μm to 20 μm.

[0010] In some embodiments, the second surface comprises a tower foundation structure, the tower foundation structure including a plurality of tower footings, some of the tower footings contacting adjacent tower footings.

[0011] In some embodiments, the first hole has a one-dimensional dimension ranging from 5 μm to 20 μm.

[0012] In some embodiments, the substrate comprises grooves, the grooves having a one-to-one correspondence with the first holes, and the textured structures located within the grooves.

[0013] In some embodiments, the groove has a depth of 0.1 μm to 4 μm.

[0014] In some embodiments, the doped semiconductor layer comprises at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0015] In some embodiments, the doped semiconductor layer comprises a boundary, and the number of first holes near the boundary is greater than the number of first holes away from the boundary.

[0016] In some embodiments, the solar cell further includes a dielectric layer located between the substrate and the doped semiconductor layer, the dielectric layer having a second hole corresponding to the first hole, and the textured structure being exposed from a bottom of the second hole.

[0017] In some embodiments, a portion of the electrode is located in the first hole and covers the textured structure.

[0018] In some embodiments, the second surface comprises alternating P regions and N regions, with spacing regions between the P regions and the N regions; the doped semiconductor layer comprises a first doped semiconductor layer located in the P regions and a second doped semiconductor layer located in the N regions; the electrode comprises a first electrode and a second electrode, the first electrode being in electrical contact with the first doped semiconductor layer and the second electrode being in electrical contact with the second doped semiconductor layer; the passivation layer covers the substrate surface in the spacing regions; the first doped semiconductor layer comprises first sub-holes, with the textured structure exposed from bottoms of the first sub-holes; and / or the second doped semiconductor layer comprises second sub-holes, with the textured structure exposed from bottoms of the second sub-holes.

[0019] According to some embodiments of the present application, in another aspect of the embodiments of the present application, there is provided a method for manufacturing a solar cell, the method for manufacturing a solar cell including: providing a substrate, the substrate having first and second surfaces opposite to each other; forming a doped semiconductor layer, the doped semiconductor layer being a doped semiconductor layer located on the substrate; performing a texture formation process on the first surface so that the first surface has a pyramid structure, the doped semiconductor layer having first holes penetrating the doped semiconductor layer; forming a texture structure on the second surface, the first holes corresponding one-to-one to the texture structure and the texture structure being exposed at bottoms of the first holes; forming a passivation layer, the passivation layer covering a surface of the doped semiconductor layer, the passivation layer filling the first holes and covering the texture structure; and forming a plurality of electrodes arranged along a first direction, the electrodes penetrating a thickness of the passivation layer and electrically contacting the doped semiconductor layer.

[0020] In some embodiments, the second surface comprises alternating P regions and N regions, with spacing regions between the P regions and the N regions, and before forming the doped semiconductor layer, the method further includes forming a doped conductive film, the doped conductive film covering the P regions, the N regions, and the spacing regions, and etching the substrate in the spacing regions to remove the doped conductive film located in the spacing regions.

[0021] According to some embodiments of the present application, in another aspect of the embodiments of the present application, there is further provided a stacked battery, the stacked battery including a bottom cell and a top cell, the bottom cell being the solar cell described in any of the above embodiments or a solar cell manufactured by the manufacturing method described in the above embodiments, and the top cell being located on a side of the bottom cell away from an electrode of a substrate.

[0022] According to some embodiments of the present application, in another aspect of the embodiments of the present application, there is further provided a photovoltaic module, which includes a cell string formed by connecting a plurality of solar cells described in any of the above embodiments, solar cells manufactured by the manufacturing method described in any of the above embodiments, or stacked cells described in any of the above embodiments, a sealing adhesive film for covering a surface of the cell string, and a cover plate for covering a surface of the sealing adhesive film remote from the cell string. [Effects of the Invention]

[0023] The technical solutions provided in the embodiments of the present application have at least the following advantages:

[0024] In the solar cell provided in this embodiment, the surface of the substrate has a textured structure, and first holes are formed in the doped semiconductor layer, with the first holes corresponding to the textured structure one-to-one and the textured structure exposed at the bottom of the first holes. The textured structure can enhance internal reflection in the substrate and reduce light loss in the solar cell. The first holes act as light trapping structures, enhancing internal reflection of incident light within the doped semiconductor layer and improving cell efficiency. A passivation layer is filled in the first holes, which can provide secondary passivation for the substrate. The passivation layer and the doped semiconductor layer simultaneously provide passivation for the substrate, thereby reducing surface defects in the substrate and improving the photoelectric conversion efficiency of the solar cell.

[0025] In addition, the doping semiconductor layer has first holes, which correspond one-to-one to the textured structure, and the passivation layer fills the first holes. The combination of the doping semiconductor layer, passivation, textured structure, and first holes ensures the passivation performance of the solar cell, and the substrate surface has several light-trapping structures to increase the internal reflectivity, improve the short-circuit current and open-circuit voltage, and ultimately increase the cell efficiency. [Brief explanation of the drawings]

[0026] One or more embodiments are illustratively described in corresponding figures in the accompanying drawings, but these illustrative descriptions are not intended to limit the embodiments, and unless otherwise specified, the figures in the accompanying drawings are not limited to scale. In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without any creative effort. [Figure 1] FIG. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. [Figure 2] FIG. 2 is an enlarged view of part C in FIG. [Figure 3] FIG. 3 is a diagram showing a cross-sectional structure taken along A1-A2 in FIG. [Figure 4] FIG. 4 is a diagram showing the structure of a doped semiconductor layer of a solar cell provided in one embodiment of the present application. [Figure 5] FIG. 5 is a diagram showing various structures of the first hole of the solar cell provided in one embodiment of the present application. [Figure 6] FIG. 6 is a diagram showing a surface structure of one of the doped semiconductor layers of the solar cell provided in one embodiment of the present application. [Figure 7] FIG. 7 is a diagram illustrating the structure of the first hole of the solar cell provided in one embodiment of the present application. [Figure 8] FIG. 8 is a diagram illustrating the configuration of a protrusion structure of a solar cell provided in one embodiment of the present application. [Figure 9] FIG. 9 is a diagram showing the structure of a substrate of a solar cell provided in one embodiment of the present application. [Figure 10] FIG. 10 is a diagram showing another cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 11] FIG. 11 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. [Figure 12] FIG. 12 is an enlarged view of part D in FIG. [Figure 13] FIG. 13 is a diagram showing a cross-sectional structure taken along B1-B2 in FIG. [Figure 14] FIG. 14 shows the structure of a solar cell corresponding to the steps in the method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 15] FIG. 15 shows the structure of a solar cell corresponding to the steps in the method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 16] FIG. 16 shows the structure of a solar cell corresponding to the steps in the method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 17] FIG. 17 shows the structure of a solar cell corresponding to the steps in the method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 18] FIG. 18 shows the structure of a solar cell corresponding to the steps in the method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 19] FIG. 19 shows the structure of a solar cell corresponding to the steps in the method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 20] FIG. 20 shows the structure of a solar cell corresponding to the steps in the method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 21] FIG. 21 is a diagram showing the structure of a stacked battery provided in one embodiment of the present application. [Figure 22] FIG. 22 is a diagram illustrating the structure of a photovoltaic module provided in one embodiment of the present application. [Figure 23] FIG. 23 is a diagram showing a cross-sectional structure taken along M1-M2 in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0027] As can be seen from the background art, the photoelectric conversion efficiency of current solar cells is poor.

[0028] In the solar cell provided in this embodiment, the surface of the substrate has a textured structure, and first holes are formed in the doped semiconductor layer, with the first holes corresponding to the textured structure one-to-one and the textured structure exposed at the bottom of the first holes. The textured structure can enhance internal reflection in the substrate and reduce light loss in the solar cell. The first holes act as light trapping structures, enhancing internal reflection of incident light within the doped semiconductor layer and improving cell efficiency. A passivation layer is filled in the first holes, which can provide secondary passivation for the substrate. The passivation layer and the doped semiconductor layer simultaneously provide passivation for the substrate, thereby reducing surface defects in the substrate and improving the photoelectric conversion efficiency of the solar cell.

[0029] In addition, the doping semiconductor layer has first holes, which correspond one-to-one to the textured structure, and the passivation layer fills the first holes. The combination of the doping semiconductor layer, passivation, textured structure, and first holes ensures the passivation performance of the solar cell, and the substrate surface has several light-trapping structures to increase the internal reflectivity, improve the short-circuit current and open-circuit voltage, and ultimately increase the cell efficiency.

[0030] Hereinafter, each embodiment of the present application will be described in detail in conjunction with the drawings. However, as will be understood by those skilled in the art, although many technical details are proposed in the embodiments of the present application to help readers better understand the present application, the technical solutions claimed for protection in the embodiments of the present application can be realized without these technical details and various changes and modifications based on the following embodiments.

[0031] FIG. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. FIG. 2 is an enlarged view of portion C in FIG. 1. FIG. 3 is a diagram showing a cross-sectional structure along A1-A2 in FIG. 2. FIG. 4 is a diagram showing the structure of a doped semiconductor layer of a solar cell provided in one embodiment of the present application. FIG. 5 is a diagram showing various structures of a first hole of a solar cell provided in one embodiment of the present application. FIG. 6 is a diagram showing one surface structure of a doped semiconductor layer of a solar cell provided in one embodiment of the present application. FIG. 7 is a diagram showing the structure of a first hole of a solar cell provided in one embodiment of the present application. FIG. 8 is a diagram showing the configuration of a protrusion structure of a solar cell provided in one embodiment of the present application. FIG. 9 is a diagram showing the structure of a substrate of a solar cell provided in one embodiment of the present application.

[0032] According to some embodiments of the present application, as shown in FIGS. 1 to 3 , in one aspect of the embodiments, a solar cell is provided, the solar cell including: a substrate 100; a doped semiconductor layer 112 located on the substrate 100; a passivation layer 113 covering a surface of the doped semiconductor layer 112; and a plurality of electrodes 114 arranged along a first direction X, wherein a portion of the surface of the substrate 100 has a textured structure 14 (see FIG. 7 ); the doped semiconductor layer 112 has first holes 1120 penetrating the doped semiconductor layer 112, the first holes 1120 corresponding one-to-one to the textured structures 14, the textured structures 14 being exposed from bottoms of the first holes 1120; the passivation layer 113 filling the first holes 1120 and covering the textured structures 14; and the electrodes 114 penetrating the passivation layer 113 to be in electrical contact with the doped semiconductor layer 112.

[0033] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material may be composed of a single element, such as silicon or germanium. Here, the elemental semiconductor material may be in a monocrystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a monocrystalline state and an amorphous state is called a microcrystalline state), and for example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0034] In some embodiments, the material of substrate 100 may be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium gallide, perovskites, cadmium telluride, copper indium selenide, etc. Substrate 100 may be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0035] In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. An N-type semiconductor substrate is doped with an N-type doping element, which may be any of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). A P-type semiconductor substrate is doped with a P-type doping element, which may be any of Group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0036] In some embodiments, the substrate 100 has a first surface 11 and a second surface 12 disposed opposite each other. The first surface 11 of the substrate 100 may be the front surface and the second surface 12 may be the back surface, or the first surface of the substrate may be the back surface and the second surface may be the front surface. The solar cell is a single-sided cell, with the front surface serving as the light-receiving surface to receive incident light and the back surface serving as the backlight surface. In some embodiments, the solar cell is a double-sided cell, with both the first and second surfaces of the substrate serving as light-receiving surfaces to receive incident light. Here, the backlight surface can also receive incident light, but its light-receiving efficiency is weaker than that of the light-receiving surface.

[0037] In the solar cell shown in Figure 3 and in Figures 10 and 13 described below, the first surface of the substrate is the front surface, and the second surface of the substrate is the back surface. In the solar cell shown in Figure 3 and in Figures 10 and 13 described below, an improvement is made to the back surface of the solar cell, and a doped semiconductor layer 112 is located on the back surface of the substrate, improving the passivation performance of the back surface of the solar cell. In the solar cell shown in Figure 3 and in Figures 10 and 13 described below, the upward-facing side of the substrate is the light-receiving surface, and the downward-facing side of the substrate is the backlight surface.

[0038] In some embodiments, the doped semiconductor layer 112 may be located on the first surface. The doped semiconductor layer 112 may also be located on the front surface, and this embodiment is not limited to whether the doped semiconductor layer 112 is located on the first surface or the second surface, but may only be located on the surface of the substrate. Take the solar cell shown in Figure 3 and the following Figures 10 and 13 as examples.

[0039] In some embodiments, the solar cell further includes a dielectric layer 111 located between the substrate 100 and the doped semiconductor layer 112, the dielectric layer 111 having a second hole 1110 corresponding to the first hole 1120, and the surface of the substrate 100 being exposed from the bottom of the second hole 1110.

[0040] The dielectric layer 111 is generally thin to ensure carrier tunneling and allow carriers to tunnel through the dielectric layer 111 into the doped semiconductor layer 112. Because the thickness of the dielectric layer 111 is less than 15 nm, the process of forming the first hole 1120 may involve removing the dielectric layer 111 exposed through the first hole 1120, so the second hole 1110 is formed in the dielectric layer 111. In some embodiments, the process of forming the first hole does not cause overall etching damage to the dielectric layer, so there is no second hole in the dielectric layer. This also falls within the scope of protection of the embodiments of the present application.

[0041] In some embodiments, a passivation contact structure is formed between the dielectric layer 111 and the doped semiconductor layer 112, and the doped semiconductor layer 112 can form a band bending at the surface of the substrate 100, and the dielectric layer 111 generates an asymmetric offset in the bands at the surface of the substrate 100, so that the potential barrier for majority carriers among the carriers is lower than the potential barrier for minority carriers among the carriers. This allows majority carriers to easily pass through the dielectric layer 111 and perform quantum tunneling, but minority carriers have difficulty passing through the dielectric layer 111, thereby realizing selective carrier transport.

[0042] The dielectric layer 111 also exhibits a chemical passivation effect. Specifically, the presence of interface state defects at the interface between the substrate 100 and the dielectric layer 111 increases the interface state density on the front surface of the substrate 100. The increased interface state density promotes the recombination of photogenerated carriers, increasing the backing factor, short-circuit current, and open-circuit voltage of the solar cell and improving the photoelectric conversion efficiency of the solar cell. By positioning the dielectric layer 111 on the second surface 12 of the substrate 100, the dielectric layer 111 can exhibit a chemical passivation effect on the surface of the substrate 100. Specifically, by saturating the dangling bonds of the substrate 100, the defect state density of the substrate 100 is reduced, the number of recombination centers in the substrate 100 is reduced, and the carrier recombination rate is reduced.

[0043] In some embodiments, the thickness of the dielectric layer 111 is 0.5 nm to 5 nm. The thickness of the dielectric layer 111 ranges from 0.5 nm to 1.3 nm, from 1.3 nm to 2.6 nm, from 2.6 nm to 4.1 nm, or from 4.1 nm to 5 nm. When the thickness of the dielectric layer 111 is within any of the above ranges, majority carriers can easily quantum tunnel through the dielectric layer 111 due to the thin thickness of the dielectric layer 111, but minority carriers have difficulty passing through the dielectric layer 111, thereby realizing selective transport of carriers.

[0044] In some embodiments, the doped semiconductor layer 112 exhibits a field passivation effect, specifically, by forming an electrostatic field at the surface of the substrate 100 that is directed toward the interior of the substrate 100, causing minority carriers to escape from the interface, reducing the minority carrier concentration, and slowing down the carrier recombination rate at the interface of the substrate 100, thereby increasing the open circuit voltage, short circuit current, and backing factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0045] The doped semiconductor layer 112 may be doped with the same type of doping element as the substrate 100, for example, the type of doping element in the substrate 100 is N-type, and the doped semiconductor layer 112 is doped with N-type doping element.

[0046] In some embodiments, doped semiconductor layer 112 comprises at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0047] As shown in FIGS. 4 and 5 , in some embodiments, the first hole 1120 has a first dimension d ranging from 5 μm to 20 μm. The first hole 1120 may have a first dimension d ranging from 5 μm to 8 μm, 8 μm to 13 μm, 13 μm to 15.2 μm, 15.2 μm to 17 μm, or 17 μm to 20 μm. When the first hole 1120 has a first dimension d ranging within any of the above ranges, the first hole 1120 is suitable. This minimizes the effect of the first hole 1120 on the strength of the doped semiconductor layer 112 itself, effectively preventing delamination between the doped semiconductor layer 112 and the substrate 100. When the first hole 1120 has a first dimension d ranging within the above ranges, the first hole 1120 is filled with the passivation layer 113 without forming a cavity, thereby improving the efficiency of the solar cell.

[0048] In some embodiments, when the first dimension d of the first holes 1120 is within any of the above ranges, the number and the first dimension d of the first holes 1120 may be used to provide space for thermal deformation of the doped semiconductor layer 112 and the passivation layer 113, thereby reducing the probability of curling of the solar cell.

[0049] In some embodiments, FIG. 5 illustrates various structures of the first hole of the solar cell provided in one embodiment of the present application. As shown in FIG. 5, the shape of the first hole 1120 may be circular, rectangular, elliptical, or triangular, as shown in the figure.

[0050] In some embodiments, the first dimension d of the first hole 1120 may be the diameter of a circle, the length of a side of a rectangle or triangle, or the long side of an ellipse, and further, the first dimension d may be the line connecting the two corners.

[0051] In some embodiments, the doped semiconductor layer 112 is doped with an N-type doping element, and the first hole 1120 has a first dimension d of 30 μm or less, a first dimension d of 28 μm or less, a first dimension d of 23 μm or less, or a first dimension d of 20 μm or less.

[0052] In some embodiments, the doped semiconductor layer 112 is doped with an N-type doping element, and the N-type doping element unifies the crystal grains of the doped semiconductor layer 112, resulting in a single crystal structure. The doped semiconductor layer 112 with the N-type doping element has small grain sizes, many and uniform grain boundaries, and a large one-dimensional dimension d of the formed first hole 1120.

[0053] In some embodiments, the doped semiconductor layer 112 is doped with a P-type doping element, and the first hole 1120 has a first dimension d of 10 μm or less. The first hole 1120 has a first dimension d of 8 μm or less, a first dimension d of 5.8 μm or less, or a first dimension d of 4.3 μm or less. When the first hole 1120 has a first dimension d within any of the above ranges, the first hole 1120 has a small diameter, so that the first hole 1120 has little effect on the strength of the doped semiconductor layer 112 itself and does not cause delamination between the doped semiconductor layer 112 and the substrate 100. When the first hole 1120 has a first dimension d within any of the above ranges, the first hole 1120 does not form a cavity and is filled with the passivation layer 113, thereby improving the cell efficiency of the solar cell.

[0054] In some embodiments, the doped semiconductor layer 112 is doped with a P-type doping element, and the compatibility between the P-type doping element and the dielectric layer 111 is good. For example, when the P-type doping element is B, B can form a B-O bond and a B-Si bond with silicon and oxygen, resulting in good contact performance between the doped semiconductor layer 112 and the dielectric layer 111 and between the doped semiconductor layer 112 and the dielectric layer, a small edge area, and a small one-dimensional dimension d of the formed first hole 1120.

[0055] As shown in Figures 6 and 9, the second surface also includes a tower base structure, which includes a plurality of tower bases 124, some of which are in contact with adjacent tower bases 124. The tower base structure refers to a polished pyramidal structure without a top, and the height of the tower base structure is less than 1 / 3 of the height of the original pyramidal structure.

[0056] As shown in FIGS. 3 and 7 , the textured structure 14 and the first holes 1120 form a light-trapping structure, and the textured structure 14 can enhance the internal reflection of sunlight and improve the light absorption of the doped semiconductor layer and the substrate. The textured structure 14 includes at least one protrusion structure 123, and the number of protrusion structures 123 corresponding to one first hole 1120 is 1 to 5. This can increase the internal reflection of incident light and improve photoelectric conversion efficiency. If the number of protrusion structures 123 within the first hole 1120 is within the above range, the dimensions of the protrusion structures 123 are relatively large, the surface defects of the substrate 100 are small, and the recombination centers of the substrate 100 are small, so the passivation layer 113 can provide good passivation for the substrate 100.

[0057] In some embodiments, the texture structure 14 may include a pyramidal structure, a prism structure, or a protrusion structure. The pyramidal structure includes an inverted pyramid and a pyramid. In Figure 7, the texture structure 14 includes two pyramids.

[0058] In some embodiments, the electrode 114 is in contact with the protruding structure 123. This increases the contact area between the protruding structure 123 and the electrode 114, improves the contact performance between the electrode 114 and the protruding structure 123, and increases the yield of the battery.

[0059] 8, the range of the one-dimensional dimension S of the protrusion structure 123 is 1 μm to 20 μm, and the height h1 of the protrusion structure 123 is 1 μm to 20 μm. In some embodiments, the one-dimensional dimension S of the protrusion structure 123 may be 1 μm to 5 μm, 5 μm to 8 μm, 8 μm to 13 μm, 13 μm to 15 μm, or 15 μm to 20 μm. The height h1 of the protrusion structure 123 may be 1 μm to 4 μm, 4 μm to 10 μm, 10 μm to 14 μm, 14 μm to 16 μm, or 16 μm to 20 μm.

[0060] In some embodiments, the passivation layer 113 may be a single layer structure or a multilayer structure, and the material of the passivation layer 113 may be one or more of materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0061] In some embodiments, the solar cell further includes an anti-reflective layer located on the surface of the passivation layer, and an electrode passes through the anti-reflective layer and the passivation layer to electrically contact the doped semiconductor layer. The anti-reflective layer is used to reduce or eliminate light reflection on the surface of the solar cell, which can increase the amount of light transmission through the surface of the solar cell and reduce or eliminate stray light in the system. Materials for the anti-reflective layer include silicon nitride and silicon oxynitride.

[0062] 10 is a diagram showing another cross-sectional structure of a solar cell provided in an embodiment of the present application, in which the substrate has grooves, the grooves correspond one-to-one to the first holes, and the textured structure is located in the grooves.

[0063] In some embodiments, the depth h of the groove 1000 is between 0.1 μm and 4 μm. The depth h of the groove 1000 may be between 0.1 μm and 0.5 μm, between 0.5 μm and 2 μm, between 2 μm and 2.6 μm, between 2.6 μm and 3.2 μm, or between 3.2 μm and 4 μm.

[0064] In some embodiments, the doped semiconductor layer 112 is doped with an N-type doping element and the depth h of the trench 1000 is less than 3 μm. In some embodiments, the doped semiconductor layer 112 is doped with a P-type doping element and the depth h of the trench 1000 is less than 4 μm.

[0065] In some embodiments, the depth h of the grooves 1000 within any of the above ranges can prevent breakdown of the substrate 100 due to the grooves 1000 penetrating through the substrate 100, and the grooves 1000 can act as light trapping structures to enhance internal reflection of the solar cell.

[0066] 4, the doped semiconductor layer 112 includes a boundary 115, and the number of first holes 1120 near the boundary is greater than the number of first holes 1120 away from the boundary 115. This means that a greater number of first holes 1120 near the boundary 115 means that a relatively smaller number of first holes 1120 away from the boundary 115, and therefore a smaller number of electrodes located within the first holes 1120, can increase the collection area of the electrodes 114. The greater the number of first holes 1120 near the boundary 115, the weaker the doped semiconductor layer 112 near the boundary 115, and the correspondingly smaller probability of edge damage.

[0067] 6 and 9, the spacing between the first holes 1120 near the boundary 115 is discontinuous, so that the first holes 1120 have a small dimension d, the doped semiconductor layer 112 is also present between the first holes 1120, and the edge regions 122 of the substrate also have the doped semiconductor layer 112 for collecting carriers in the substrate and ultimately for collection in the electrode.

[0068] In some embodiments, having more first holes 1120 closer to the boundary 115 can correspondingly reduce the total doping concentration corresponding to the doped semiconductor layer 112 closer to the boundary 115, thereby reducing the probability of edge leakage.

[0069] In some embodiments, some of the electrodes 114 are located in the first holes 1120 and cover the textured structure 14. The electrodes 114 are in direct electrical contact with the substrate 100 through the first holes 1120, and can directly collect carriers generated in the substrate 100. The first holes 1120 can serve as extra conductive channels, which can improve the current collection efficiency in the edge region 122 and offset the low efficiency caused by the pinhole effect in the dielectric layer 111.

[0070] As shown in FIG. 3, the solar cell further includes an emitter 101 located on the first surface 11, a first passivation layer 103 covering the surface of the emitter 101, and a thin grid 104 penetrating the first passivation layer 103 and making electrical contact with the emitter 101.

[0071] In some embodiments, the emitter 101 and the substrate 100 are made of the same material, and the emitter 101 and the substrate 100 can be formed by doping the same original substrate. The type of doping element in the emitter 101 is different from the type of doping element in the substrate 100. A portion of the original substrate is doped, and the doped portion of the original substrate serves as the emitter, and the remaining original substrate serves as the substrate.

[0072] In some embodiments, the emitter 101 is a doped layer formed on the first surface of the substrate, which is a semiconductor layer doped with an N-type doping element or a P-type doping element formed by a deposition process, and the semiconductor layer may be silicon, germanium, or polycrystalline silicon.

[0073] In some embodiments, the surface of the first surface 11 comprises a first textured structure 13 , which includes a plurality of protruding structures 123 .

[0074] In some embodiments, the first passivation layer 103 may be a single layer structure or a multilayer structure, and the material of the first passivation layer 103 may be one or more of materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0075] In some embodiments, the material of the first passivation layer 103 is the same as the material of the passivation layer 113 , and the first passivation layer 103 is manufactured in the same manufacturing process as the passivation layer 113 .

[0076] In some embodiments, either the electrode 114 or the fine grid 104 may be sintered with a burn-through paste. A method for forming the electrode 114 includes using a silk screen printing technique to print a metal paste on a portion of the surface of the passivation layer 113. A method for forming the fine grid 104 includes using a silk screen printing technique to print a metal paste on a portion of the surface of the first passivation layer 103. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

[0077] In some embodiments, when the solar cell is a bifacial TOPCon cell structure, the solar cell further includes a tunnel dielectric layer located on the first surface and a polycrystalline silicon doped layer located on the surface of the tunnel dielectric layer, and the type of doping element in the polycrystalline silicon doped layer is different from the type of doping element in the substrate, for example, an N-type doping element is doped in the substrate and a P-type doping element is doped in the polycrystalline silicon doped layer.

[0078] In some embodiments, the dielectric layer and the doped semiconductor layer are located on a first surface of the substrate, and the tunnel dielectric layer and the doped polysilicon layer are located on a second surface of the substrate.

[0079] In some embodiments, the dielectric layer and the doped semiconductor layer are located on a first surface of the substrate, and further include an intrinsic dielectric layer, an amorphous silicon doped layer, and a transparent conductive layer, wherein the intrinsic dielectric layer is located on a second surface of the substrate, the amorphous silicon doped layer is located on a surface of the intrinsic dielectric layer, the transparent conductive layer is located on a surface of the amorphous silicon doped layer, the electrode is in electrical contact with the doped semiconductor layer, and the thin grid is in electrical contact with the transparent conductive layer.

[0080] As shown in FIG. 3, the first surface comprises a pyramidal structure 13, which includes a plurality of pyramids 105, and the second surface comprises a textured structure 14, the one-dimensional dimension of the protruding structure 123 of the textured structure 14 being equal to or smaller than the one-dimensional dimension of the pyramids 105.

[0081] In the solar cell provided in this embodiment, the surface of the substrate 100 has a textured structure 14, and the doped semiconductor layer 112 has first holes 1120, which correspond one-to-one to the textured structure 14 and are exposed at the bottom of the first holes 1120. The textured structure 14 can enhance the internal reflection of the substrate 100 and reduce light loss in the solar cell. The first holes 1120 act as light trapping structures, enhancing the internal reflection of incident light within the doped semiconductor layer 112 and improving cell efficiency. The first holes 1120 are filled with a passivation layer 1123, which provides secondary passivation for the substrate 100. The passivation layer 113 and the doped semiconductor layer 112 simultaneously passivate the substrate 100, reducing surface defects in the substrate 100 and improving the photoelectric conversion efficiency of the solar cell.

[0082] In addition, the doped semiconductor layer 112 has first holes 1120, which correspond one-to-one to the textured structure 14, and the first holes 1120 are filled with a passivation layer 113. The combination of the doped semiconductor layer 112, the passivation layer 113, the textured structure 14 and the first holes 1120 ensures the passivation performance of the solar cell, and at the same time, the surface of the substrate 100 has some light-trapping structures to enhance internal reflectivity, improve short-circuit current and open-circuit voltage, and thus increase cell efficiency.

[0083] In another aspect of this embodiment, another solar cell is further provided. In the above embodiment, an electrode having a first polarity and a fine grid having a second polarity are located on the first surface and the second surface of the substrate, respectively, but in another embodiment, a first electrode having a first polarity and a second electrode having a second polarity are both located on the second surface of the substrate. Technical features that are the same as or corresponding to those of the above embodiment will not be described again here.

[0084] FIG. 11 is a diagram showing the structure of a solar cell provided in one embodiment of the present application, FIG. 12 is an enlarged view of portion D in FIG. 11, and FIG. 13 is a diagram showing the cross-sectional structure along the B1-B2 cross section of FIG. 12.

[0085] As shown in FIGS. 11 to 13, the solar cell includes a substrate 200, a doped semiconductor layer located on the substrate 200, a passivation layer 213 covering the surface of the doped semiconductor layer, and a plurality of electrodes arranged along a first direction X, wherein a portion of the surface of the substrate 200 has a textured structure, the doped semiconductor layer has first holes penetrating the doped semiconductor layer, the first holes correspond one-to-one to the textured structure, the textured structure is exposed from the bottom of the first holes, the passivation layer 213 fills the first holes and covers the textured structure, and the electrodes penetrate the passivation layer 213 to be in electrical contact with the doped semiconductor layer.

[0086] In some embodiments, the substrate 200 includes opposing first and second surfaces 21, 22, the surface of the first surface 21 including a pyramidal structure 23, the pyramidal structure 23 including a plurality of pyramids 205. The first surface 21 includes a front surface field (FSF) whose dopant ions have the same conductivity type as the dopant ions of the substrate 200, and the field passivation effect can be utilized to reduce the surface minority carrier concentration, decrease the surface recombination velocity, reduce the series resistance, and increase the electron transport capacity.

[0087] In some embodiments, second surface 22 comprises alternating P and N regions with spaced apart regions gap between the P and N regions.

[0088] In some embodiments, as shown in FIG. 13, the gap region is flush with the P region and the N region, i.e., the substrate is not etched, and the P region and the N region are isolated from each other by some isolation film layers, which may be passivation layers.

[0089] Note that the above-mentioned gap being flush with the P and N regions means that the difference in height between the top surface of the gap and the P and N regions is within 1 μm, and that the gap is not absolutely flush.

[0090] In some embodiments, the gap is lower than the P and N regions, and the gap comprises a trench extending from the second surface toward the first surface, where the trench is used to achieve automatic isolation between regions of different conductivity types and prevent heavily doped P and N regions in an IBC (Interdigitated Back Contact) cell from forming a PN junction, which could cause leakage current and affect cell efficiency.

[0091] In some embodiments, the surface of the gap may be a polished surface structure, and the surface of the gap may be a second textured structure, where the roughness of the first textured structure is equal to or greater than the roughness of the second textured structure.

[0092] Here, "roughness" refers to the arithmetic mean of the absolute values of the vertical deviations of the peaks and valleys within a sampled length from the average horizontal line, which is set at a single sampled length. Roughness can be measured by the comparative method, the light section method, the interferometry method, and the probe scanning method.

[0093] In some embodiments, the doped semiconductor layer includes a first doped semiconductor layer 244 located in a P region and a second doped semiconductor layer 254 located in an N region, the electrodes include a first electrode 2141 and a second electrode 2142, the first electrode 2141 is in electrical contact with the first doped semiconductor layer 244, the second electrode 2142 is in electrical contact with the second doped semiconductor layer 254, a passivation layer 213 covers the substrate surface in the gap region gap, the first doped semiconductor layer 244 has a first sub-hole 2121, and the textured structure is exposed from the bottom of the first sub-hole 2121, and / or the second doped semiconductor layer 254 has a second sub-hole 2122, and the textured structure is exposed from the bottom of the second sub-hole 2122.

[0094] In some embodiments, one dimension of the first subhole 2121 is smaller than one dimension of the second subhole 2122 .

[0095] In some embodiments, the dielectric layer includes a first dielectric layer 243 and a second dielectric layer 253, with the first doped semiconductor layer 244 located in the first dielectric layer 243 and the second doped semiconductor layer 254 located in the second dielectric layer 253.

[0096] In some embodiments, there is a second hole 2110 in the first dielectric layer and a second hole 2110 in the second dielectric layer.

[0097] In some embodiments, the first dielectric layer 243 and the second dielectric layer 253 may be the same as the dielectric layer 111 in the previous embodiment, i.e., the first dielectric layer 243 and the second dielectric layer 253 are tunnel dielectric layers. Similarly, the first doped semiconductor layer 244 and the second doped semiconductor layer 254 may be the doped semiconductor layer 112 in the previous embodiment. The difference is that the first doped semiconductor layer 244 is doped with a P-type doping element, and the second doped semiconductor layer 254 is doped with an N-type doping element.

[0098] In some embodiments, the first electrode 2141 and the second electrode 2142 may refer to the electrode 114 in the previous embodiment, the pyramid structure 23, the pyramid 205, and the first passivation layer 203 on the first surface 21 may refer to the pyramid structure 13, the pyramid 105, and the first passivation layer 103 in the previous embodiment, and the passivation layer 213 may refer to the passivation layer 113 in the previous embodiment, and will not be described again here.

[0099] 14 to 20 are diagrams showing cross-sectional structures of a solar cell corresponding to each step in a method for manufacturing a solar cell provided in one embodiment of the present application. In this embodiment, the solar cell provided in another embodiment is taken as an example.

[0100] 14, the manufacturing method includes providing a substrate 200. The substrate 200 has a first surface 22 and a second surface 22 disposed opposite each other.

[0101] In some embodiments, second surface 22 comprises P regions and N regions with a spacer region gap between adjacent P and N regions.

[0102] 14 to 18, the manufacturing method includes forming a doped semiconductor layer, which is a doped semiconductor layer located on a substrate.

[0103] 14 to 17, the manufacturing method includes forming a doped conductive film, which covers the P region, the N region and the gap region, and etching the substrate in the gap region to remove the doped conductive film located in the gap region.

[0104] 14, the manufacturing method includes forming a first dielectric film 225 located on the second surface 22 of the substrate, and forming a first doped semiconductor film located on the surface of the first dielectric film 225. Here, while forming the first doped semiconductor film 226, a first silicon-doped glass layer 227 is formed on the first surface of the substrate 200 and the surface of the first doped semiconductor film 226.

[0105] In some embodiments, thermal oxidation or chemical deposition is used to form the first dielectric film 225. The first dielectric film 225 is located in the P region, the N region, and the gap region.

[0106] In some embodiments, a manufacturing method for forming the first doped semiconductor film 226 includes a first deposition, a second deposition, and a high-temperature oxidation step, where in the first deposition, the deposition gas includes silane, the flow rate of which is controlled to 100-1,000 sccm, and the deposition temperature of which is controlled to 400-700°C to form an intrinsic semiconductor film. In the second deposition, the deposition gas includes a doping source gas and oxygen gas, the flow rate of which is controlled to 100-3,000 sccm, and the deposition temperature of which is controlled to 700-1,000°C to form a doped semiconductor film. In the high-temperature oxidation step, the gas includes nitrogen gas and oxygen gas, and in the process, the doped semiconductor film is converted into the first doped semiconductor film 226 and a first silicon-doped glass layer 227 is formed on the first surface of the substrate 200 and the surface of the first doped semiconductor film 226.

[0107] As shown in FIG. 15, the manufacturing method includes removing the first silicon-doped glass layer 227 in the spacing region and the N region. Using the first silicon-doped glass layer 227 in the first surface and the P region as a doping source, a high-temperature diffusion process is performed to diffuse the P-type doping element in the first silicon-doped glass layer 227 located in the P region into the first doped semiconductor film 226 located in the P region, and dope the P-type doping element in the first silicon-doped glass layer 227 on the first surface into a part of the substrate near the first surface. After the high-temperature diffusion process, the first silicon-doped glass layer 227 in the first surface and the P region is removed.

[0108] In some embodiments, during the process of removing the first silicon-doped glass layer 227, the etchant may etch the first doped semiconductor film 226 and the first dielectric film 225, thereby removing the first doped semiconductor film 226 and the first dielectric film 225.

[0109] As shown in FIG. 16, the manufacturing method includes forming a second dielectric film 228 and a second doped semiconductor film 229 on the surface of the N region and the surface of the first doped semiconductor film 226, where, simultaneously with forming the second doped semiconductor film 229, a second silicon-doped glass layer 235 is formed on the first surface of the substrate 200 and the surface of the second doped semiconductor film 229.

[0110] As shown in FIG. 17 , the manufacturing method includes removing the second silicon-doped glass layer 235 on the first surface and the second silicon-doped glass layer 235 in the P region, removing the second dielectric film 228 and the second doped semiconductor film 229 in the P region, and making the first dielectric film and the first doped semiconductor film in the P region into a first dielectric layer 243 and a first doped semiconductor layer 244, respectively, and making the second dielectric film and the second doped semiconductor film in the N region into a second dielectric layer 253 and a second doped semiconductor layer 254, respectively.

[0111] 18, the manufacturing method includes forming a protective layer 282 on the first doped semiconductor layer 244, the second doped semiconductor layer 254, and the gap region 282. The protective layer 282 may be a shielding gas, a water film, a mask layer, or the like.

[0112] 19, the manufacturing method includes performing a texturing process on the first surface so that the first surface has a pyramid structure, the doped semiconductor layer has first holes penetrating the doped semiconductor layer, and the second surface has a textured structure, the first holes correspond one-to-one to the textured structure, and the textured structure is exposed from the bottom of the first holes.

[0113] In some embodiments, the texture formation process may include chemical etching. For example, the substrate 200 may be cleaned with a mixed solution of potassium hydroxide and hydrogen peroxide. Specifically, the concentration ratio of the potassium hydroxide and hydrogen peroxide solutions may be controlled to form pyramidal structures with a desired shape. In some embodiments, the pyramidal structures may be formed by laser etching, mechanical methods, plasma etching, or other methods. In laser etching, the parameters of the laser process may be controlled to form a textured structure with a desired shape.

[0114] In some embodiments, the etching process of the etching solution is controlled to form first sub-holes 2121 in a portion of the first doped semiconductor layer 244 and second sub-holes 2122 in the second doped semiconductor layer 254 during the process of removing and texturing the first silicon-doped glass layer 227 and the second silicon-doped glass layer 235.

[0115] In some embodiments, as shown in FIG. 20 , before the doped semiconductor film is formed, the substrate is provided with impurities 281, and the thickness of the formed doped semiconductor film is thin, so that the thickness of the doped semiconductor film located above the impurities 281 is thin, and during the process of forming a texture on the first surface of the substrate, an unavoidable etching effect is caused on the doped semiconductor layer, forming a first hole and a texture structure.

[0116] In some embodiments, due to limitations of the protective layer, the doped semiconductor layer cannot be effectively protected across the entire surface. During the texturing process on the substrate, the etchant etches the substrate surface, thus forming the textured structure.

[0117] In some embodiments, the process parameters for the texture formation process include a mixture of sodium hydroxide solution, additives, and an aqueous solution, a reaction temperature of 50°C to 100°C, and a reaction time of 200 to 1200 seconds, where the concentration of the sodium hydroxide solution is 1% to 5%, and the concentration of the additive is 0.01% to 1%.

[0118] In some embodiments, the first holes may be formed during texturing, or may be formed during either the removal of first silicon-doped glass layer 227 or the removal of second silicon-doped glass layer 235, or may be formed by etching during both or all of these.

[0119] In some embodiments, the gaps may be formed before, after, or during the texturing process. The gaps may have a surface morphology resembling a pyramid structure.

[0120] 13, the manufacturing method includes forming a passivation layer 213 and forming a plurality of electrodes arranged along a first direction, where the passivation layer 213 covers the surface of the doped semiconductor layer, the passivation layer fills the first holes, and covers the textured structure, and the electrodes penetrate the thickness of the passivation layer to electrically contact the doped semiconductor layer.

[0121] As shown in FIG. 13, the manufacturing method includes forming a passivation layer 213 covering the surfaces of the first sub-hole 2121, the second sub-hole 2122, the gap region gap, the first doped semiconductor layer 244, and the second doped semiconductor layer 254.

[0122] As shown in FIG. 13, the manufacturing method includes forming a first passivation layer 203 overlying a first surface 21 of a substrate 200 .

[0123] In some embodiments, the passivation layer 213 and the first passivation layer 203 are formed in the same manufacturing process.

[0124] 13, the manufacturing method includes forming a first electrode 2141 and a second electrode 2142. Here, the first electrode 2141 penetrates the passivation layer 213 to electrically contact the first doped semiconductor layer 244, and the second electrode 2142 penetrates the passivation layer 213 to electrically contact the second doped semiconductor layer 254.

[0125] In some embodiments, a method for manufacturing the first electrode 2141 and the second electrode 2142 includes printing a metal paste on a portion of the surface of the passivation layer 213 using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. The metal paste is then sintered. The metal paste may include a highly corrosive component, such as glass powder, which corrodes the passivation layer 213 during the sintering process. The metal paste penetrates the passivation layer 213 and makes electrical contact with the first doped semiconductor layer 244 to form the first electrode 2141 and with the second doped semiconductor layer 254 to form the second electrode 2142.

[0126] Accordingly, Fig. 21 is a diagram showing the structure of a tandem solar cell provided in one embodiment of the present application. As shown in Fig. 21, this embodiment provides a tandem solar cell including a bottom cell 350 and a top cell 360, where the bottom cell 350 may be a solar cell as shown in one embodiment (Figs. 1 to 10), and the top cell 360 is located on the surface of an emitter or a surface of a doped semiconductor layer in the bottom cell 350.

[0127] In some embodiments, the stacked battery includes first grid lines 366 of a first polarity and second grid lines 367 of a second polarity, with the first grid lines 366 in electrical contact with the top cells 360 and the second grid lines 367 in electrical contact with the bottom cells 350.

[0128] In some embodiments, there is an interface layer 361 between the top cell and the bottom cell, and the interface layer 361 fills the first hole 1120 .

[0129] It should be noted that the stacked cell in the present embodiment only shows two layers of solar cells, and those skilled in the art can install three or more layers of solar cells according to actual needs.

[0130] In some embodiments, the top cell 360 may be a perovskite solar cell that includes a stack of a first transport layer 362, a perovskite substrate 363, a second transport layer 364, a transparent conductive layer 365, and an anti-reflective layer (not shown), where the first transport layer faces the bottom cell.

[0131] In some embodiments, the first transport layer can be one of an electron transport layer or a hole transport layer, and the second transport layer can be the other of an electron transport layer or a hole transport layer.

[0132] FIG. 22 is a diagram showing the structure of a photovoltaic module provided in one embodiment of the present application, and FIG. 23 is a diagram showing the cross-sectional structure along the M1-M2 cross section of FIG.

[0133] In some embodiments, as shown in Figures 22 and 23, another aspect of this embodiment further provides a photovoltaic module including a cell string formed by connecting a plurality of solar cells according to any of the above embodiments, a sealing adhesive film for covering the surface of the cell string, and a cover plate for covering the surface of the sealing adhesive film away from the cell string.

[0134] Specifically, in some embodiments, multiple battery cells may be electrically connected to each other by connection members 409, and the connection members 409 may be welded to the main grids 264 of the battery cells.

[0135] In some embodiments, there is no space between the battery cells, i.e., the battery cells overlap each other.

[0136] In some embodiments, welding is performed between the connection member and a sub-grid in the battery cell, the sub-grid including a first electrode 2141 and a second electrode 2142. In some embodiments, welding is performed between the connection member and a bus bar 264 in the battery cell, the main grid including a first main grid and a second main grid, the first main grid welded to the first electrode 2141 and the second main grid welded to the second electrode 2142.

[0137] In some embodiments, the sealing adhesive film includes a first sealing adhesive film and a second sealing adhesive film, where the first sealing adhesive film covers one of the front and back surfaces of the solar cell, and the second sealing adhesive film covers the other of the front and back surfaces of the solar cell. Specifically, at least one of the first sealing adhesive film and the second sealing adhesive film may be an organic sealing adhesive film such as a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0138] Before lamination processing, there is a boundary between the first sealing adhesive film and the second sealing adhesive film, and after lamination processing, when the photovoltaic module is formed, the concepts of the first sealing adhesive film and the second sealing adhesive film no longer exist; in other words, the first sealing adhesive film and the second sealing adhesive film are integrated to form a sealing adhesive film 47.

[0139] In some embodiments, the cover plate 48 may be a light-transmitting cover plate, such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 48 facing the sealing adhesive film 47 may be textured, which can improve the utilization efficiency of incident light. The cover plate 48 includes a first cover plate and a second cover plate, where the first cover plate faces the first sealing adhesive film and the second cover plate faces the second sealing adhesive film, or the first cover plate faces one side of the solar cell and the second cover plate faces the other side of the solar cell.

[0140] Those skilled in the art will understand that the above embodiments are specific examples of realizing the present application, but that various changes in form and details are possible in practice without departing from the scope of the present application. Since anyone skilled in the art can make changes and modifications without departing from the spirit and scope of the present application, the scope of protection of the present application should be based on the scope limited by the claims.

Claims

1. The semiconductor device includes a substrate, a doped semiconductor layer located on the substrate, a passivation layer covering a surface of the doped semiconductor layer, and a plurality of electrodes arranged along a first direction, the substrate has a first surface and a second surface disposed opposite to each other, the first surface or the second surface of the substrate has a textured structure, the doped semiconductor layer has a first hole penetrating the doped semiconductor layer, the first hole corresponds to the textured structure one-to-one, and the textured structure is exposed from a bottom of the first hole; the passivation layer fills the first holes and covers the textured structure; the electrode extends through the thickness of the passivation layer and is in electrical contact with the doped semiconductor layer; A solar cell characterized by:

2. the textured structure includes at least one protrusion structure, and the number of the protrusion structures corresponding to one first hole is 1 to 5; The solar cell according to claim 1 .

3. the first surface has a pyramid structure, the pyramid structure including a plurality of pyramids; the second surface has a textured structure, and one dimension of a protrusion structure of the textured structure is equal to or smaller than one dimension of the pyramids; The solar cell according to claim 1 .

4. The range of one-dimensional dimensions of the protrusion structure is 1 μm to 20 μm, and the height of the protrusion structure is 1 μm to 20 μm. The solar cell according to claim 2 .

5. The second surface comprises a tower foundation structure, the tower foundation structure including a plurality of tower foundations, some of the tower foundations being in contact with adjacent tower foundations. The solar cell according to claim 3 .

6. The range of one dimension of the first hole is 5 μm to 20 μm. The solar cell according to claim 1 .

7. the substrate has grooves, the grooves correspond one-to-one to the first holes, and the textured structure is located within the grooves; The solar cell according to claim 1 .

8. The depth of the groove is 0.1 μm to 4 μm. The solar cell according to claim 7 .

9. the doped semiconductor layer comprises at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer; The solar cell according to claim 1 .

10. the doped semiconductor layer has a boundary, and the number of first holes near the boundary is greater than the number of first holes away from the boundary; The solar cell according to claim 1 .

11. the dielectric layer is located between the substrate and the doped semiconductor layer, and the dielectric layer has a second hole corresponding to the first hole, and the textured structure is exposed from a bottom of the second hole. The solar cell according to claim 1 .

12. a portion of the electrode is located in the first hole and covers the textured structure; The solar cell according to claim 1 .

13. the second surface comprises alternating P regions and N regions, with spacing regions between the P regions and the N regions; the doped semiconductor layer comprises a first doped semiconductor layer located in the P region and a second doped semiconductor layer located in the N region; the electrode comprises a first electrode and a second electrode, the first electrode being in electrical contact with the first doped semiconductor layer and the second electrode being in electrical contact with the second doped semiconductor layer; the passivation layer covers the substrate surface in the spacing regions; the first doped semiconductor layer comprises first sub-holes, with the textured structure exposed from bottoms of the first sub-holes; and / or the second doped semiconductor layer comprises second sub-holes, with the textured structure exposed from bottoms of the second sub-holes. The solar cell according to claim 3 .

14. providing a substrate, the substrate having oppositely disposed first and second surfaces; forming a doped semiconductor layer, the doped semiconductor layer being located on a first surface or a second surface of the substrate; performing a texture forming process on the first surface so that the first surface has a pyramid structure, wherein the doped semiconductor layer has a first hole penetrating the doped semiconductor layer, and the texture structure is formed on the second surface, the first hole corresponds one-to-one to the texture structure, and the texture structure is exposed from a bottom of the first hole; forming a passivation layer, the passivation layer covering a surface of the doped semiconductor layer, the passivation layer filling the first holes and covering the textured structure; forming a plurality of electrodes arranged along a first direction, the electrodes penetrating a thickness of the passivation and electrically contacting the doped semiconductor layer; A method for manufacturing a solar cell comprising the steps of:

15. the second surface includes P regions and N regions alternately arranged, and there are space regions between the P regions and the N regions; and before forming the doped semiconductor layer, the method further includes forming a doped conductive film, the doped conductive film covering the P regions, the N regions, and the space regions; and etching the substrate in the space regions to remove the doped conductive film located in the space regions. The method for manufacturing a solar cell according to claim 14 .

16. a bottom cell and a top cell, wherein the bottom cell is a solar cell according to any one of claims 1 to 13 or a solar cell manufactured by the manufacturing method according to claim 14; The top cell is located on a side of the bottom cell away from the electrode of the substrate. A stacked battery characterized by:

17. a cell string formed by connecting a plurality of solar cells according to any one of claims 1 to 13, solar cells manufactured by the manufacturing method according to any one of claims 14 to 15, or stacked batteries according to claim 16; a sealing adhesive film for covering the surface of the cell string; a cover plate for covering a surface of the sealing adhesive film away from the cell string, A photovoltaic module characterized by:

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