Semiconductor device and method for fabricating the same

Abstract

To provide a semiconductor device with the improved degree of integration and a method for fabricating the same.SOLUTION: A semiconductor device of the present embodiment includes: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines disposed separately from and over the plurality of first conductive lines and extending in a second direction intersecting the first direction; and a plurality of memory cells overlapping intersection areas between the first conductive lines and the second conductive lines, respectively. The plurality of memory cells include a plurality of first memory cells each including a first memory pattern and a first selector pattern disposed on the first memory pattern, and a plurality of second memory cells each including a second selector pattern and a second memory pattern disposed on the second selector pattern. In each of the first direction and the second direction, one or more of the first memory cells and one or more of the second memory cells may be alternately arranged.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] This patent document relates to semiconductor technology, and more particularly to a semiconductor device having a cross-point structure and a method for manufacturing the same.

[0002] [CROSS-REFERENCE TO PRIORITY CLAIM AND RELATED APPLICATION] This application claims the benefit of Korean Patent Application No. 10-2024-0018785, filed on February 7, 2024, which is incorporated herein by reference in its entirety. [Background technology]

[0003] In recent years, the miniaturization, low power consumption, high performance, and diversification of electronic devices have led to a demand for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices, and research into this field is ongoing. Such semiconductor devices can store data by utilizing the property of switching between different resistance states depending on the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electronic fuses (E-fuses). Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a semiconductor device with improved integration density and a method for manufacturing the same, and the present invention simplifies and facilitates the manufacturing process of the semiconductor device. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment of the present invention for solving the above problem comprises a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines arranged on the plurality of first conductive lines and extending in a second direction intersecting the first direction, and a plurality of memory cells each overlapping an intersection region between the first conductive lines and the second conductive lines, wherein the plurality of memory cells comprise a first memory cell having a first memory pattern and a first selector pattern arranged on the first memory pattern, and a second memory cell having a second selector pattern and a second memory pattern arranged on the second selector pattern, and one or more of the first memory cells and one or more of the second memory cells can be arranged alternately in each of the first direction and the second direction.

[0006] Furthermore, a manufacturing method of a semiconductor device according to one embodiment of the present invention for solving the above problem includes the steps of forming a plurality of first conductive lines extending in a first direction; forming a plurality of memory cells on the plurality of first conductive lines, the memory cells comprising a first memory cell having a first memory pattern and a first selector pattern arranged on the first memory pattern, and a second memory cell having a second selector pattern and a second memory pattern arranged on the second selector pattern; and forming a plurality of second conductive lines on the plurality of memory cells, the second conductive lines extending in a second direction intersecting the first direction, wherein one or more of the first memory cells and one or more of the second memory cells can be arranged alternately in each of the first direction and the second direction. [Effects of the Invention]

[0007] According to the embodiments of the present invention, the integration degree of the semiconductor device can be improved and the manufacturing process can be simplified. [Brief explanation of the drawings]

[0008] [Figure 1A] 1 is an exemplary diagram illustrating a semiconductor device according to some implementations of the present disclosure. [Figure 1B]1B is a view of the semiconductor device taken along line A1-A1' in FIG. 1A. [Figure 1C] 1B is a view of the semiconductor device taken along line C1-C1' in FIG. 1A. [Figure 1D] 1 is a cross-sectional view illustrating an example of a first memory pattern 120A or a second memory pattern 120B based on some implementations of the present disclosure. [Figure 2A] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 2B] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 3A] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 3B] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 4] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 5A] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 5B] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 6] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 7A] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 7B] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 8A] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 8B]10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 9] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 10A] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 10B] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 11] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 12A] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. [Figure 12B] 10A to 10C are exemplary diagrams illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Various embodiments will now be described in detail with reference to the accompanying drawings.

[0010] The drawings are not necessarily drawn to scale, and in some instances, the proportions of at least some of the structures depicted in the drawings may be exaggerated to clearly illustrate features of the embodiments. When the drawings or detailed description disclose a multilayer structure having two or more layers, the relative positions and order of the layers as shown reflect a particular embodiment only and are not intended to limit the scope of the present invention; the relative positions and order of the layers may vary. Furthermore, the drawings or detailed description of a multilayer structure may not reflect all layers present in a particular multilayer structure (e.g., one or more additional layers may exist between two layers shown). For example, when a first layer is shown on a second layer or on a substrate in a multilayer structure in the drawings or detailed description, it may not only represent that the first layer can be formed directly on the second layer or on the substrate, but also represent that one or more other layers exist between the first layer and the second layer or the first layer and the substrate.

[0011] 1A to 1C are diagrams for explaining an example of a semiconductor device according to one embodiment of the present invention, in which FIG. 1A shows a plan view, FIG. 1B shows a cross-sectional view along line A1-A1' in FIG. 1A, and FIG. 1C shows a cross-sectional view along line C1-C1' in FIG. 1A.

[0012] 1A to 1C, the semiconductor device of this embodiment may include a substrate 100, a plurality of first conductive lines 110 formed on the substrate 100 and extending in a first direction, a plurality of second conductive lines 140 formed separately on the first conductive lines 110 and extending in a second direction intersecting the first direction, and a plurality of memory cells MCA and MCB overlapping the intersection regions between the first conductive lines 110 and the second conductive lines 140. In the example illustrated in FIGS. 1B and 1C, the memory cells MCA and MCB are located below the second conductive lines 140 and above the first conductive lines 110 and are connected to the first conductive lines 110 and the second conductive lines 140. Herein, the first and second directions may correspond to a horizontal direction substantially parallel to the top surface of the substrate 100 and may be substantially perpendicular to each other. A direction substantially perpendicular to the top surface of the substrate 100 will hereinafter be referred to as a vertical direction, in comparison with the horizontal direction.

[0013] The substrate 100 may include a semiconductor material such as silicon. In addition, desired substructures (not shown) may be formed in the substrate 100. For example, a driving circuit for driving the first conductive line 110 and / or the second conductive line 140 may be formed in the substrate 100.

[0014] The first conductive lines 110 may be spaced apart from one another in the second direction and positioned at the same level as one another in the vertical direction. The first conductive lines 110 may include various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), or combinations thereof.

[0015] The second conductive lines 140 may be spaced apart from one another in a first direction and positioned at the same level as one another in a vertical direction. The second conductive lines 140 may include various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), or combinations thereof.

[0016] The plurality of memory cells MCA, MCB may include a first memory cell MCA and a second memory cell MCB. The first memory cell MCA may include a first memory pattern 120A and a first selector pattern 130A on the first memory pattern 120A, and the second memory cell MCB may include a second selector pattern 130B and a second memory pattern 120B on the second selector pattern 130B. In the vertical direction, the first memory pattern 120A and the second selector pattern 130B may be located at substantially the same level, and the second memory pattern 120B and the first selector pattern 130A may be located at substantially the same level. In such an implementation, the bottom and top surfaces of the first memory pattern 120A may be located at substantially the same level as the bottom and top surfaces of the second selector pattern 130B, and the bottom and top surfaces of the second memory pattern 120B may be located at substantially the same level as the bottom and top surfaces of the first selector pattern 130A.

[0017] Here, one or more first memory cells MCA and one or more second memory cells MCB may be alternately arranged along each of the first and second directions. While the present embodiment illustrates an example in which two first memory cells MCA and two second memory cells MCB are alternately arranged in each of the first and second directions, the present disclosure is not limited thereto, and the number of first memory cells MCA and the number of second memory cells MCB may be variously modified. Furthermore, in a third direction intersecting the first and second directions, a plurality of first memory cells MCA may be arranged in a row, and a plurality of second memory cells MCB may be arranged in a row. Here, the third direction may be on the same plane as the horizontal direction and may correspond to a diagonal direction, for example, a direction at an angle of approximately 45 degrees to each of the first and second directions. When the distance between the centers of a first memory cell MCA and a second memory cell MCB adjacent to each other in the first direction is defined as a first distance P1 and the distance between the centers of two first memory cells MCA adjacent to each other in the first direction is defined as a second distance P2, the second distance P2 may be greater than the first distance P1. For example, the second distance P2 may be approximately twice the first distance P1. Although not shown, the distance between the centers of two second memory cells MCB adjacent to each other in the first direction may be substantially the same as the second distance P2. Also, although not shown, the distance between the centers of a first memory cell MCA and a second memory cell MCB adjacent to each other in the second direction may be substantially the same as the first distance P1, and the distance between the centers of two first memory cells MCA adjacent to each other in the second direction and the distance between the centers of two second memory cells MCB adjacent to each other in the second direction may each be substantially the same as the second distance P2. When the distance between the centers of two first memory cells MCA adjacent to each other in the third direction is a third distance P3, the third distance P3 may be greater than the first distance P1 and less than the second distance P2. For example, the third distance P3 may correspond to approximately √2 times the first distance P1.Although not shown, the distance between the centers of two second memory cells MCB adjacent in the third direction can be substantially the same as the third distance P3.

[0018] The first memory pattern 120A and the second memory pattern 120B may be portions for storing data in the first memory cell MCA and the second memory cell MCB, respectively. For example, the first memory pattern 120A and the second memory pattern 120B may correspond to variable resistance elements that store different data by switching between different resistance states. For example, the first memory pattern 120A and the second memory pattern 120B may have a single-layer structure or a multi-layer structure including various materials used in RRAM, PRAM, FRAM, MRAM, etc., such as metal oxides (e.g., transition metal oxides, perovskite-based materials), phase-change materials (e.g., chalcogenide-based materials), ferroelectric materials, and ferromagnetic materials. Although different hatching is used to distinguish the first memory pattern 120A from the second memory pattern 120B in the drawings, the first memory pattern 120A and the second memory pattern 120B may be substantially identical. For example, each of the first memory pattern 120A and the second memory pattern 120B may include the same magnetic tunnel junction structure. This will be described in more detail with reference to FIG. 1D.

[0019] 1D is a cross-sectional view illustrating an example of the first memory pattern 120A or the second memory pattern 120B. Therefore, the example illustrated in FIG. 1D can be applied to at least one of the first memory pattern 120A or the second memory pattern 120B.

[0020] As shown in FIG. 1D, the first memory pattern 120A or the second memory pattern 120B may include a magnetic tunnel junction structure having a stacked structure of a first electrode layer 121, a fixed layer 123, a tunnel barrier layer 125, a free layer 127, and a second electrode layer 129.

[0021] The pinned layer 123 has a fixed magnetization direction and can be compared with the magnetization direction of the free layer 127, and may also be referred to as a reference layer. The free layer 127 has a changeable magnetization direction and can store different data, and may also be referred to as a storage layer. In this embodiment, the pinned layer 123 and the free layer 127 may have magnetization directions substantially perpendicular to the surface of the layer, the magnetization direction of the pinned layer 123 is fixed in a top-to-bottom direction, and the magnetization direction of the free layer 127 may be variable between a top-to-bottom direction and a bottom-to-top direction. However, the present disclosure is not limited thereto. In other embodiments, the magnetization direction of the pinned layer 123 may be fixed in a bottom-to-top direction. Alternatively, in other embodiments, the pinned layer 123 and the free layer 127 may have magnetization directions substantially parallel to the surface of the layer. The tunnel barrier layer 125 is interposed between the pinned layer 123 and the free layer 127 to physically separate them and enable tunneling of electrons between the pinned layer 123 and the free layer 127 in response to a voltage or current applied to the magnetic tunnel junction structure. The pinned layer 123 and the free layer 127 may each have a single-layer structure or a multi-layer structure including a ferromagnetic material. For example, the pinned layer 123 and the free layer 127 may each include at least one of an alloy mainly containing Fe, Ni, or Co, such as an Fe-Pt alloy, an Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, an Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, or a Co-Fe-B alloy, or at least one of a Co / Pt stacked structure or a Co / Pd stacked structure. The tunnel barrier layer 125 may have a single-layer structure or a multi-layer structure including an insulating material. By way of example, the tunnel barrier layer 125 may include insulating oxides such as MgO, CaO, SrO, TiO, VO, and NbO.

[0022] Each of the first electrode layer 121 and the second electrode layer 129 is configured to transmit voltage or current and may include various conductive materials, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), or combinations thereof. Each of the first electrode layer 121 and the second electrode layer 129 may also function to assist the formation process of the magnetic tunnel junction structure or improve the characteristics of the magnetic tunnel junction structure, as needed, and therefore may also be referred to as a capping layer, hard mask layer, underlayer, seed layer, etc.

[0023] Such a magnetic tunnel junction structure can store different data by switching between different resistance states depending on a voltage or current applied across its upper and lower ends. More specifically, when the magnetization direction of the free layer 127 is changed to be parallel to the magnetization direction of the fixed layer 123 by a voltage or current applied to the magnetic tunnel junction structure, the magnetic tunnel junction structure can have a low resistance state and store data "1," for example. On the other hand, when the magnetization direction of the free layer 127 is changed to be antiparallel to the magnetization direction of the fixed layer 123 by a voltage or current applied to the magnetic tunnel junction structure, the magnetic tunnel junction structure can have a high or low resistance state and store data "0," for example. In other implementations, when the magnetic tunnel junction structure has a high resistance state, data "1" can be stored, and when the magnetic tunnel junction structure has a low resistance state, data "0" can be stored.

[0024] As long as the magnetic tunnel junction structure includes the fixed layer 123, the free layer 127, and the tunnel barrier layer 125 interposed therebetween, the layer structure of the magnetic tunnel junction structure may be modified in various ways. For example, the magnetic tunnel junction structure may further include one or more layers for improving the characteristics of the magnetic tunnel junction structure. Alternatively, for example, at least one of the first electrode layer 121 and the second electrode layer 129 may be omitted. Alternatively, for example, the positions of the fixed layer 123 and the free layer 127 may be reversed.

[0025] 1A to 1C, the first selector pattern 130A can function to control access to the first memory pattern 120A while preventing or reducing current leakage that may occur between first memory cells MCA that share the first conductive line 110 or the second conductive line 140. The second selector pattern 130B can function to control access to the second memory pattern 120B while preventing or reducing current leakage that may occur between second memory cells MCB that share the first conductive line 110 or the second conductive line 140. In such an implementation, each of the first selector pattern 130A and the second selector pattern 130B has a threshold switching characteristic and can selectively switch between two electrical conductive states: (1) an electrically non-conductive state in which current is blocked or little current flows when the magnitude of the voltage supplied to its upper and lower ends is below a predetermined threshold voltage, and (2) an electrically conductive state in which current flows rapidly when the supplied voltage exceeds the predetermined threshold voltage. Thus, each of the first selector pattern 130A and the second selector pattern 130B can be turned on above the threshold voltage and turned off below the threshold voltage.

[0026] Each of the first selector pattern 130A and the second selector pattern 130B may include an OTS (Ovonic Threshold Switching) material such as a diode or chalcogenide-based material, an MIEC (Mixed Ionic Electronic Conducting) material such as a metal-containing chalcogenide-based material, an MIT (Metal Insulator Transition) material such as NbO2 or VO2, or a tunneling insulating material having a relatively wide bandgap such as SiO2 or Al2O3.

[0027] Alternatively, each of the first selector pattern 130A and the second selector pattern 130B may include an insulating material containing a dopant implanted by, for example, ion implantation. Here, the insulating material may include a silicon-containing insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, an insulating metal oxide, an insulating metal nitride, or a combination thereof. The dopant may function to capture conductive carriers moving within the insulating material or to create trap sites that provide a path for the captured conductive carriers to move again. To form such trap sites, various elements that create energy levels within the insulating material that can accommodate conductive carriers may be used as dopants. For example, if the insulating material includes a silicon-containing insulating material, the dopant may include a substance having a valence different from that of silicon, such as aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), or a combination thereof. Alternatively, if the insulating material includes an insulating metal oxide or an insulating metal nitride, the dopant may include a substance having a valence different from that of the metal of the metal oxide or metal nitride, or silicon. For example, the first selector pattern 130A or the second selector pattern 130B may include silicon dioxide (SiO2) doped with arsenic (As). When a voltage equal to or greater than the threshold voltage is applied to such a first selector pattern 130A or second selector pattern 130B, conductive carriers move through trap sites, thereby realizing an on state in which current flows through the first selector pattern 130A or second selector pattern 130B, and when the voltage applied to the first selector pattern 130A or second selector pattern 130B is reduced to below the threshold voltage, conductive carriers do not move, thereby realizing an off state in which no current flows.

[0028] Although different hatching is used in the drawings to distinguish the first selector pattern 130A from the second selector pattern 130B, in some implementations, the first selector pattern 130A and the second selector pattern 130B may be substantially identical. For example, each of the first selector pattern 130A and the second selector pattern 130B may include arsenic-doped silicon dioxide, and the arsenic concentration of the first selector pattern 130A and the arsenic concentration of the second selector pattern 130B may be substantially identical to each other.

[0029] Each of the first memory cell MCA and the second memory cell MCB may have a columnar shape overlapping an intersection region between the first conductive line 110 and the second conductive line 120. Also, each of the first memory pattern 120A and the first selector pattern 130A of the first memory cell MCA may have a columnar shape, and each of the second memory pattern 120B and the second selector pattern 130B of the second memory cell MCB may have a columnar shape. In the present embodiment, the first memory pattern 120A and the first selector pattern 130A have sidewalls that are aligned with each other to form a columnar first memory cell MCA, and the second memory pattern 120B and the second selector pattern 130B have sidewalls that are aligned with each other to form a columnar second memory cell MCB. However, the present disclosure is not limited to this. As another example, while the first memory pattern 120A and the first selector pattern 130A have sidewalls that are aligned with each other, the pillar shape of the first memory cell MCA may be variously modified into an elliptical cylinder, a rectangular cylinder, etc., and while the second memory pattern 120B and the second selector pattern 130B have sidewalls that are aligned with each other, the pillar shape of the second memory cell MCB may be variously modified into an elliptical cylinder, a rectangular cylinder, etc. Here, the pillar shapes of the first memory cell MCA and the second memory cell MCB may be the same. Alternatively, as another example, while the sidewalls of the first memory pattern 120A and the first selector pattern 130A are not aligned with each other, they may have different pillar shapes, and while the sidewalls of the second memory pattern 120B and the second selector pattern 130B are not aligned with each other, they may have different pillar shapes. In some implementations, the columnar shapes of the first memory pattern 120A and the second memory pattern 120B can be identical to each other. In some other implementations, the columnar shapes of the first selector pattern 130A and the second selector pattern 130B can be identical to each other.

[0030] The semiconductor device described above can provide various advantages over the semiconductor device of the comparative example.

[0031] In the semiconductor device of the comparative example, all memory cells may have the same layer structure. For example, all memory cells in the semiconductor device of the comparative example may have a structure in which a selector pattern is located on a memory pattern, similar to the first memory cell MCA described above. Alternatively, all memory cells in the semiconductor device of the comparative example may have a structure in which a memory pattern is located on a selector pattern, similar to the second memory cell MCB described above. As a result, all memory patterns may be located at the same level in the vertical direction. In this case, the pitch of the memory cells in the comparative example, i.e., the distance between the centers of two adjacent memory cells, may be the same as the pitch of the memory patterns. Reducing the memory cell pitch is essential for high integration of semiconductor devices. In this case, if the memory patterns are located at the same level in the vertical direction, reducing the memory cell pitch also reduces the memory pattern pitch. Reducing the memory pattern pitch may increase the difficulty of an etching process for forming the memory patterns. For example, if the memory pattern includes a magnetic tunnel junction structure, difficulties such as a reduced etchable angle may occur during an IBE (Ion Beam Etching) process used to etch the magnetic tunnel junction structure.

[0032] In this embodiment, the first memory cell MCA and the second memory cell MCB have inverted layer structures, allowing the first memory pattern 120A and the second memory pattern 120B to be located at different levels in the vertical direction. In this case, the pitch of the first memory pattern 120A and the pitch of the second memory pattern 120B can be significantly increased in the same area compared to the semiconductor device of the comparative example. For example, if the pitch of the memory patterns in the semiconductor device of the comparative example corresponds to the first distance P1, the pitch of the first memory pattern 120A in the semiconductor device of this embodiment corresponds to the second distance P2, and the pitch of the second memory pattern 120B in the semiconductor device of this embodiment corresponds to the second distance P2. As a result, the difficulty of the etching process for forming the first memory pattern 120A and the second memory pattern 120B can be reduced. For example, if each of the first memory pattern 120A and the second memory pattern 120B includes a magnetic tunnel junction structure, the etchable angle may increase during the IBE process for forming the first memory pattern 120A and the second memory pattern 120B.

[0033] Furthermore, in this embodiment, the second selector pattern 130B may be located between two adjacent first memory patterns 120A in each of the first and second directions, and the first selector pattern 130A may be located between two adjacent second memory patterns 120B. In this case, when the first and second selector patterns 130A and 130B are formed using a manufacturing method described below, the process is easy and damage to the first and second selector patterns 130A and 130B due to etching can be prevented.

[0034] 2A to 12B are diagrams illustrating a semiconductor device and a manufacturing method thereof according to another embodiment of the present invention. FIGS. 2A, 3A, 5A, 7A, 8A, 10A, and 12A are plan views. FIGS. 2B, 3B, 5B, 7B, 8B, 10B, and 12B are cross-sectional views taken along line A2-A2′ in FIGS. 2A, 3A, 5A, 7A, 8A, 10A, and 12A, respectively. FIGS. 4, 6, 9, and 11 are cross-sectional views illustrating the steps between FIGS. 3B and 5B, between FIGS. 5B and 7B, between FIGS. 8B and 10B, and between FIGS. 10B and 12B, respectively. Detailed descriptions of parts that are substantially the same as those in the above-described embodiment will be omitted.

[0035] First, the manufacturing method will be described.

[0036] 2A and 2B, a plurality of first conductive lines 210 extending in a first direction may be formed on a substrate 200. The first conductive lines 210 may be formed by depositing a conductive material on the substrate 200 and selectively etching the conductive material. Then, although not shown, an interlayer insulating film may be formed to fill spaces between the first conductive lines 210. The interlayer insulating film may be formed by depositing an insulating material on the substrate 200 to a thickness sufficient to cover the first conductive lines 210, and then performing a planarization process, such as chemical mechanical polishing (CMP) or etch-back, until the top surfaces of the first conductive lines 210 are exposed.

[0037] Next, a first memory layer 220 may be formed on the first conductive lines 210 and the interlayer insulating film between the first conductive lines 210. In plan view, the first memory layer 220 may have a plate shape covering the substrate 200. The first memory layer 220 is used to form a first memory pattern (described later) and may have a multilayer structure. For example, the first memory layer 220 may have a multilayer structure for forming a magnetic tunnel junction structure. The first memory layer 220 may be formed by sequentially depositing layers forming the multilayer structure.

[0038] 3A and 3B, a mask pattern (not shown) covering an area where the first memory pattern is to be formed on the first memory layer 220 may be formed, and then the first memory layer 220 may be etched using the mask pattern as an etching barrier to form a plurality of first memory patterns 220A. The etching process for the first memory layer 220 may be performed by, for example, an IBE method.

[0039] The plurality of first memory patterns 220A may have the same shape and arrangement as the first memory patterns 220A of the above-described embodiment (see 120A in FIGS. 1A to 1C). In this embodiment, the first memory patterns 220A may have a columnar shape. The plurality of first memory patterns 220A may be arranged on the first conductive lines 210 to overlap the first conductive lines 210, and may be arranged at a pitch corresponding to a second distance (see P2 in FIGS. 1A and 1B) in each of the first and second directions, and at a pitch corresponding to a third distance (see P3 in FIGS. 1A and 1C) in the third direction. In this case, since the pitch of the plurality of first memory patterns 220A is relatively large, an etching process of the first memory layer 220, e.g., an IBE process, may be performed relatively easily.

[0040] 4, a first insulating layer 232 may be formed to cover the resultant structure of the processes of FIGS. 3A and 3B. The first insulating layer 232 may cover the sidewalls and top surface of the first memory pattern 220A, thereby having an upper surface of the first insulating layer 232 positioned above the top surface of the first memory pattern 220A. The first insulating layer 232 may be formed by depositing an insulating material. Furthermore, after depositing the insulating material, a planarization process may be performed to form the first insulating layer 232 having a planarized upper surface.

[0041] Here, the first insulating layer 232 can be used as a matrix for forming a first selector pattern, which will be described later. The first insulating layer 232 can include various insulating materials, such as silicon-containing insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, insulating metal oxides, insulating metal nitrides, or combinations thereof. As an example, the first insulating layer 232 can include silicon dioxide.

[0042] 5A and 5B, a first mask pattern M1 exposing an area where the second selector pattern will be formed is formed on the first insulating layer 232, and then a plurality of initial second selector patterns 230B' can be formed by doping a dopant into a portion of the first insulating layer 232 exposed by the first mask pattern M1. The doping of the dopant can be performed by ion implantation (see arrows). The dopant can function to generate trap sites that provide paths for conductive carriers to move within the first insulating layer 232. When the first insulating layer 232 includes a silicon-containing insulating material, the dopant can include a substance having a valence different from that of silicon, such as aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), or a combination thereof. Alternatively, when the first insulating layer 232 includes an insulating metal oxide or an insulating metal nitride, the dopant can include a substance having a valence different from that of the metal of the metal oxide or metal nitride, or silicon. When the first insulating layer 232 includes silicon dioxide, the dopant can include arsenic. Therefore, the initial second selector pattern 230B′ can include arsenic-doped silicon dioxide. The remainder of the first insulating layer 232 not exposed by the first mask pattern M1 may remain intact.

[0043] The initial second selector patterns 230B' may have the same arrangement as the second selector patterns (see 130B in FIG. 1B ) of the previously described embodiment. Therefore, the initial second selector patterns 230B' may be arranged on the first conductive lines 210 to overlap the first conductive lines 210, with a pitch corresponding to a second distance (see P2 in FIGS. 1A and 1B ) in each of the first and second directions, and a pitch corresponding to a third distance (see P3 in FIGS. 1A and 1C ) in each of the third directions. Furthermore, the initial second selector patterns 230B' may be arranged alternately with the first memory patterns 220A in each of the first and second directions. However, the top surface of the initial second selector pattern 230B' may be located above the top surface of the first memory pattern 220A or the top surface of the second selector pattern (see 130B in FIG. 1B ) of the previously described embodiment.

[0044] 6, a planarization process, such as CMP or etch-back, can be performed until the top surface of the first memory pattern 220A is exposed. As a result of this process, a second selector pattern 230B can be formed, having an upper surface that is substantially at the same level as the top surface of the first memory pattern 220A. In this process, the top surface of the first insulating layer 232 is also lowered, forming a flat surface in which the top surfaces of the first memory pattern 220A, the second selector pattern 230B, and the first insulating layer 232 are all at the same level.

[0045] Forming the second selector pattern 230B in this manner may allow for a simple and easy process without damaging the previously formed first memory pattern 220A.

[0046] As shown in FIGS. 7A and 7B, a second memory layer 225 may be formed on the resultant structure of the process of FIG. 6. In a plan view, the second memory layer 225 may have a flat plate shape covering the substrate 200. The second memory layer 225 may be used to form a second memory pattern (described later) and may have a multilayer structure. For example, the multilayer structure of the second memory layer 225 may form a magnetic tunnel junction structure. The second memory layer 225 is identical to the first memory layer 220 and may be formed using the same method as the first memory layer 220 formation process.

[0047] 8A and 8B, a mask pattern (not shown) covering an area where the second memory pattern is to be formed on the second memory layer 225 is formed, and then the second memory layer 225 is etched using the mask pattern as an etching barrier to form a plurality of second memory patterns 220B. The etching process for the second memory layer 225 may be performed by, for example, an IBE method.

[0048] The second memory patterns 220B may have the same shape and arrangement as the second memory patterns 220B of the above-described embodiment (see 120B in FIGS. 1A and 1B). In this case, since the pitch of the second memory patterns 220B is relatively large, the etching process of the second memory layer 225, for example, the IBE process, may be relatively easy. The second memory patterns 220B may be formed on the second selector patterns 230B so as to overlap each of them. To this end, a mask pattern (not shown) for forming the second memory patterns 220B may have a shape that covers portions exposed by the first mask pattern (see M1 in FIG. 5B) and exposes portions covered by the first mask pattern.

[0049] As shown in FIG. 9, a second insulating layer 234 may be formed covering the resultant structure of the processes of FIGS. 8A and 8B.

[0050] Here, the second insulating layer 234 can be used as a base for forming a second selector pattern, which will be described later. The second insulating layer 234 can include various insulating materials, such as silicon-containing insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., insulating metal oxides, insulating metal nitrides, or combinations thereof. As an example, the second insulating layer 234 can include silicon dioxide. The second insulating layer 234 can include the same insulating material as the first insulating layer 232.

[0051] 10A and 10B, a second mask pattern M2 is formed on the second insulating layer 234 to expose the region where the first selector pattern will be formed. Then, a portion of the second insulating layer 234 exposed by the second mask pattern M2 is doped with a dopant to form a plurality of first initial selector patterns 230A'. The doping of the dopant may be performed by ion implantation (see arrows). Furthermore, various process conditions, such as the dopant concentration and ion implantation energy, for forming the first initial selector patterns 230A' may be substantially the same as various process conditions, such as the dopant concentration and ion implantation energy, for forming the initial second selector patterns 230B'. The dopant may function to generate trap sites that provide paths for conductive carriers to move within the second insulating layer 234. When the second insulating layer 234 includes a silicon-containing insulating material, the dopant can include a substance having a valence different from that of silicon, such as aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), or a combination thereof. Alternatively, when the second insulating layer 234 includes an insulating metal oxide or an insulating metal nitride, the dopant can include a substance having a valence different from that of the metal of the metal oxide or metal nitride, or silicon. When the second insulating layer 234 includes silicon dioxide, the dopant can include arsenic. Therefore, the first initial selector pattern 230A′ can include arsenic-doped silicon dioxide. The remainder of the second insulating layer 234 that is not exposed by the second mask pattern M2 may remain intact.

[0052] The plurality of first initial selector patterns 230A' may have the same arrangement as the first selector pattern (see 130A in FIGS. 1B and 1C) in the above-described embodiment. The plurality of first initial selector patterns 230A' may be formed on the plurality of first memory patterns 220A so as to overlap each of them. In some implementation examples, the second mask pattern M2 may have a shape that covers a portion exposed by a mask pattern (not shown) for forming the plurality of first memory patterns 220A and exposes a portion covered by this mask pattern.

[0053] 11, a planarization process, such as CMP or etch-back, can be performed until the top surface of the second memory pattern 220B appears. As a result of this process, a first selector pattern 230A having an upper surface positioned at substantially the same level as the top surface of the second memory pattern 220B can be formed. In this process, the top surface of the second insulating layer 234 is also lowered, forming a flat surface in which the top surfaces of the second memory pattern 220B, the first selector pattern 230A, and the second insulating layer 234 are positioned at the same level.

[0054] 12A and 12B, a plurality of second conductive lines 240 extending in a second direction may be formed on the structure resulting from the process of Fig. 11. The second conductive lines 240 may be formed by depositing a conductive material on the structure resulting from the process of Fig. 11 and selectively etching the conductive material.

[0055] Next, an interlayer insulating film 242 may be formed to fill the spaces between the second conductive lines 240. The interlayer insulating film 242 may be formed by depositing an insulating material on the resultant structure of the process of FIG. 11 to a thickness that sufficiently covers the second conductive lines 240, and then performing a planarization process until the top surfaces of the second conductive lines 240 are exposed.

[0056] By the steps described above, the semiconductor device shown in FIGS. 12A and 12B can be manufactured.

[0057] 12A and 12B , the semiconductor device of this embodiment may include a plurality of first conductive lines 210 extending in a first direction, a plurality of second conductive lines 240 disposed separately on the first conductive lines 210 and extending in a second direction, a stacked structure of a first memory pattern 220A and a first selector pattern 230A overlapping the intersection regions between the first conductive lines 210 and the second conductive lines 240, and a stacked structure of a second selector pattern 230B and a second memory pattern 220B. In the embodiment of FIGS. 12A and 12B , the first memory pattern 220A and the first selector pattern 230A form first memory cells, and the second selector pattern 230B and the second memory pattern 220B form second memory cells. The first memory cells and the second memory cells may be alternately arranged in each of the first and second directions. Furthermore, the plurality of first memory cells can be arranged in a line in the third direction, and the plurality of second memory cells can be arranged in a line in the third direction.

[0058] Here, each of the first selector pattern 230A and the second selector pattern 230B may include an insulating material and a dopant doped into the insulating material. The insulating material of the first selector pattern 230A may be the same as the second insulating layer 234, and the insulating material of the second selector pattern 230B may be the same as the first insulating layer 232.

[0059] The components of the semiconductor device of this embodiment have been described in more detail in the manufacturing method, so a detailed description thereof will be omitted here.

[0060] Although exemplary embodiments of the present disclosure have been described above, various modifications and other variations are possible based on the present disclosure. [Explanation of symbols]

[0061] 100 boards 110 first conductive line MCA 1st memory cell 120A First memory pattern 130A First Selector Pattern MCB Second Memory Cell 120B Second memory pattern 130B Second selector pattern 140 second conductive line

Claims

1. a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines disposed separately on the plurality of first conductive lines and extending in a second direction intersecting the first direction; a plurality of memory cells each overlapping an intersection region between the plurality of first conductive lines and the plurality of second conductive lines; Equipped with the plurality of memory cells include a first memory cell having a first memory pattern and a first selector pattern disposed on the first memory pattern, and a second memory cell having a second selector pattern and a second memory pattern disposed on the second selector pattern, each of the first memory pattern and the second memory pattern being configured to store data, and each of the first selector pattern and the second selector pattern being configured to exhibit different electrical conductivity characteristics corresponding to a supply voltage relative to a threshold voltage; The semiconductor device is such that any one of the plurality of first memory cells and any one of the plurality of second memory cells are alternately arranged in each of the first direction and the second direction.

2. 2. The semiconductor device according to claim 1, wherein a plurality of the first memory cells are arranged in a line in a third direction that intersects with the first direction and the second direction.

3. 3. The semiconductor device according to claim 2, wherein the distance between the centers of two adjacent first memory cells in the first direction or the second direction is greater than the distance between the centers of two adjacent first memory cells in the third direction.

4. 2. The semiconductor device according to claim 1, wherein a plurality of the second memory cells are arranged in a line in a third direction that intersects with the first direction and the second direction.

5. 5. The semiconductor device according to claim 4, wherein the distance between the centers of two adjacent second memory cells in the first direction or the second direction is greater than the distance between the centers of two adjacent second memory cells in the third direction.

6. the first memory pattern and the second selector pattern are located at a first level in the vertical direction; 2. The semiconductor device according to claim 1, wherein the second memory pattern and the first selector pattern are located on a second level in the vertical direction.

7. The semiconductor device of claim 1 , wherein at least one of the first memory pattern and the second memory pattern includes a magnetic tunnel junction structure.

8. At least one of the first selector pattern and the second selector pattern includes an insulating material and a dopant doped into the insulating material; The semiconductor device of claim 1 , wherein the dopant is configured to create trap sites that provide migration paths for conductive carriers within the insulating material.

9. a first insulating layer including an insulating material and filling a space between the first memory pattern and the second selector pattern; The semiconductor device according to claim 1 , wherein the second selector pattern includes the insulating material and a dopant doped into the insulating material.

10. a second insulating layer filling a space between the second memory pattern and the first selector pattern; The semiconductor device according to claim 1 , wherein the first selector pattern includes the same insulating material as the second insulating layer and a dopant doped into the insulating material.

11. 2. The semiconductor device according to claim 1, wherein the first memory pattern and the second memory pattern are identical to each other.

12. 2. The semiconductor device according to claim 1, wherein the first selector pattern and the second selector pattern are identical to each other.

13. a first insulating layer filling a space between the first memory pattern and the second selector pattern; a second insulating layer filling a space between the second memory pattern and the first selector pattern; Furthermore, 2. The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are identical to each other.

14. forming a plurality of first conductive lines extending in a first direction; forming a plurality of memory cells on the plurality of first conductive lines, the memory cells comprising a first memory cell comprising a first memory pattern and a first selector pattern disposed on the first memory pattern, and a second memory cell comprising a second selector pattern and a second memory pattern disposed on the second selector pattern, each of the first memory pattern and the second memory pattern being configured to store data, and each of the first selector pattern and the second selector pattern being configured to exhibit different electrical conductivity characteristics corresponding to a supply voltage relative to a threshold voltage; forming a plurality of second conductive lines extending in a second direction intersecting the first direction on the plurality of memory cells, the plurality of memory cells being coupled between the plurality of first conductive lines and the plurality of second conductive lines; Including, A method for manufacturing a semiconductor device, wherein one of the plurality of first memory cells and one of the plurality of second memory cells are arranged alternately in each of the first direction and the second direction.

15. The step of forming a plurality of memory cells includes: forming the first memory pattern and the second selector pattern on a first conductive line; forming the first selector pattern and the second memory pattern on the first memory pattern and the second selector pattern, respectively; 15. The method of claim 14, comprising:

16. The second selector pattern forming step includes: forming a first insulating layer covering the first memory pattern; forming a first mask pattern on the first insulating layer to expose an area where the second selector pattern is to be formed; doping a portion of the first insulating layer exposed by the first mask pattern with a dopant that creates trap sites that provide paths for conductive carriers to travel within the first insulating layer; performing a planarization process to expose an upper surface of the first memory pattern; 16. The method of claim 15, comprising:

17. The first selector pattern forming step includes: forming a second insulating layer covering the second memory pattern; forming a second mask pattern on the second insulating layer to expose an area where the first selector pattern is to be formed; doping a portion of the second insulating layer exposed by the second mask pattern with a dopant that creates trap sites that provide paths for conductive carriers to travel within the second insulating layer; performing a planarization process to expose an upper surface of the second memory pattern; 16. The method of claim 15, comprising:

18. The first memory pattern forming step or the second memory pattern forming step includes: forming a memory layer; selectively etching the memory layer; 16. The method of claim 15, comprising:

19. the memory layer includes a magnetic tunnel junction structure; 20. The method of claim 18, wherein the step of etching the memory layer comprises performing an ion beam etching (IBE) process.

20. a plurality of the first memory cells are arranged in a line in a third direction intersecting the first direction and the second direction; 15. The method of claim 14, wherein a plurality of the second memory cells are arranged in a line in the third direction.

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