Pixel array, and image sensor including the same

Abstract

To provide a pixel array with a pixel structure sharing a floating diffusion region, and an image sensor including the same.SOLUTION: A pixel of a pixel array and an image sensor is formed by four subpixels. The pixel includes: a reset gate that resets four floating diffusion regions with a power source voltage connecting to an internal wire; a first driving gate that receives a first voltage through the internal wire; and a first selection gate that is disposed adjacent to the first driving gate in a first direction. The four subpixels include four photoelectric conversion elements, the floating diffusion regions where charges generated by the four photoelectric conversion elements are saved, and four transmission gates that transmit the charges generated in the four photoelectric conversion elements to the floating diffusion regions. The four floating diffusion regions in the four subpixels are electrically connected to each other through the internal wire.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an image sensor, and more particularly to a pixel array having a pixel structure in which a plurality of photoelectric conversion elements share a floating diffusion region, and an image sensor including the pixel array. [Background technology]

[0002] An image sensor is a device that captures two-dimensional or three-dimensional images of an object. Image sensors generate images of the object using photoelectric conversion elements that react to the intensity of light reflected from the object. Recently, with the development of CMOS (complementary metal oxide semiconductor) technology, CMOS image sensors using CMOS have become widely used. As the resolution of image sensors increases, the spacing between pixels in the pixel array of the image sensor becomes narrower, requiring a pixel structure with a reduced area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-057898 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems in the conventional art, and an object of the present invention is to provide a pixel array having a pixel structure in which 16 photoelectric conversion elements share a floating diffusion region, and an image sensor including the same. [Means for solving the problem]

[0005] In order to achieve the above object, an image sensor according to one aspect of the present invention includes a substrate including a first surface and a second surface opposite to the first surface, a first pixel including first four photoelectric conversion elements (PDs) in the substrate and a first floating diffusion region (FD) shared by the first four PDs, a second pixel including second four PDs in the substrate and a second FD shared by the second four PDs, a third pixel including third four PDs in the substrate and a third FD shared by the third four PDs, and a third pixel including a third floating diffusion region (FD) in the substrate. a fourth pixel including four PDs and a fourth FD shared by the fourth four PDs; and a reset transistor configured to be connected to a pixel power supply voltage, wherein the first FD is connected to the fourth FD via a first wiring, and the second FD is connected to a third FD via a second wiring, and the first four PDs to the fourth four PDs are arranged in a 2x2 matrix, and the reset transistor is configured to provide the pixel power supply voltage to the first to fourth FDs.

[0006] According to another aspect of the present invention, an image sensor that achieves the above object includes a substrate having a first surface and a second surface opposite to the first surface, and a pixel array arranged in an N×M matrix, wherein the pixel array includes 16 photoelectric conversion elements (PDs) in the substrate, four floating diffusion regions (FDs) including a first FD, a second FD, a third FD, and a fourth FD, a reset transistor configured to be connected to a pixel power supply voltage, and a gain control transistor configured to be connected to the reset transistor, wherein the reset transistor is configured to provide the pixel power supply voltage to the first to fourth FDs, and each of the first to fourth FDs is shared by four of the 16 PDs.

[0007] In order to achieve the above object, an image sensor according to still another aspect of the present invention includes a substrate including a first surface and a second surface opposite to the first surface, a first pixel including first four photoelectric conversion elements (PDs) in the substrate and a first floating diffusion region (FD) shared by the first four PDs, a second pixel including second four PDs in the substrate and a second FD shared by the second four PDs, a third pixel including third four PDs in the substrate and a third FD shared by the third four PDs, and a fourth pixel including fourth four PDs in the substrate and a fourth FD shared by the fourth four PDs. a reset transistor configured to be connected to a pixel power supply voltage; a first drive transistor configured to be connected to the first four FDs and the fourth four FDs; and a second drive transistor configured to be connected to the second four FDs and the third four FDs, wherein the first FD is connected to the fourth FD and the second FD is connected to the third FD, and the first four PDs to the fourth four PDs are arranged in a 2x2 matrix, and the reset transistor is configured to provide the pixel power supply voltage to the first to fourth FDs.

[0008] A pixel array according to the technical concept of the present invention includes a semiconductor substrate having a first surface and a second surface, the semiconductor substrate including a plurality of floating diffusion regions adjacent to the first surface, and a wiring structure disposed on the first surface, the wiring structure including a plurality of transfer gates symmetrically disposed around each of the plurality of floating diffusion regions, and wiring electrically connecting four adjacent floating diffusion regions among the plurality of floating diffusion regions. [Effects of the Invention]

[0009] In the pixel array and image sensor including the same according to the present invention, a plurality of sub-pixels, each including a plurality of photoelectric conversion elements, share a floating diffusion region and an output circuit, thereby reducing the size of the unit pixel and increasing the resolution and sensing sensitivity of the pixel array. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an image sensor according to one embodiment of the present invention. [Figure 2] FIG. 2 illustrates a pixel array according to one embodiment of the present invention. [Figure 3] 1 is a circuit diagram illustrating an example of a pixel included in a pixel array according to an embodiment of the present invention; [Figure 4] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 5] 1 is a vertical cross-sectional view of a pixel array according to one embodiment of the present invention. [Figure 6A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 6B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 7] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 8] 1 is a circuit diagram illustrating an example of a pixel according to an embodiment of the present invention; [Figure 9A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 9B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 9C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 10A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 10B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 11A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 11B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 11C]1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 12A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 12B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 12C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13D] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13E] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 13F] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14D] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14E] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 14F] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 15A] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 15B] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 15C] 1 is a plan view illustrating an example of a pixel according to an embodiment of the present invention; [Figure 16A] FIG. 2 illustrates a microlens disposed in a pixel according to an embodiment of the present invention. [Figure 16B] FIG. 2 illustrates a microlens disposed in a pixel according to an embodiment of the present invention. [Figure 16C] FIG. 2 illustrates a microlens disposed in a pixel according to an embodiment of the present invention. [Figure 16D] FIG. 2 illustrates a microlens disposed in a pixel according to an embodiment of the present invention. [Figure 17A] FIG. 2 illustrates a color filter disposed in a pixel array according to an embodiment of the present invention. [Figure 17B] FIG. 2 illustrates a color filter disposed in a pixel array according to an embodiment of the present invention. [Figure 17C] FIG. 2 illustrates a color filter disposed in a pixel array according to an embodiment of the present invention. [Figure 17D] FIG. 2 illustrates a color filter disposed in a pixel array according to an embodiment of the present invention. [Figure 17E] FIG. 2 illustrates a color filter disposed in a pixel array according to an embodiment of the present invention. [Figure 17F] FIG. 2 illustrates a color filter disposed in a pixel array according to an embodiment of the present invention. [Figure 18] FIG. 1 is a block diagram of an electronic device including a multi-camera module. [Figure 19] FIG. 19 is a detailed block diagram of the camera module of FIG. 18. DETAILED DESCRIPTION OF THE INVENTION

[0011] FIG. 1 is a block diagram illustrating an image sensor according to one embodiment of the present invention.

[0012] The image sensor 100 is mounted in an electronic device having an image sensing function or an optical sensing function. For example, the image sensor 100 is mounted in electronic devices such as a camera, a smartphone, a wearable device, an Internet of Things (IoT), a tablet PC (personal computer), a PDA (personal digital assistant), a PMP (portable multimedia player), and a navigation device. The image sensor 100 is also mounted in electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, and the like.

[0013] The image sensor 100 includes a pixel array 110, a row driver 120, a ramp signal generator 130, an analog-to-digital converter (ADC) circuit 140, a data output circuit 150, and a timing controller 160. The image sensor 100 may further include a signal processing unit 170.

[0014] The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in a matrix. Pixels PX arranged at the same position in the column direction are connected to the same column line CL.

[0015] The pixel PX senses light using a photoelectric conversion element and outputs an image signal, which is an electrical signal based on the sensed light. The photoelectric conversion element is a light sensing element made of organic or inorganic materials, such as an inorganic photodiode, organic photodiode, perovskite photodiode, phototransistor, photogate, or pinned photodiode.

[0016] In the pixel array 110 according to an embodiment of the present invention, the pixel PX includes a plurality of sub-pixels, each of which includes a plurality of photoelectric conversion elements. The sub-pixels include floating diffusion regions in which charges generated by the photoelectric conversion elements are stored. The floating diffusion regions included in each of the sub-pixels are electrically connected to each other via internal wiring. This allows the sub-pixels included in the pixel PX to share the floating diffusion regions.

[0017] In one embodiment, pixel PX includes four sub-pixels, each of which includes four photoelectric conversion elements arranged in a matrix and four transfer transistors respectively connected to the four photoelectric conversion elements. A floating diffusion region is disposed at the center of each sub-pixel, and the four floating diffusion regions of the four sub-pixels are electrically connected to each other via internal wiring to form a floating diffusion node.

[0018] The pixel PX includes an output circuit that outputs an image signal based on the charges stored in the floating diffusion regions to a column line. The output circuit includes a plurality of transistors, such as a reset transistor, a drive transistor, and a selection transistor.

[0019] The pixel array 110 according to an embodiment of the present invention and the pixels PX included in the pixel array 110 will be described in detail below with reference to FIGS. 2 to 17F.

[0020] The row driver 120 drives the pixel array 110 row by row. The row driver 120 decodes a row control signal (e.g., an address signal) received from the timing controller 160 and selects at least one row line constituting the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 generates a selection signal for selecting one of a plurality of rows. The pixel array 110 then outputs a pixel signal, e.g., a pixel voltage, from the row selected by the selection signal provided by the row driver 120. The pixel signal includes a reset signal and an image signal.

[0021] The row driver 120 transmits control signals for outputting pixel signals to the pixel array 110, and the pixels PX operate in response to the control signals to output the pixel signals.

[0022] The ramp signal generator 130 generates a ramp signal (e.g., a ramp voltage) whose level rises and falls at a predetermined gradient under the control of the timing controller 160. The ramp signal RAMP is provided to each of a plurality of correlated double sampling (CDS) circuits 141 included in an analog-to-digital converter (ADC) circuit 140.

[0023] The ADC circuit 140 includes a plurality of CDS circuits 141 and a plurality of counters 142. The ADC circuit 140 converts pixel signals (e.g., pixel voltages) input from the pixel array 110 into pixel values, which are digital signals. Each pixel signal received via each of the plurality of column lines CL is converted into a pixel value, which is a digital signal, by the CDS circuit 141 and the counter 142.

[0024] The CDS circuit 141 compares a pixel signal, e.g., a pixel voltage, received via a column line CL with a ramp signal RAMP and outputs the comparison result as a comparison result signal. When the level of the ramp signal RAMP is the same as the level of the pixel signal, the CDS circuit 141 outputs a comparison signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low). The point in time at which the level of the comparison signal transitions is determined by the level of the pixel signal.

[0025] The CDS circuit 141 samples the pixel signal provided from the pixel PX using a correlated double sampling (CDS) method. The CDS circuit 141 samples a reset signal received as the pixel signal, compares the reset signal with a ramp signal RAMP, and generates a comparison signal based on the reset signal. The CDS circuit 141 stores the reset signal. Thereafter, the CDS circuit 141 samples an image signal correlated with the reset signal, compares the image signal with the ramp signal RAMP, and generates a comparison signal based on the image signal.

[0026] The counter 142 counts the time points at which the level of the comparison result signal output from the CDS circuit 141 transitions, and outputs the count value as a pixel value.

[0027] In one embodiment, the counter circuit 142 is implemented as an up counter and an arithmetic circuit, an up / down counter, or a bit-wise inversion counter whose count value sequentially increases based on a counting clock signal provided from the timing controller 160. In one embodiment, the image sensor 100 further includes a code generator that generates a plurality of code values having a resolution according to a set number of bits as a counting code, and the counter 142 includes a latch circuit that latches the value of the counting code based on the comparison result signal, and an arithmetic circuit.

[0028] The data output circuit 150 temporarily stores and then outputs the pixel values output from the ADC circuit 140. The data output circuit 150 includes a plurality of column memories 151 and a column decoder 152. The column memory 151 stores the pixel values received from the counter 142. In one embodiment, each of the plurality of column memories 151 is included in the counter 142. The plurality of pixel values stored in the plurality of column memories 151 are output as image data IDTA under the control of the column decoder 152.

[0029] The timing controller 160 outputs control signals to each of the row driver 120, the ramp signal generator 130, the ADC circuit 140, and the data output circuit 150, and controls the operation or timing of the row driver 120, the ramp signal generator 130, the ADC circuit 140, and the data output circuit 150.

[0030] The signal processing unit 170 performs noise reduction, gain adjustment, waveform shaping, interpolation, white balance, gamma adjustment, edge enhancement, binning, etc. on the image data IDTA. In one embodiment, the signal processing unit 170 is provided in a processor external to the image sensor 100.

[0031] FIG. 2 is a diagram illustrating a pixel array according to one embodiment of the present invention.

[0032] 2, the pixel array 110 is in the form of a matrix and includes a plurality of pixels, for example, a first pixel PX1 to a fourth pixel PX4. The plurality of pixels are arranged in a plurality of rows and columns. In FIG. 2, the first pixel PX1 to the fourth pixel PX4 are illustrated arranged in a first row R1 and a second row R2 and a first column C1 and a second column C2. However, this is merely for convenience of explanation. The pixel array 110 may include a greater number of pixels, and the number of pixels is determined by the resolution of the pixel array 110.

[0033] A plurality of row lines RL (FIG. 1) extend in a first direction, e.g., the X-axis direction, and pixels arranged in the same row are connected to the same row line. For example, the first pixel PX1 and the second pixel PX2 arranged in the first row R1 are connected to the same row line, and the third pixel PX3 and the fourth pixel PX4 arranged in the second row R2 are connected to another same row line.

[0034] A plurality of column lines CL (FIG. 1) extend in a second direction, e.g., the Y-axis direction, and pixels arranged in the same column are connected to the same column line. For example, the first pixel PX1 and the third pixel PX3 arranged in the first column C1 are connected to the same column line, and the second pixel PX2 and the fourth pixel PX4 arranged in the second column C2 are connected to another same column line. Pixel signals are read from the plurality of pixels row by row via the column lines.

[0035] Each of the first pixel PX1 to the fourth pixel PX4 includes a plurality of floating diffusion regions FD in which charges are stored, and the plurality of floating diffusion regions FD are electrically connected via internal wiring WR extending in a first direction and a second direction within the pixel. The first pixel PX1 to the fourth pixel PX4 have the same pixel structure, which will be described in detail with reference to FIG.

[0036] 3 is a circuit diagram illustrating an example of a pixel included in a pixel array according to an embodiment of the present invention. The pixel PXa in FIG. 3 is applied to the first pixel PX1 to the fourth pixel PX4 of the pixel array 110 in FIG.

[0037] 3, pixel PXa includes first to fourth subpixels SPX1 to SPX4, a reset transistor RX, first and second drive transistors DX1 and DX2, and first and second select transistors SX1 and SX2. The reset transistor RX, first and second drive transistors DX1 and DX2, and first and second select transistors SX1 and SX2 constitute an output circuit of pixel PXa.

[0038] The first sub-pixel SPX1 includes a first photoelectric conversion element PD11 to a fourth photoelectric conversion element PD14 and a first transfer transistor TX11 to a fourth transfer transistor TX14.

[0039] The first photoelectric conversion element PD11 to the fourth photoelectric conversion element PD14 generate photoelectric charges (hereinafter referred to as charges) corresponding to the received optical signals.

[0040] The first through fourth photoelectric conversion elements PD11 through PD14 are respectively connected to the first through fourth transfer transistors TX11 through TX14 of the first sub-pixel SPX1, which are turned on in response to the activation levels (e.g., logic high) of the transfer signals TS11 through TS14.

[0041] The second sub-pixel SPX2 includes first through fourth photoelectric conversion elements PD21 through PD24 and first through fourth transfer transistors TX21 through TX24 connected to the first through fourth photoelectric conversion elements PD21 through PD24, respectively. The first through fourth transfer transistors TX21 through TX24 of the second sub-pixel SPX2 are turned on in response to the activation levels (e.g., logic high) of the transfer signals TS21 through TS24, respectively.

[0042] The third sub-pixel SPX3 includes first through fourth photoelectric conversion elements PD31 through PD34 and first through fourth transfer transistors TX31 through TX34 connected to the first through fourth photoelectric conversion elements PD31 through PD34, respectively. The first through fourth transfer transistors TX31 through TX34 of the third sub-pixel SPX3 are turned on in response to the activation levels (e.g., logic high) of the transfer signals TS31 through TS34, respectively.

[0043] The fourth sub-pixel SPX4 includes first through fourth photoelectric conversion elements PD41 through PD44 and first through fourth transfer transistors TX41 through TX44 connected to the first through fourth photoelectric conversion elements PD41 through PD44, respectively. The first through fourth transfer transistors TX41 through TX44 of the fourth sub-pixel SPX4 are turned on in response to the activation levels (e.g., logic high) of the transfer signals TS41 through TS44, respectively.

[0044] The multiple transmission signals TS11-TS14, TS21-TS24, TS3-TS34, and TS41-TS44 have active levels at the same time or at different times depending on the read mode. For example, in the first read mode, the multiple transmission signals TS11-TS14, TS21-TS24, TS31-TS34, and TS41-TS44 are different signals and have active levels at different times. In the second read mode (e.g., charge summing mode), the multiple transmission signals TS11-TS14, TS21-TS24, TS31-TS34, and TS41-TS44 are the same signals and have active levels at the same time. In the third reading mode, the transmission signals TS11 to TS14 of the first subpixel SPX1 are the same signal, the transmission signals TS21 to TS24 of the second subpixel SPX2 are the same signal, the transmission signals TS31 to TS34 of the third subpixel SPX3 are the same signal, and the transmission signals TS41 to TS44 of the fourth subpixel SPX4 are the same signal.

[0045] The first to fourth transfer transistors TX11 to TX14, TX21 to TX24, TX31 to TX34, and TX41 to TX44 provided in the first to fourth sub-pixels SPX1 to SPX4, respectively, are turned on and transfer the charges generated in the corresponding photoelectric conversion elements to the floating diffusion nodes FN.

[0046] The first to fourth floating diffusion regions FD1 (FIG. 4) to FD4 (FIG. 4) included in the first to fourth sub-pixels SPX1 to SPX4, respectively, are electrically connected via internal wiring WR to form a floating diffusion node FN. Therefore, the capacitance of the capacitor formed at the floating diffusion node FN is four times the capacitance of each of the first to fourth floating diffusion regions FD1 (FIG. 4) to FD4 (FIG. 4).

[0047] The drain of the reset transistor RX is applied with the pixel power supply voltage VDDP, and the source of the reset transistor RX is connected to the floating diffusion node FN. The reset transistor RX is turned on in response to an active level of a reset signal RS to provide the pixel power supply voltage VDDP to the floating diffusion node FN as a reset voltage, thereby resetting the floating diffusion node FN.

[0048] The pixel power supply voltage VDDP is applied to the drains of the first and second drive transistors DX1 and DX2, and their sources are connected to the drains of the first and second selection transistors SX1 and SX2. The gates of the first and second drive transistors DX1 and DX2 are connected to a floating diffusion node FN. The first and second drive transistors DX1 and DX2 operate as source followers. The first and second drive transistors DX1 and DX2 receive a voltage corresponding to the potential of the floating diffusion node FN applied to their gates and output pixel signals corresponding to the received voltages.

[0049] The sources of the first and second selection transistors SX1 and SX2 are connected to a column line CL, and the first and second selection transistors SX1 and SX2 are turned on in response to an active level of a selection signal SEL applied to their gates to output pixel signals output from the first and second driving transistors DX1 and DX2 to the column line CL. When the first and second selection transistors SX1 and SX2 are turned on, pixel signals output from the sources of the first and second driving transistors DX1 and DX2 are output to the column line CL.

[0050] 3, pixel PXa is illustrated as including two drive transistors (DX1, DX2) and two select transistors (SX1, SX2), but is not limited to this. Each pixel in pixel array 110 (FIG. 2) includes one drive transistor and one select transistor. Alternatively, each pixel may include three or more drive transistors and three or more select transistors.

[0051] 4 is a plan view illustrating an example of a pixel according to an embodiment of the present invention, in which the pixel PXa corresponds to the first pixel PX1 to the fourth pixel PX4 of the pixel array 110 of FIG.

[0052] 4, pixel PXa includes first to fourth sub-pixels SPX1 to SPX4, which have the same pixel structure.

[0053] The first sub-pixel SPX1 includes first to fourth photoelectric conversion elements PD11 to PD14, first to fourth transfer gates TG11 to TG14, and a first floating diffusion region FD1.

[0054] The first through fourth transmission gates TG11 through TG14 are the gates of the first through fourth transmission transistors TX11 (FIG. 3) through TX14 (FIG. 3), respectively. The first through fourth transmission transistors TX11 through TX14 transfer the charges generated in the first through fourth photoelectric conversion elements PD11 through PD14, respectively, to the first floating diffusion region FD1. The charges received by the first floating diffusion region FD1 are stored.

[0055] The first through fourth photoelectric conversion elements PD11 through PD14 are arranged in a matrix. The first floating diffusion region FD1 is located at the center of the first sub-pixel SPX1. The first through fourth transfer gates TG11 through TG14 are arranged symmetrically with respect to the first floating diffusion region FD1. In one embodiment, the first through fourth transfer gates TG11 through TG14 are arranged to surround the first floating diffusion region FD1.

[0056] The second subpixel SPX2 includes the first through fourth photoelectric conversion elements PD21 through PD24, the first through fourth transfer gates TG21 through TG24, and the second floating diffusion region FD2. The third subpixel SPX3 includes the first through fourth photoelectric conversion elements PD31 through PD34, the first through fourth transfer gates TG31 through TG34, and the third floating diffusion region FD3. The fourth subpixel SPX4 includes the first through fourth photoelectric conversion elements PD41 through PD44, the first through fourth transfer gates TG41 through TG44, and the fourth floating diffusion region FD4. The pixel structures of the second subpixel SPX2, the third subpixel SPX3, and the fourth subpixel SX4 are the same as those of the first subpixel SPX1, so repeated description will be omitted.

[0057] The internal wiring WR is connected to the first floating diffusion region FD1 through the fourth floating diffusion region FD4 via contacts CT. The first floating diffusion region FD1 through the fourth floating diffusion region FD4 are electrically connected to each other via the internal wiring WR to form a floating diffusion node FN (FIG. 3). The internal wiring WR is formed within a pixel region in which the pixel PXa is formed, for example, on a two-dimensional plane along the first direction (X-axis direction) and the second direction (Y-axis direction). For example, in FIG. 2, the internal wiring WR provided in the first pixel PX1 is formed within the pixel region of the first pixel PX1 and does not extend to other pixels, for example, the second pixel PX2 through the fourth pixel PX4.

[0058] In one embodiment, the internal wiring WR extends in a first direction, e.g., the X-axis direction, to connect the first floating diffusion region FD1 to the second floating diffusion region FD2 and to connect the third floating diffusion region FD3 to the fourth floating diffusion region FD4. The internal wiring WR extends in a second direction, e.g., the Y-axis direction, to connect the first floating diffusion region FD1 to the second floating diffusion region FD2 and the third floating diffusion region FD3 to the fourth floating diffusion region FD4. This allows the first to fourth subpixels SPX1 to SPX4 to share the first to fourth floating diffusion regions FD1 to FD4. This increases the useful area of the pixel PXa.

[0059] Pixel PXa may further include a reset gate RG, a first drive gate SFG1 and a second drive gate SFG2, and a first select gate SG1 and a second select gate SG2. In one embodiment, pixel PXa may further include a dummy gate DMY.

[0060] The reset gate RG is the gate of the reset transistor RX (FIG. 3). The pixel power supply voltage VDDP (FIG. 3) is applied to the drain of the reset transistor RX, and the source of the reset transistor RX is connected to the internal wiring WR via the contact CT. When the reset transistor RX is turned on, the pixel power supply voltage is applied to the first through fourth floating diffusion regions FD1 through FD4 via the internal wiring WR, thereby resetting the first through fourth floating diffusion regions FD1 through FD4. In other words, any charges remaining in the first through fourth floating diffusion regions FD1 through FD4 are removed.

[0061] The first drive gate SFG1 and the second drive gate SFG2 are the gates of the first drive transistor DX1 (FIG. 3) and the second drive transistor DX2 (FIG. 3), respectively, and the first select gate SG1 and the second select gate SG2 are the gates of the first select transistor SX1 (FIG. 3) and the second select transistor SX2 (FIG. 3). The first drive gate SFG1 and the second drive gate SFG2 are connected to the internal wiring WR via contacts CT.

[0062] The drains of the first selection transistor SX1 and the second selection transistor SX2 are connected to the sources of the first driving transistor DX1 and the second driving transistor DX2, respectively, and the sources of the first selection transistor SX1 and the second selection transistor SX2 are connected to the column line via the contact CT. When the first selection transistor SX1 and the second selection transistor SX2 are turned on, pixel signals output from the sources of the first driving transistor DX1 and the second driving transistor DX2 are output to the column line.

[0063] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in a first direction, for example, the X-axis direction, on one side of the pixel PXa, for example, on the top or bottom, and are arranged parallel to the row line RL (FIG. 1).

[0064] The first and second drive gates SFG1 and SFG2 are connected to the internal wiring WR via contacts CT. The first drive gate SFG1 is connected to a first end T1 of the internal wiring WR, and the second drive gate SFG2 is connected to a second end T2 of the internal wiring WR.

[0065] The first select gate SG1 and the second select gate SG2 are disposed between the first drive gate SFG1 and the second drive gate SFG2. In one embodiment, the first select gate SG1 and the second select gate SG2 are disposed outside the first drive gate SFG1 and the second drive gate SFG2.

[0066] The reset gate RG is disposed at the center of the pixel PXa, and the dummy gate DMY is disposed alongside the reset gate RG in the first direction. The reset gate RG and the dummy gate DMY are disposed between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. In one embodiment, the reset gate RG and the dummy gate DMY are disposed symmetrically in the first direction with respect to the center of the pixel PXa. In one embodiment (not shown in FIG. 4), the pixel PXa does not include a dummy gate DMY.

[0067] As described above, within pixel PXa, the first to fourth subpixels SPX1 to SPX4 share the first to fourth floating diffusion regions FD1 to FD4. The first to fourth subpixels SPX1 to SPX4 also share an output circuit. This expands the useful area of pixel PXa and reduces the size of pixel PXa. Because the first to fourth floating diffusion regions FD1 to FD4 are shared within pixel PXa, the sensing sensitivity of pixel PXa is increased. Therefore, the resolution and sensing sensitivity of pixel array 110 (FIG. 2) are increased.

[0068] 5 is a vertical cross-sectional view of a pixel array according to one embodiment of the present invention, taken along line AA' in FIG.

[0069] Referring to FIG. 5, the pixel array 110 includes a semiconductor substrate 111 (hereinafter referred to as the "substrate") having a first surface 111B and a second surface 111F facing each other, an incident layer 112 arranged on the first surface 111B of the substrate 111, and a wiring layer 113 (also referred to as the wiring structure) arranged on the second surface 111F of the substrate 111.

[0070] The substrate 111 includes, for example, at least one selected from the group consisting of Si, Ge, SiGe, SiC, GaAs, InAs, and InP. In one embodiment, the substrate 111 is doped with impurities of a first conductivity type. For example, the first conductivity type is P-type, and the impurities of the first conductivity type are boron.

[0071] A first deep trench isolation (DTI) portion DTI1 and a second DTI portion DTI2 are disposed on the substrate 111. The first DTI portion DTI1 penetrates the substrate 111 and extends from the first surface 111B to the second surface 111F. The second DTI portion DTI2 extends from the first surface 111B toward the second surface 111F but is spaced apart from the second surface 111F. The first DTI1 portion DTI1 and the second DTI portion DTI2 include at least one of a silicon oxide film, a hafnium oxide film, an aluminum oxide film, and an impurity-doped polysilicon film. Each of the first DTI1 portion DTI1 and the second DTI portion DTI2 has a single-layer structure or a multi-layer structure.

[0072] The first DTI1 portion DTI1 separates subpixels, e.g., the first subpixel SPX1 and the second subpixel SPX2, and the second DTI portion DTI2 separates regions within the subpixels. For example, the second DTI portion DTI2 separates the first region AR11 and the second region AR12 in a first direction, e.g., the X-axis direction, within the first subpixel SPX1, and separates the first region AR21 and the second region AR22 within the second subpixel SPX2. The first DTI1 portion DTI1 and the second DTI2 prevent crosstalk between pixels PXa, between subpixels, and between regions of the subpixels.

[0073] A first photoelectric conversion element PD11 and a second photoelectric conversion element PD12 are arranged in the first region AR11 and the second region AR12 of the first subpixel SPX1, respectively. A first photoelectric conversion element PD21 and a second photoelectric conversion element PD22 are arranged in the first region AR21 and the second region AR22 of the second subpixel SPX2, respectively. Each of the photoelectric conversion elements (PD11, PD12, PD21, PD22) includes a region doped with impurities of a second conductivity type opposite to the first conductivity type. For example, the second conductivity type is N-type, and the impurities of the second conductivity type include impurities such as phosphorus, arsenic, bismuth, and / or antimony. The region doped with impurities of the second conductivity type forms a PN junction with an adjacent region of the substrate 111 doped with impurities of the first conductivity type, thereby constituting the photoelectric conversion elements (PD11, PD12, PD21, PD22).

[0074] The first surface 111B of the substrate 111 is a light incident surface, and light is incident through the incident layer 112 and the first surface 111B. The incident layer 112 includes a microlens ML and a color filter CF. In one embodiment, an antireflection layer AF is disposed between the first surface 111B of the substrate 111 and the color filter CF. In one embodiment, the antireflection layer AF, the color filter CF, and the microlens ML are sequentially stacked on the first surface 110B of the semiconductor substrate 111.

[0075] 5 illustrates a single microlens ML disposed above a plurality of photoelectric conversion elements, for example, the first and second photoelectric conversion elements PD11 and PD12 of the first subpixel SPX1 and the first and second photoelectric conversion elements PD21 and PD22 of the second subpixel SPX2. However, the present invention is not limited to this. In one embodiment, a single microlens ML is disposed above two or four photoelectric conversion elements. For example, a single microlens ML may be disposed above the first and second photoelectric conversion elements PD11 and PD12 of the first subpixel SPX1, and another microlens ML may be disposed above the first and second photoelectric conversion elements PD21 and PD22 of the second subpixel SPX2. As another example, for each subpixel, for example, one microlens ML may be arranged on top of the fourth photoelectric conversion element included in one subpixel (first subpixel SPX1 consisting of first photoelectric conversion element PD11 to fourth photoelectric conversion element PD14).

[0076] The color filter CF transmits light in a specific spectral band, in other words, light of a specific color. A plurality of color filters CF constitute a color filter array. In one embodiment, the color filter array has a Bayer pattern. The plurality of color filters includes a red filter, a blue filter, and two green filters, which are arranged in a 2x2 array, with the two green filters arranged diagonally. In one embodiment, the plurality of color filters CF includes a red filter, a blue filter, a green filter, and a white filter arranged in a 2x2 array. In another embodiment, the plurality of color filters CF includes a red filter, two yellow filters, and a blue filter arranged in a 2x2 array, with the two yellow filters arranged diagonally. However, the plurality of color filters may include filters of other hues combined. For example, the plurality of color filters may include a yellow filter, a cyan filter, and a green filter.

[0077] A first color filter CF1 is disposed on the first subpixel SPX1, and a second color filter CF2 is disposed on the second subpixel SPX2. The first color filter CF1 and the second color filter CF2 transmit light of the same color or different colors. The color of light transmitted by the color filter CF determines the hue sensed by the corresponding subpixel (first subpixel SPX1 or second subpixel SPX2) or the corresponding pixel PXa.

[0078] The floating diffusion regions, for example, the first floating diffusion region FD1 and the second floating diffusion region FD2, are formed adjacent to the second surface 111F of the substrate 111 and are located at the centers of the first sub-pixel SPX1 and the second sub-pixel SPX2, respectively. The first floating diffusion region FD1 and the second floating diffusion region FD2 are regions doped with impurities of the second conductivity type.

[0079] Transistor gates, for example, first transmission gates (TG11, TG21) and second transmission gates (TG12, TG22), are formed in the wiring layer 113 adjacent to the second surface 111F of the substrate 111. The first transmission gates (TG11, TG21) and second transmission gates (TG12, TG22) are formed adjacent to the first floating diffusion region FD1 and the second floating diffusion region FD2. Although only the transmission gates, for example, the first transmission gates (TG11, TG21) and second transmission gates (TG12, TG22), are shown in FIG. 5, a reset gate RG (FIG. 4), drive gates SFG1, SFG2 (FIG. 4), select gates SG1, SG2 (FIG. 4), and dummy gate DMY (FIG. 4) are formed adjacent to the second surface 111F of the substrate 111.

[0080] Well regions (not shown) are formed around the gates, for example, the first transmission gates (TG11, TG21) and the second transmission gates (TG12, TG22). The well regions are formed in the substrate 111 adjacent to the second face 111F. The well regions act as the drain and source of the transistors.

[0081] The wiring layer 113 includes multi-layer conductive lines 113-2 disposed within an interlayer insulating film 113-1. The conductive lines 113-2 transmit control signals supplied to each transistor or signals between the pixel and the outside. The conductive lines 113-2 are formed by patterning a conductive material, for example, a metal material such as copper or aluminum, and extend in a first direction (X-axis direction) and a second direction (Y-axis direction).

[0082] Of the conductive lines 113-2, the internal wiring WR formed in the pixel PXa (FIG. 4) is connected to the first floating diffusion region FD1 and the second floating diffusion region FD2 via contacts CT that penetrate the interlayer insulating film 113-1, electrically connecting the first floating diffusion region FD1 and the second floating diffusion region FD2. The internal wiring WR is formed in the pixel region AR_PX.

[0083] In this manner, the internal wiring WR electrically connects multiple floating diffusion regions (e.g., the first floating diffusion region FD1 to the fourth floating diffusion region FD4 (FIG. 4)) between multiple subpixels (e.g., the first subpixel SPX1 to the fourth subpixel SPX4 (FIG. 3)) within the pixel PXa.

[0084] 6A and 6B are plan views showing an example of a pixel according to an embodiment of the present invention. Pixels PXb and PXc in Fig. 6A and 6B are modifications of pixel PXa in Fig. 4. Therefore, the following description will focus on the differences from Fig. 4.

[0085] 6A and 6B, pixel (PXb, PXc) includes first to fourth subpixels SPX1 to SPX4, which have the same structure. Each of the first to fourth subpixels SPX1 to SPX4 includes a first to fourth photoelectric conversion element PD1 to PD4, a first to fourth transfer gate TG1 to TG4, and a floating diffusion region. A first to fourth floating diffusion region FD1 to FD4 is disposed at the center of each of the first to fourth subpixels SPX1 to SPX4. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0086] The pixel (PXb, PXc) includes a reset gate RG, a first drive gate SFG1, a second drive gate SFG2, and a first select gate SG1, a second select gate SG2. In one embodiment, the pixel (PXb, PXc) may further include a dummy gate DMY. The first drive gate SFG1 and the second drive gate SFG2 are connected to the internal wiring WR via contacts CT.

[0087] 6A, the internal wiring WR extends in the second direction to connect the first floating diffusion region FD1 and the third floating diffusion region FD3 and the second floating diffusion region FD2 and the fourth floating diffusion region FD4, and also extends in the first direction to connect the first floating diffusion region FD1 and the second floating diffusion region FD2.

[0088] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in a first direction, for example, the X-axis direction, at the center of the pixel PXb. The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged between the first sub-pixel SPX1 and the second sub-pixel SPX2 and the third sub-pixel SPX3 and the fourth sub-pixel SPX4.

[0089] The reset gate RG is disposed at the top or bottom of the pixel PXb, and the dummy gate DMY is disposed symmetrically with the reset gate RG in the first direction with respect to the center of the pixel PXb. In one embodiment, the reset gate RG and the dummy gate DMY are disposed symmetrically with respect to the first direction with respect to the internal wiring WR.

[0090] 6B, the internal wiring WR extends in the second direction to connect the first floating diffusion region FD1 and the third floating diffusion region FD3 and to connect the second floating diffusion region FD2 and the fourth floating diffusion region FD4, and also extends in the first direction to connect the first floating diffusion region FD1 and the third floating diffusion region FD3 and the second floating diffusion region FD2 and the fourth floating diffusion region FD4.

[0091] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in a second direction, for example, the Y-axis direction, on one side of the pixel PXc, for example, the left side or the right side, and are arranged parallel to the column line CL (FIG. 1).

[0092] The reset gate RG and the dummy gate DMY are disposed at the center of the pixel PXc, and are disposed symmetrically in the second direction with respect to the center of the pixel PXc.

[0093] 6A, the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are disposed in the center of the pixel PXc, and the dummy gate DMY is disposed outside the pixel PXc, for example, on the left or right side of the pixel PXc. The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are disposed side by side in the second direction in the center of the pixel PXc, and the reset gate RG and the dummy gate DMY are disposed side by side in the second direction on the left or right side of the pixel PXc.

[0094] 7 is a plan view showing an example of a pixel according to an embodiment of the present invention. The pixel PXd in FIG. 7 is a modified example of the pixel PXa in FIG. 4. Therefore, the following description will focus on the differences from FIG.

[0095] 7, pixel PXd includes first to fourth subpixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth subpixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0096] The pixel PXd further includes a reset gate RG, a drive gate SFG, and a select gate SG. In one embodiment, the pixel PXd may further include a dummy gate DMY. The drive gate SFG is coupled to the internal wiring WR via a contact CT.

[0097] Unlike pixel PXa in Figure 4, pixel PXd includes one drive gate SFG and one select gate SG. The drive gate SFG and select gate SG are located at the top center of pixel PXd. In one embodiment, a dummy gate is located symmetrically with the select gate SG in the first direction around the drive gate SFG.

[0098] The internal wiring WR extends in a first direction to connect the first floating diffusion region FD1 and the second floating diffusion region FD2 and to connect the third floating diffusion region FD3 and the fourth floating diffusion region FD4. The internal wiring WR extends in a second direction to connect the first floating diffusion region FD1 and the second floating diffusion region FD2 and the third floating diffusion region FD3 and the fourth floating diffusion region FD4. A first end T1 of the internal wiring WR is connected to the drive gate SFG via a contact CT.

[0099] 8 is a circuit diagram showing an example of a pixel according to an embodiment of the present invention, in which the pixel PXf of FIG. 8 is applied to the first pixel PX1 to the fourth pixel PX4 of the pixel array 110 of FIG.

[0100] 8, pixel PXf includes first to fourth subpixels SPX1 to SPX4, a reset transistor RX, a gain control transistor CX, a first drive transistor DX1 and a second drive transistor DX2, and a first select transistor SX1 and a second select transistor SX2. The reset transistor RX, the gain control transistor CX, the first drive transistor DX1 and the second drive transistor DX2, and the first select transistor SX1 and the second select transistor SX2 constitute an output circuit of pixel PXf.

[0101] Compared to pixel PXa of FIG. 3, pixel PXf further includes a gain control transistor CX. The gain control transistor CX is turned on in response to a gain control signal CS. A capacitor is formed at the drain of the gain control transistor CX to store charge. The drain of the gain control transistor CX is referred to as a floating diffusion node FN1. When the reset transistor RX is turned off and the gain control transistor CX is turned on, the floating diffusion node FN1 is electrically connected to the floating diffusion node FN, increasing the capacitance of the floating diffusion node FN.

[0102] The conversion gain of pixel PXf is inversely proportional to the capacitance of floating diffusion node FN, so the conversion gain when gain control transistor CX is turned off is higher than the conversion gain when gain control transistor CX is turned on. When gain control transistor CX is turned off, it is called HCG (high conversion gain) mode, and when gain control transistor CX is turned on, it is called LCG (low conversion gain) mode.

[0103] At night or in a dark environment, when the amount of light incident on the pixel array 110 of the image sensor 100 (FIG. 1) is low, the pixel array 110 operates in HCG mode. This increases the signal-to-noise ratio (SNR) of the image sensor 100 (FIG. 1), lowering the minimum detectable light level and improving the low-light sensing performance of the image sensor 100. During the day or in a bright environment, when the amount of light incident on the pixel array 110 of the image sensor 100 is high, the pixel array 110 operates in LCG mode. This increases the full-well capacity (FWC) of the pixel PXf, thereby improving the high-light sensing performance of the image sensor 100.

[0104] In this way, pixel PXf provides dual conversion gain, allowing image sensor 100 to generate high-quality images in both bright and dark environments. Image sensor 100 can also generate a first image generated in HCG mode and a second image generated in LCG mode in succession, and merge the first and second images to generate an image with a high dynamic range.

[0105] 8 illustrates pixel PXf including one gain control transistor CX, but is not limited to this. In one embodiment, pixel PXf includes two or more gain control transistors CX connected in series, and the conversion gain of pixel PXf is determined by the number of gain control transistors CX that are turned on. For example, if pixel PXf includes two gain control transistors CX, when both gain control transistors CX are turned off, it is referred to as HCG mode, when one gain control transistor CX is turned on, it is referred to as MCG mode (middle conversion gain), and when both gain control transistors CX are turned on, it is referred to as LCG mode.

[0106] 9A, 9B, and 9C are plan views illustrating examples of pixels according to an embodiment of the present invention. The pixels PXf1, PXf2, and PXf3 in FIGS. 9A through 9C are modifications of the pixel PXa in FIG. 4. Therefore, the following description will focus on the differences from FIG. 4.

[0107] 9A, pixel PXf1 includes first to fourth subpixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth subpixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0108] The pixel PXf1 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY. The first drive gate SFG1 and the second drive gate SFG2 are connected to the internal wiring WR via contacts CT.

[0109] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in a first direction at the top or bottom of the pixel PXf1, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4, with the reset gate RG being arranged in the center of the pixel PXf1, and the gain control gate CG and the dummy gate DMY being arranged symmetrically around the reset gate RG.

[0110] A wiring WRfd is connected to a well region between the gain control gate CG and the reset gate RG, in other words, a floating diffusion node FN1 (FIG. 8), via a contact CT. The wiring WRfd extends in a first direction and / or a second direction, thereby forming a capacitor at the floating diffusion node FN1. The longer the length of the wiring WRfd, the greater the capacitance of the floating diffusion node FN1. In one embodiment, the wiring WRfd is connected to the floating diffusion node FN1 of an adjacent pixel PXf1. The floating diffusion node FN1 is shared between the adjacent pixels PXf1.

[0111] In one embodiment (not shown in FIG. 9A), the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the second direction on the left or right side of pixel PXf1, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4.

[0112] Referring to FIG. 9B, pixel PXf2 includes first subpixel SPX1 to fourth subpixel SPX4, first drive gate SFG1 and second drive gate SFG2, first select gate SG1 and second select gate SG2, first drive gate SFG1 and second drive gate SFG2, reset gate RG, gain control gate CG, and dummy gate DMY.

[0113] The first and second select gates SG1 and SG2 are arranged side by side in the first direction between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. The reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXf2.

[0114] In one embodiment (not shown in FIG. 9B), the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXf2.

[0115] Referring to FIG. 9C, pixel PXf3 includes first to fourth subpixels SPX1 to SPX4, a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and a gain control gate CG.

[0116] The structure of pixel PXf3 in Fig. 9C is similar to the structure of pixel PXf1 in Fig. 9A, except that pixel PXf3 does not include a dummy gate DMY, and the reset gate RG and gain control gate CG are arranged symmetrically in the first direction with respect to the center of pixel PXf3.

[0117] 10A and 10B are plan views illustrating an example of a pixel according to an embodiment of the present invention. The pixel PXg1 in Fig. 10A is a modified example of the pixel PXf1 in Fig. 9A. Therefore, the following description will focus on the differences from Fig. 9A.

[0118] 10A, pixel PXg1 includes first to fourth subpixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth subpixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0119] The pixel PXg1 may further include a drive gate SFG, a select gate SG, a reset gate RG, and a gain control gate CG. In one embodiment, the pixel PXg1 may further include a dummy gate DMY. The drive gate SFG is coupled to the internal wiring WR via a contact CT.

[0120] The reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. The gain control gate CG and the dummy gate DMY are arranged symmetrically in the first direction with the reset gate RG at the center.

[0121] Unlike pixel PXf1 of FIG. 9A, pixel PXg1 includes one drive gate SFG and one select gate SG. The drive gate SFG and select gate SG are centrally located at the top or bottom of pixel PXg1. In one embodiment (not shown in FIG. 10A), a dummy gate DMY is positioned symmetrically with the select gate SG in the first direction around the drive gate SFG.

[0122] In one embodiment (not shown in FIG. 10A), the drive gate SFG and the select gate SG are arranged side by side in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXg1.

[0123] In one embodiment (not shown in FIG. 10A ), the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction between the first and third subpixels SPX1 and SPX3 and the second and fourth subpixels SPX2 and SPX4, and the drive gate SFG and the select gate SG are arranged side by side in the second direction at the center of the left or right side of the pixel PXg1. Alternatively, the drive gate SFG and the select gate SG are arranged side by side in the second direction between the first and third subpixels SPX1 and SPX3 and the second and fourth subpixels SPX2 and SPX4, and the reset gate RG, the gain control gate CG, and the dummy gate DMY are arranged side by side in the second direction at the center of the left or right side of the pixel PXg1.

[0124] Referring to FIG. 10B, the pixel PXg2 does not include a dummy gate DMY, and the reset gate RG and the gain control gate CG are arranged symmetrically in the first direction with respect to the center of the pixel PXg2.

[0125] 11A, 11B, and 11C are plan views illustrating examples of pixels according to an embodiment of the present invention. The pixel PXh1 in FIG. 11A is a modified example of the pixel PXf1 in FIG. 9A. Therefore, the following description will focus on the differences from FIG. 9A.

[0126] 11A, pixel PXh1 includes first to fourth subpixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth subpixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0127] The pixel PXh1 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY. The first drive gate SFG1 and the second drive gate SFG2 are connected to the internal wiring WR via contacts CT.

[0128] The first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the first direction at the top or bottom of the pixel PXh1, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4. With respect to the center of the pixel PXh1 as the reference, the second gain control gate CG2 and the dummy gate DMY are arranged symmetrically in the first direction, and the first gain control gate CG1 and the reset gate RG are arranged symmetrically in the first direction.

[0129] A wiring WRfd1 is connected to a well region between the first gain control gate CG1 and the reset gate RG via a contact CT, and a wiring WRfd2 is connected to a well region between the second gain control gate CG2 and the first gain control gate CG1. The wirings (WRfd1, WRfd2) extend in a first direction and / or a second direction. In one embodiment, at least one of the wirings (WRfd1, WRfd2) is connected to one of the floating diffusion nodes of the adjacent pixel PXh1.

[0130] In one embodiment (not shown in FIG. 11A), the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the second direction on the left or right side of pixel PXh1, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4.

[0131] Referring to FIG. 11B, pixel PXh2 includes first subpixel SPX1 to fourth subpixel SPX4, first drive gate SFG1 and second drive gate SFG2, first select gate SG1 and second select gate SG2, first drive gate SFG1 and second drive gate SFG2, reset gate RG, second gain control gate CG2, first gain control gate CG1, second gain control gate CG2, and dummy gate DMY.

[0132] The first and second select gates SG1 and SG2, and the first and second drive gates SFG1 and SFG2 are arranged side by side in the first direction between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. The second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXh2.

[0133] In one embodiment (not shown in FIG. 11B), the first drive gate SFG1 and the second drive gate SFG2, and the first select gate SG1 and the second select gate SG2 are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of pixel PXh2.

[0134] Referring to FIG. 11C, pixel PXh3 includes first subpixel SPX1 to fourth subpixel SPX4, first drive gate SFG1 and second drive gate SFG2, first select gate SG1 and second select gate SG2, reset gate RG, and first gain control gate CG1 and second gain control gate CG2.

[0135] The structure of pixel PXh3 in Figure 11C is similar to the structure of pixel PXh1 in Figure 11A. However, pixel PXh3 does not include a dummy gate DMY, and the second gain control gate CG2, the first gain control gate CG1, and the reset gate RG are arranged side by side in the first direction at the center of pixel PXh3. In one embodiment, the first gain control gate CG1 is arranged at the center of pixel PXh3, and the second gain control gate CG2 and the reset gate RG are arranged symmetrically in the first direction around the first gain control gate CG1.

[0136] 12A, 12B, and 12C are plan views illustrating examples of pixels according to an embodiment of the present invention. Pixel PXil in Fig. 12A is a modified example of pixel PXh1 in Fig. 11A. Therefore, the following description will focus on the differences from Fig. 11A.

[0137] 12A, pixel PXi1 includes first to fourth subpixels SPX1 to SPX4, which have the same structure. First to fourth floating diffusion regions FD1 to FD4 are disposed at the centers of the first to fourth subpixels SPX1 to SPX4, respectively. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0138] The pixel PXil includes a drive gate SFG, a select gate SG, a reset gate RG, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY. The drive gate SFG is connected to the internal wiring WR via a contact CT.

[0139] The drive gate SFG and the select gate SG are arranged side by side in the first direction at the top or bottom of the pixel PXil. In one embodiment (not shown in FIG. 12A), the dummy gate DMY is arranged symmetrically with the select gate SG in the first direction around the drive gate SFG.

[0140] The second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction between the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 and the fourth subpixel SPX4.

[0141] In one embodiment (not shown in FIG. 12A), the drive gate SFG and the select gate SG are arranged side by side in the second direction on the left or right side of the pixel PXi1, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4.

[0142] Referring to FIG. 12B, pixel PXi2 includes first subpixel SPX1 to fourth subpixel SPX4, a drive gate SFG, a select gate SG, a reset gate RG, a second gain control gate CG2, a first gain control gate CG1, a second gain control gate CG2, and a dummy gate DMY.

[0143] The drive gate SFG and the select gate SG are arranged side by side in the first direction between the first and second subpixels SPX1 and SPX2 and the third and fourth subpixels SPX3 and SPX4. The second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXi2.

[0144] In one embodiment (not shown in FIG. 12B), the drive gate SFG and the select gate SG are arranged side by side in the second direction between the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 and the fourth subpixel SPX4, and the second gain control gate CG2, the first gain control gate CG1, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXi2.

[0145] Referring to FIG. 12C, pixel PXi3 includes first to fourth subpixels SPX1 to SPX4, a drive gate SFG, a select gate SG, a second gain control gate CG2, a first gain control gate CG1, and a reset gate RG.

[0146] The structure of pixel PXi3 in Figure 12C is similar to the structure of pixel PXi1 in Figure 12A, except that pixel PXi3 does not include a dummy gate DMY, and the second gain control gate CG2, the first gain control gate CG1, and the reset gate RG are arranged side by side in the first direction at the center of pixel PXi3. In one embodiment, the first gain control gate CG1 is arranged at the center of pixel PXi3, and the second gain control gate CG2 and the reset gate RG are arranged symmetrically in the first direction around the first gain control gate CG1.

[0147] 13A, 13B, 13C, 13D, 13E, and 13F are plan views illustrating examples of pixels according to embodiments of the present invention.

[0148] 13A to 13F, pixels PXj1, PXj2, PXj3, PXj4, PXj5, and PXj6 include first to fourth subpixels SPX1 to SPX4, which are arranged in a first direction, e.g., the X-axis direction. Here, the first direction is the row direction of the pixel array 110 (FIG. 1). Each of the first to fourth subpixels SPX1 to SPX4 includes a first to fourth photoelectric conversion element PD1 to PD4, a first to fourth transfer gate TG1 to TG4, and a floating diffusion region FD. A first to fourth floating diffusion region FD1 to FD4 are disposed at the center of each of the first to fourth subpixels SPX1 to SPX4. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0149] 13A, the pixel PXj1 further includes a drive gate SFG, a select gate SG, a reset gate RG, and a dummy gate DMY, which are arranged side by side in the first direction at the top or bottom of the pixel PXj1.

[0150] The drive gate SFG, the select gate SG, the reset gate RG, and the dummy gate DMY are disposed at the center of the top or bottom of the pixel PXj1, but are not limited thereto, and the positions of the drive gate SFG, the select gate SG, the reset gate RG, and the dummy gate DMY can be adjusted.

[0151] The source of the reset gate RG and the drive gate SFG are connected to the internal wiring WR via contacts CT, respectively.

[0152] 13B, pixel PXj2 further includes a drive gate SFG, a select gate SG, a reset gate RG, a gain control gate CG, and a dummy gate DMY, which are arranged side by side in the first direction at the top or bottom of pixel PXj2.

[0153] A gain control gate CG and a dummy gate DMY are disposed on both sides of the reset gate RG. A wiring WRfd1 is connected to a well region between the reset gate RG and the gain control gate CG via a contact CT, and the wiring WRfd1 extends in a first direction and a second direction.

[0154] Referring to FIG. 13C, the pixel PXj3 further includes a drive gate SFG, a select gate SG, a reset gate RG, a first control gate CG1, a second gain control gate CG2, and a dummy gate DMY.

[0155] The drive gate SFG, the select gate SG, the reset gate RG, the first control gate CG1, the second gain control gate CG2, and the dummy gate DMY are arranged side by side in the first direction above or below the pixel PXj3.

[0156] Wirings WRfd1 and WRfd2 are connected to the well region between the reset gate RG and the first gain control gate CG1, and to the well region between the first gain control gate CG1 and the second gain control gate CG2, respectively, via contacts CT, and the wirings WRfd1 and WRfd2 extend in the first and second directions.

[0157] Referring to FIG. 13D, the pixel PXj4 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and a dummy gate DMY.

[0158] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, and the dummy gate DMY are arranged side by side in the first direction above or below the pixel PXj4, and the first select gate SG1 and the second select gate SG2 are arranged between the first drive gate SFG1 and the second drive gate SFG2.

[0159] The source of the reset gate RG, the first driving gate SFG1, and the second driving gate SFG2 are connected to the internal wiring WR via contacts CT, respectively.

[0160] 13E, pixel PXj5 may further include a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY, which are arranged side by side in the first direction at the top or bottom of pixel PXj5.

[0161] Referring to FIG. 13F, pixel PXj6 may further include a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a first control gate CG1 and a second gain control gate CG2, and a dummy gate DMY.

[0162] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, the first control gate CG1 and the second gain control gate CG2, and the dummy gate DMY are arranged side by side in the first direction at the top or bottom of the pixel PXj6.

[0163] 14A, 14B, 14C, 14D, 14E, and 14F are plan views illustrating examples of pixels according to embodiments of the present invention.

[0164] 14A to 14F, pixels PXk1, PXk2, PXk3, PXk4, PXk5, and PXk6 include first to fourth subpixels SPX1 to SPX4, which are arranged in a second direction, e.g., the Y-axis direction. Here, the second direction is the column direction of the pixel array 110 (FIG. 1). Each of the first to fourth subpixels SPX1 to SPX4 includes a first to fourth photoelectric conversion element PD1 to PD4, a first to fourth transfer gate TG1 to TG4, and a floating diffusion region. A first to fourth floating diffusion region FD1 to FD4 are disposed at the center of each of the first to fourth subpixels SPX1 to SPX4. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0165] 14A, pixel PXk1 may further include a drive gate SFG, a select gate SG, a reset gate RG, and a dummy gate DMY, which are arranged side by side in the second direction on the left or right side of pixel PXk1.

[0166] The drive gate SFG, the select gate SG, the reset gate RG, and the dummy gate DMY are disposed in the center of the left or right side of the pixel PXk1, but are not limited to this, and the positions of the drive gate SFG, the select gate SG, the reset gate RG, and the dummy gate DMY may be adjusted.

[0167] The source of the reset gate RG and the drive gate SFG are connected to the internal wiring WR via contacts CT, respectively.

[0168] 14B, pixel PXk2 may further include a drive gate SFG, a select gate SG, a reset gate RG, a gain control gate CG, and a dummy gate DMY, which are arranged side by side in the second direction on the left or right side of pixel PXk2.

[0169] A gain control gate CG and a dummy gate DMY are respectively disposed above and below the reset gate RG. A wiring WRfd is connected to a well region between the reset gate RG and the gain control gate CG via a contact CT, and the wiring WRfd extends in a first direction and a second direction.

[0170] Referring to FIG. 14C, pixel PXk3 may further include a drive gate SFG, a select gate SG, a reset gate RG, a first control gate CG1 and a second gain control gate CG2, and a dummy gate DMY.

[0171] The drive gate SFG, select gate SG, reset gate RG, first control gate CG1, second gain control gate CG2, and dummy gate DMY are arranged side by side in the second direction on the left or right side of pixel PXk3.

[0172] Wirings WRfd1 and WRfd2 are connected to the well region between the reset gate RG and the first gain control gate CG1, and to the well region between the first gain control gate CG1 and the second gain control gate CG2, respectively, via contacts CT, and the wirings WRfd1 and WRfd2 extend in the first and second directions.

[0173] Referring to FIG. 14D, pixel PXk4 may further include a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and a dummy gate DMY.

[0174] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXk4, and the first select gate SG1 and the second select gate SG2 are arranged between the first drive gate SFG1 and the second drive gate SFG2.

[0175] The source of the reset gate RG, the first drive gate SFG1 and the second drive gate SFG2 are connected to the internal wiring WR via contacts CT, respectively.

[0176] 14E, pixel PXk5 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a gain control gate CG, and a dummy gate DMY, which are arranged side by side in the second direction on the left or right side of pixel PXk5.

[0177] Referring to FIG. 14F, the pixel PXj6 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, a first control gate CG1 and a second gain control gate CG2, and a dummy gate DMY.

[0178] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, the first control gate CG1 and the second gain control gate CG2, and the dummy gate DMY are arranged side by side in the second direction on the left or right side of the pixel PXk6.

[0179] 15A, 15B, and 15C are plan views illustrating examples of pixels according to embodiments of the present invention.

[0180] 15A to 15C, pixels PX11, PX12, and PX13 include first to fourth subpixels SPX1 to SPX4, which are arranged in a second direction, e.g., the Y-axis direction. Here, the second direction is the column direction of pixel array 110 (FIG. 1). Each of the first to fourth subpixels SPX1 to SPX4 includes a first to fourth photoelectric conversion element PD1 to PD4, a first to fourth transfer gate TG1 to TG4, and a floating diffusion region. A first to fourth floating diffusion region FD1 to FD4 are disposed at the center of each of the first to fourth subpixels SPX1 to SPX4. Internal wiring WR is connected to the first to fourth floating diffusion regions FD1 to FD4 via contacts CT.

[0181] Referring to FIG. 15A, pixel PX11 further includes a first drive gate SFG1 and a second drive gate SFG2, a first select gate SG1 and a second select gate SG2, a reset gate RG, and first to third dummy gates DMY1 to DMY3.

[0182] The first drive gate SFG1 and the second drive gate SFG2, the first select gate SG1 and the second select gate SG2, the reset gate RG, and the first dummy gate DMY1 to the third dummy gate DMY3 are arranged side by side in the second direction on the left or right side of the pixel PX11.

[0183] A first drive gate SFG1 and a first select gate SG1 are arranged between the first dummy gate DMY1 and the second dummy gate DMY, and a reset gate RG, a second drive gate SFG2, and a second select gate SG are arranged in this order between the second dummy gate DMY2 and the third dummy gate DMY3.

[0184] The source of the reset gate RG, the first drive gate SFG1 and the second drive gate SFG2 are connected to the internal wiring WR via contacts CT, respectively.

[0185] 15B, pixel PX12 further includes a gain control gate CG, which is disposed between reset gate RG and second drive gate SFG2. A well region between reset gate RG and gain control gate CG is connected to wiring WRfd via contact CT, and wiring WRfd extends in the first and second directions.

[0186] 15C, pixel PX13 further includes a first control gate CG1 and a second gain control gate CG2, as compared with pixel PX11 of FIG. 15A. The first control gate CG1 and the second gain control gate CG2 are disposed between reset gate RG and second drive gate SFG2. The well region between reset gate RG and first gain control gate CG1 and the well region between first gain control gate CG1 and second gain control gate CG2 are connected to wirings WRfd1 and WRfd2 via contacts CT, respectively, and the wirings WRfd1 and WRfd2 extend in the first and second directions.

[0187] 16A, 16B, 16C, and 16D show microlenses disposed in pixels according to one embodiment of the present invention.

[0188] The pixel PX according to the various embodiments described above may be applied as the pixel PX of this embodiment. The pixel PX includes first to fourth sub-pixels SPX1 to SPX4, each of which includes a plurality of photoelectric conversion elements PD and a floating diffusion region FD. The photoelectric conversion elements PD included in the first to fourth sub-pixels SPX1 to SPX4 are electrically connected to each other via internal wiring.

[0189] 16A, a microlens ML is disposed above a photoelectric conversion element PD. A plurality of microlenses ML are disposed on a plurality of photoelectric conversion elements PD included in a pixel PX. The pixel PX outputs a pixel signal based on charges generated in each of the plurality of photoelectric conversion elements PD, or outputs a pixel signal based on charges generated in some or all of the plurality of photoelectric conversion elements PD.

[0190] 16B, a plurality of microlenses ML are disposed on the four photoelectric conversion elements PD included in each of the first to fourth sub-pixels SPX1 to SPX4. In other words, a microlens ML is disposed in each of the first to fourth sub-pixels SPX1 to SPX4. The pixel PX outputs a pixel signal based on charges generated in each of the first to fourth sub-pixels SPX1 to SPX4, or outputs a pixel signal based on charges generated in some or all of the first to fourth sub-pixels SPX1 to SPX4.

[0191] 16C and 16D, a microlens ML is disposed on every two adjacent photoelectric conversion elements among the plurality of photoelectric conversion elements PD. As shown in Fig. 16C, a microlens ML is disposed on every two adjacent photoelectric conversion elements in the first direction, or as shown in Fig. 16D, a microlens ML is disposed on every two adjacent photoelectric conversion elements in the second direction.

[0192] In one embodiment, in some of the first subpixel SPX1 to the fourth subpixel SPX4, a microlens ML is arranged on two photoelectric conversion elements adjacent to each other in the first direction, and in other subpixels, a microlens ML is arranged on two photoelectric conversion elements adjacent to each other in the second direction.

[0193] 17A, 17B, 17C, 17D, 17E, and 17F show color filters disposed on pixel array 110 according to one embodiment of the present invention.

[0194] The pixel PX of this embodiment is one of the pixels according to the various embodiments described above. The pixel PX includes first to fourth sub-pixels SPX1 to SPX4, each of which includes a plurality of photoelectric conversion elements PD and a floating diffusion region FD. The photoelectric conversion elements PD included in the first to fourth sub-pixels SPX1 to SPX4 are electrically connected to each other via internal wiring.

[0195] Referring to FIG. 17A , the first pixel PX1 through the fourth pixel PX4 are arranged in a 2×2 matrix. A red color filter CF_R is arranged over the first pixel PX1, a green color filter CF_G is arranged over the second pixel PX2 and the third pixel PX3, and a blue color filter CF_B is arranged over the fourth pixel PX4. This combination of one red color filter CF_R, two green color filters CF_G, and one blue color filter CF_G is referred to as a Bayer pattern. In the pixel array 110, every four pixels arranged in a 2×2 matrix have a Bayer pattern. In one embodiment, the color combination of the color filters arranged over the first pixel PX1 through the fourth pixel PX4 may be changed. For example, a white color filter may be arranged over one of the second pixel PX2 and the third pixel PX3. As another example, a white color filter may be arranged over the second pixel PX2 and the third pixel PX3. As another example, a yellow color filter may be disposed over the second pixel PX2 and the third pixel PX3.

[0196] 17B, the first sub-pixel SPX1 to the fourth sub-pixel SPX4 are arranged in a 2x2 matrix, with a red color filter CF_R arranged on the first sub-pixel SPX1, a green color filter CF_G arranged on the second sub-pixel SPX2 and the third sub-pixel SPX3, and a blue color filter CF_B arranged on the fourth sub-pixel SPX4. Each of the pixels PX arranged in the pixel array 110 has a Bayer pattern.

[0197] Referring to Figure 17C, the first pixel PX1 to the fourth pixel PX4 are arranged side by side in the second direction, and each of the first pixel PX1 to the fourth pixel PX4 includes the first sub-pixel SPX1 to the fourth sub-pixel SPX4 arranged side by side in the first direction.

[0198] A red color filter CF_R is arranged in the first sub-pixel SPX1 and the second sub-pixel SPX2 of the first pixel PX1 and the second pixel PX2, a green color filter CF_G is arranged in the third sub-pixel SPX3 and the fourth sub-pixel SPX4 of the first pixel PX1 and the second pixel PX2 and the first sub-pixel SPX1 and the second sub-pixel SPX2 of the third pixel PX3 and the fourth pixel PX4, and a blue color filter CF_B is arranged in the third sub-pixel SPX3 and the fourth sub-pixel SPX4 of the third pixel PX3 and the fourth pixel X4. In this way, in the pixel array 110, each of the 16 sub-pixels arranged in a 4x4 matrix has a Bayer pattern.

[0199] Referring to Figure 17D, a first pixel PX1 and a second pixel PX2 are arranged side by side in the second direction, and each of the first pixel PX1 and the second pixel PX2 includes a first sub-pixel SPX1 to a fourth sub-pixel SPX4 arranged side by side in the first direction.

[0200] A red color filter CF_R is arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the first pixel PX1, and a green color filter CF_G is arranged in the second sub-pixel SPX2 and the fourth sub-pixel PSX4 of the first pixel PX1. A green color filter CF_G is arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the second pixel PX2, and a blue color filter CF_B is arranged in the second sub-pixel SPX2 and the fourth sub-pixel PSX4 of the second pixel PX1. In this way, every four sub-pixels arranged in a 2x2 matrix have a Bayer pattern.

[0201] Referring to Figure 17E, the first pixel PX1 to the fourth pixel PX4 are arranged side by side in the first direction, and each of the first pixel PX1 to the fourth pixel PX4 includes the first sub-pixel SPX1 to the fourth sub-pixel SPX4 arranged side by side in the second direction.

[0202] A red color filter CF_R is disposed in the first sub-pixel SPX1 and the second sub-pixel SPX2 of the first pixel PX1 and the second pixel PX2, a green color filter CF_G is disposed in the third sub-pixel SPX3 and the fourth sub-pixel SPX4 of the first pixel PX1 and the second pixel PX2 and the first sub-pixel SPX1 and the second sub-pixel SPX2 of the third pixel PX3 and the fourth pixel PX4, and a blue color filter CF_B is disposed in the third sub-pixel SPX3 and the fourth sub-pixel SPX4 of the third and fourth pixels PX3 and PX4. In this way, the pixel array 110 has a Bayer pattern for each of the 16 sub-pixels arranged in a 4x4 matrix.

[0203] Referring to Figure 17F, a first pixel PX1 and a second pixel PX2 are arranged side by side in a first direction, and each of the first pixel PX1 and the second pixel PX2 includes a first sub-pixel SPX1 to a fourth sub-pixel SPX4 arranged side by side in a second direction.

[0204] A red color filter CF_R is arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the first pixel PX1, and a green color filter CF_G is arranged in the second sub-pixel SPX2 and the fourth sub-pixel PSX4 of the first pixel PX1. A green color filter CF_G is arranged in the first sub-pixel SPX1 and the third sub-pixel SPX3 of the second pixel PX2, and a blue color filter CF_B is arranged in the second sub-pixel SPX2 and the fourth sub-pixel PSX4 of the second pixel PX2. In this way, every four sub-pixels arranged in a 2x2 matrix have a Bayer pattern.

[0205] 18 and 19 are block diagrams of an electronic device including a multi-camera module, and FIG. 19 is a detailed block diagram of the camera module of FIG.

[0206] Referring to FIG. 18, an electronic device 1000 includes a camera module group 1100, an application processor 1200, a PMIC (power management integrated circuit) 1300, and an external memory 1400.

[0207] The camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). While FIG. 18 illustrates an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, this embodiment is not limited to this. In some embodiments, the camera module group 1100 is modified to include only two camera modules. In some embodiments, the camera module group 1100 is modified to include k camera modules (k is a natural number greater than or equal to 4).

[0208] The detailed configuration of camera module 1100b will be described in more detail below with reference to FIG. 19, but the following description also applies equally to other camera modules (1100a, 1100c) depending on the embodiment.

[0209] Referring to FIG. 19, a camera module 1100 b includes a prism 1105 , an optical path folding element (OPFE) 1110 , an actuator 1130 , an image sensing device 1140 , and a storage unit 1150 .

[0210] The prism 1105 includes a reflecting surface 1107 made of a light-reflecting material, and changes the path of light L incident from the outside.

[0211] In some embodiments, the prism 1105 changes the path of light L incident from a first direction X to a second direction Y perpendicular to the first direction X. The prism 1105 also changes the path of light L incident in the first direction X to the second direction Y perpendicular thereto by rotating a reflective surface 1107 of a light-reflecting material around a central axis 1106 in a direction A or by rotating the central axis 1106 in a direction B. At this time, the OPFE 1110 also moves in a third direction Z perpendicular to the first direction X and the second direction Y.

[0212] In some embodiments, as shown, the maximum rotation angle of prism 1105 in the A direction is 15° or less in the positive (+) A direction and 15° or more in the negative (-) A direction, although the present embodiments are not limited thereto.

[0213] In some embodiments, the prism 1105 moves in the plus (+) B direction or the minus (-) B direction by around 20°, or between 10° and 20°, or between 15° and 20°, where the angle of movement is the same angle in the plus (+) B direction or the minus (-) B direction, or to a similar angle within a range of around 1°.

[0214] In some embodiments, the prism 1105 moves the reflective surface 1107 of the light-reflecting material in a third direction (eg, the Z direction) parallel to the extension direction of the central axis 1106 .

[0215] The OPFE 1110 includes, for example, m (where m is a natural number) groups of optical lenses. The m lenses move in the second direction Y to change the optical zoom ratio of the camera module 1100b. For example, if the basic optical zoom ratio of the camera module 1100b is Z, when the m optical lenses included in the OPFE 1110 are moved, the optical zoom ratio of the camera module 1100b is changed to 3Z, 5Z, or an optical zoom ratio of 5Z or more.

[0216] The actuator 1130 moves the OPFE 1110 (or the optical lens) to a specific position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0217] The image sensing device 1140 includes an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 senses an image of a sensing target using light L provided through an optical lens. The pixel and pixel array described with reference to FIGS. 2 to 17F are applied to the image sensor 1142. The pixel includes multiple sub-pixels (e.g., four sub-pixels), each including multiple photoelectric conversion elements and floating diffusion regions, and the multiple floating diffusion regions of the multiple sub-pixels are electrically connected via wiring. The multiple sub-pixels have multiple sensitivities. Therefore, the resolution and image quality of the image sensor 1142 are improved.

[0218] Control logic 1144 controls the overall operation of camera module 1100b, for example, via control signals provided over control signal line CSLb.

[0219] The memory 1146 stores information necessary for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 includes information necessary for the camera module 1100b to generate image data using externally provided light L. For example, the calibration data 1147 includes information related to the degree of rotation, the focal length, and the optical axis. If the camera module 1100b is implemented as a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 1147 includes the focal length value for each position (or each state) of the optical lens and information related to autofocusing.

[0220] The storage unit 1150 stores image data sensed through the image sensor 1142. The storage unit 1150 is disposed outside the image sensing device 1140 and is implemented in a stacked form on a sensor chip constituting the image sensing device 1140.

[0221] In some embodiments, the storage unit 1150 is implemented by an EEPROM (electrically erasable programmable read-only memory), but the present embodiment is not limited thereto. In some embodiments, the image sensor 1142 is configured by a pixel array, and the control logic 1144 includes an analog to digital converter and an image signal processing unit for processing the sensed image.

[0222] 18 and 19, in some embodiments, each of the multiple camera modules (1100a, 1100b, 1100c) includes an actuator 1130. As a result, each of the multiple camera modules (1100a, 1100b, 1100c) includes calibration data 1147 that may be identical to or different from one another depending on the operation of the actuator 1130 included therein.

[0223] In some embodiments, among the multiple camera modules (1100a, 1100b, 1100c), for example, one camera module 1100b is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (1100a, 1100c) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but this embodiment is not limited to these.

[0224] In some embodiments, one of the camera modules (1100a, 1100b, 1100c), for example, camera module 1100c, is a vertical depth camera that extracts depth information using infrared ray (IR). In this case, application processor 1200 may, for example, merge image data provided by the vertical depth camera with image data provided by a different camera module (1100a or 1100b) to generate a 3D depth image.

[0225] In some embodiments, for example, at least two of the camera modules (1100a, 1100b, 1100c) have different fields of view (fields of view). In this case, for example, at least two of the camera modules (1100a, 1100b, 1100c) have different optical lenses, but this is not limiting.

[0226] In some embodiments, the viewing angles of the camera modules (1100a, 1100b, 1100c) are different from one another. For example, but not limited to, camera module 1100a is an ultrawide camera, camera module 1100b is a wide camera, and camera module 1100c is a telephoto camera. In this case, the optical lenses included in the camera modules (1100a, 1100b, 1100c) are also different from one another, but are not limited to this.

[0227] In some embodiments, the multiple camera modules (1100a, 1100b, 1100c) are arranged to be physically separated from one another. That is, instead of the multiple camera modules (1100a, 1100b, 1100c) sharing the sensing area of one image sensor 1142, an independent image sensor 1142 is arranged inside each of the multiple camera modules (1100a, 1100b, 1100c).

[0228] 18, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 is implemented separately from the camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c are implemented separately from each other as separate semiconductor chips.

[0229] The image processing device 1210 includes a number of sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216.

[0230] The image processing device 1210 includes a plurality of sub-image processors (1212a, 1212b, 1212c) whose number corresponds to the number of the camera modules (1100a, 1100b, 1100c).

[0231] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to the corresponding sub-image processor (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such image data transmission is performed using, for example, a camera serial interface (CSI) based on MIPI (mobile industry processor interface), but the present embodiment is not limited thereto.

[0232] In some embodiments, one sub-image processor is arranged to correspond to multiple camera modules. For example, sub-image processor 1212a and sub-image processor 1212c are not implemented separately from each other as shown in the figure, but are integrated into one sub-image processor, and image data provided from camera module 1100a and camera module 1100c is selected via a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. In this case, sub-image processor 1212b is not integrated and receives image data from camera module 1100b.

[0233] In some embodiments, image data generated by camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated by camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated by camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. The image data processed by sub-image processor 1212b is provided immediately to image generator 1214, but either the image data processed by sub-image processor 1212a or the image data processed by sub-image processor 1212c is selected via a selection element (e.g., a multiplexer) or the like and then provided to image generator 1214.

[0234] Each sub-image processor (1212a, 1212b, 1212c) performs image processing such as bad pixel correction, 3A (auto-focus correction, auto-white balance, auto-exposure) adjustment, noise reduction, sharpening, gamma control, and remosaic on the image data provided by the camera modules (1100a, 1100b, 1100c).

[0235] In some embodiments, the re-mosaic signal processing is performed in each camera module (1100a, 1100b, 1100c) before being provided to the sub-image processors (1212a, 1212b, 1212c).

[0236] The image data processed by each of the sub-image processors (1212a, 1212b, 1212c) is provided to an image generator 1214. The image generator 1214 generates an output image using the image data provided by each of the sub-image processors (1212a, 1212b, 1212c) according to image generation information or a mode signal.

[0237] Specifically, the image generator 1214 generates an output image by combining at least some of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or mode signal. Also, the image generator 1214 generates an output image by selecting one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or mode signal.

[0238] In some embodiments, the image generation information includes a zoom signal (zoom signal or zoom factor), and in some embodiments, the mode signal is based on, for example, a mode selected by a user.

[0239] When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different field of view (viewing angle), the image generator 1214 performs different operations depending on the type of zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 generates an output image using the image data output from sub-image processor 1212a and the image data output from sub-image processor 1212b among the image data output from sub-image processor 1212a and the image data output from sub-image processor 1212c. When the zoom signal is a second signal different from the first signal, the image generator 1214 generates an output image using the image data output from sub-image processor 1212a and the image data output from sub-image processor 1212c among the image data output from sub-image processor 1212a and the image data output from sub-image processor 1212c. If the zoom signal is a third signal different from the first and second signals, the image generator 1214 does not perform such image data merging, but instead selects one of the image data output from each of the sub-image processors (1212a, 1212b, 1212c) to generate an output image. However, this embodiment is not limited to this, and the method of processing image data can be modified in any way as needed.

[0240] In some embodiments, the image processing device 1210 may further include a selection unit that selects the output of the sub-image processors (1212a, 1212b, 1212c) and transmits it to the image generator 1214.

[0241] In this case, the selector performs different operations depending on the zoom signal or zoom factor. For example, if the zoom signal is the fourth signal (the zoom magnification is the first magnification), the selector selects one of the outputs of the sub-image processors 1212a, 1212b, and 1212c and transmits it to the image generator 1214.

[0242] Furthermore, for example, when the zoom signal is a fifth signal (the zoom magnification is second) different from the fourth signal, the selector sequentially transmits p outputs (p is a natural number greater than or equal to 2) of the outputs of the sub-image processors (1212a, 1212b, 1212c) to the image generator 1214. For example, the selector sequentially transmits the outputs of the sub-image processors 1212b and 1212c to the image generator 1214. The selector sequentially transmits the outputs of the sub-image processors 1212a and 1212b to the image generator 1214. The image generator 1214 merges the p outputs sequentially provided to generate one output image.

[0243] Here, image processing such as demosaic, video / preview, resolution size downscaling, gamma correction, and HDR (high dynamic range) processing is performed in advance in the sub-image processors 1212a, 1212b, and 1212c, and then the processed image data is transmitted to the image generator 1214. Therefore, even though the processed image data is provided to the image generator 1214 via a single signal line via a selection unit, the image merging operation of the image generator 1214 can be performed at high speed.

[0244] In some embodiments, the image generator 1214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors (1212a, 1212b, 1212c) and performs HDR processing on the multiple image data to generate merged image data with an increased dynamic range.

[0245] The camera module controller 1216 provides control signals to each of the camera modules (1100a, 1100b, 1100c). The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via mutually separated control signal lines (CSLa, CSLb, CSLc).

[0246] One of the camera modules 1100a, 1100b, and 1100c is designated as a master camera 1100b, for example, by image generation information including a zoom signal or a mode signal, and the remaining camera modules 1100a and 1100c are designated as slave cameras, for example. Such information is included in a control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0247] The camera modules operating as master and slave are changed depending on the zoom factor or operation mode signal. For example, if the viewing angle of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a low zoom ratio, camera module 1100b operates as the master and camera module 1100a operates as the slave. Conversely, if the zoom factor indicates a high zoom ratio, camera module 1100a operates as the master and camera module 1100b operates as the slave.

[0248] In some embodiments, the control signals provided from camera module controller 1216 to each camera module (1100a, 1100b, 1100c) include a sync enable signal. For example, if camera module 1100b is the master camera and camera modules 1100a and 1100c are slave cameras, camera module controller 1216 transmits the sync enable signal to camera module 1100b. Upon receiving such a sync enable signal, camera module 1100b generates a sync signal based on the received sync enable signal and provides the generated sync signal to camera modules 1100a and 1100c via sync signal line SSL. Camera modules 1100b and 1100a and 1100c are synchronized by the sync signal and transmit image data to application processor 1200.

[0249] In some embodiments, the control signals provided to the camera modules (1100a, 1100b, 1100c) from the camera module controller 1216 include mode information in the form of a mode signal, and based on the mode information, the camera modules (1100a, 1100b, 1100c) operate in a first operation mode or a second operation mode, which are related to sensing speeds.

[0250] In a first operation mode, the camera modules (1100a, 1100b, 1100c) generate, for example, an image signal (image signal having a first frame rate) at a first rate, encode the image signal at a second rate (second frame rate higher than the first frame rate) that is higher than the first rate, and transmit the encoded image signal to the application processor 1200. In this case, the second rate is 30 times or less than the first rate.

[0251] The application processor 1200 stores the received image signal, in other words, the encoded image signal, in an internal memory 1230 provided therein or in an external memory 1400 outside the application processor 1200, and then reads and decodes the encoded image signal from the internal memory 1230 or the external memory 1400, and displays image data generated based on the decoded image signal. For example, a corresponding one of the multiple sub-processors (1212a, 1212b, 1212c) of the image processing device 1210 performs decoding and image processing on the decoded image signal.

[0252] In the second operating mode, the camera modules (1100a, 1100b, 1100c) generate image signals at, for example, a third speed slower than the first speed (image signals at a third frame rate slower than the first frame rate) and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 are unencoded signals. The application processor 1200 performs image processing on the received image signals or stores the image signals in the internal memory 1230 or the external memory 1400.

[0253] The PMIC 1300 supplies power, e.g., a power supply voltage, to each of the multiple camera modules (1100a, 1100b, 1100c). For example, under the control of the application processor 1200, the PMIC 1300 supplies a first power to the camera module 1100a via a power signal line PSLa, a second power to the camera module 1100b via a power signal line PSLb, and a third power to the camera module 1100c via a power signal line PSLc.

[0254] The PMIC 1300 generates power and adjusts the power level corresponding to each of the camera modules (1100a, 1100b, 1100c) in response to a power control signal PCON from the application processor 1200. The power control signal PCON includes a power adjustment signal for each operation mode of the camera modules (1100a, 1100b, 1100c). For example, the operation mode includes a low power mode, and the power control signal PCON includes information related to the camera module operating in the low power mode and the power level to be set. The power levels provided to each of the camera modules (1100a, 1100b, 1100c) may be the same or different from each other. Furthermore, the power levels may be dynamically changed.

[0255] The exemplary embodiments have been disclosed above with reference to the drawings and the specification. Although specific terms have been used to describe the embodiments in this specification, they are used merely to explain the technical idea of the present invention and are not used to limit the meaning or the technical scope of the present invention. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. [Explanation of symbols]

[0256] 100, 1142 image sensor 110 pixel array 111 Substrate 112 Incidence layer 113 Wiring layer 120 Row Driver 130 Ramp Signal Generator 140 Analog-to-Digital Conversion Circuit 141 CDS circuit 142 Counter (CNTR) 150 Data output circuit 151 Column Memory (BF) 152 Column Decoder 160 Timing Controller 170 Signal Processing Unit 1000 electronic devices 1100 Camera Module Group 1105 Prism 1106 Center axis 1107 Reflective surface 1110 OPEF 1130 Actuator 1140 Image sensing device 1144 Control logic 1146 memory 1147 Calibration Data 1150 Preservation Department 1200 Application Processor 1210 Image Processing Device 1212a, 1212b, 1212c Sub-Image Processors 1214 Image Generator 1216 Camera Module Controller 1220 memory controller 1230 internal memory 1300 PMIC 1400 external memory PX pixels SPX1 1st subpixel SPX2 Second subpixel SPX3 3rd subpixel SPX4 4th subpixel

Claims

1. a substrate including a first surface and a second surface opposite to the first surface; a first pixel including first four photoelectric conversion elements (PDs) in the substrate and a first floating diffusion region (FD) shared by the first four PDs; a second pixel including four second PDs in the substrate and a second FD shared by the four second PDs; a third pixel including a third four PDs in the substrate and a third FD shared by the third four PDs; a fourth pixel including four fourth PDs in the substrate and a fourth FD shared by the four fourth PDs; a reset transistor configured to be coupled to a pixel power supply voltage; The first FD is connected to a fourth FD via a first wiring, The second FD is connected to a third FD via a second wiring, the first four PDs to the fourth four PDs are arranged in a 2×2 matrix; The image sensor, wherein the reset transistor is configured to provide the pixel power supply voltage to the first through fourth FDs.

2. The image sensor of claim 1 , further comprising a gain control transistor coupled to the reset transistor.

3. a first driving transistor configured to be connected to the first four FDs and the fourth four FDs; The image sensor of claim 1 , further comprising: a second driving transistor configured to be connected to the second four FDs and the third four FDs.

4. The image sensor of claim 1 , wherein the first pixel is connected to the second pixel through a third wiring.

5. 5. The image sensor of claim 4, wherein the first and second wirings extend in a first direction, and the third wirings extend in a second direction perpendicular to the first direction.

6. 6. The image sensor of claim 5, wherein the first wiring is connected to the second wiring via the third wiring.

7. The image sensor of claim 6 , wherein the second pixel is disposed directly adjacent to the first pixel in the second direction.

8. a first via contact arranged vertically to the first FD; a second via contact arranged vertically to the fourth FD, 6. The image sensor of claim 5, wherein the first FD is directly connected to the fourth FD through the first via contact, the first wiring, and the second via contact.

9. The image sensor of claim 8 , wherein the first via contact, the first wiring, and the second via contact are sequentially arranged in the first direction on a plane.

10. 6. The image sensor of claim 5, wherein each of the first through fourth pixels includes four microlenses.

11. a first color filter on the first four PDs; a second color filter on the second four PDs; a third color filter on the third four PDs; The image sensor of claim 5 , further comprising: a fourth color filter on the fourth four PDs.

12. a substrate including a first surface and a second surface opposite to the first surface; an array of pixels arranged in an N by M matrix; The pixel array 16 photoelectric conversion elements (PDs) in the substrate; four floating diffusion regions (FDs) including a first FD, a second FD, a third FD, and a fourth FD; a reset transistor configured to be coupled to a pixel power supply voltage; a gain control transistor configured to be coupled to the reset transistor; the reset transistor is configured to provide the pixel power supply voltage to the first through fourth FDs; The image sensor, wherein each of the first to fourth FDs is shared by four of the 16 PDs.

13. 13. The image sensor of claim 12, wherein the first through fourth FDs are connected to each other.

14. 14. The image sensor of claim 13, wherein the first through fourth FDs are connected to each other via wiring.

15. 13. The image sensor of claim 12, wherein N is four and M is four.

16. 13. The image sensor of claim 12, wherein N is 2 and M is 8.

17. 16. The image sensor of claim 15, wherein each of the first through fourth FDs is shared by pixels arranged in a 2x2 matrix.

18. a substrate including a first surface and a second surface opposite to the first surface; a first pixel including first four photoelectric conversion elements (PDs) in the substrate and a first floating diffusion region (FD) shared by the first four PDs; a second pixel including four second PDs in the substrate and a second FD shared by the four second PDs; a third pixel including a third four PDs in the substrate and a third FD shared by the third four PDs; a fourth pixel including four fourth PDs in the substrate and a fourth FD shared by the four fourth PDs; a reset transistor configured to be coupled to a pixel power supply voltage; a first driving transistor configured to be connected to the first four FDs and the fourth four FDs; a second driving transistor configured to be connected to the second four FDs and the third four FDs; The first FD is connected to a fourth FD, The second FD is connected to a third FD, the first four PDs to the fourth four PDs are arranged in a 2×2 matrix; The image sensor, wherein the reset transistor is configured to provide the pixel power supply voltage to the first through fourth FDs.

19. 20. The image sensor of claim 18, wherein the first through fourth FDs are connected to each other.

20. 20. The image sensor of claim 18, wherein the second pixel is disposed to be directly adjacent to the first pixel in a first direction, and the fourth pixel is disposed to be directly adjacent to the first pixel in a second direction perpendicular to the first direction.

Images