Semiconductor element

Abstract

To minimize short circuit between a gate and a contact.SOLUTION: A semiconductor element includes: a plurality of channel layers 140 disposed apart from each other in a vertical direction on an active region 105; a gate structure 160 including a gate electrode 165 surrounding the plurality of channel layers while intersecting with the active region and the plurality of channel layers, a gate spacer layer 164 on a side surface of the gate electrode, and a gate capping layer 166 on the gate electrode and the gate spacer layer and extending in a second direction Y; a source / drain region 150 disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers; and a contact structure 180CA disposed on the source / drain region on at least one side of the gate structure and connected to the source / drain region. An upper region of the capping layer of the gate structure has a first region and a second region that is positioned on at least one end of the first region and has a round upper surface.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices. [Background technology]

[0002] As demands for higher performance, higher speed, and / or more functionality of semiconductor devices increase, the integration level of semiconductor devices is increasing. In order to manufacture semiconductor devices having fine patterns that meet the trend toward higher integration of semiconductor devices, it is necessary to realize patterns having fine widths or fine separation distances. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device including a stopper layer having a step to prevent a short circuit between a contact structure connected to a source / drain region and a gate contact structure connected to a gate electrode. [Means for solving the problem]

[0004] In order to achieve the above object, one aspect of the present invention provides a semiconductor device comprising: an active region extending in a first direction on a substrate; a plurality of channel layers disposed on the active region at a distance from each other in a vertical direction perpendicular to an upper surface of the substrate; gate structures extending in a second direction on the substrate, intersecting the active region and the plurality of channel layers and surrounding each of the plurality of channel layers, the gate structures including: a lower portion disposed below each of the plurality of channel layers in a region vertically overlapping the plurality of channel layers; and an upper portion disposed on an uppermost channel layer of the plurality of channel layers and including a gate electrode and a gate capping layer on the gate electrode; source / drain regions disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers; a contact structure disposed on at least one side of the source / drain region and connected to the source / drain region, extending in the second direction; a stopper layer disposed on the upper portion of the gate structure and on the contact structure, the stopper layer including a first portion disposed on an upper portion of the gate capping layer, a second portion disposed on an upper portion of the contact structure, and at least one third portion disposed at an edge portion of the gate capping layer and connecting the first portion and the second portion; and a gate contact structure penetrating the first portion of the stopper layer and the gate capping layer in the upper portion of the gate structure and connected to the gate electrode of the gate structure, wherein at least a portion of the third portion has a portion inclined with respect to an upper surface of the contact structure.

[0005] and a gate structure extending in a second direction, the gate structure including: an active region extending in a first direction on a substrate; a plurality of channel layers disposed on the active region and spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; gate electrodes on the substrate intersecting the active region and the plurality of channel layers and surrounding the plurality of channel layers; gate spacers on side surfaces of the gate electrode; and a gate capping layer on the gate electrode and the gate spacer. The gate structure extends in a second direction; source / drain regions disposed on at least one side of the gate structure on the active region and in contact with the plurality of channel layers; and contact structures disposed on the source / drain regions on at least one side of the gate structure and connected to the source / drain regions, wherein an upper region of the gate capping layer of the gate structure has a first region and a second region located at at least one end of the first region and having a rounded upper surface.

[0006] Furthermore, one embodiment of the present invention provides a gate structure extending in a second direction, the gate structure including: an active region extending in a first direction on a substrate; a plurality of channel layers disposed on the active region and spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; gate electrodes on the substrate intersecting the active region and the plurality of channel layers and surrounding each of the plurality of channel layers; gate spacers on side surfaces of the gate electrodes; and a gate capping layer on the gate electrodes and the gate spacers, the gate structure including: an upper region of the gate structure having a first region having a substantially flat upper surface and a second region located on at least one side of the first region and having a rounded upper surface; a contact structure disposed on the source / drain regions on at least one side of the gate structure and connected to the source / drain regions; and a stopper layer disposed on the gate structure and the contact structure, the stopper layer having a first portion disposed on the first region of the gate capping layer, a second portion disposed on an upper surface of the contact structure, and a third portion extending downward along the second region of the gate capping layer on at least one side of the first portion and connected to one side of the second portion. [Effects of the Invention]

[0007] According to the present invention, a semiconductor device can be provided that includes a stopper layer having a step to prevent a short circuit between a contact structure connected to a source / drain region and a gate contact structure connected to a gate electrode.

[0008] Specifically, the semiconductor device of the present invention includes a gate capping layer having rounded ends at both ends of its upper region, a contact structure having an upper surface at a level lower than the upper surface level of the gate capping layer, and a stopper layer having a step disposed on the gate capping layer and the contact structure, thereby minimizing or preventing shorts between the contact structure and the gate contact structure. This is achieved by a self-aligned contact etching process.

[0009] The various beneficial advantages and effects of the present invention are not limited to the above-mentioned contents, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to an exemplary embodiment; [Figure 2] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 3] FIG. 3 is a partially enlarged view of the semiconductor element shown in FIG. [Figure 4] 1 is an enlarged view of a portion of a semiconductor device according to an exemplary embodiment. [Figure 5] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 6] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 7] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 9] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10]2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 11] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 12] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 13] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 15] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 16] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 17] 2A to 2C are vertical cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present invention will now be described with reference to the drawings.

[0012] FIG. 1 is a plan view of a semiconductor device according to an exemplary embodiment.

[0013] Fig. 2 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment. Fig. 2 shows cross-sectional views of the semiconductor device of Fig. 1 taken along cutting lines I-I', II-II', and III-III'. For convenience of explanation, Figs. 1 and 2 show only the main components of the semiconductor device.

[0014] Fig. 3 is a partial enlarged view of the semiconductor device shown in Fig. 2. Fig. 3 is a partial enlarged view of region "A" in the cross-sectional view taken along line II' in Fig. 2.

[0015] 1 to 3, a semiconductor device 100 includes a substrate 101, an active region 105 on the substrate 101, a channel structure 140 including a plurality of channel layers 141, 142, and 143 disposed vertically spaced apart from one another on the active region 105, source / drain regions 150 in contact with the plurality of channel layers 141, 142, and 143, a gate structure 160 extending across the active region 105, contact plugs (contact structures) 180CA connected to the source / drain regions 150, a wiring via structure VA connected to the contact plug 180CA, and a gate contact plug 180CB connected to a gate electrode 165. The semiconductor device 100 further includes an isolation layer 110, a stopper layer SL, and a plurality of interlayer insulating layers 190, 191, and 192. According to an exemplary embodiment, the semiconductor device 100 further includes a wiring line structure M1. The gate structure 160 includes a gate spacer layer 164 , first and second gate dielectric layers 162 a , 162 b , a gate electrode 165 , and a gate capping layer 166 .

[0016] In the semiconductor device 100, the active region 105 has a fin structure, and the gate electrode 165 is disposed between the active region 105 and the channel structure 140, between the channel layers 141, 142, and 143 of the channel structure 140, and on top of the channel structure 140. As a result, the semiconductor device 100 includes a gate-all-around field effect transistor, i.e., an MBCFET (registered trademark) (Multi Bridge Channel FET), consisting of the channel structure 140, the source / drain regions 150, and the gate structure 160. The transistor may be, for example, an NMOS transistor.

[0017] The substrate 101 has an upper surface extending in the X and Y directions. The substrate 101 includes a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor includes silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like.

[0018] The isolation layer 110 defines the active region 105 in the substrate 101. The isolation layer 110 is formed, for example, by a shallow trench isolation (STI) process. Depending on the embodiment, the isolation layer 110 may further include a region that has a step in the lower part of the substrate 101 and extends deeper. The isolation layer 110 partially exposes the upper part of the active region 105. Depending on the embodiment, the isolation layer 110 has a curved upper surface that is higher as it is adjacent to the active region 105. The isolation layer 110 is made of an insulating material. The isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0019] The active region 105 is defined by an isolation layer 110 in the substrate 101 and is arranged to extend in a first direction, for example, the X direction. The active region 105 has a structure that protrudes from the substrate 101. An upper end of the active region 105 is arranged to protrude by a predetermined height from an upper surface of the isolation layer 110. The active region 105 may be made of a part of the substrate 101 or may include an epitaxial layer grown on the substrate 101. However, on both sides of the gate structure 160, the active region 105 on the substrate 101 is partially recessed, and the source / drain regions 150 are arranged on the recessed active region 105. The active region 105 contains impurities or includes a doped region containing impurities.

[0020] The channel structure 140 includes first to third channel layers 141, 142, and 143, which are two or more channel layers arranged on the active region 105 and spaced apart from each other in a direction perpendicular to the top surface of the active region 105, e.g., the Z direction. The first to third channel layers 141, 142, and 143 are connected to the source / drain regions 150 and spaced apart from the top surface of the active region 105. The first to third channel layers 141, 142, and 143 have widths in the Y direction that are the same as or similar to that of the active region 105 and widths in the X direction that are the same as or similar to that of the gate structure 160. However, depending on the embodiment, the first to third channel layers 141, 142, and 143 may have reduced widths in the X direction so that their side surfaces are located below the gate structure 160. This reduces the contact area between the source / drain regions 150 and the channel layers 141, 142, and 143.

[0021] The first to third channel layers 141, 142, and 143 are made of a semiconductor material, for example, silicon (Si). The first to third channel layers 141, 142, and 143 may be made of the same material as the substrate 101. The number and shape of the channel layers 141, 142, and 143 constituting one channel structure 140 may vary depending on the embodiment. For example, depending on the embodiment, the channel structure 140 may further include a channel layer disposed on the upper surface of the active region 105.

[0022] The source / drain regions 150 are disposed on the active region 105 on both sides of the channel layers 141, 142, and 143. The source / drain regions 150 serve as source or drain regions of a transistor. The source / drain regions 150 are disposed by partially recessing the upper portion of the active region 105. However, the presence or absence of a recess and the depth of the recess may vary depending on the embodiment. The source / drain regions 150 include epitaxial layers disposed along the respective sides of the channel layers 141, 142, and 143. The source / drain regions 150 may be semiconductor layers including silicon (Si) and / or germanium (Ge). The source / drain regions 150 may include impurities of different types and / or concentrations. For example, the source / drain regions 150 may include n-type doped silicon (Si) and / or p-type doped silicon germanium (SiGe). In an exemplary embodiment, the source / drain region 150 may include multiple regions containing different concentrations of elements and / or doping elements. The source / drain region 150 may have a cross-section along the Y direction that is circular, elliptical, pentagonal, hexagonal, or similar. However, in an embodiment, the source / drain region 150 may have various shapes, such as any one of a polygon, a circle, and a rectangle.

[0023] The gate structure 160 is disposed above the active region 105 and the plurality of channel layers 141, 142, and 143, extending in one direction, for example, the Y direction, intersecting the active region 105 and the plurality of channel layers 141, 142, and 143. The active region 105 and the plurality of channel layers 141, 142, and 143 intersecting with the gate structure 160 form channel regions of transistors. The gate structure 160 includes an upper portion 160A disposed on the uppermost channel layer of the plurality of channel layers 141, 142, and 143 in a region vertically overlapping the plurality of channel layers 141, 142, and 143, and a lower portion 160B disposed below each of the plurality of channel layers 141, 142, and 143. According to an exemplary embodiment, the bottom of the source / drain region 150 is disposed at a lower level than the bottom of the lower portion 160B of the gate structure 160. The gate structure 160 includes a gate electrode 165, first and second gate dielectric layers 162a, 162b between the gate electrode 165 and the multiple channel layers 141, 142, 143, a gate spacer layer 164 on the sides of the gate electrode 165, and a gate capping layer 166 on the top surface of the gate electrode 165.

[0024] The first and second gate dielectric layers 162a and 162b are disposed between the active region 105 and the gate electrode 165, and between the plurality of channel layers 141, 142, and 143 and the gate electrode 165, and are disposed so as to cover at least a portion of the surface of the gate electrode 165. For example, in the upper portion 160A of the gate structure 160, the first gate dielectric layer 162a is disposed on the lower surface of the second gate dielectric layer 162b, which is disposed on the lower surface of the gate electrode 165. The second gate dielectric layer 162b is disposed so as to surround all surfaces of the gate electrode 165 except for the top surface. The first and second gate dielectric layers 162a and 162b extend between the gate electrode 165 and the gate spacer layer 164, but are not limited thereto. The first and second gate dielectric layers 162a and 162b may have the same or different thicknesses.

[0025] The first and second gate dielectric layers 162a and 162b may be made of the same material or different materials. The first and second gate dielectric layers 162a and 162b may include oxide, nitride, or high-k material. A high-k material refers to a dielectric material having a higher dielectric constant than silicon dioxide (SiO2). Examples of high-k materials include aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr2O3).

[0026] The gate electrode 165 is disposed over the active region 105, filling the spaces between the channel layers 141, 142, and 143 and extending over the channel layers 141, 142, and 143. The gate electrode 165 is separated from the channel layers 141, 142, and 143 by first and second gate dielectric layers 162a and 162b. The gate electrode 165 includes a conductive material, such as a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon.

[0027] The gate electrode 165 may be composed of two or more multilayers. Gate spacer layers 164 are disposed on both sides of the gate electrode 165. The gate spacer layers 164 insulate the source / drain regions 150 from the gate electrode 165. Depending on the embodiment, the gate spacer layer 164 may have a multilayer structure. The width of each of the gate spacer layers 164 along the first direction, e.g., the horizontal width along the X direction, may vary depending on the depth along the third direction, e.g., the height along the Z direction. For example, the horizontal width of each of the gate spacer layers 164 increases from the upper surface of the gate spacer layer 164 toward the lower surface of the gate spacer layer 164. In other words, the thickness of each gate spacer layer 164 in the X direction increases toward the upper surface of the substrate 101. The gate spacer layer 164 includes at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0028] The gate capping layer 166 is disposed on the upper surface of the gate electrode 165. The gate capping layer 166 is disposed to extend in a second direction, for example, the Y direction, along the upper surface of the gate electrode 165. The lower surface of the gate capping layer 166 contacts the upper surface of the gate electrode 165 and the upper surface of the gate spacer layer 164.

[0029] The width of the gate capping layer 166 in the first direction, e.g., the horizontal width in the X direction, may vary depending on the depth in the third direction, e.g., the height in the Z direction. For example, the horizontal width of the gate capping layer 166 increases from the upper surface of the gate capping layer 166 toward the lower surface of the gate capping layer 166. In other words, the thickness of the gate capping layer 166 in the X direction increases toward the upper surface of the substrate 101.

[0030] The gate capping layer 166 includes an upper region 166UR and a lower region 166LR. The upper region 166UR of the gate capping layer is defined as having a first region 166UR_1 and a second region 166UR_2 (or "edge region") located on at least one side of the first region 166UR_1. The first region 166UR_1 is defined as a region having a substantially flat upper surface, and the second region 166UR_2 is defined as a region having an upper surface with an upwardly curved, curved shape. For example, the second region 166UR_2 may be a region having a rounded upper surface. The upper surface of the second region 166UR_2 is a portion that physically connects the upper surface of the first region 166UR_1 and the outer surface of the lower region 166LR.

[0031] The gate capping layer 166 is made of an oxide, a nitride, and an oxynitride, and specifically includes at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0032] The first interlayer insulating layer 190 is disposed to cover the source / drain regions 150 and the element isolation layer 110. The first interlayer insulating layer 190 includes, for example, at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0033] The contact structures 180CA are disposed between the gate structures 160 at intervals in a first direction, e.g., the X direction, and extend in a second direction, e.g., the Y direction, on the source / drain regions 150 (see FIG. 1). The contact structures 180CA contact the source / drain regions 150 between the gate structures 160 and apply electrical signals to the source / drain regions 150.

[0034] The contact structure 180CA includes a metal-semiconductor compound layer 182 located at the bottom, a barrier layer 184 disposed along the sidewall, and a plug conductive layer 186. The metal-semiconductor compound layer 182 may be, for example, a metal silicide layer. The barrier layer 184 includes a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The plug conductive layer 186 includes a metal material, such as aluminum (Al), tungsten (W), or molybdenum (Mo). In the exemplary embodiment, each of the contact structures 180CA is disposed to penetrate at least a portion of the source / drain region 150. In the exemplary embodiment, the number and arrangement of the conductive layers constituting the contact structure 180CA may be varied.

[0035] The contact structure 180CA has sloping sidewalls such that the width at the bottom is narrower than the width at the top depending on the aspect ratio, but is not limited thereto. The contact structure 180CA is positioned to recess the source / drain region 150 to a predetermined depth. The upper surface 180CA_US of the contact structure is substantially flat. The upper surface 180CA_US of the contact structure is located at a level lower than the level of the upper surface of the gate capping layer 166. The difference in level between the upper surface 180CA_US of the contact structure and the upper surface of the gate capping layer 166 is defined as a first gap L1. The first gap L1 may be 10 nm or less, for example, 3 nm to 7 nm, 3 nm to 5 nm, or 3.5 nm to 4 nm.

[0036] The stopper layer SL is disposed to cover the gate structure 160 and the contact structure 180CA. The stopper layer SL is defined to include a plurality of portions, for example, a first stopper layer portion SLa, a second stopper layer portion SLb, and a third stopper layer portion SLc.

[0037] The first stopper layer portion SLa is defined as a portion covering the top surface of the first region 166UR_1 in the upper region of the gate capping layer. The second stopper layer portion SLb is defined as a portion covering the top surface 180CA_US of the contact structure. The third stopper layer portion SLc is defined as a portion covering the top surface of the second region 166UR_2 in the upper region of the gate capping layer. The third stopper layer portion SLc is disposed between the first stopper layer portion SLa and the second stopper layer portion SLb and connects the first stopper layer portion SLa and the second stopper layer portion SLb to each other.

[0038] The lower surface of the second stopper layer portion SLb is located at a level lower than the lower surface of the first stopper layer portion SLa. The level difference between the lower surfaces of the second stopper layer portion SLb and the first stopper layer portion SLa is defined as a first gap L1. Here, the first gap L1 is the same as the first gap L1 described when describing the level difference between the upper surface 180CA_US of the contact structure and the upper surface of the gate capping layer 166.

[0039] At least a portion of the third stopper layer portion SLc includes a portion inclined with respect to the upper surface 180CA_US of the contact structure. In other words, unlike the first stopper layer portion SLa and the second stopper layer portion SLb, the third stopper layer portion SLc does not include a flat upper surface and / or lower surface. The shape of the third stopper layer portion SLc is similar to the shape of the upper surface of the second region 166UR_2 of the upper region of the gate capping layer. For example, in cross section, the third stopper layer portion SLc has a curved shape that bends upward. Specifically, both the portion of the third stopper layer portion SLc that contacts the surface of the gate capping layer 166 and the portion that contacts the second interlayer insulating layer 191 have rounded shapes.

[0040] The stopper layer SL includes, for example, at least one of silicon nitride and silicon oxynitride.

[0041] The second interlayer insulating layer 191 is disposed to cover the stopper layer SL. The second interlayer insulating layer 191 includes, for example, at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0042] The gate contact structure 180CB penetrates at least a portion of the second interlayer insulating layer 191, the stopper layer SL, and the gate capping layer 166 to contact the gate electrode 165 and apply an electrical signal to the gate electrode 165. The gate contact structure 180CB penetrates the first stopper layer portion SLa between the third stopper layer portions SLc of the stopper layer SL. The third stopper layer portions SLc forming the step of the stopper layer SL can minimize or prevent a short circuit that may occur between the gate contact structure 180CB and the contact structure 180CA.

[0043] The gate contact structure 180CB includes a barrier layer 181 disposed along a sidewall thereof and a plug conductive layer 183. The barrier layer 181 includes a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The plug conductive layer 183 includes a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In the exemplary embodiment, the gate contact structure 180CB is disposed to penetrate at least a portion of the gate electrode 165. In the exemplary embodiment, the number and arrangement of the conductive layers constituting the gate contact structure 180CB may be varied.

[0044] The wiring via structure VA penetrates at least a part of the second interlayer insulating layer 191 and the stopper layer SL to come into contact with the contact structure 180CA, and applies an electrical signal to the contact structure 180CA.

[0045] The wiring via structure VA includes a barrier layer VAa disposed along a sidewall and a via plug conductive layer VAb. The barrier layer VAa includes a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The via plug conductive layer VAb includes a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In an exemplary embodiment, the wiring via structure VA is disposed to penetrate at least a portion of the contact structure 180CA. In an exemplary embodiment, the number and arrangement of conductive layers constituting the wiring via structure VA may be variously changed.

[0046] The third interlayer insulating layer 192 is disposed on the second interlayer insulating layer 191 to cover the gate contact structure 180CB and the wiring via structure VA. The third interlayer insulating layer 192 includes, for example, at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0047] The wiring line structure M1 includes a first metal wiring M1a and a second metal wiring M1b. The first metal wiring M1a is electrically coupled to the source / drain region 150 via a wiring via structure VA and a contact structure 180CA, and the second metal wiring M1b is electrically coupled to the gate electrode 165 via a gate contact structure 180CB. A side portion of the wiring line structure M1 is surrounded by a third interlayer insulating layer 192. If necessary, additional wiring line structures, wiring via structures, and interlayer insulating layers may be disposed on the wiring line structure M1 and the third interlayer insulating layer 192 (not shown).

[0048] FIG. 4 is an enlarged view of a portion of a semiconductor device according to an example embodiment.

[0049] Referring to FIG. 4, the semiconductor device 100a is the same as or similar to that described with reference to FIGS. 1 to 3, except that the upper surface 180CA_US of the contact structure has a curved shape.

[0050] 4, the upper surface 180CA_US of the contact structure has a downwardly curved curved shape. For example, the upper surface 180CA_US of the contact structure has a downwardly convex shape in cross section.

[0051] As a result, the shape of the second stopper layer portion SLb of the stopper layer SL disposed on the upper surface 180CA_US of the contact structure is similar to the shape of the upper surface 180CA_US of the contact structure. Specifically, from a cross-sectional perspective, the second stopper layer portion SLb has a downwardly curved shape, for example, a downwardly convex shape. In this case, the level difference between the lower surface of the first stopper layer portion SLa and the lowermost surface of the second stopper layer portion SLb is greater than the first gap L1 described with reference to FIGS. 1 to 3. Here, the lowermost surface of the second stopper layer portion SLb is defined as the lower surface of a portion formed in the central portion of the upper surface of the contact structure 180CA.

[0052] The level difference between the bottom surface of the first stopper layer portion SLa and the bottommost surface of the second stopper layer portion SLb is defined as a second gap L2. The second gap L2 may be 11 nm or less, for example, 4 nm to 8 nm, or 3.5 nm to 6 nm, or 4 nm to 4.5 nm.

[0053] 5 to 17 are vertical cross-sectional views showing a sequence of steps for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0054] Referring to FIG. 5, a sacrificial layer 120 and a plurality of channel layers 141, 142, and 143 are alternately stacked on a substrate 101.

[0055] 2, the sacrificial layer 120 is replaced by first and second gate dielectric layers 162a and 162b and a gate electrode 165. The sacrificial layer 120 is made of a material that has etch selectivity with respect to the channel layers 141, 142, and 143. The channel layers 141, 142, and 143 comprise a different material from the sacrificial layer 120. In an exemplary embodiment, the channel layers 141, 142, and 142 comprise silicon (Si), and the sacrificial layer 120 comprises silicon germanium (SiGe).

[0056] The sacrificial layer 120 and the channel layers 141, 142, and 143 are formed by performing an epitaxial growth process using the substrate 101 as a seed. Each of the sacrificial layer 120 and the channel layers 141, 142, and 143 has a thickness ranging from about 1 Å to 100 nm. The number of layers of the channel layers 141, 142, and 143 alternately stacked with the sacrificial layer 120 may vary depending on the embodiment.

[0057] Referring to FIG. 6, the stacked structure of the sacrificial layer 120 and the channel layers 141, 142, 143, as well as a portion of the substrate 101, are removed to form an active structure.

[0058] The active structure includes a sacrificial layer 120 and a plurality of channel layers 141, 142, and 143 alternately stacked with each other, and further includes active regions 105 formed by removing portions of the substrate 101 and protruding from the upper surface of the substrate 101. The active structures are formed in a line shape extending in one direction, for example, the X direction, and are spaced apart from each other in the Y direction. Depending on the aspect ratio, the active regions 105 may have a sloped shape such that their width increases toward the bottom.

[0059] An insulating material is filled into the region where the portion of the substrate 101 has been removed, and then the region is recessed so that the active region 105 protrudes, thereby forming an isolation layer 110. The top surface of the isolation layer 110 is formed lower than the top surface of the active region 105.

[0060] Referring to FIG. 7, a sacrificial gate structure 170 and a gate spacer layer 164 are formed over the active structure.

[0061] The sacrificial gate structure 170 is formed in a subsequent process in the region where the first and second gate dielectric layers 162a and 162b and the gate electrode 165 are to be disposed on top of the plurality of channel layers 141, 142, and 143, as shown in FIG. 2 . The sacrificial gate structure 170 includes first and second sacrificial gate layers 172 and 175, which are sequentially stacked, and a mask pattern layer 176. The first and second sacrificial gate layers 172 and 175 are patterned using the mask pattern layer 176. The first and second sacrificial gate layers 172 and 175 are an insulating layer and a conductive layer, respectively. For example, the first sacrificial gate layer 172 includes silicon oxide, and the second sacrificial gate layer 175 includes polysilicon. The mask pattern layer 176 includes silicon nitride. The sacrificial gate structure 170 has a line shape extending in one direction and intersecting the active structure. The sacrificial gate structures 170 extend, for example, in the Y direction and are spaced apart from one another in the X direction.

[0062] The gate spacer layer 164 is formed on both sidewalls of the sacrificial gate structure 170. The gate spacer layer 164 is formed by forming a film of uniform thickness along the top and side surfaces of the sacrificial gate structure 170 and the active structure, and then performing anisotropic etching. The gate spacer layer 164 is made of a low-k material, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0063] Referring to FIG. 8, the exposed sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 are partially removed between the sacrificial gate structures 170 to form recess regions RC, and the plurality of channel layers 141, 142, and 143 and the active region 105 are partially removed.

[0064] Using the sacrificial gate structure 170 and the gate spacer layer 164 as a mask, the exposed sacrificial layer 120 and portions of the plurality of channel layers 141, 142, and 143 are removed to form recess regions RC. The recess process is performed, for example, by sequentially applying a dry etching process and a wet etching process. First, the recess regions RC are formed in the vertical direction by the dry etching process. Next, the recess regions RC are formed in the horizontal direction by the wet etching process. As a result, the plurality of channel layers 141, 142, and 143 have a limited length along the X direction.

[0065] Crystallographic anisotropic etching is used to etch the channel layers 141, 142, and 143 and the active region 105. Wet crystallographic anisotropic etching uses an etchant such as KOH, NaOH, NH4OH, or TMAH (tetramethyl ammonium hydroxide). When crystallographic anisotropic etching is used, the channel layers 141, 142, and 143 are etched at different etching rates depending on the crystal orientations of the channel layers 141, 142, and 143 and the substrate 101. As a result, at least a portion of the outer surfaces of the channel layers 141, 142, and 143 and the top surface of the active region 105 have a (111) crystal orientation, and the channel layers 141, 142, and 143 have a sharp sigma shape toward their centers. However, the specific shapes of the side surfaces of the plurality of channel layers 141, 142, and 143 and the upper portion of the active region 105 are not limited to those shown in FIG.

[0066] Referring to FIG. 9, an epitaxial layer of source / drain regions 150 is formed to fill recess regions RC.

[0067] The source / drain regions 150 are formed by an epitaxial growth process. The source / drain regions 150 are formed by repeating epitaxial growth and etching processes and extend to contact the plurality of channel layers 141, 142, and 143 and the lower portion 160B of the gate structure 160. The source / drain regions 150 contain impurities by in-situ doping. The upper surfaces of the source / drain regions 150 are substantially flush with or higher than the lower surface of the upper portion 160A of the gate structure 160, but are not limited thereto.

[0068] Referring to FIG. 10, a first interlayer insulating layer 190 is formed, and the sacrificial layer 120 and the sacrificial gate structure 170 are removed.

[0069] The first interlayer insulating layer 190 is formed by forming an insulating film covering the sacrificial gate structure 170 and the source / drain regions 150 and then performing a planarization process.

[0070] The sacrificial layer 120 and the sacrificial gate structure 170 are selectively removed relative to the gate spacer layer 164, the first interlayer insulating layer 190, and the plurality of channel layers 141, 142, and 143. First, the sacrificial gate structure 170 is removed to form an upper gap region UR, and then the sacrificial layer 120 exposed through the upper gap region UR is removed to form a lower gap region LR. For example, if the sacrificial layer 120 includes silicon germanium (SiGe) and the plurality of channel layers 141, 142, and 143 include silicon (Si), the sacrificial layer 120 is selectively removed by performing a wet etching process using peracetic acid and / or a solution used in an SC1 (Standard Clean-1) cleaning process (NH4OH:H2O2:H2O = 1:1:5) as an etchant.

[0071] Referring to FIG. 11, a gate structure 160 is formed in the upper gap region UR and the lower gap region LR.

[0072] The first and second gate dielectric layers 162a and 162b are formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 is formed to fill the upper gap region UR and the lower gap region LR. The gate electrode 165 and the gate spacer layer 164 are removed from the top of the upper gap region UR to a predetermined depth. A gate capping layer 166 is formed in the region of the upper gap region UR from which the gate electrode 165 and the gate spacer layer 164 have been removed. This forms a gate structure 160 including the first and second gate dielectric layers 162a and 162b, the gate electrode 165, the gate spacer layer 164, and the gate capping layer 166.

[0073] Referring to FIG. 12, a plurality of contact holes H1 are formed between the gate structures 160, at least partially penetrating the source / drain regions 150.

[0074] The contact holes H1 are formed by a self-aligned contact (SAC) etching process (hereinafter referred to as the SAC process). The self-aligned contact etching process is performed using the difference in etching selectivity between the gate capping layer 166 and the first interlayer insulating layer 190. Therefore, it is preferable that the gate capping layer 166 and the first interlayer insulating layer 190 include different materials. In this embodiment, the gate capping layer 166 includes silicon nitride, and the first interlayer insulating layer 190 includes silicon oxide.

[0075] Each of the contact holes H1 formed by the SAC process has an upper region that is wider than a lower region, so that the edge portion 166UR_2 of the upper region of the gate capping layer 166 is at least partially etched to have a rounded shape (see FIGS. 2 and 3).

[0076] Referring to FIG. 13, a metal-semiconductor compound layer 182, a barrier layer 184, and a plug conductive layer 186 are sequentially formed in the plurality of contact holes H1.

[0077] 13, a metal-semiconductor compound layer 182 is formed at the bottom of the plurality of contact holes H1 to conformally cover the surfaces of the source / drain regions 150. A barrier layer 184 is formed to cover the surfaces of the metal-semiconductor compound layer 182 and the gate structure 160. Then, a plug conductive layer 186 is formed on the barrier layer 184 to extend in a first direction (X direction) and a second direction (Y direction).

[0078] Referring to FIG. 14, a planarization process is performed to form a plurality of plug conductive layers 186 spaced apart in a first direction, for example, the X direction.

[0079] The planarization process removes the plug conductive layer 186 and the barrier layer 184 that vertically overlap the gate structure 160, thereby exposing the upper region of the gate capping layer 166.

[0080] Referring to FIG. 15, an etch-back process is performed to form contact structure 180CA.

[0081] The etch-back process removes a portion of the upper regions of the plug conductive layer 186 and the barrier layer 184. This results in, but is not limited to, the formation of the plug conductive layer 186 and the barrier layer 184 each having a substantially flat upper surface. For example, referring to FIG. 4, the formation of the plug conductive layer 186 and the barrier layer 184 has a downwardly curved upper surface.

[0082] Referring to FIG. 16, a stopper layer SL is formed on the gate structure 160 and the contact structure 180CA.

[0083] The stopper layer SL is formed by depositing an insulating film on the gate structure 160 and the contact structure 180CA. The stopper layer SL is formed to substantially the same thickness on the gate structure 160 and the contact structure 180CA.

[0084] Referring to FIG. 17, a second interlayer insulating layer 191 is formed on the stopper layer SL, and a plurality of contact holes H2 penetrating at least a portion of the second interlayer insulating layer 191 are formed.

[0085] The second interlayer insulating layer 191 is formed by forming an insulating film that covers the stopper layer SL and then performing a planarization process.

[0086] The second interlayer insulating layer 191 is patterned to form a plurality of contact holes H2 that penetrate the second interlayer insulating layer 191, the stopper layer SL, and the gate capping layer 166 and expose the surface of the gate electrode 165.

[0087] 2 and 3, gate contact structures 180CB are formed in the plurality of contact holes H2. The gate contact structures 180CB include a barrier layer 181 formed along the sidewalls thereof and a plug conductive layer 183 on the barrier layer 181.

[0088] A material for forming the barrier layer 181 is deposited in the contact holes H2, and then a conductive material is filled in the contact holes H2 to form the gate contact structures 180CB.

[0089] Then, although not shown, the second interlayer insulating layer 191 is patterned to form a plurality of via holes penetrating the second interlayer insulating layer 191 and the stopper layer SL to expose the contact structures 180CA. Wiring via structures VA are formed in the via holes (see FIGS. 2 and 3). Specifically, a material forming a barrier layer VAa is deposited in the via holes, and then a conductive material is filled to form via plug conductive layers VAb. Next, a third interlayer insulating layer 192 is formed on the second interlayer insulating layer 191 to cover the gate contact structures 180CB and the wiring via structures VA. Then, a plurality of open regions are formed penetrating the third interlayer insulating layer 192 to expose the gate contact structures 180CB and the wiring via structures VA, respectively. Wiring line structures M1 including first metal wires M1a and second metal wires M1b connected to the gate contact structures 180CB and the wiring via structures VA are formed in the open regions.

[0090] The present invention is not limited to the above-described embodiments and drawings, and various substitutions, modifications, and alterations can be made by those skilled in the art without departing from the technical spirit of the present invention, and these also fall within the scope of the present invention. [Explanation of symbols]

[0091] 100: Semiconductor element 101: Circuit board 105: Active area 110: Element isolation layer 120: Sacrificial Layer 140: Channel Structure 150: Source / drain region 160: Gate Structure 165: Gate electrode 166: Gate capping layer 170: Sacrificial Gate Structure 180CA: Contact plug (contact structure) 180CB: Gate contact plug (gate contact structure) SL: Stopper layer 190, 191, 192: (first, second, third) interlayer insulating layers VA: Wiring via structure M1: Wiring line structure

Claims

1. an active region extending in a first direction on a substrate; a plurality of channel layers disposed on the active region and spaced apart from one another in a vertical direction perpendicular to the upper surface of the substrate; a gate structure extending in a second direction on the substrate, the gate structure intersecting the active region and the plurality of channel layers and surrounding each of the plurality of channel layers, the gate structure including: a lower portion disposed below each of the plurality of channel layers in a region vertically overlapping the plurality of channel layers; and an upper portion disposed on an uppermost channel layer of the plurality of channel layers, the upper portion including a gate electrode and a gate capping layer on the gate electrode; source / drain regions disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers; a contact structure disposed on at least one side of the gate structure and connected to the source / drain region, the contact structure extending in the second direction; a stopper layer disposed on the upper portion of the gate structure and the contact structure, the stopper layer including a first portion disposed on an upper portion of the gate capping layer, a second portion disposed on an upper portion of the contact structure, and at least one third portion disposed on an edge portion of the gate capping layer and connecting the first portion and the second portion; a gate contact structure passing through the first portion of the stopper layer and the gate capping layer of the upper portion of the gate structure and connected to the gate electrode of the gate structure, At least a part of the third portion has a portion inclined with respect to an upper surface of the contact structure.

2. further comprising a gate spacer disposed on a side surface of the gate electrode of the gate structure; a lower surface of the gate capping layer contacts an upper surface of the gate electrode and an upper surface of the gate spacer; 2. The semiconductor device of claim 1, wherein the horizontal width of the gate spacer increases with increasing distance from the bottom surface of the gate capping layer in a downward direction.

3. 3. The semiconductor device of claim 2, wherein a horizontal width of the gate capping layer increases from an upper surface of the gate capping layer toward the lower surface of the gate capping layer.

4. a lower surface of the first portion of the stopper layer contacts an upper surface of the gate capping layer of the upper portion of the gate structure; a lower surface of the second portion of the stopper layer contacting an upper surface of the contact structure; 2. The semiconductor device of claim 1, wherein the bottom surface of the second portion of the stopper layer is at a lower level than the bottom surface of the first portion of the stopper layer.

5. 5. The semiconductor device of claim 4, wherein the upper surface of the contact structure and the lower surface of the second portion of the stopper layer have downwardly curved shapes.

6. 2. The semiconductor device of claim 1, wherein the edge portion of the gate capping layer has a rounded shape in cross section.

7. 7. The semiconductor device according to claim 6, wherein the third portion of the stopper layer has a rounded shape in cross section.

8. the at least one third portion includes a plurality of third portions disposed on both sides of the first portion; The semiconductor device of claim 1 , wherein the gate contact structure is located on the gate structure between the third portions of the stopper layer.

9. The semiconductor device of claim 8 , further comprising a wiring via structure that penetrates the second portion of the stopper layer on the contact structure and is connected to the contact structure.

10. the at least one third portion includes a plurality of third portions disposed on both sides of the second portion; The semiconductor device according to claim 9 , wherein the wiring via structure is located between the third portions of the stopper layer on the contact structure.

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